STMICROELECTRONICS L6743

L6743
L6743Q
High current MOSFET driver
Features
■
Dual MOSFET driver for synchronous rectified
converters
■
High driving current for fast external MOSFET
switching
■
Integrated bootstrap diode
■
High frequency operation
■
Enable pin
■
Adaptive dead-time management
■
Flexible gate-drive: 5V to 12V compatible
■
High-impedance (HiZ) management for output
stage Shutdown
■
Preliminary OV protection
■
SO-8 and DFN10 3x3 packages
SO-8
Combined with ST PWM Controllers, the driver
allows implementing complete voltage regulator
solutions for modern high-current CPUs and
DCDC conversion in general. L6743, L6743Q
embeds high-current drivers for both high-side
and low-side MOSFETS. The device accepts
flexible power supply (5V to 12V) to optimize the
gate-drive voltage for High-Side and Low-Side
maximizing the System Efficiency.
The Bootstrap diode is embedded saving the use
of external diodes. Anti shoot-through
management avoids high-side and low-side
mosfet to conduct simultaneously and, combined
with Adaptive Dead-Time control, minimizes the
LS body diode conduction time.
Applications
■
High current VRM / VRD for Desktop / Server /
Workstation CPUs
■
High current and high efficiency DC / DC
converters
L6743, L6743Q embeds Preliminary OV
Protection: after Vcc overcomes the UVLO and
while the device is in HiZ, the LS MOSFET is
turned ON to protect the load in case the output
voltage overcomes a warning threshold protecting
the output against HS failures.
Description
L6743, L6743Q is a flexible, high-frequency dualdriver specifically designed to drive N-channel
MOSFETs connected in Synchronous-Rectified
Buck topology.
Table 1.
August 2007
DFN10 3x3
The driver is available is SO8 and DFN10 3x3
packages
Device summary
Order code
Package
Packaging
L6743
SO-8
Tube
L6743TR
SO-8
Tape & Reel
L6743Q
DFN10
Tube
L6743QTR
DFN10
Tape & Reel
Rev 1
1/17
www.st.com
1
Contents
L6743, L6743Q
Contents
1
2
Typical application circuit and block diagram . . . . . . . . . . . . . . . . . . . . 3
1.1
Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pins description and connection diagrams . . . . . . . . . . . . . . . . . . . . . . 4
2.1
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
5
4.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4.2
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Device description and operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
5.1
High-impedance (HiZ) management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5.2
Preliminary OV protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5.3
Internal BOOT diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.4
Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.5
Layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
6
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
7
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2/17
L6743, L6743Q
Typical application circuit and block diagram
1
Typical application circuit and block diagram
1.1
Application circuit
Figure 1.
Typical application circuit
VCC = 5V to 12V
CDEC
VIN = 5V to 12V
VCC
BOOT
PWM
EN Input
EN
L6743
CHF
PWM Input
GND
Vout
L
PHASE
COUT
LS
LGATE
NC*
CBULK
HS
UGATE
NC*
L6743 Reference Schematic
1.2
Block diagram
Figure 2.
Block diagram
VCC
BOOT
EN
GND
L6743
PWM
CONTROL LOGIC
& PROTECTIONS
PWM
ADAPTIVE ANTI
CROSS CONDUCTION
15k
HS
UGATE
PHASE
VCC
LS
LGATE
GND
3/17
Pins description and connection diagrams
2
L6743, L6743Q
Pins description and connection diagrams
Figure 3.
Pins connection (Top view)
BOOT
PWM
EN
VCC
1
2
3
8
L6743
4
2.1
Pin description
Table 2.
Pins escriptions
7
6
5
BOOT
PWM
EN
VCC
VCC
UGATE
PHASE
GND
LGATE
1
10
2
9
3
L6743Q
8
4
7
5
6
UGATE
PHASE
GND
GND
LGATE
Pin n
Name
DFN10
1
2
Function
SO-8
1
2
BOOT
High-Side Driver Supply.
This pin supplies the High-Side floating driver. Connect through a RBOOT - CBOOT
capacitor to the PHASE pin.
Internally connected to the cathode of the integrated Bootstrap diode. See
Section 5.3 for guidance in designing the capacitor value.
PWM
Control input for the driver, 5V compatible.
This pin controls the state of the driver and which external MOSFET have to be
turned-ON according to EN status. If left floating and in conjunction with EN
asserted, it causes the driver to enter the High-Impedance (HiZ) state which causes
all mosfets to be OFF. See Section 5.1 for details about HiZ.
3
3
EN
Enable Input for the Driver. Internally pulled low by 15kΩ.
Pull High to enable the driver according to the PWM status. If pulled low will cause
the drive to enter HiZ state with all mosfet OFF regardless of the PWM status.
See Section 5.1 for details about HiZ.
4, 5
4
VCC
Device and LS Driver power supply. Connect to any voltage between 5V and 12V.
Bypass with low-ESR MLCC capacitor to GND.
6
5
LGATE
7, 8
6
GND
9
7
PHASE
High-Side Driver return Path. Connect to the High-Side MOSFET Source.
This pin is also monitored for the adaptive dead-time management and Pre-OV
Protection.
10
8
UGATE
High-Side Driver Output.
Connect to High-Side MOSFET gate.
PAD
-
TH. PAD
Thermal pad connects the Silicon substrate and makes good thermal contact with
the PCB. Connect to the PGND plane. (DFN10 only)
4/17
Low-Side Driver Output.
Connect directly to the Low-Side MOSFET gate. A small series resistor can be
useful to reduce dissipated power especially in high frequency applications.
All internal references, logic and drivers are referenced to this pin. Connect to the
PCB ground plane.
L6743, L6743Q
3
Thermal data
Thermal data
Table 3.
Thermal data
Value
Symbol
Parameter
RthJA
Thermal resistance junction to ambient
(Device soldered on 2s2p, 67mm x 69mm board)
RTHJC
Thermal resistance junction to case
TMAX
Maximum junction temperature
TSTG
TJ
PTOT
DFN10
85
45
°C/W
-
5
°C/W
150
°C
Storage temperature range
0 to 150
°C
Junction temperature range
0 to 125
°C
Maximum power dissipation at 25°C
(Device soldered on 2s2p PC Board)
4
Electrical specifications
4.1
Absolute maximum ratings
Table 4.
Unit
SO8
1.15
2.25
W
Absolute maximum ratings
Symbol
Parameter
Value
Unit
-0.3 to 15
V
41
15
V
VCC,VPVCC
to GND
VBOOT, VUGATE
to GND
to PHASE
VPHASE
to GND
-8 to 26
V
VLGATE
to GND
-0.3 to VCC + 0.3
V
VPWM, VEN
to GND
-0.3 to 7
V
VCC,VPVCC
to GND
-0.3 to 15
V
5/17
Electrical specifications
L6743, L6743Q
4.2
Electrical characteristics
Table 5.
Electrical characteristics
(VCC = 12V±15%, Tj = 0°C to 70°C unless otherwise specified).
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
Supply current and power-ON
ICC
IBOOT
UVLOVCC
VCC supply current
UGATE and LGATE = OPEN
BOOT = 12V
5
mA
BOOT supply current
UGATE = OPEN;
PHASE to GND; BOOT = 12V
2
mA
VCC turn-ON
VCC rising
VCC turn-OFF
VCC falling
3.5
V
Input high - VPWM_IH
PWM rising
2
V
Input low - VPWM_IL
PWM falling
4.1
V
PWM and EN input
PWM
tHiZ
0.8
HiZ hold-off time
150
V
ns
Input high - VEN_IH
EN rising
Input low - VEN_IH
EN falling
Input resistance
to GND
15
RHIHS
HS source resistance
BOOT - PHASE = 12V; 100mA
2.3
IUGATE
HS source current (1)
BOOT - PHASE = 12V;
CUGATE to PHASE = 3.3nF
2
RLOHS
HS sink resistance
BOOT - PHASE = 12V; 100mA
2
2.5
Ω
RHILS
LS source resistance
100mA
1.3
1.8
Ω
ILGATE
LS source current (1)
CLGATE to GND = 5.6nF
3
RLOLS
LS sink resistance
100mA
1
Pre-OV Threshold
PHASE rising
EN
2
V
0.8
V
kΩ
Gate drivers
2.8
Ω
A
A
1.5
Ω
Protections
VPRE_OV
1. Parameter(s) guaranteed by designed, not fully tested in production
6/17
1.8
V
L6743, L6743Q
Device description and operation
L6743, L6743Q provides high-current driving control for both High-Side and Low-Side NChannel MOSFETS connected as Step-Down DC-DC Converter driven by an external PWM
signal. The integrated high-current drivers allow using different types of power MOSFETs
(also multiple MOS to reduce the equivalent RdsON), maintaining fast switching transition.
The driver for the High-Side MOSFET use BOOT pin for supply and PHASE pin for return.
The driver for the Low-Side MOSFET use the VCC pin for supply and PGND pin for return.
The Driver embodies a anti-shoot-through and adaptive dead-time control to minimize LowSide body diode conduction time maintaining good efficiency saving the use of Schottky
diodes: when the high-side mosfet turns off, the voltage on its source begins to fall; when
the voltage reaches about 2V, the Low-Side MOSFET gate drive voltage is suddenly
applied. When the Low-Side MOSFET turns off, the voltage at LGATE pin is sensed. When
it drops below about 1V, the High-Side MOSFET gate drive voltage is suddenly applied. If
the current flowing in the inductor is negative, the source of highside mosfet will never drop.
To allow the Low-Side MOSFET to turn-on even in this case, a watchdog controller is
enabled: if the source of the High-Side MOSFET doesn't drop, the Low-Side MOSFET is
switched on so allowing the negative current of the inductor to recirculate. This mechanism
allows the system to regulate even if the current is negative.
Before VCC to overcome the UVLO threshold, L6743, L6743Q keeps firmly-OFF both HighSide and Low-Side MOSFETS then, after the UVLO has been crossed, the EN and PWM
inputs take the control over driver’s operations. EN pin enables the driver: if low will keep all
mosfet OFF (HiZ) regardless of the status of PWM. When EN is high, the PWM input takes
the control: if left floating, the internal resistor divider sets the HiZ State: both MOSFETS are
kept in the OFF state until PWM transition.
After UVLO crossing and while in HiZ, the Preliminary-OV protection is activated: if the
voltage senses through the PHASE pin overcomes about 1.8V, the Low-Side MOSFET is
latched ON in order to protect the load from dangerous over-voltage. The Driver status is
reset from a PWM transition.
Driver power supply as well as power conversion input are flexible: 5V and 12V can be
chosen for High-Side and Low-Side MOSFET voltage drive.
Figure 4.
Timing diagram (EN = High)
HiZ Window
HiZ Window
PWM
HiZ
HiZ
HS Gate
thold-off
tprop_ L
tdead_HL
tprop_H
tdead_LH
LS Gate
tprop_L
5
Device description and operation
thold-off
7/17
Device description and operation
5.1
L6743, L6743Q
High-impedance (HiZ) management
The Driver is able to manage High-Impedance state by keeping all MOSFETs in off state in
two different ways.
●
If the EN signal is pulled low, the device will keep all mosfets OFF careless of the PWM
status.
●
When EN is asserted, if the PWM signal remains in the HiZ window for a time longer
than the hold-off time, the device detects the HiZ condition so turning off all the
MOSFETs. The HiZ window is defined as the PWM voltage range comprised between
VPWM_IL and VPWM_IH.
The device exits from the HiZ state only after a PWM transition to logic zero (VPWM <
VPWM_IL).
See Figure 4 for details about HiZ timings.
The implementation of the High-Impedance state allows the controller that will be connected
to the driver to manage High-Impedance state of its output, avoiding to produce negative
undershoot on the regulated voltage during the shut-down stage. Furthermore, different
power management states may be managed such as pre-bias start-up.
5.2
Preliminary OV protection
After VCC has overcome its UVLO threshold and while in HiZ, L6743, L6743Q activates the
Preliminary-OV protection.
The intent of this protection is to protect the load especially from High-Side MOSFET
failures during the system start-up. In fact, VRM, and more in general PWM controllers, have
a 12V bus compatible turn-on threshold and results to be non-operative if VCC is below that
turn-on thresholds (that results being in the range of about 10V). In case of a High-Side
mosfet failure, the controller won’t recognize the over voltage until VCC = ~10V (unless
other special features are implemented): but in that case the output voltage is already at the
same voltage (~10V) and the load (CPU in most cases) already burnt.
L6743, L6743Q by-pass the PWM controller by latching on the Low-Side MOSFET in case
the PHASE pin voltage overcome 2V during the HiZ state. When the PWM input exits form
the HiZ window, the protection is reset and the control of the output voltage is transferred to
the controller connected to the PWM input.
Since the Driver has its own UVLO threshold, a simple way to provide protection to the
output in all conditions when the device is OFF consists in supplying the controller through
the 5VSB bus: 5VSB is always present before any other voltage and, in case of High-Side
short, the Low-Side mosfet is driven with 5V assuring a reliable protection of the load.
Preliminary OV is active after UVLO and while the Driver is in HiZ state and it is disabled
after the first PWM transition. The controller will have to manage its output voltage from that
time on.
8/17
L6743, L6743Q
5.3
Device description and operation
Internal BOOT diode
L6743, L6743Q embeds a boot diode to supply the High-Side driver saving the use of an
external component. Simply connecting an external capacitor between BOOT and PHASE
complete the High-Side supply connections.
To prevent bootstrap capacitor to extra-charge as a consequence of large negative spikes,
an external series resistance RBOOT (in the range of few ohms) may be required in series to
BOOT pin.
Bootstrap capacitor needs to be designed in order to show a negligible discharge due to the
High-Side MOSFET turn-on. In fact it must give a stable voltage supply to the High-Side
driver during the MOSFET turn-on also minimizing the power dissipated by the embedded
Boot Diode. Figure 5 gives some guidelines on how to select the capacitance value for the
bootstrap according to the desired discharge and depending on the selected mosfet.
Figure 5.
Bootstrap capacitance design
2.5
2500
Cboot = 47nF
Cboot = 100nF
Qg = 10nC
Qg = 25nC
2000
Cboot = 220nF
Qg = 50nC
Cboot = 330nF
Cboot = 470nF
Bootstrap Cap [uF]
BOOT Cap discharge [V]
2.0
1.5
1.0
0.5
Qg = 100nC
1500
1000
500
0.0
0
0
10
20
30
40
50
60
70
80
90
100
0.0
0.2
High-Side MOSFET Gate Charge [nC]
5.4
0.4
0.6
0.8
1.0
Boot Cap Delta Voltage [V]
Power dissipation
L6743, L6743Q embeds high current drivers for both High-Side and Low-Side MOSFETs: it
is then important to consider the power that the device is going to dissipate in driving them
in order to avoid overcoming the maximum junction operative temperature.
Two main terms contribute in the device power dissipation: bias power and drivers' power.
●
Device Power (PDC) depends on the static consumption of the device through the
supply pins and it is simply quantifiable as follow:
P DC = V CC ⋅ I CC + V PVCC ⋅ I PVCC
●
Drivers' power is the power needed by the driver to continuously switch ON and OFF
the external MOSFETs; it is a function of the switching frequency and total gate charge
of the selected MOSFETs. It can be quantified considering that the total power PSW
dissipated to switch the MOSFETs dissipated by three main factors: external gate
resistance (when present), intrinsic MOSFET resistance and intrinsic driver resistance.
This last term is the important one to be determined to calculate the device power
dissipation.
The total power dissipated to switch the mosfets results:
P SW = F SW ⋅ ( Q GHS ⋅ PVCC + Q GLS ⋅ VCC )
9/17
Device description and operation
L6743, L6743Q
When designing an application based on L6743, L6743Q it is recommended to take into
consideration the effect of external gate resistors on the power dissipated by the driver.
External gate resistors helps the device to dissipate the switching power since the same
power PSW will be shared between the internal driver impedance and the external resistor
resulting in a general cooling of the device.
Referring to Figure 6, classical mosfet driver can be represented by a push-pull output stage
with two different mosfets: P-MOSFET to drive the external gate high and N-MOSFET to
drive the external gate low (with their own RdsON: Rhi_HS, Rlo_HS, Rhi_LS, Rlo_LS). The
external power mosfet can be represented in this case as a capacitance (CG_HS, CG_LS)
that stores the gate-charge (QG_HS, QG_LS) required by the external power MOSFET to
reach the driving voltage (PVCC for HS and VCC for LS). This capacitance is charged and
discharged at the driver switching frequency FSW.
The total power Psw is dissipated among the resistive components distributed along the
driving path. According to the external Gate resistance and the power-MOSFET intrinsic
gate resistance, the driver dissipates only a portion of Psw as follow:
R loHS
R hiHS
1
2
- + ---------------------------------------------------------------⎞
P SW – HS = --- ⋅ C GHS ⋅ PVCC ⋅ Fsw ⋅ ⎛⎝ --------------------------------------------------------------2
R hiHS + R GateHS + R iHS R loHS + R GateHS + R iHS⎠
R loLS
R hiLS
1
2
- + -------------------------------------------------------------⎞
P SW – LS = --- ⋅ C GLS ⋅ VCC ⋅ Fsw ⋅ ⎛⎝ ------------------------------------------------------------2
R hiLS + R GateLS + R iLS R loLS + R GateLS + R iLS⎠
The total power dissipated from the driver can then be determined as follow:
P = P DC + P SW – HS + P SW – LS
Figure 6.
Equivalent circuit for MOSFET drive
VCC
LGATE
RILS
CGLS
LS MOSFET
RhiHS
RGATELS
GND
LS DRIVER
10/17
BOOT
RloHS
RloLS
RhiLS
VCC
RGATEHS
RIHS
HGATE
PHASE
HS DRIVER
CGHS
HS MOSFET
L6743, L6743Q
5.5
Device description and operation
Layout guidelines
L6743, L6743Q provides driving capability to implement high-current step-down DC-DC
converters.
The first priority when placing components for these applications has to be reserved to the
power section, minimizing the length of each connection and loop as much as possible. To
minimize noise and voltage spikes (also EMI and losses) power connections must be a part
of a power plane and anyway realized by wide and thick copper traces: loop must be anyway
minimized. The critical components, such as the power MOSFETs, must be close one to the
other. However, some space between the power MOSFET is still required to assure good
thermal cooling and airflow.
Traces between the driver and the MOSFETS should be short and wide to minimize the
inductance of the trace so minimizing ringing in the driving signals. Moreover, VIAs count
needs to be minimized to reduce the related parasitic effect.
The use of multi-layer printed circuit board is recommended.
Small signal components and connections to critical nodes of the application as well as
bypass capacitors for the device supply are also important. Locate the bypass capacitor
(VCC, PVCC and BOOT capacitors) close to the device with the shortest possible loop and
use wide copper traces to minimize parasitic inductance.
Systems that do not use Schottky diodes in parallel to the Low-Side MOSFET might show
big negative spikes on the phase pin. This spike can be limited as well as the positive spike
but has an additional consequence: it causes the bootstrap capacitor to be over-charged.
This extra-charge can cause, in the worst case condition of maximum input voltage and
during particular transients, that boot-to-phase voltage overcomes the abs.max.ratings also
causing device failures. It is then suggested in this cases to limit this extra-charge by adding
a small resistor RBOOT in series to the boot capacitor. The use of RBOOT also contributes in
the limitation of the spike present on the BOOT pin.
For heat dissipation, place copper area under the IC. This copper area may be connected
with internal copper layers through several VIAs to improve the thermal conductivity. The
combination of copper pad, copper plane and VIAs under the driver allows the device to
reach its best thermal performances.
Figure 7.
Driver turn-on and turn-off paths
VCC
VCC
BOOT
CGD
RBOOT
RGATE
RINT
RGATE
LGATE
CBOOT
LS DRIVER
GND
CGD
RBOOT
RINT
HGATE
CGS
LS MOSFET
CDS
CBOOT
HS DRIVER
PHASE
CGS
CDS
HS MOSFET
11/17
Device description and operation
Figure 8.
External components placement example
Rboot
BOOT
PWM
EN
VCC
12/17
L6743, L6743Q
1
8
2
7
3
4
Rboot
Cboot
L6743
6
5
UGATE
PHASE
GND
LGATE
BOOT
PWM
EN
VCC
VCC
Cboot
1
10
2
9
3
8
5
6
L6743Q 7
4
UGATE
PHASE
GND
GND
LGATE
L6743, L6743Q
6
Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect. The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com
13/17
Package mechanical data
Table 6.
L6743, L6743Q
SO-8 mechanical data
mm
inch
Dim.
Min
Typ
Max
Min
Typ
Max
A
1.35
1.75
0.053
0.069
A1
0.10
0.25
0.004
0.010
A2
1.10
1.65
0.043
0.065
B
0.33
0.51
0.013
0.020
C
0.19
0.25
0.007
0.010
(1)
4.80
5.00
0.189
0.197
E
3.80
4.00
0.15
0.157
D
e
1.27
0.050
H
5.80
6.20
0.228
0.244
h
0.25
0.50
0.010
0.020
L
0.40
1.27
0.016
0.050
k
0° (min.), 8° (max.)
ddd
0.10
0.004
1. Dimensions D does not include mold flash, protru-sions or gate burrs. Mold flash, potrusions or gate burrs
shall not exceed 0.15mm (.006inch) in total (both side).
Figure 9.
14/17
Package dimensions
L6743, L6743Q
Package mechanical data
Table 7.
DFN10 mechanical data
mm
inch
Dim.
Min
Typ
Max
Min
Typ
Max
0.80
0.90
1.00
0.031
0.035
0.039
A1
0.02
0.05
0.001
0.002
A2
0.70
0.028
A3
0.20
0.008
A
b
0.18
D
D2
2.21
0.007
0.009
2.26
1.49
1.64
2.31
0.087
0.089
0.4
0.091
0.118
1.74
0.059
0.065
0.50
0.3
0.012
0.118
3.00
e
L
0.30
3.00
E
E2
0.23
0.069
0.20
0.5
0.012
0.016
M
0.75
0.295
m
0.25
0.098
0.020
M
m
Figure 10. Package dimensions
15/17
Revision history
7
L6743, L6743Q
Revision history
Table 8.
16/17
Document revision history
Date
Revision
20-Aug-2007
1
Changes
Initial release
L6743, L6743Q
Please Read Carefully:
Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the
right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any
time, without notice.
All ST products are sold pursuant to ST’s terms and conditions of sale.
Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no
liability whatsoever relating to the choice, selection or use of the ST products and services described herein.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this
document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products
or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such
third party products or services or any intellectual property contained therein.
UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED
WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED
WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS
OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE, ST PRODUCTS ARE NOT
RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING
APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY,
DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE
GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER’S OWN RISK.
Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void
any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any
liability of ST.
ST and the ST logo are trademarks or registered trademarks of ST in various countries.
Information in this document supersedes and replaces all information previously supplied.
The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.
© 2007 STMicroelectronics - All rights reserved
STMicroelectronics group of companies
Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America
www.st.com
17/17