STMICROELECTRONICS L9733

L9733
Octal self configuring Low/High side driver
Preliminary Data
Features
■
Eight independently self configuring low/high
drivers
■
Supply voltage from 4.5V to 5.5V
■
RON(max)=0.7Ω @ Tj = 25°C,
RON(max)=1.2Ω @Tj = 125°C
SO-28
■
Minimum current limit of each output 1A
■
Output voltage clamping min. 40V in low side
configuration
■
Output voltage clamping max. -14V in high side
configuration
■
SPI interface for outputs control and for
diagnosis data communication
■
Additional PWM inputs for 3 outputs
■
Independent thermal shutdown for all outputs
Open load, Short to GND, short to Vb,
Overcurrent diagnostics in latched or unlatched
mode for each channel
■
Internal charge pump without need of external
capacitor
■
Controlled SR for reduced EMC
Description
The L9733 IC is a highly flexible monolithic,
medium current, output driver that incorporates 8
outputs that can be used as either internal low or
high side drives in any combination.
PowerSSO-28
Outputs 1-8 are self-configuring as high or low
side drives. Self-configuration allows a user to
connect a high or low side load to any of these
outputs and the L9733 will drive them correctly as
well as provide proper fault mode operation with
no other needed inputs. In additon, Outputs 6, 7 and
8 can be PWM controlled via a external pins (IN6-8).
This device is capable of switching variable load
currents over the ambient range of -40°C to
+125°C. The outputs are MOSFET drivers to
minimize Vdd current requirements. For low side
configured outputs an internal zener clamp from
the drain to gate with a breakdown of 50V
minimum will provide fast turn off of inductive
loads. When a high side configured output is
commanded OFF after having been commanded
ON, the source voltage will go to (VGND - 15V).
An 16 bit SPI input is used to command the 8
output drivers either "On" or "Off", reducing the
I/O port requirement of the microcontroller.
Multiple L9733 can be daisy-chained. In addition
the SPI output indicates latched fault conditions
that may have occurred.
Order codes
August 2006
Part number
Package
Packing
L9733
SO-28
Tube
L9733XP
PowerSSO-28 (Exposed pad)
Tube
Rev 3
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.
1/33
www.st.com
1
Contents
L9733
Contents
1
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3
4
2.1
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2
Absolute maximun ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Electrical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1
DC Characteristics: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.2
AC Characteristics: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.3
SPI Characteristics and timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.1
2/33
4.1.1
Low Side Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.1.2
High Side Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.2
Outputs 1-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.3
Outputs 6-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.4
Drn1-8 Susceptibility To Negative Voltage Transients . . . . . . . . . . . . . . . 18
4.5
Supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.6
5
Configurations for Outputs 1-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.5.1
Main Power Input (Vdd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.5.2
Battery supply (Vbat) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.5.3
Discrete Inputs Voltage Supply (VDO) . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Discrete inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.6.1
Output 6-8 Enable Input (In6, ln7, ln8) . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.6.2
Reset Input (RES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.1
Serial Data Output (DO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.2
Serial Data Input (DI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.3
Chip Select (CS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.4
Serial Clock (SCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.5
Initial Input Command Register & Fault Register SPI Cycle . . . . . . . . . . . 21
5.6
Input Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
L9733
6
7
Contents
Other L9733 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.1
Charge Pump Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.2
Waveshaping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.3
POR Register Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.4
Thermal Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Fault Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.1
7.2
Low Side Configured Output Fault Operation . . . . . . . . . . . . . . . . . . . . . . 24
7.1.1
No latch mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.1.2
Latch mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
High Side Configured Output Fault Operation . . . . . . . . . . . . . . . . . . . . . 26
7.2.1
No latch mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.2.2
Latch mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8
Package informations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
9
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3/33
List of tables
L9733
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
4/33
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Absolute maximun ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Thermal Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
SPI Characteristics and timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Bit Command Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Command Register Logic Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Fault Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Fault Logic Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
L9733
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Pin Connection (Top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Output Turn On/Off Delays and Slew Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
DO Loading for Disable Time Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
SPI Input/Output Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
SPI Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
L9733 Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
L9733 HVAC applicative examplesL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
L9733 Powertrain applicative examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
SO28 Mechanical Data & Package Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
PowerSSO28 Mechanical Data & Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5/33
Pin description
1
L9733
Pin description
Figure 1.
Pin Connection (Top view)
VDD
1
28
VDO
SCLK
2
27
D0
CS
3
26
D1
SRC1
4
25
SRC8
DRN1
5
24
DRN8
DRN2
6
23
DRN7
SRC2
7
22
SRC7
SRC3
8
21
SRC6
DRN3
9
20
DRN6
DRN4
10
19
DRN5
SRC4
11
18
SRC5
IN6
12
17
RES
IN7
13
16
IN8
Vbat
14
15
GND
D06AT544
Table 1.
6/33
Pin Description
N°
Pin
Function
1
VDD
5 Volt Supply Input
2
SCLK
SPI Serial Clock Input
3
CS
4
SRC1
Source Pin of Configurable Driver #1 (0.7 Ω Rdson @+25°)
5
DRN1
Drain Pin of Configurable Driver #1(0.7 Ω Rdson @+25°)
6
DRN2
Drain Pin of Configurable Driver #2 (0.7 Ω Rdson @+25°)
7
SRC2
Source Pin of Configurable Driver #2 (0.7 Ω Rdson @+25°)
8
SRC3
Source Pin of Configurable Driver #3 (0.7 Ω Rdson @+25°)
9
DRN3
Drain Pin of Configurable Driver #3 (0.7 Ω Rdson @+25°)
10
DRN4
Drain Pin of Configurable Driver #4 (0.7 Ω Rdson @+25°)
11
SRC4
Source Pin of Configurable Driver #4 (0.7 Ω Rdson @+25°)
12
IN6
Discrete Input used to PWM Output Driver #6
13
IN7
Discrete Input used to PWM Output Driver #7
14
Vbat
Battery Supply Voltage
15
GND
Analog Ground
16
IN8
Discrete Input used to PWM Output Driver #8
17
RES
Reset Input (Active Low)
18
SRC5
SPI Chip Select (Active Low)
Source Pin of Configurable Driver #5 (0.7 Ω Rdson @+25°)
L9733
Pin description
Table 1.
Pin Description (continued)
N°
Pin
Function
19
DRN5
Drain Pin of Configurable Driver #5 (0.7 Ω Rdson @+25°)
20
DRN6
Drain Pin of Configurable Driver #6 (0.7 Ω Rdson @+25°)
21
SRC6
Source Pin of Configurable Driver #6 (0.7 Ω Rdson @+25°)
22
SRC7
Source Pin of Configurable Driver #7 (0.7 Ω Rdson @+25°)
23
DRN7
Drain Pin of Low Side Driver #7 (0.7 Ω Rdson @+25°)
24
DRN8
Drain Pin of Low Side Driver #8 (0.7 Ω Rdson @+25°)
25
SRC8
Source Pin of Configurable Driver #8 (0.7 Ω Rdson @+25°)
26
DI
SPI Data In
27
DO
SPI Data Out
28
VDO
Microcontroller Logic Interface Voltage
7/33
Operating conditions
L9733
2
Operating conditions
2.1
Maximum ratings
This part may not operate if taken outside the maximum ratings. Once the condition is
returned to within the specified maximum rating or the power is recycled, the part will
recover with no damage or degradation.
Table 2.
Maximum ratings
Symbol
Parameter
Unit
Vdd
Supply Voltage
4.5 to 5.5
V
Vbat
Battery Supply Voltage
4.5 to 18
V
-40 to 150
°C
min 50
VDC
max 800
mA
Tj
Thermal Junction Temperature Range
Snubbing Volatage of DRN1-8
IO
2.2
Value
Output Current 1-8
Absolute maximun ratings
This part may be irreparably damaged if taken outside the specified Absolute Maximum
Ratings. Operation outside the Absolute Maximum Ratings may also cause a decrease in
reliability.
Table 3.
Absolute maximun ratings
Symbol
Parameter
Unit
VDD
Supply Voltage
-0.3 to 7
V
Vbat
Supply Voltage
-0.3 to 40
V
CS,DI,DO,SCLK,EN,IN6,IN7,IN8,VDO
-0.3 to 7.0
V
SRC 1-8
-24 to 40
VDC
DRN1-8
-0.3 to 60
VDC
2.5
A
IOL
Current Limit of Output 1-8 ( -40°C)
IOP
OverCurrent protection at Output 1-8 ( -40°C)
3
A
Maximum Clamping Energy
20
mj
±2 vs. GND
kV
Typ
Max
Unit
ESD
Table 4.
Human Body Model
Thermal Data
Symbol
8/33
Value
Parameter
Min
Tamb
Operating Ambient Temperature
-40
125
°C
Tstg
StorageTemperature
-50
150
°C
150
°C
200
°C
Tj
Maximum Operating Junction Temperature
Rth
Thermal Shut-down Temperature
151
175
L9733
Operating conditions
Table 4.
Symbol
Rth-hys
Thermal Data
Parameter
Thermal Shut-down Temperature Hysteresis
Min
Typ
Max
Unit
7
10
25
°C
RTh j-amb
Thermal resistance junction to ambient
for SO28 (1)
for PowerSSO28 (2)
55
24
°C/W
°C/W
RTh j-case
Thermal resistance junction to case (PowerSSO28)
3
°C/W
RTh j-pins
Thermal resistance junction to pins (SO28)
20
°C/W
1. With 6cm2 on board heat sink area.
2. With 2s2p PCB thermally enhanced.
9/33
Electrical performance characteristics
3
L9733
Electrical performance characteristics
These are the electrical capabilities this part was designed to meet. It is required that every
part meet these characteristics.
3.1
DC Characteristics:
Tamb = -40 to 125°C, Vdd = 4.5 to 5.5 Vdc, Vbat = 4.5 to 18Vdc (high side configuration),
unless otherwise specified.
Table 5.
Symbol
IN6vih
DC Characteristics
Parameter
Conditions
In6 = 0 VDC
In6 = VDO
In7 = VDO
In8 = VDO
DOoh
10/33
µA
0.7vdo
V
V
|10|
µA
100
µA
0.7vdo
V
V
|10|
µA
10
100
µA
0.7vdo
V
CS Input Voltage
0.3vdo
CS = VDO
V
|10|
µA
100
µA
0.7vdo
V
CS Input Current
CS = 0 VDC
10
SCLK Input Voltage
0.3vdo
SCLK = VDO
V
|10|
µA
100
µA
0.7vdo
V
SCLK Input Current
SCLK = 0 VDC
10
DI Input Voltage
0.3vdo
DI = VDO
V
|10|
µA
100
µA
0.4
V
DI Input Current
IDIil
DOol
10
In8 = 0 VDC
DIil
IDIih
100
IN8 Input Current
ISCLKil
DIih
µA
0.3vdo
SCLKil
ISCLKih
|10|
IN8 Input Voltage
ICSil
SCLKih
10
In7 = 0 VDC
CSil
ICSih
V
IN7 Input Current
IIN8ih
CSih
V
0.3vdo
IN8vil
IIN8il
0.7vdo
IN7 Input Voltage Voltage
IIN7ih
IN8vih
Units
IN6 Input Current
IN7vil
IIN7il
Max
0.3vdo
IIN6ih
IN7vih
Typ
IN6 Input Voltage
IN6vil
IIN6il
Min
DI = 0 VDC
DO Output Voltages
10
IDO = 2.5 mA
IDO = -2.5 mA
vdo-0.6
V
L9733
Table 5.
Symbol
Symbol
IDOzol
Electrical performance characteristics
DC Characteristics (continued)
Parameter
Parameter
Min
Typ
Max
Units
Min
Typ
Max
Units
DO = 0 VDC
|10|
µA
DO = VDO
|10|
µA
0.7vdo
V
Conditions
DO Tri-State Currents
IDOzoh
RESih
Conditions
RES Input Voltage
RESil
0.3vdo
V
100
µA
RES = VDO
|10|
µA
Vbat Sleep Current
VDD = SRC1-8 = 0VDC
DRN1-DRN8=18VDC , Vb. Sum
currents(Tamb > 0°C)
(Tamb @ -40°C)
10
3
µA
µA
Ivbat
Vbat current
VDD=5V
All Outputs Commanded On
15
mA
IVDD
Max VDD Current
All Outputs Commanded On
8.5
mA
IVDD
Min VDD Current
All Outputs Commanded Off
IDRN1lk IDRN8lk
DRN1 - DRN8
Leakage Currents
(Low Side)
VDD = 0 VDC : SRC1-8 = 0 VDC
DRN1- DRN8 = 16 VDC
DRN1- DRN8 = 40 VDC
5
10
µA
µA
ISRC1lk ISRC8lk.
SRC1 – SRC8
Leakage Currents (High
Side)
VDD = 0 VDC : SRC1-8 = 0 VDC
DRN1- 8 = 16 V
DRN1- 8 = 40 VDC
-5
-10
µA
µA
IDrn1-8sink
DRN1 – DRN8 Sink
Current (Low Side)
SRC1-8 = GND DI = AC00h
Rload ≤ 11KΩ
Rload ≤ 200KΩ
10
120
100
280
µA
µA
Open Load Detection
Resistance
VBAT>=9V
11
200
KΩ
DRN1-DRN8 = GND
-10
-100
µA
10
100
µA
-18
-100
µA
SRC1- 8 = GND, DI = AC00h
DRN1- DRN8 = Open
Vdd=4.9 to 5.1 Vdc
2.7
3.1
V
SRC1- 8 = GND, DI = AC00h
DRN1- DRN8 = Open
2.5
3.5
V
2.0
2.8
V
IRESil
RES = 0 VDC
IRESih
Islp
RDRN1-8
IDrn1-8source Source Current
Isrc1-8sink
Isrc1-8source
VDrn1-8open
Vsrc1-8open
10
RES Input Current
DRN1- 8 = Vb, DI = AC00h
SRC1 – SRC8 Sink/Source SCR1- 8 = Vb
Current High Side)
SCR1- 8 = GND
DRN1 – DRN8 Open Load
Voltage (Low Side)
SRC1 – SRC8 Open Load DRN1-8 = Vb, DI = AC00h
Voltage (High Side) DRN1 SCR1-8 = open
DRN8
0.5
mA
11/33
Electrical performance characteristics
Table 5.
Symbol
IDRN1limit IDRN8limit
Symbol
IDRN1OVCIDRN8OVC
ISRC1limitISRC8limit
ISRC1OVCISRC8OVC
L9733
DC Characteristics (continued)
Parameter
Conditions
Min
Typ
Max
Units
2.2
2.5
A
A
Max
Units
DRN1 - DRN8
Current Limits (Low Side)
DI = ACFFh, DI = AAFFh
SRC1 – SRC8 = 0 VDC
DRN1 - DRN8 = 4.5 - 16 VDC
(Tamb > 0°C)
(Tamb @ -40°C )
Parameter
Conditions
DRN1 - DRN8 Overcurrent
threshold (Low Side)
DI = AC00h, DI = AA00h SRC1 –
SRC8 = 0 VDC
DRN1 - DRN8 = 4.5 - 16 VDC
(Tamb > 0°C)
(Tamb - 40°C)
1
1
2.7
3
A
A
SRC1 – SRC8 Current
Limits (High Side)
DI = ACFFh, DI = AAFFh
DRN1 - DRN8 = Vb
SRC1 – SRC8 = GND
(Tamb > 0°C)
(Tamb - 40°C)
1
1
2.2
2.5
A
A
SRC1 – SRC8
DI = AC00h, DI = AA00h
Overcurrent threshold
(High Side)
DRN1 - DRN8 = Vbat
SRC1 – SRC8 = GND
(Tamb > 0°C)
(Tamb - 40°C)
1
1
2.7
3
A
A
1
1
Min
Typ
DRN1 - DRN8
DRN1Cl+ DRN8Cl+
DRN1 - DRN8
DI = AC00h
Clamp Voltages (Low Side) SRC1-8 = GND, IDRN1-8 = 350 mA
50
60
V
SRC1Cl+SRC8Cl+
SRC1 – SRC8
DI = AC00h
Clamp Voltages (High Side) DRN1-8 = Vbat, ISRC1-8 = -350 mA
-24
-14
V
DRN1 - DRN8
DI = AC00h
VDrn1-8open
- DRN18VthGND
Short to GND threshold
distance from open load
voltage (Low side)
SRC1 – SRC8 = GND:
Decrease Drn1 - Drn8 until Faults
are ”Set”
0.3
0.7
V
DRN18VthVbatVDrn1-8open
DRN1 - DRN8
Short to Vbat threshold
distance from open load
voltage (Low Side)
DI = AC00h
SRC1 – SRC8 = GND : Increase
Drn1 - Drn8 until Faults are ”Not
Set”
0.3
0.7
V
VDrn1-8open
- SRC18VthGND
SRC1 - SRC8
Short to GND threshold
distance from open load
voltage (High Side)
DI = AC00h
Drn1 – Drn8 = Vb: Decrease SRC1
- SRC8 until Faults are ”Not Set”
0.2
0.6
V
SRC18VthVbatVDrn1-8open
SRC1 – SRC8
Short to Vbat threshold
distance from open load
voltage (High Side)
DI = AC00h
Drn1 – Drn8 = Vbat: Increase
SCR1 - SCR8 until Faults are ”
Set”
0.2
0.6
V
12/33
L9733
Electrical performance characteristics
Table 5.
DC Characteristics (continued)
Symbol
Parameter
On Resistance
RdsonDrn1-8
(Drn to SRC1-8)
Drn1-8ther
(1)
Thermal Shutdown
Temperature
Drn1-8hyst(1) Hysteresis
Conditions
Min
Max
Units
@ +125°C @ IDRN = 350mA
1.2
W
@ +25o C @ IDRN = 350mA
0.7
W
@ -40°C @ IDRN = 350mA
0.5
W
151
200
°C
5
15
°C
DI = ACFFh, IDrn1-8 = 1 mA,
SRC1 – SRC8 = GND, Increase
temperature until Drn1 - Drn8 > 2
VDC, Verify DO Bits 0-15 are ”Set”
Drn1 - Drn8 < 2 VDC
Typ
1. Design Information, Not Tested.
3.2
AC Characteristics:
Tamb= -40 to 125°C, Vdd = 4.5 to 5.5 Vdc, Vbat = 4.5 to 18Vdc, unless otherwise specified
Table 6.
Symbol
AC Characteristics
Parameter
Conditions
Min
Typ
Max
Units
TfiltDRN1-8
DRN1 - DRN8
Open load & short to
GND filter time (Low
Side)
(Latch mode)
DI = AC00h, DI = A3FFh
SRC1 – SRC8 = GND
300
900
µs
TfiltSRC1-8
SRC1 - SRC8
Open load & short to
Vbatfilter time (High
Side)
(Latch mode)
DI = AC00h, DI = A3FFh
DRN1 – DRN8 = Vb
300
900
µs
TdelDRN1-8
DRN1 - DRN8
Overcurrent Switch Off
Delay
(Low Side)
DI = ACFFh, DI = AA00h
SRC1 – SRC8 = GND
10
60
µs
TdelSRC1-8
SRC1 - SRC8
Overcurrent Switch Off
Delay
(High Side)
DI = ACFFh, DI = AA00h
DRN1 – DRN8 = Vb
10
60
µs
Restart time after
overcurrent switch off
Time (Int)
DI = ACFFh, DI = AA00h
120
450
ms
Drn1-8htol
Slew Rate
Turn On
Outputs loaded per Figure 5
See Figure 2
0.65
1.95
V/µs
Drn1-8ltoh
Turn Off (Low Side)
See Figure 2
0.5
1.5
V/µs
Tres
13/33
Electrical performance characteristics
Table 6.
Symbol
L9733
AC Characteristics (continued)
Parameter
Conditions
SRC1-8htol
Slew Rate
Turn On
SRC1-8ltoh
Turn Off (High Side)
Drn1-8tondly
Delay time
Turn On
Drn1-8toffdly
Turn Off (Low Side)
SRC1-8tondly
Delay time
Turn On
Min
Outputs loaded per Figure 5
See Figure 2
See Figure 2
Outputs loaded per Figure 5
See Figure 2
See Figure 2
Outputs loaded per Figure 5
See Figure 2
SRC1-8toffdly Turn Off (High Side)
See Figure 2
Typ
Max
Units
0.65
1.95
V/µs
0.5
1.5
V/µs
2
20
µs
10
100
µs
Figure 2
2
20
µs
10
100
µs
Drn1-8offon
Delay Delta
Drn1-8toffdly - Drn1-8tondly
10
60
µs
SRC1-8offon
Delay Delta
SRC1-8toffdly - SRC1-8tondly
10
60
µs
Figure 2.
Output Turn On/Off Delays and Slew Rates
IN 6- 8
LSD
IN 6-8
90%
DRN1-8
20%
DRN1-8 20%
DRN1-8ltoh
DRN1-8htol
DRN1-8toffdly
DRN1-8tondly
HSD
90%
80%
SRC1-8
10%
80%
SRC1-8
SRC1-8htol
SRC1-8ltoh
SRC1-8tondly
SRC1-8toffdly
IN1- 5 are available on wafer only
14/33
10%
L9733
3.3
Electrical performance characteristics
SPI Characteristics and timings
Tamb= -40 to 125°C, Vdd = 4.5 to 5.5 Vdc, Vbat = 4.5 to 18Vdc, unless otherwise specified
Table 7.
SPI Characteristics and timings
Symbol
DINCin
Parameter
Conditions
Min
Typ
Max
Units
20
pF
20
pF
70
ns
70
ns
350
ns
Input Capacitance
SCLKCin
DOrise
Output Data (DO)
Rise Time
50 pF from DO to Ground
See Figure 4
DOfall
Output Data (DO)
Fall Time
See Figure 4
DOa
Access Time
See Figure 5
DOsum
Set Up Time
See Figure 5
20
ns
DOhm
Hold Time
See Figure 5
10
ns
DOdis
Output Data (DO)
Disable Time
No Capacitor on DO, See Figure 4
tthFilt
Filter Time
All Fault bits are “Set”
SCLKwid
SCLK Width
Figure
5
5
400
ns
20
µs
See Figure 4, @ fSCLK =
5.4MHz(1)
185
ns
5.4MHz(1)
58
ns
58
ns
SCLKlm
SCLK Low Time
See Figure 4, @ fSCLK =
SCLKhm
SCLK High Time
See Figure 4, @ fSCLK = 5.4MHz(1)
SCLK Rise Time
See Figure 4, @ fSCLK =
5.4MHz(1)
21
ns
SCLK Fall Time
See Figure 4, @ fSCLK =
5.4MHz(1)
21
ns
CSrise
Channel Select (CS)
Rise Time
See Figure 4(1)
100
ns
CSfall
Channel Select (CS)
Fall Time
See Figure 4(1)
100
ns
CSlead
Channel Select (CS)
Lead Time
See Figure 5(1)
165
CSlag
Channel Select (CS)
Lag Time
See Figure 5(1)
50
DIrise
Input Data (DI)
Rise Time
See Figure 4, @ fSCLK = 5.4MHz(1)
30
ns
DIfall
Input Data (DI)
Fall Time
See Figure 4, 5,
@ fSCLK = 5.4MHz(1)
30
ns
DIsus
Input Data (DI)
Set-up Time
See Figure 5, @ fSCLK = 5.4MHz(1)
15
DIhs
Input Data (DI)
Hold Time
See Figure 5, @ fSCLK = 5.4MHz(1)
10
SCLKrise
SCLKfall
1. Guaranteed by design
15/33
Electrical performance characteristics
Figure 3.
L9733
DO Loading for Disable Time Measurement
+5 V
Vcc
4.0 V
1kΩ
DO
DOdis
1.0 V
DO
0V
1kΩ
CS
Figure 4.
SPI Input/Output Slew Rate
SCLKwid
SCLKlm
SCLKhm
90%
SCLKrise
SCLK
10%
90%
CSrise
90%
CS
CSfall
10%
90%
DOrise
DIrise
DI
DIfall
10%
DO
10%
Figure 5.
SCLKfall
DOfall
SPI Timing Diagram
CS
CSlead
CSlag
SCLK
DOa
DOhm
DOsum
FAULT LSB
FAULT MSB
DI LSB
DI MSB
DIsus
DIhs
16/33
DOdis
DO
DI
DI
L9733
4
Functional description
Functional description
L9733 integrates 8 self-configuring outputs (OUT1-8) which are able to drive either
incandescent lamps, inductive loads (non-pwm'd, in pwm is necessary an external diode to
reduce flyback power dissipation), or resistive loads biased to Vbat ( low side configuration)
or to GND (high side configuration). These outputs can be enabled and disabled via the SPI
bus. Each of these outputs has a short circuit protection (with 0.8-2.4 Amps threshold)
selectable via SPI bus between a filtered switching OFF overcurrent protection or a linear
current limitation (default condition after power ON is switching OFF protection enabled).
An over-temperature protection as described in Section 2.1 is available for each outputs.
When a high side configured output is commanded OFF after having been commanded ON,
the source voltage will go to (VGND - 15V). This is due to the design of the circuitry and the
transconductance of the MOSFET. When a low side configured output is commanded OFF
after having been commanded ON, the output voltage will rise to the internal zener clamp
voltage (50 VDC minimum) due to the flyback of the inductive load.
Outputs 1-8 are able to drive any combination of inductive loads or lamps at one time.
Inductive loads for the L9733 can range from 35mH to a maximum of 325mH. The
recommended worst-case solenoid loads (at -40°C) are calculated using a minimum
resistance of 40Ω for each output. The maximum single pulse inductive load energy the
L9733 outputs is able to be safely handle is 20mJ at -40°C to 125°C (Worst-case load of
325mH & 40Ω).
4.1
Configurations for Outputs 1-8
The drain and source pins for each Output must be connected in one of the two following
configurations (see Figure 6).
4.1.1
Low Side Drivers
When any combination of Outputs 1-8 are connected in a low side drive configuration the
source of the applicable Output (Src1-8) shall be connected to ground. The drain of the
applicable Output (Drn1-8) shall be connected to the low side of the load.
4.1.2
High Side Drivers
When any combination of Outputs 1-8 are connected in a high side drive configuration the
Drain of the applicable Output (Drn1-8) shall be connected to Vbat. The source of the
applicable Output (Src1-8) shall be connected to the high side of the load.
4.2
Outputs 1-5
These five outputs can be used as either high or low side drives. The room temperature
Rdson of these outputs is 0.7Ω. A current limited (100µA max) voltage generator is
connected to Src 1-5 for open load and short to GND detection when a low side configured
output is commanded OFF. Another current limited (100µA max if VDrn 1-5 > 60%Vbat,
280µA max if VDrn 1-5 < 60%Vbat) voltage generator is connected to Drn 1-5 for open load
and short to Vbat detection when a high side configured output is commanded OFF.
Drain pins of Outputs 1-5 (Drn1-5) are connected to the drains of the N channel MOSFET
17/33
Functional description
L9733
transistors. Source pins of Outputs 1-5 (Src1-5) are connected to the sources of the N
channel MOSFET transistors.
4.3
Outputs 6-8
These three self-configuring outputs can be used to drive either high or low side loads. In
addition to being controlled by the SPI BUS these outputs can also be enabled and disabled
via the IN6 & IN7& IN8 inputs. The IN6, IN7 and IN8 inputs are logically or'd with the SPI
commands to allow either the IN6 & IN7 & IN8 inputs or the SPI commands to activate these
outputs. The use of the IN6 & IN7 & IN8 pins for PWM control on these outputs should only
be done with non-inductive loads if an external flyback diode is not present. The room
temperature Rdson of these four outputs is 0.7Ω. A current limited (100µA max) voltage
generator is connected to Src 6-8 for open load and short to GND detection when a low side
configured output is commanded OFF. Another current limited (100µA max if VDrn 6-8 >
60%Vbat, 280µA max if VDrn 6-8 < 60%Vbat) voltage generator is connected to Drn 6-8 for
open load and short to Vbat detection when a high side configured output is commanded
OFF.
Drain pins of Outputs 6-8 (Drn6-8) are connected to the drains of the N channel MOSFET
transistors. Source pins of Outputs 6-8 (Src6-8) are connected to the sources of the N
channel MOSFET transistors.
4.4
Drn1-8 Susceptibility To Negative Voltage Transients
All outputs connected in the low side configuration must have a ceramic chip capacitor of
0.01µF to 0.1µF connected from drain to ground. This is needed to prevent potential
problems with the device operation due to the presence of fast negative transient(s) on the
drain(s) of the device. Adequate de-coupling capacitors from the Drain (VBAT) to ground
shall be provided for high side configured outputs.
4.5
Supply pins
4.5.1
Main Power Input (Vdd)
An external +5.0 ±0.5 VDC supply provided from an external source is the primary power
source to the L9733. This supply is used as the power source for all of its internal logic
circuitry and other miscellaneous functions.
4.5.2
Battery supply (Vbat)
This input is the supply for the on board charge pump. This input shall be connected directly
to battery. If this input is not connected to the same supply, without additional voltage drops,
of the drains of any high side connected outputs, then the Rdson of that given output will be
higher than the specified maximum.
4.5.3
Discrete Inputs Voltage Supply (VDO)
This pin is used to supply the discrete input stages of L9733 and must be connected to the
same voltage used to supply the peripherals of the processor interfaced to L9733.
18/33
L9733
Functional description
4.6
Discrete inputs
4.6.1
Output 6-8 Enable Input (In6, ln7, ln8)
This input allows Output 6 (or Output 7, or Output 8) to be enabled via this external pin
without the use of the SPI. The SPI command and the In6-7 input are logically or'd together.
A logic "1" on this input (In6, ln7 or ln8) will enable this output no matter what the status of
the SPI command register. A logic "0" on this input will disable this output if the SPI
command register is not commanding this output on. This pins (In6, ln7 or ln8) can be left
"open" if the internal output device is being controlled only via the SPI. This input has a
nominal 100kΩ resistor connected from this pin to ground, which will pull this pin to ground if
an open circuit condition occur. This input is ideally suited for non-inductive loads that are
pulse width modulated (PWM'd). This allows PWM control without the use of the SPI inputs.
4.6.2
Reset Input (RES)
When this input goes low it resets all the internal registers and switches off all the output
stages. This input has a nominal 100 kΩ resistor connected from this pin to VDD, which will
pull this pin to VDD if an open circuit condition occur.
19/33
Serial Peripheral Interface (SPI)
5
L9733
Serial Peripheral Interface (SPI)
The L9733 has a serial peripheral interface consisting of Serial Clock (SCLK), Data Out
(DO), Data In (DI), and Chip Select (CS). All outputs will be controlled via the SPI. The input
pins CS, SCLK, and DI, thanks to VDO pin, have level input voltages allowing proper
operation from microcontrollers that are using 5.0 or 3.3 volts for their Vdd supply. The
design of the L9733 allows a "daisy-chaining" of multiple L9733's to further reduce the need
for controller pins.
5.1
Serial Data Output (DO)
This output pin is in a tri-state condition when CS is a logic '1'. When CS is a logic '0', this
pin transmits 16 bits of data from the fault register to the digital controller. After the first 16
bits of DO fault data are transmitted (after a CS transition from a logic '1' to a logic '0'), then
the DO output sequentially transmits the digital data that was just received (16 SCLK cycles
earlier) on the DI pin. The DO output continues to transmit the 16 SCLK delayed bit data
from the DI input until CS eventually transitions from a logic '0' to a logic '1'. DO data
changes state 10 nsec or later, after the falling edge of SCLK. The LSB is the first bit of the
byte transmitted on DO and the MSB is the last bit of the byte transmitted on DO, once CS
transitions from a logic '1' to a logic '0'.
5.2
Serial Data Input (DI)
This input takes data from the digital controller while CS is low. The L9733 accepts an 16 bit
byte to command the outputs on or off. The L9733 also serially wraps around the DI input
bits to the DO output after the DO output transmits its 16 fault flag bits. The LSB is the first
bit of each byte received on DI and the MSB is the last bit of each byte received on DI, once
CS transitions from a logic '1' to a logic '0'. The last 4 bits (b15-b12) of the first 16 bit byte
are used as key-word. The 4 bits (b11-b8) of the first 16 bits byte are used to select writing
mode between OUT8-1 status and diagnosis operating mode . The DI input has a nominal
100 kΩ resistor connected from this pin to the VDO pin, which pulls this pin to VDO if an
open circuit condition occurs.
5.3
Chip Select (CS)
This is the chip select input pin. On the falling edge of CS, the DO pin is released from tristate mode. While CS is low, register data are shifted in and shifted out the DI pin and DO
pin, respectively, on each subsequent SCLK. On the rising edge of CS, the DO pin is tristated and the fault register is "Cleared" if a valid DI byte has been received. A valid DI byte
is defined as such:
–
1 A multiple of 16 bits was received.
–
2 A valid key-word was received
The fault data is not cleared unless all of the 2 previous conditions have been met. The CS
input has a nominal 100kΩ resistor connected from this pin to the VDO pin, which pulls this
pin to VDO if an open circuit condition occurs.
20/33
L9733
Serial Peripheral Interface (SPI)
5.4
Serial Clock (SCLK)
This is the clock signal input for synchronization of serial data transfer. DI data is shifted into
the DI input on the rising edge of SCLK and DO data changes on the falling edge of SCLK.
The SCLK input has a nominal 100kΩ resistor connected from this pin to the VDO pin,
which pulls this pin to VDO if an open circuit condition occurs.
5.5
Initial Input Command Register & Fault Register SPI Cycle
After initial application of Vdd to the L9733, the input command register and the fault register
are "Cleared" by the POR circuitry and that means that the default condition for the output
status is Off , the default diagnostic mode is No Latch and the switching OFF overcurrent
protection is enable. During the initial SPI cycle, and all subsequent cycles, valid fault data
will be clocked out of DO (fault bits).
5.6
Input Command Register
An input byte (16 bits) is routed to the Command Register. The content of this Command
Register is given in table 9. Additional DI data will continue to be wrapped around to the DO
pin. If CS should happen to go high before complete reception of the current byte, this just
transmitted byte shall be ignored (invalid).
Table 8.
Bit Command Register Definition
Key Word
Writing Mode: Output
Output Status
MSB
LSB
1
0
1
0
1
1
0
0
b15
b14
b13
b12
b11
b10
b9
b8
Key Word
OUT 8 OUT 7 OUT 6 OUT 5 OUT 4 OUT 3 OUT 2 OUT 1
b7
b6
b5
Writing Mode: Diag
b4
b3
b2
b1
b0
Driver Diag Mode
MSB
LSB
1
0
1
0
0
0
1
1
b15
b14
b13
b12
b11
b10
b9
b8
Key Word
Diag 8 Diag 7 Diag 6 Diag 5 Diag 4 Diag 3 Diag 2 Diag 1
b7
b6
Writing Mode: Protect
b5
b4
b3
b2
b1
b0
Driver Overcurrent Protection
MSB
LSB
1
0
1
0
1
0
1
0
b15
b14
b13
b12
b11
b10
b9
b8
Ilim 8 Ilim 7 Ilim 6 Ilim 5 Ilim 4 Ilim 3 Ilim 2
b7
b6
b5
b4
b3
b2
b1
Ilim 1
b0
21/33
Serial Peripheral Interface (SPI)
Table 9.
22/33
L9733
Command Register Logic Definition
BIT
STATE
STATUS
Writing Mode
b0-b7
0
OUT1 - OUT8 are Commanded Off
Output
b0-b7
1
OUT1 - OUT8 are Commanded On
Output
b0-b7
0
OUT1 - OUT8 Diagnostic is No Latch Mode
Diag
b0-b7
1
OUT1 - OUT8 Diagnostic is Latch Mode
Diag
b0-b7
0
OUT1 - OUT8 Switching OFF Overcurrent Protection
Protection
b0-b7
1
OUT1 - OUT8 Linear Overcurrent Protection
Protection
L9733
Other L9733 Features
6
Other L9733 Features
6.1
Charge Pump Usage
In order to provide low Rdson values when connected in a high side configuration, a charge
pump to drive the internal gate voltage(s) above Vbat is implemented. The charge pump
used on the L9733 doesn't need external capacitor. The L9733 uses a common charge
pump and oscillator for all the 8 configurable output channels. The charge pump uses the
Vbat supply connected directly to the Vb pin. The normal range of the Vbat voltage is 10 to
18V18V. However, the L9733 is functional with Vbat voltages as low as 4.5V DC with
eventually a degradation of Rdson.
The frequency range of this charge pump is from 3.6 to to 7.6 MHz. The frequency is above
1.8MHz in order to be above the AM radio band and below 8.0MHz so that harmonics do not
get within the FM radio band.
6.2
Waveshaping
Both the turn on and the turn off slew rates on all outputs (OUT1-8) are limited to between
10µs and 100µs for both rise and fall times (10 to 90%, and vice versa), to reduce conducted
EMC energy in the vehicle's wiring harness. The characteristics of the turn-on and turn-off
voltage is linear, with no discontinuities, during the output driver state transition.
6.3
POR Register Initialization
When the L9733 wakes up, the Vdd supply to the L9733 is allowed from 0 to 5 VDC in 0.3 to
3ms. The L9733 has a POR circuit, which monitors the Vdd voltage. When the Vdd voltage
reaches an internal threshold, and remains above this trip level for at least 5 to 20µs, the
Command and Fault registers are "cleared". Before Vdd reaches this trip level, none of the
eight outputs are allowed to momentarily glitch on.
6.4
Thermal Shutdown
Each of the eight outputs has independent thermal protection circuitry that disables each
output driver once the local N-Channel MOSFET's device temperature reaches between
+151 and +200°C. A filter is present to validate the thermal fault (5µs to 20µs). There is a 5
to 15°C hysteresis between the enable and disable temperature levels. The faulted channel
will periodically turn off and on until the fault condition is cleared, the ambient temperature is
decreased sufficiently or the output is commanded off. If a thermal shutdown, of one or
more output drivers, is active during the falling edge of the chip select (CS) signal all the bits
of the Fault Register are "setted" to "1" (thermal shutdown is not latched and could be read
only in the moment it is present). The thermal fault is cleared on the rising edge of Chip
Select if a valid DI byte was received.
Note:
Due to the design of the L9733 each output's thermal limit "may not" be truly independent to
the extent that if one output is shorted, it may impact the operation of other outputs (due to
lateral heating in the die).
23/33
Fault Operation
7
L9733
Fault Operation
The fault diagnostic capability consists of one internal 16 bits shift register and 2 bits are
used for each output. The diagnostic information are: no fault present, overcurrent, open
load and short circuit.
All of the faults will be cleared on the rising edge of Chip Select if a valid DI byte was
received
Table 10.
Fault Register Definition
OUT 8
OUT 7
OUT6
OUT5
OUT4
OUT3
OUT2
OUT1
MSB
LSB
D1
D0
D1
D0
D1
D0
D1
D0
D1
D0
D1
D0
D1
D0
D1
D0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
Table 11.
Fault Logic Definition
D1
D0
FAULT STATUS
0
0
No fault is present
0
1
Open load
1
0
Short circuit to GND (low side) or Short circuit to Vbat(high side)
1
1
Overcurrent
If all the bits b0-b15 of the fault register have value '1' it means that a thermal fault, at least
on one of the eight independent Outputs, occurred.
7.1
Low Side Configured Output Fault Operation
The diagnostic circuitry verifies for the low side configured output the following condition:
Normal operation, open load, short circuit to GND and overcurrent (only if the switching OFF
protection, selectable for each channel via SPI bus, is active).
The diagnostic circuitry operates in two different modes, selected for each channel by SPI:
no latch mode and latch mode. The fault priority is overcurrent and then open load or short
circuit to GND, this means that if an overcurrent occurs the fault register is always
overwritten and following open load or short to GND faults that happen before that the
register is cleared will be ignored.
7.1.1
No latch mode
This diagnostic operating mode doesn't latch open load and short to GND faults.
1.
24/33
Open load
The diagnostic of open load is detected only in OFF condition sensing the Drn1-8
output voltage. This fault is detected on the falling edge of the CS input if the power
drain voltage is inside the voltage range limited by the two thresholds Vth_Vbat and
L9733
Fault Operation
Vth_GND. An internal current limited voltage regulator fixes the drain voltage inside
the described range when no load is connected.
2.
Short Circuit to GND
The diagnostic of short circuit to GND is detected only in OFF condition sensing the
Drn1-8 output voltage. This fault is detected on the falling edge of the CS input if the
power drain voltage is lower than the Vth_GND threshold.
3.
Overcurrent
The diagnostic of overcurrent is detected only in ON condition, if the switching OFF
protection of the channel is enabled (default), sensing the current level of the output
power transistor. If the output current has been above the short threshold Iovc for the
filtering time Tdel the output power is switched off and at the same time an overcurrent
fault is written in the fault register.
There are three possibilities to restart one output after the fault has occourred:
–
Automatically after a time Tres
–
On the rising edge of CS if two valid DI byte has been received and first the Output
Status in the command register is written with logic '0' and then with a logic “1” in
the following SPI cycle
–
On the rising edge (low to high transition) at the corresponding parallel input pin
(only for Outputs 6-8).
–
If the switching OFF protection is not active the On phase overcurrent protection is
a linear current limitation and no diagnosis is available.
The use of the IN6-8 pins for PWM control on the outputs 6-8 could generates bad
diagnostic behavior when the falling edge of CS happens a short time after the falling edge
of IN6-8 during the power MOS transient. Software filtering may be needed to ignore fault
signals during Drn6-8 transient after falling edge of IN6-8.
7.1.2
Latch mode
This diagnostic operating mode latches all faults when they happen.
1.
Open load
The diagnostic of open load is detected only in OFF condition sensing the Drn1-8
output voltage. This fault is detected if the power drain voltage is inside the voltage
range limited by the two thresholds Vth_Vbat and Vth_GND for the filtering time Tfilt.
An internal current limited voltage regulator fixes the drain voltage inside the described
range when no load is connected.
2.
Short Circuit to GND
The diagnostic of short circuit to GND is detected only in OFF condition sensing the
Drn1-8 output voltage. This fault is detected if the power drain voltage is lower than the
Vth_GND threshold for the filtering time Tfilt.
3.
Overcurrent
The diagnostic of overcurrent is detected only in ON condition, if the switching OFF
protection of the channel is enabled (default), sensing the current level of the output
power transistor. If the output current has been above the short threshold Iovc for the
filtering time Tdel the output power is switched off and at the same time an overcurrent
fault is written in the fault register. If the switching OFF protection is not active the On
25/33
Fault Operation
L9733
phase overcurrent protection is a linear current limitation and no diagnosis is available.
There are three possibilities to restart one output after the fault has occourred:
7.2
–
Automatically after a time Tres
–
On the rising edge of CS if two valid DI byte has been received and first the Output
Status in the command register is written with logic '0' and then with a logic “1” in
the following SPI cycle
–
On the rising edge (low to high transition) at the corresponding parallel input pin
(only for Outputs 6-8).
If the power MOS transient, after a switching-off command, is longer than Tdel
filtering time, a bad diagnostic behavior happens and software filtering may be
needed.
High Side Configured Output Fault Operation
The diagnostic circuitry verifies for the high side configured output the following condition:
Normal operation, open load, short circuit to Vbat and overcurrent (only if the switching OFF
protection, selectable for each channel via SPI bus, is active).
The diagnostic circuitry operates in two different modes, selected for each channel by SPI:
no latch mode and latch mode. The fault priority is overcurrent and then open load or short
circuit to Vb, this means that if an overcurrent occurs the fault register is always overwritten
and following open load or short to Vbat faults that happen before that the register is cleared
will be ignored.
7.2.1
No latch mode
This diagnostic operating mode doesn't latch open load and short to Vbat faults.
26/33
1.
Open load
The diagnostic of open load is detected only in OFF condition sensing the Src1-8
output voltage. This fault is detected on the falling edge of the CS input if the power
drain voltage is inside the voltage range limited by the two thresholds Vth_Vbat and
Vth_GND. An internal current limited voltage regulator fixes the drain voltage inside the
described range when no load is connected.
2.
Short Circuit to Vb
The diagnostic of short circuit to Vbat is detected only in OFF condition sensing the
Src1-8 output voltage. This fault is detected on the falling edge of the CS input if the
power drain voltage is higher than the Vth_Vbat threshold.
3.
Overcurrent
The diagnostic of overcurrent is detected only in ON condition, if the switching OFF
protection of the channel is enabled (default),sensing the current level of the output
power transistor. If the output current has been above the short threshold Iovc for the
filtering time Tdel the output power is switched off and at the same time an overcurrent
L9733
Fault Operation
fault is written in the fault register.
There are three possibilities to restart one output after the fault has occourred:
7.2.2
–
Automatically after a time Tres
–
On the rising edge of CS if two valid DI byte has been received and first the Output
Status in the command register is written with logic '0' and then with a logic “1” in
the following SPI cycle
–
On the rising edge (low to high transition) at the corresponding parallel input pin
(only for Outputs 6-8).
–
If the switching OFF protection is not active the On phase overcurrent protection is
a linear current limitation and no diagnosis is available.
The use of the IN6-8 pins for PWM control on the outputs 6-8 could generates bad
diagnostic behavior when the falling edge of CS happens a short time after the
falling edge of IN6-8 during the power MOS transient. Software filtering may be
needed to ignore fault signals during Drn6-8 transient after falling edge of IN6-8.
Latch mode
This diagnostic operating mode latches all faults when they happen.
1.
Open load
The diagnostic of open load is detected only in OFF condition sensing the Src1-8
output voltage. This fault is detected if the power drain voltage is inside the voltage
range limited by the two thresholds Vth_Vbat and Vth_GND for the filtering time Tfilt.
An internal current limited voltage regulator fixes the drain voltage inside the described
range when no load is connected.
2.
Short Circuit to Vb
The diagnostic of short circuit to Vbat is detected only in OFF condition sensing the
Src1-8 output voltage. This fault is detected if the power drain voltage is higher than the
Vth_Vbat threshold for the filtering time Tfilt.
3.
Overcurrent
The diagnostic of overcurrent is detected only in ON condition, if the switching OFF
protection of the channel is enabled (default), sensing the current level of the output
power transistor. If the output current has been above the short threshold Iovc for the
filtering time Tdel the output power is switched off and at the same time an overcurrent
fault is written in the fault register.
There are three possibilities to restart one output after the fault has occourred:
–
Automatically after a time Tres
–
On the rising edge of CS if two valid DI byte has been received and first the Output
Status in the command register is written with logic '0' and then with a logic “1” in
the following SPI cycle
–
On the rising edge (low to high transition) at the corresponding parallel input pin
(only for Outputs 6-8).
If the switching OFF protection is not active the On phase overcurrent protection is
a linear current limitation and no diagnosis is available.
If the power MOS transient, after a switching-off command, is longer than Tdel filtering time,
a bad diagnostic behavior happens and software filtering may be needed.
27/33
Fault Operation
L9733 Application schematic
VDD
VBAT
Figure 6.
L9733
8 HIGH/LOW SIDE DRIVER
VBAT
CP
RES
DO
CS
VDO
DRN[x]
Registers
DI
SPI Control Logic
SCLK
High Side Driver
Configuration
SRC[x]
DRN[x]
IN6
To driver 6
IN7
To driver 7
IN8
To driver 8
Low Side Driver
Configuration
SRC[x]
GND
Figure 7.
L9733 HVAC applicative examples
Vbatt
SM
SM
SM
Control Logic
SM
SPI
SPI
Control Logic
Vbatt
MM
MM
MM
L9733
L9733
Stall sense
4 channels configured to low- and 4 channels
Four flap motors become sequentially driven. Unipolar stepper motor are
selected by 4 high-side configured switches. If the decoupling diodes are inside
the motor housing, only 8 wires are needed to drive this arrangement.
28/33
configured to high side build a quad half bridge.
This allows to drive 3 DC-motors in sequential ly.
L9733
L9733 Powertrain applicative examples
Vbatt
Vbatt
Key-On Relay
Power Latch Relay
Control Logic
Starter Relay
SPI
Control Logic
Tach-Out
(PWM)
SPI
Figure 8.
Fault Operation
A/C Fan Relay
A/C Compressor Relay
Canister Purge Relay
(opt PWM)
Air Pump Relay
MIL Lamp
Water Lamp
L9733
Fuel Pump Relay
(opt PWM)
SM
Idle Speed Control
L9733
Coolant Fan Relay
Main Relays and Lamps Driving
Idle speed stepper motor driving and auxiliary loads
29/33
Package informations
8
L9733
Package informations
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect. The category of
second Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com.
Figure 9.
SO28 Mechanical Data & Package Dimensions
mm
DIM.
MIN.
TYP.
A
MIN.
TYP.
2.65
MAX.
0.1
0.3
0.004
0.012
b
0.35
0.49
0.014
0.019
b1
0.23
0.32
0.009
0.013
C
0.5
0.020
45° (typ.)
D
17.7
18.1
0.697
0.713
E
10
10.65
0.394
0.419
e
1.27
0.050
e3
16.51
0.65
F
7.4
7.6
0.291
0.299
L
0.4
1.27
0.016
0.050
S
OUTLINE AND
MECHANICAL DATA
0.104
a1
c1
30/33
inch
MAX.
8 ° (max.)
SO-28
L9733
Package informations
Figure 10. PowerSSO28 Mechanical Data & Package Dimensions
DIM.
A
A2
a1
b
c
D (1)
E (1)
e
e3
F
G
G1
H
h
k
L
M
N
O
Q
S
T
U
X
Y
mm
TYP.
MIN.
2.15
2.15
0
0.18
0.23
10.10
7.4
MAX.
2.47
2.40
0.075
0.36
0.32
10.50
MIN.
0.084
0.084
0
0.007
0.009
0.398
7.6
0.291
0.65
8.45
2.3
0.004
0.002
0.413
0.016
5˚
0.85
0.022
4.3
0.033
0.169
10˚
10˚
1.2
0.8
2.9
3.65
1.0
4.2
6.6
0.047
0.031
0.114
0.144
0.039
4.8
7.2
0.165
0.260
0.190
0.283
PowerSSO-28
(exposed-pad)
A2
(1) "D" and "E" do not include mold flash or protrusions Mold flash
or protrusions shall not exceed 0.15 mm per side(0.006")
c
h x 45û
C
G
LEAD COMPLANARITY
A
a1
D
k
e
S
E
H
X
O
Y
F
A
OUTLINE AND
MECHANICAL DATA
0.299
0.398
5˚
0.55
MAX.
0.097
0.094
0.003
0.014
0.012
0.413
0.025
0.033
0.090
0.10
0.06
10.50
0.40
10.10
inch
TYP.
U
Q
BOTTOM VIEW
B
0.1 M A B
M
b
e3
7633868 A
31/33
Revision history
9
L9733
Revision history
Table 12.
32/33
Document revision history
Date
Revision
Changes
13-Apr-2005
1
Initial release.
15-Jun-2006
2
Changed only look and fill.
08-Aug-06
3
Modified Table 8: Bit Command Register Definition on page 21
L9733
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