STMICROELECTRONICS M4T32

M48T86
5.0 V PC real-time clock
Features
■
Drop-in replacement for PC computer
clock/calendar
■
Counts seconds, minutes, hours, days, day of
the week, date, month, and year with leap year
compensation
■
Clock accuracy better than ±1 minute per
month
■
Interfaced with software as 128 RAM locations:
– 14 bytes of clock and control registers
– 114 bytes of general purpose RAM
■
Selectable bus timing (Intel/Motorola)
■
Three interrupts are separately softwaremaskable and testable
– Time-of-day alarm (once/second to
once/day)
– Periodic rates from 122µs to 500ms
– End-of-clock update cycle
■
Programmable square wave output
■
10 years of data retention and clock operation
in the absence of power
■
Self-contained battery and crystal in the caphat
dip package
■
Packaging includes a 28-lead SOIC and
Snaphat® top (to be ordered separately)
■
SOIC package provides direct connection for a
snaphat top contains the battery and crystal
■
24
1
PCDIP24 (PC)
Battery/Crystal
CAPHAT
SNAPHAT (SH)
Battery/Crystal
28
1
SOH28 (MH)
Pin and function compatible with bq3285/7A
and DS12887
February 2007
Rev 5
1/36
www.st.com
1
Contents
M48T86
Contents
Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
VCC, VSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
SQW (square wave output).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
AD0-AD7 (multiplexed bi-directional address/data bus). . . . . . . . . . . . . . . . . . . . . . 9
AS (address strobe input). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
MOT (mode select). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
DS (data strobe input). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
E (chip enable input). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
IRQ (interrupt request output). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
RST (reset input).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
RCL (RAM clear).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
R/W (READ/WRITE input). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Non-volatile RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Clock operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Address map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Time, calendar, and alarm locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Periodic interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Alarm interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Update cycle interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Oscillator control bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Update cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Square wave output selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Register A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
UIP update in progress . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
OSC0, OSC1, OSC2 oscillator control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
RS3, RS2, RS1, RS0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Register B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2/36
M48T86
Contents
PIE: periodic interrupt enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
AIE: alarm interrupt enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
UIE: update ended interrupt enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
SQWE: square wave enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
DM: data mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
24/12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
DSE: daylight savings enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Register C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
IRQF: interrupt request flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
PF: periodic interrupt flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
AF: alarm flag. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
UF: update ended interrupt flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
BIT 0 through 3: unused bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Register D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
VRT: valid RAM and time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
BIT 0 through 6: unused bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
VCC noise and negative going transients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Maximum rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3/36
List of tables
M48T86
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
4/36
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Time, calendar, and alarm formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Square wave frequency/periodic interrupt rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Register A MSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Register B MSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Register C MSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Register D MSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Power down/up mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Power down/up trip points DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
PCDIP24 – 24-pin plastic DIP, battery CAPHAT, package mechanical data . . . . . . . . . . . 29
SOH28 – 28-lead plastic small outline, 4-socket battery SNAPHAT, package mechanical
data30
SH – 4-pin SNAPHAT housing for 48mAh battery and crystal, package mechanical data. 31
SH – 4-pin SNAPHAT housing for 120mAh battery and crystal, package mechanical data32
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
SNAPHAT battery table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
M48T86
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
24-pin DIP connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
28-pin SOIC connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Intel bus READ AC waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Intel bus WRITE mode AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Motorola bus READ/WRITE mode AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Address map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Update period timing and UIP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Update-ended/periodic interrupt relationship . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Supply voltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
AC testing load circuit (no IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
AC testing load circuit (with IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Power down/up mode AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
PCDIP24 – 24-pin plastic DIP, battery CAPHAT, package outline . . . . . . . . . . . . . . . . . . . 28
SOH28 – 28-lead plastic small outline, 4-socket SNAPHAT, package outline . . . . . . . . . . 29
SH – 4-pin SNAPHAT housing for 48mAh battery and crystal, package outline . . . . . . . . 30
SH – 4-pin SNAPHAT housing for 120mAh battery and crystal, package outline . . . . . . . 31
5/36
Summary description
M48T86
Summary description
The M48T86 is an industry standard Real Time Clock (RTC). The M48T86 is composed of a
lithium energy source, quartz crystal, write protection circuitry, and a 128-byte RAM array.
This provides the user with a complete subsystem packaged in either a 24-pin DIP
CAPHAT™ or 28-pin SNAPHAT® SOIC. Functions available to the user include a nonvolatile time-of-day clock, alarm interrupts, a one-hundred-year clock with programmable
interrupts, square wave output, and 128 bytes of non-volatile static RAM.
The 24-pin, 600mil DIP CAPHAT houses the M48T86 silicon with a quartz crystal and a
long-life lithium button cell in a single package.
The 28-pin, 330mil SOIC provides sockets with gold plated contacts at both ends for direct
connection to a separate SNAPHAT® housing containing the battery and crystal. The
unique design allows the SNAPHAT battery package to be mounted on top of the SOIC
package after the completion of the surface mount process.
Insertion of the SNAPHAT housing after reflow prevents potential battery and crystal
damage due to the high temperatures required for device surface-mounting. The SNAPHAT
housing is keyed to prevent reverse insertion.
The SOIC and battery packages are shipped separately in plastic anti-static tubes or in
Tape & Reel form.
For the 28-lead SOIC, the battery/crystal package part number is “M4T28-BR12SH” (see
Table 20 on page 34).
Figure 1.
Logic diagram
VCC
8
AD0-AD7
SQW
E
IRQ
R/W
DS
M48T86
AS
RST
RCL
MOT
VSS
AI01640
6/36
M48T86
Summary description
Table 1.
Signal names
AD0-AD7
E
Figure 2.
Multiplexed address/data bus
Chip enable input
R/W
WRITE enable input
DS
Data strobe input
AS
Address strobe input
RST
Reset Input
RCL
RAM clear input
MOT
Bus type select input
SQW
Square wave output
IRQ
Interrupt request output
(open drain)
VCC
Supply voltage
VSS
Ground
NC
Not connected internally
24-pin DIP connections
MOT
NC
NC
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
VSS
1
24
2
23
3
22
4
21
5
20
6
19
M48T86
7
18
8
17
9
16
10
15
11
14
12
13
VCC
SQW
NC
RCL
NC
IRQ
RST
DS
NC
R/W
AS
E
AI01641
7/36
Summary description
Figure 3.
M48T86
28-pin SOIC connections
NC
MOT
NC
NC
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
VSS
VSS
NC
VCC
SQW
NC
RCL
NC
IRQ
RST
DS
NC
R/W
AS
E
NC
28
1
2
27
26
3
25
4
5
24
6
23
7
22
M48T86
8
21
9
20
10
19
11
18
12
17
13
16
14
15
AI01642
Figure 4.
Block diagram
OSCILLATOR
E
VCC
VBAT
POWER
SWITCH
AND
WRITE
PROTECT
VCC
/8
/ 64
/ 64
PERIODIC INTERRUPT/SQUARE WAVE SELECTOR
POK
SQUARE WAVE
OUTPUT
SQW
IRQ
REGISTERS A,B,C,D
CLOCK/
CALENDAR
UPDATE
CLOCK CALENDAR,
AND ALARM RAM
RST
DOUBLE
BUFFERED
DS
R/W
AS
BUS
INTERFACE
BCD/BINARY
INCREMENT
RCL
STORAGE
REGISTERS
(114 BYTES)
AD0-AD7
AI01643
8/36
M48T86
Operation
Operation
The M48T86 clock is driven by a quartz-controlled oscillator with a nominal frequency of
32,768 Hz. The devices are tested not to exceed 23 ppm (parts per million) oscillator
frequency error at 25°C, which equates to approximately ±1 minute per month. Automatic
deselection of the device ensures the data integrity is not compromised should VCC fall
below specified Power-fail Deselect Voltage (VPFD) levels (see Figure 14 on page 27). The
automatic deselection of the device remains in effect upon power up for a period of 200ms
(max) after VCC rises above VPFD, provided that the Real Time Clock is running and the
count-down chain is not reset. This allows sufficient time for VCC to stabilize and gives the
system clock a wake-up period so that a valid system reset can be established.
The block diagram in Figure 4 on page 8 shows the pin connections and the major internal
functions of the M48T86.
Signal description
VCC, VSS.
DC power is provided to the device on these pins.The M48T86 uses a 5V VCC.
SQW (square wave output).
During normal operation (e.g., valid VCC), the SQW pin can output a signal from one of 13
taps. The frequency of the SQW pin can be changed by programming Register A as shown
in Table 4 on page 18. The SQW signal can be turned on and off using the SQWE Bit
(Register B; Bit 3). The SQW signal is not available when VCC is less than VPFD.
AD0-AD7 (multiplexed bi-directional address/data bus).
The M48T86 provides a multiplexed bus in which address and data information share the
same signal path. The bus cycle consists of two stages; first the address is latched, followed
by the data. Address/Data multiplexing does not slow the access time of the M48T86,
because the bus change from address to data occurs during the internal RAM access time.
Addresses must be valid prior to the falling edge of AS (see Figure 5 on page 11), at which
time the M48T86 latches the address present on AD0-AD7. Valid WRITE data must be
present and held stable during the latter portion of the R/W pulse (see Figure 6 on page 11).
In a READ cycle, the M48T86 outputs 8 bits of data during the latter portion of the DS pulse.
The READ cycle is terminated and the bus returns to a high impedance state upon a high
transition on R/W.
AS (address strobe input).
A positive going pulse on the Address Strobe (AS) input serves to demultiplex the bus. The
falling edge of AS causes the address present on AD0-AD7 to be latched within the
M48T86.
9/36
Operation
M48T86
MOT (mode select).
The MOT pin offers the flexibility to choose between two bus types (see Figure 7 on
page 12). When connected to VCC, Motorola bus timing is selected. When connected to VSS
or left disconnected, Intel bus timing is selected. The pin has an internal pull-down
resistance of approximately 20KΩ.
DS (data strobe input).
The DS pin is also referred to as READ (RD). A falling edge transition on the Data Strobe
(DS) input enables the output during a a READ cycle. This is very similar to an Output
Enable (G) signal on other memory devices.
E (chip enable input).
The Chip Enable pin must be asserted low for a bus cycle in the M48T86 to be accessed.
Bus cycles which take place without asserting E will latch the addresses present, but no
data access will occur.
IRQ (interrupt request output).
The IRQ pin is an open drain output that can be used as an interrupt input to a processor.
The IRQ output remains low as long as the status bit causing the interrupt is present and the
corresponding interrupt-enable bit is set. IRQ returns to a high impedance state whenever
Register C is read. The RST pin can also be used to clear pending interrupts. The IRQ bus
is an open drain output so it requires an external pull-up resistor to VCC.
RST (reset input).
The M48T86 is reset when the RST input is pulled low. With a valid VCC applied and a low
on RST, the following events occur:
1.
Periodic Interrupt Enable (PIE) Bit is cleared to a zero (Register B; Bit 6);
2.
Alarm Interrupt Enable (AIE) Bit is cleared to a zero (Register B; Bit 5);
3.
Update Ended Interrupt Request (UF) Bit is cleared to a zero (Register C; Bit 4);
4.
Interrupt Request (IRQF) Bit is cleared to a zero (Register C Bit 7);
5.
Periodic Interrupt Flag (PF) Bit is cleared to a zero (Register C; Bit 6);
6.
The device is not accessible until RST is returned high;
7.
Alarm Interrupt Flag (AF) Bit is cleared to a zero (Register C; Bit 5);
8.
The IRQ pin is in the high impedance state
9.
Square Wave Output Enable (SQWE) Bit is cleared to zero (Register B; Bit 3); and
10. Update Ended Interrupt Enable (UIE) is cleared to a zero (Register B; Bit 4).
RCL (RAM clear).
The RCL pin is used to clear all 114 storage bytes, excluding clock and control registers, of
the array to FF(hex) value. The array will be cleared when the RCL pin is held low for at
least 100ms with the oscillator running. Usage of this pin does not affect battery load. This
function is applicable only when VCC is applied.
10/36
M48T86
Operation
R/W (READ/WRITE input).
The R/W pin is used to latch data into the M48T86 and provides functionality similar to W in
other memory systems.
Non-volatile RAM
The 114 general-purpose non-volatile RAM bytes are not dedicated to any special function
within the M48T86. They can be used by the processor program as non-volatile memory
and are fully accessible during the update cycle.
Figure 5.
Intel bus READ AC waveform
tCYC
AS
tASW
tASD
DS
tDSL
tDSH
R/W
tDAS
tCS
tOD
tCH
E
tAS
tAH
tDHR
AD0-AD7
AI01647
Figure 6.
Intel bus WRITE mode AC waveform
tCYC
AS
tDAS
tASW
tASD
DS
tDSL
tDSH
R/W
tCS
tCH
E
tAS
tAH
tDW
tDHW
AD0-AD7
AI01648
11/36
Operation
Figure 7.
M48T86
Motorola bus READ/WRITE mode AC waveforms
AS
tDAS
tASW
tASD
tCYC
DS
tDSL
tDSH
tRWS
tRWH
R/W
tCH
tCS
E
tAH
tDW
tAS
tDHW
AD0-AD7
(Write)
tAS
tOD
tAH
tDHR
AD0-AD7
(Read)
AI01649
12/36
M48T86
Operation
Table 2.
AC characteristics
M48T86
Parameter(1)
Symbol
Unit
Min
Typ
Max
tCYC
Cycle time
160
ns
tDSL
Pulse width, data strobe low or R/W high
80
ns
tDSH
Pulse width, data strobe high or R/W low
55
ns
tRWH
R/W hold time
0
ns
tRWS
R/W setup time
10
ns
tCS
Chip select setup time
5
ns
tCH
Chip select hold time
0
ns
tDHR
READ data hold time
0
tDHW
WRITE data hold time
0
ns
tAS
Address setup time
20
ns
tAH
Address hold time
5
ns
tDAS
Delay time, data strobe to address strobe
rise
10
ns
tASW
Pulse width address strobe high
30
ns
tASD
Delay time, address strobe to data strobe
rise
35
ns
tOD
Output data delay time from data strobe
rise
tDW
WRITE setup time
tBUC
Delay time before update cycle
tPI(2)
Periodic interrupt time interval
tUC
Time of update cycle
25
50
30
1.
Valid for ambient operating temperature: TA = 0 to 70°C; VCC = 4.5 to 5.5V (except where noted).
2.
See Table 4 on page 18.
ns
ns
244
–
ns
–
1
µs
–
µs
13/36
Clock operations
M48T86
Clock operations
Address map
The address map of the M48T86 is shown in Figure 8. It consists of 114 bytes of user RAM,
10 bytes of RAM that contain the RTC time, calendar and alarm data, and 4 bytes which are
used for control and status. All bytes can be read or written to except for the following:
1.
Registers C & D are “Read only.”
2.
Bit 7 of Register A is “Read only.”
The contents of the four Registers A, B, C, and D are described in the “Registers” section.
Time, calendar, and alarm locations
The time and calendar information is obtained by reading the appropriate memory bytes.
The time, calendar, and alarm registers are set or initialized by writing the appropriate RAM
bytes. The contents of the time, calendar, and alarm bytes can be either Binary or BinaryCoded Decimal (BCD) format. Before writing the internal time, calendar, and alarm register,
the SET Bit (Register B; Bit 7) should be written to a logic '1.' This will prevent updates from
occurring while access is being attempted. In addition to writing the time, calendar, and
alarm registers in a selected format (binary or BCD), the Data Mode (DM) Bit (Register B;
Bit 2), must be set to the appropriate logic level ('1' signifies binary data; '0' signifies Binary
Coded Decimal (BCD data). All time, calendar, and alarm bytes must use the same data
mode. The SET Bit should be cleared after the Data Mode Bit has been written to allow the
Real Time Clock to update the time and calendar bytes. Once initialized, the Real Time
Clock makes all updates in the selected mode. The data mode cannot be changed without
reinitializing the ten data bytes. Table 3 on page 15 shows the binary and BCD formats of
the time, calendar, and alarm locations. The 24/12 Bit (Register B; Bit 1) cannot be changed
without reinitializing the hour locations. When the 12-hour format is selected, a logic '1' in
the high order bit of the hours byte represents PM. The time, calendar, and alarm bytes are
always accessible because they are double-buffered. Once per second the ten bytes are
advanced by one second and checked for an alarm condition. If a READ of the time and
calendar data occurs during an update, a problem exists where data such as seconds,
minutes, or hours may not correlate. However, the probability of reading incorrect time and
calendar data is low. Methods of avoiding possible incorrect time and calendar READs are
reviewed later in this text.
14/36
M48T86
Clock operations
Figure 8.
Address map
0
14
BYTES
00
CLOCK AND CONTROL
STATUS REGISTERS
0
SECONDS
1
SECONDS ALARM
2
MINUTES
MINUTES ALARM
13
0D
3
14
0E
4
HOURS
5
HOURS ALARM
114
BYTES
STORAGE REGISTERS
127
6
DAY OF WEEK
7
DATE OF MONTH
8
MONTH
9
YEAR
10
REGISTER A
11
REGISTER B
12
REGISTER C
13
REGISTER D
BCD OR
BINARY
FORMAT
7F
AI01650
Table 3.
Time, calendar, and alarm formats
Range
Address
RTC Bytes
Decimal
Binary
BCD
0
Seconds
0-59
00-3B
00-59
1
Seconds alarm
0-59
00-3B
00-59
2
Minutes
0-59
00-3B
00-59
3
Minutes alarm
0-59
00-3B
00-59
Hours, 12-hrs
1-12
01-0C AM
81-8C PM
01-12 AM
81-92 PM
Hours, 24-hrs
0-23
00-17
00-23
Hours alarm, 12-hrs
1-12
01-0C AM
81-8C PM
01-12 AM
81-92 PM
Hours alarm, 24-hrs
0-23
00-17
00-23
6
Day of week (1 = Sun)
1-7
01-07
01-07
7
Day of month
1-31
01-1F
01-31
8
Month
1-12
01-0C
01-12
9
Year
0-99
00-63
00-99
4
5
15/36
Clock operations
M48T86
Interrupts
The RTC plus RAM includes three separate, fully automatic sources of interrupt (alarm,
periodic, update-in-progress) available to a processor. The alarm interrupt can be
programmed to occur at rates from once per second to once per day. The periodic interrupt
can be selected from rates of 500ms to 122µs. The update-ended interrupt can be used to
indicate that an update cycle has completed.
The processor program can select which interrupts, if any, are going to be used. Three bits
in Register B enable the interrupts. Writing a logic '1' to an interrupt-enable bit (Register B;
Bit 6 = PIE; Bit 5 = AIE; Bit 4 = UIE) permits an interrupt to be initialized when the event
occurs. A '0' in an interrupt-enable bit prohibits the IRQ pin from being asserted from that
interrupt condition. If an interrupt flag is already set when an interrupt is enabled, IRQ is
immediately set at an active level, although the interrupt initiating the event may have
occurred much earlier. As a result, there are cases where the program should clear such
earlier initiated interrupts before first enabling new interrupts.
When an interrupt event occurs, the related flag bit (Register C; Bit 6 = PF; Bit 5 = AF; Bit 4
= UF) is set to a logic '1.' These flag bits are set independent of the state of the
corresponding enable bit in Register B and can be used in a polling mode without enabling
the corresponding enable bits. The interrupt flag bits are status bits which software can
interrogate as necessary.
When a flag is set, an indication is given to software that an interrupt event has occurred
since the flag bit was last read; however, care should be taken when using the flag bits as all
are cleared each time Register C is read. Double latching is included with Register C so that
bits which are set remain stable throughout the READ cycle. All bits which are set high are
cleared when read. Any new interrupts which are pending during the READ cycle are held
until after the cycle is completed. One, two, or three bits can be set when reading Register
C. Each utilized flag bit should be examined when read to ensure that no interrupts are lost.
The second flag bit usage method is with fully enabled interrupts. When an interrupt flag bit
is set and the corresponding enable bit is also set, the IRQ pin is asserted low. IRQ is
asserted as long as at least one of the three interrupt sources has its flag and enable bits
both set. The IRQF Bit (Register C; Bit 7) is a '1' whenever the IRQ pin is being driven low.
Determination that the RTC initiated an interrupt is accomplished by reading Register C. A
logic '1' in the IRQF Bit indicates that one or more interrupts have been initiated by the
M48T86. The act of reading Register C clears all active flag bits and the IRQF Bit.
Periodic interrupt
The periodic interrupt will cause the IRQ pin to go to an active state from once every 500ms
to once every 122µs. This function is separate from the alarm interrupt which can be output
from once per second to once per day. The periodic interrupt rate is selected using the
same Register A bits which select the square wave frequency (see Table 4 on page 18).
Changing the Register A bits affects both the square wave frequency and the periodic
interrupt output. However, each function has a separate enable bit in Register B. The
periodic interrupt is enabled by the PIE Bit (Register B; Bit 6). The periodic interrupt can be
used with software counters to measure inputs, create output intervals, or await the next
needed software function.
16/36
M48T86
Clock operations
Alarm interrupt
The alarm interrupt provides the system processor with an interrupt when a match is made
between the RTC's hours, minutes, and seconds bytes and the corresponding alarm bytes.
The three alarm bytes can be used in two ways. First, when the alarm time is written in the
appropriate hours, minutes, and seconds alarm locations, the alarm interrupt is initiated at
the specified time each day if the Alarm Interrupt Enable Bit (Register B; Bit 5) is high. The
second use is to insert a “Don't care” state in one or more of the three alarm bytes. The
“Don't care” code is any hexadecimal value from C0 to FF. The two most significant bits of
each byte set the “Don't care” condition when at logic '1.' An alarm will be generated each
hour when the “Don't care” is are set in the hours byte. Similarly, an alarm is generated
every minute with “Don't care” codes in the hour and minute alarm bytes. The “Don't care”
codes in all three alarm bytes create an interrupt every second.
Update cycle interrupt
After each update cycle, the Update Cycle Ended Flag Bit (UF) (Register C; Bit 4) is set to a
'1.' If the Update Interrupt Enable Bit (UIE) (Register B; Bit 4) is set to a '1,' and the SET Bit
(Register B; Bit 7) is a '0,' then an interrupt request is generated at the end of each update
cycle.
Oscillator control bits
When the M48T86 is shipped from the factory the internal oscillator is turned off. This
feature prevents the lithium energy cell from being discharged until it is installed in a system.
A pattern of “010” in Bits 4-6 of Register A will turn the oscillator on and enable the
countdown chain. A pattern of “11X” will turn the oscillator on, but holds the countdown
chain of the oscillator in reset. All other combinations of Bits 4-6 keep the oscillator off.
Update cycle
The M48T86 executes an update cycle once per second regardless of the SET Bit (Register
B; Bit 7). When the SET Bit is asserted, the user copy of the double buffered time, calendar,
and alarm bytes is frozen and will not update as the time increments. However, the time
countdown chain continues to update the internal copy of the buffer. This feature allows
accurate time to be maintained, independent of reading and writing the time, calendar, and
alarm buffers. This also guarantees that the time and calendar information will be
consistent. The update cycle also compares each alarm byte with the corresponding time
byte and issues an alarm if a match or if a “Don't care” code is present in all three positions.
There are three methods of accessing the real time clock that will avoid any possibility of
obtaining inconsistent time and calendar data. The first method uses the update-ended
interrupt. If enabled, an interrupt occurs after every update cycle which indicates that over
999ms are available to read valid time and date information. If this interrupt is used, the
IRQF Bit (Register C; Bit 7) should be cleared before leaving the interrupt routine.
A second method uses the Update-In-Progress (UIP) Bit (Register A; Bit 7) to determine if
the update cycle is in progress. The UIP Bit will pulse once per second. After the UIP Bit
goes high, the update transfer occurs 244µs later. If a low is read on the UIP Bit, the user
has at least 244µs before the time/calendar data will be changed. Therefore, the user
17/36
Clock operations
M48T86
should avoid interrupt service routines that would cause the time needed to read valid
time/calendar data to exceed 244µs.
The third method uses a periodic interrupt to determine if an update cycle is in progress.
The UIP Bit is set high between the setting of the PF Bit (Register C; Bit 6). Periodic
interrupts that occur at a rate greater than tBUC allow valid time and date information to be
reached at each occurrence of the periodic interrupt.The READs should be completed
within 1/(tPL/2 + tBUC) to ensure that data is not read during the update cycle.
Square wave output selection
Thirteen of the 15 divider taps are made available to a 1-of-15 selector, as shown in the
block diagram of Figure 4 on page 8. The purpose of selecting a divider tap is to generate a
square wave output signal on the SQW pin. The RS3-RS0 bits in Register A establish the
square wave output frequency. These frequencies are listed in Table 4 on page 18. The
SQW frequency selection shares the 1-of-15 selector with the periodic interrupt generator.
Once the frequency is selected, the output of the SQW pin can be turned on and off under
program control with the Square Wave Enabled (SQWE) Bit.
Table 4.
Square wave frequency/periodic interrupt rate
Register A bits
18/36
Square wave
Units
Periodic interrupt
RS3
RS2
RS1
RS0
Frequency
Period
Units
0
0
0
0
None
0
0
0
1
256
Hz
3.90625
ms
0
0
1
0
128
Hz
7.8125
ms
0
0
1
1
8.192
kHz
122.070
us
0
1
0
0
4.096
kHz
244.141
us
0
1
0
1
2.048
kHz
488.281
us
0
1
1
0
1.024
kHz
976.5625
us
0
1
1
1
512
Hz
1.953125
ms
1
0
0
0
256
Hz
3.90625
ms
1
0
0
1
128
Hz
7.8125
ms
1
0
1
0
64
Hz
15.625
ms
1
0
1
1
32
Hz
31.25
ms
1
1
0
0
16
Hz
62.5
ms
1
1
0
1
8
Hz
125
ms
1
1
1
0
4
Hz
250
ms
1
1
1
1
2
Hz
500
ms
None
M48T86
Clock operations
Register A
UIP update in progress
The Update in Progress (UIP) Bit is a status flag that can be monitored. When the UIP Bit is
'1,' the update transfer will soon occur (see Figure 9). When UIP is a '0,' the update transfer
will not occur for at least 244µs. The time, calendar, and alarm information in RAM is fully
available for access when the UIP Bit is '0.' The UIP Bit is “Read only” and is not affected by
RST. Writing the SET Bit in Register B to a '1' inhibits any update transfer and clears the
UIP Status Bit.
OSC0, OSC1, OSC2 oscillator control
These three bits are used to control the oscillator and reset the countdown chain. A pattern
of “010” enables operation by turning on the oscillator and enabling the divider chain. A
pattern of 11X turns the oscillator on, but keeps the frequency divider disabled. When “010”
is written, the first update begins after 500ms.
RS3, RS2, RS1, RS0
These four rate-selection bits select one of the 13 taps on the 15-stage divider or disable the
divider output. The tap selected may be used to generate an output square wave (SQW pin)
and/or a periodic interrupt. The user may do one of the following:
1.
Enable the interrupt with the PIE Bit;
or
2.
Enable the SQW output with the SQWE Bit;
or
3.
Enable both at the same time and same rate;
or
4.
Enable neither.
Table 4 on page 18 lists the periodic interrupt rates and the square wave frequencies that
may be chosen with the RS Bits. These four READ/WRITE bits are not affected by RST.
Table 5.
Register A MSB
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
UIP
OSC2
OSC1
OSC0
RS3
RS2
RS1
RS0
Figure 9.
Update period timing and UIP
UPDATE PERIOD (1sec)
UIP
tBUC
tUC
AI01651
19/36
Clock operations
M48T86
Register B
SET
When the SET Bit is a '0,' the update transfer functions normally by advancing the counts
once per second. When the SET Bit is written to a '1,' any update transfer is inhibited and
the program may initialize the time and calendar bytes without an update occurring. READ
cycles can be executed in a similar manner. SET is a READ/WRITE bit which is not
modified by RST or internal functions of the M48T86.
PIE: periodic interrupt enable
The Periodic Interrupt Enable Bit (PIE) is a READ/WRITE bit which allows the Periodic
Interrupt Flag (PF) Bit in Register C to cause the IRQ pin to be driven low (see Figure 10 on
page 21 for the relationship between PIE and UIE). When the PIE Bit is set to '1,' periodic
interrupts are generated by driving the IRQ pin low at a rate specified by the RS3-RS0 bits
of Register A. A '0' in the PIE Bit blocks the IRQ output from being driven by a periodic
interrupt, but the Periodic Flag (PF) Bit is still set at the periodic rate. PIE is not modified by
any internal M48T86 functions, but is cleared to '0' on RST.
AIE: alarm interrupt enable
The Alarm Interrupt Enable (AIE) Bit is a READ/WRITE bit which, when set to a '1,' permits
the Alarm Flag (AF) Bit in Register C to assert IRQ. An alarm interrupt occurs for each
second that the three time bytes equal the three alarm bytes including a “Don't care” alarm
code of binary 1XXXXXXX. When the AIE Bit is set to '0,' the AF Bit does not initiate the IRQ
signal. The RST pin clears AIE to '0.' The internal functions of the M48T86 do not affect the
AIE Bit.
UIE: update ended interrupt enable
The Update Ended Interrupt Enable (UIE) Bit is a READ/WRITE bit which enables the
Update End Flag (UF) Bit in Register C to assert IRQ. A transition low on the RST pin or the
SET Bit going high clears the UIE Bit.
SQWE: square wave enable
When the Square Wave Enable (SQWE) Bit is set to a '1,' a square wave signal is driven out
on the SQW pin. The frequency is determined by the rate-selection bits RS3-RS0. When the
SQWE Bit is set to '0,' the SQW pin is held low. The SQWE Bit is cleared by the RST pin.
SQWE is a READ/WRITE bit.
DM: data mode
The Data Mode (DM) Bit indicates whether time and calendar information are in binary or
BCD format. The DM Bit is set by the program to the appropriate format and can be read as
required. This bit is not modified by internal function or RST. A '1' in DM signifies binary data
and a '0' specifies Binary Coded Decimal (BCD) data.
20/36
M48T86
Clock operations
24/12
The 24/12 Control Bit establishes the format of the hours byte. A '1' indicates the 24-hour
mode and a '0' indicates the 12-hour mode. This bit is READ/WRITE and is not affected by
internal functions or RST.
DSE: daylight savings enable
The Daylight Savings Enable (DSE) Bit is a READ/WRITE bit which enables two special
updates when set to a '1.' On the first Sunday in April, the time increments from 1:59:59AM
to 3:00:00 AM. On the last Sunday in October, when the time reaches 1:59:59 AM, it
changes to 1:00:00 AM. These special updates do not occur when the DSE Bit is a '0.' This
bit is not affected by internal functions or RST.
Table 6.
Register B MSB
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
SET
PIE
AIE
UIE
SQWE
DM
24/12
DSE
Figure 10. Update-ended/periodic interrupt relationship
UPDATE PERIOD (1sec)
UIP
tBUC
tPI
tPI
tUC
tPI
PF
UF
AI01652B
Register C
IRQF: interrupt request flag
The Interrupt Request Flag (IRQF) Bit is set to a '1' when one or more of the following are
true:
PF = PIE = 1
AF = AIE = 1
UF = UIE = 1
(e.g., IRQF = PF*PIE+AF*AIE+UF*UIE)
21/36
Clock operations
M48T86
PF: periodic interrupt flag
The Periodic Interrupt Flag (PF) is a “Read only” bit which is set to a '1' when an edge is
detected on the selected tap of the divider chain. The RS3-RS0 bits establish the periodic
rate. PF is set to a '1' independent of the state of the PIE Bit. The IRQ signal is active and
will set the IRQF Bit. The PF Bit is cleared by a RST or a software READ of Register C.
AF: alarm flag
A '1' in the AF (Alarm Interrupt Flag) Bit indicates that the current time has matched the
alarm time. If the AIE Bit is also a '1,' the IRQ pin will go low and a '1' will appear in the IRQF
Bit. A RST or a READ of Register C will clear AF.
UF: update ended interrupt flag
The Update Ended Interrupt Flag (UF) Bit is set after each update cycle. When the UIE Bit is
set to a '1,' the '1' in the UF Bit causes the IRQF Bit to be a '1.' This will assert the IRQ pin.
UF is cleared by reading Register C or a RST.
BIT 0 through 3: unused bits
Bit 3 through Bit 0 are unused. These bits always read '0' and cannot be written.
Register D
VRT: valid RAM and time
The Valid RAM and Time (VRT) Bit is set to the '1' state by STMicroelectronics prior to
shipment. This bit is not writable and should always be a '1' when read. If a '0' is ever
present, an exhausted internal lithium cell is indicated and both the contents of the RTC
data and RAM data are questionable. This bit is unaffected by RST.
BIT 0 through 6: unused bits
The remaining bits of Register D are not usable. They cannot be written and when read,
they will always read '0.'
Table 7.
Register C MSB
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
IRQF
PF
AF
UF
0
0
0
0
Table 8.
Register D MSB
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
VRT
0
0
0
0
0
0
0
VCC noise and negative going transients
ICC transients, including those produced by output switching, can produce voltage
fluctuations, resulting in spikes on the VCC bus. These transients can be reduced if
22/36
M48T86
Clock operations
capacitors are used to store energy which stabilizes the VCC bus. The energy stored in the
bypass capacitors will be released as low going spikes are generated or energy will be
absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1µF (as shown in
Figure 11) is recommended in order to provide the needed filtering.
In addition to transients that are caused by normal SRAM operation, power cycling can
generate negative voltage spikes on VCC that drive it to values below VSS by as much as
one volt. These negative spikes can cause data corruption in the SRAM while in battery
backup mode. To protect from these voltage spikes, it is recommended to connect a
schottky diode from VCC to VSS (cathode connected to VCC, anode to VSS). Schottky diode
1N5817 is recommended for through hole and MBRS120T3 is recommended for surface
mount.
Figure 11. Supply voltage protection
VCC
VCC
0.1μF
DEVICE
VSS
AI02169
23/36
Maximum rating
M48T86
Maximum rating
Stressing the device above the rating listed in the “Absolute Maximum Ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to Absolute Maximum Rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality documents.
Table 9.
Absolute maximum ratings
Symbol
TA
TSTG
Parameter
Ambient operating temperature
Storage temperature (VCC off, oscillator off)
TSLD(1),(2),(3) Lead solder temperature for 10 seconds
24/36
Value
Unit
0 to 70
°C
–40 to 85
°C
260
°C
VIO
Input or output voltages
–0.3 to 7.0
V
VCC
Supply voltage
–0.3 to 7.0
V
PD
Power dissipation
1
W
1.
For DIP package: soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer
than 30 seconds).
2.
For SO package, standard (SnPb) lead finish: reflow at peak temperature of 225°C (total thermal budget not to exceed 180°C for
between 90 to 150 seconds).
3.
For SO package, Lead-free (Pb-free) lead finish: reflow at peak temperature of 260°C (total thermal budget not to exceed 245°C
for greater than 30 seconds).
Warning:
Negative undershoots below –0.3V are not allowed on any
pin while in the Battery Back-up mode.
Warning:
Do NOT wave solder SOIC to avoid damaging SNAPHAT
sockets.
M48T86
DC and AC parameters
DC and AC parameters
This section summarizes the operating and measurement conditions, as well as the DC and
AC characteristics of the device. The parameters in the following DC and AC Characteristic
tables are derived from tests performed under the Measurement Conditions listed in the
relevant tables. Designers should check that the operating conditions in their projects match
the measurement conditions when using the quoted parameters.
Table 10.
Operating and AC measurement conditions
Parameter
M48T86
Unit
4.5 to 5.5
V
0 to 70
°C
Load capacitance (CL)
100
pF
Input rise and fall times
≤5
ns
0 to 3
V
1.5
V
Supply voltage (VCC)
Ambient operating temperature (TA)
Input pulse voltages
Input and output timing ref. voltages
Note:
Output Hi-Z is defined as the point where data is no longer driven.
Figure 12. AC testing load circuit (no IRQ)
5V
960Ω
FOR ALL
OUTPUTS
EXCEPT IRQ
510Ω
50pF
AI01644
25/36
DC and AC parameters
M48T86
Figure 13. AC testing load circuit (with IRQ)
5V
1.15kΩ
IRQ
130pF
AI01645
Table 11.
Capacitance
Parameter(1),(2)
Symbol
CIN
CIO(3)
Max
Unit
Input capacitance
7
pF
Input / output capacitance
5
pF
1.
Effective capacitance measured with power supply at 5V; sampled only, not 100% tested.
2.
At 25°C, f = 1MHz.
3.
Outputs deselected.
Table 12.
DC characteristics
Symbol
Parameter
ILI
ILO(2)
Input leakage current
Output leakage current
Test Condition(1)
Min
Max
Unit
0V ≤ VIN ≤ VCC
±1
µA
0V ≤ VOUT ≤ VCC
±1
µA
Outputs open
15
mA
ICC
Supply current
VIL
Input low voltage
–0.3
0.8
V
VIH
Input high voltage
2.2
VCC + 0.3
V
IOL = 4mA
0.4
V
Output low voltage (IRQ)
IOL = 0.5mA
0.4
V
Output high voltage
IOH = –1mA
Output low voltage
VOL
VOH
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Min
2.4
1.
Valid for ambient operating temperature: TA = 0 to 70°C; VCC = 4.5 to 5.5V (except where noted).
2.
Outputs deselected.
V
M48T86
DC and AC parameters
Figure 14. Power down/up mode AC waveforms
VCC
4.5V
VPFD
VSO
tF
tR
trec
E
AI01646
Table 13.
Power down/up mode AC characteristics
Parameter(1)
Symbol
Min
Max
tF(2)
VCC fall time
300
µs
tR
VCC rise time
100
µs
trec
VPFD to E high
20
200
1.
Valid for ambient operating temperature: TA = 0 to 70°C; VCC = 4.5 to 5.5V (except where noted).
2.
VCC fall time of less than tF may result in deselection/write protection not occurring until 200µs after VCC passes VPFD.
Table 14.
Parameter(1)(2)
VPFD
Power-fail deselect voltage
VSO
Battery back-up switchover voltage
tDR
ms
Power down/up trip points DC characteristics
Symbol
(3)
Unit
Expected data retention time
Min
Typ
4.0
3.0
10
1.
Valid for ambient operating temperature: TA = 0 to 70°C; VCC = 4.5 to 5.5V (except where noted).
2.
All voltages referenced to VSS.
3.
At 25°C, VCC = 0V.
Max
Unit
4.35
V
V
YEARS
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DC and AC parameters
M48T86
Figure 15. PCDIP24 – 24-pin plastic DIP, battery CAPHAT, package outline
A2
A1
B1
B
e1
A
L
C
eA
e3
D
N
E
1
Note:
28/36
Drawing is not to scale.
PCDIP
M48T86
DC and AC parameters
Table 15.
PCDIP24 – 24-pin plastic DIP, battery CAPHAT, package mechanical data
mm
inches
Symb
Typ
Min
Max
A
8.89
A1
Typ
Min
Max
9.65
0.3500
0.3799
0.38
0.76
0.0150
0.0299
A2
8.36
8.89
0.3291
0.3500
B
0.38
053
0.0150
0.0209
B1
1.14
1.78
0.0449
0.0701
C
0.20
0.31
0.0079
0.0122
D
34.29
34.80
1.3500
1.3701
E
17.83
18.34
0.7020
0.7220
e1
2.29
2.79
0.0902
0.1098
e3
25.15
30.73
0.9902
1.2098
eA
15.24
16.00
0.6000
0.6299
L
3.05
3.81
0.1201
0.1500
N
24
24
Figure 16. SOH28 – 28-lead plastic small outline, 4-socket SNAPHAT, package
outline
A2
A
C
B
eB
e
CP
D
N
E
H
A1
α
L
1
SOH-A
Note:
Drawing is not to scale.
29/36
DC and AC parameters
Table 16.
M48T86
SOH28 – 28-lead plastic small outline, 4-socket battery SNAPHAT, package
mechanical data
mm
inches
Symb
Typ
Min
A
Max
Typ
Min
Max
3.05
0.1201
A1
0.05
0.36
0.0020
0.0142
A2
2.34
2.69
0.0921
0.1059
B
0.36
0.51
0.0142
0.0201
C
0.15
0.32
0.0059
0.0126
D
17.71
18.49
0.6972
0.7280
E
8.23
8.89
0.3240
0.3500
–
–
–
–
eB
3.20
3.61
0.1260
0.1421
H
11.51
12.70
0.4531
0.5000
L
0.41
1.27
0.0161
0.0500
a
0°
8°
0°
8°
N
28
e
1.27
CP
0.0500
28
0.10
0.0039
Figure 17. SH – 4-pin SNAPHAT housing for 48mAh battery and crystal, package
outline
A1
eA
A2
A3
A
B
L
eB
D
E
SH
Note:
30/36
Drawing is not to scale.
M48T86
DC and AC parameters
Table 17.
SH – 4-pin SNAPHAT housing for 48mAh battery and crystal, package
mechanical data
mm
inches
Symb
Typ
Min
A
Max
Typ
Min
Max
9.78
0.3850
A1
6.73
7.24
0.2650
0.2850
A2
6.48
6.99
0.2551
0.2752
A3
0.38
0.0150
B
0.46
0.56
0.0181
0.0220
D
21.21
21.84
0.8350
0.8598
E
14.22
14.99
0.5598
0.5902
eA
15.55
15.95
0.6122
0.6280
eB
3.20
3.61
0.1260
0.1421
L
2.03
2.29
0.0799
0.0902
Figure 18. SH – 4-pin SNAPHAT housing for 120mAh battery and crystal, package
outline
A1
eA
A2
A3
A
B
L
eB
D
E
SHTK-A
Note:
Drawing is not to scale.
31/36
DC and AC parameters
Table 18.
M48T86
SH – 4-pin SNAPHAT housing for 120mAh battery and crystal, package
mechanical data
mm
inches
Symb
Typ
Min
A
Typ
Min
10.54
Max
0.415
A1
8.00
8.51
0.315
.0335
A2
7.24
8.00
0.285
0.315
A3
32/36
Max
0.38
0.015
B
0.46
0.56
0.018
0.022
D
21.21
21.84
0.835
0.860
E
17.27
18.03
0.680
.0710
eA
15.55
15.95
0.612
0.628
eB
3.20
3.61
0.126
0.142
L
2.03
2.29
0.080
0.090
M48T86
Part numbering
Part numbering
Table 19.
Ordering information scheme
Example:
M48T
86
MH
1
E
Device Type
M48T
Supply Voltage and Write Protect Voltage
86 = VCC = 4.5 to 5.5V; VPFD = 4.2 to 4.5V
Package
PC = PCDIP24
MH(1) = SOH28
Temperature Range
1 = 0 to 70°C
Shipping Method
For SOH28:
blank = Tubes (Not for New Design - Use E)
E = Lead-free Package (ECO PACK®), Tubes
F = Lead-free Package (ECO PACK®), Tape & Reel
TR = Tape & Reel (Not for New Design - Use F)
For PCDIP28:
blank = Tubes
1.
The SOIC package (SOH28) requires the SNAPHAT® battery/crystal package which is ordered separately under the part number “M4T28BR12SH” in plastic tube or “M4T28-BR12SHTR” in Tape & Reel form (see Table 20).
Warning:
Do not place the SNAPHAT battery package “M4TXXBR12SH” in conductive foam as it will drain the lithium
button-cell battery.
For other options, or for more information on any aspect of this device, please contact the
ST Sales Office nearest you.
33/36
Part numbering
M48T86
Table 20.
SNAPHAT battery table
Part Number
34/36
Description
Package
M4T28-BR12SH
Lithium battery (48mAh) SNAPHAT
SH
M4T32-BR12SH
Lithium battery (120mAh) SNAPHAT
SH
M48T86
Revision history
Revision history
Table 21.
Document revision history
Date
Revision
Changes
Mar-1999
1.0
First Issue
04-May-2000
1.1
Page layout changed
31-Jul-2001
2.0
Reformatted; temp/voltage info. added to tables (Table 12, 2, 13,14)
20-May-2002
2.1
Modify reflow time and temperature footnotes (Table 9)
01-Apr-2003
3.0
V2.2 template applied; test condition updated (Table 14 )
02-Apr-2004
4.0
Reformatted; update Lead-free package information (Table 9,19)
20-Feb-2007
5.0
Update cover page (features) and Section : Operation on page 9.
35/36
M48T86
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