M5450 M5451 LED DISPLAY DRIVERS .. . .. .. . .. .. M5450 34 OUTPUTS/15mA SINK M5451 35 OUTPUTS/15mA SINK CURRENT GENERATOR OUTPUTS (NO EXTERNAL RESISTORS REQUIRED) CONTINUOUS BRIGHTNESS CONTROL SERIAL DATA INPUT ENABLE (ON M5450) WIDE SUPPLY VOLTAGE OPERATION TTL COMPATIBILITY Application Examples : MICROPROCESSOR DISPLAYS INDUSTRIAL CONTROL INDICATOR RELAY DRIVER INSTRUMENTATION READOUTS A single pin controls the LED display brightness by setting a reference current through a variable resistor connected to VDD or to a separate supply of 13.2V maximum. DIP40 (Plastic Package) ORDER CODE : M5450B7 / M5451B7 DESCRIPTION The M5450 and M5451 are monolithic MOS integrated circuits produced with an N-channel silicon gate technology. They are available in 40-pin dual in-line plastic packages. PLCC44 (Plastic Chip Carrier) ORDER CODE : M5451Q PIN CONNECTION 8 OUTPUT BIT 10 9 OUTPUT BIT 13 7 39 OUTPUT BIT 23 OUTPUT BIT 12 8 38 OUTPUT BIT 24 OUTPUT BIT 24 OUTPUT BIT 11 9 37 OUTPUT BIT 25 33 OUTPUT BIT 25 OUTPUT BIT 10 10 36 OUTPUT BIT 26 32 OUTPUT BIT 26 OUTPUT BIT 9 11 35 OUTPUT BIT 27 N.C. 12 34 N.C. OUTPUT BIT 8 13 33 OUTPUT BIT 28 OUTPUT BIT 5 16 30 OUTPUT BIT 31 OUTPUT BIT 4 17 29 OUTPUT BIT 32 OUTPUT BIT 5 14 27 OUTPUT BIT 31 OUTPUT BIT 4 15 26 OUTPUT BIT 32 OUTPUT BIT 3 16 25 OUTPUT BIT 33 OUTPUT BIT 2 17 24 OUTPUT BIT 1 18 23 OUTPUT BIT 34 DATA ENABLE FOR M5450 OUTPUT BIT 35 FOR M5451 BRIGHTNESS CONTROL 19 22 DATA IN V DD 20 21 CLOCK IN September 1993 28 OUTPUT BIT 30 OUTPUT BIT 33 28 27 13 OUTPUT BIT 34 OUTPUT BIT 30 OUTPUT BIT 6 26 31 OUTPUT BIT 35 15 25 OUTPUT BIT 6 DATA IN OUTPUT BIT 29 24 29 CLOCK IN 12 23 OUTPUT BIT 29 OUTPUT BIT 7 N.C. 32 22 14 VDD OUTPUT BIT 7 21 OUTPUT BIT 28 BRIGHTNESS CONTROL 30 20 11 OUTPUT BIT 1 OUTPUT BIT 8 19 OUTPUT BIT 27 18 31 OUTPUT BIT 2 10 OUTPUT BIT 3 OUTPUT BIT 9 5450-01.EPS - 5450-02.EPS OUTPUT BIT 11 OUTPUT BIT 22 34 OUTPUT BIT 21 7 40 OUTPUT BIT 12 OUTPUT BIT 20 OUTPUT BIT 23 41 35 OUTPUT BIT 19 6 42 OUTPUT BIT 22 OUTPUT BIT 13 OUTPUT BIT 18 36 43 5 N.C. OUTPUT BIT 21 OUTPUT BIT 14 44 37 VSS 4 1 OUTPUT BIT 20 OUTPUT BIT 15 OUTPUT BIT 17 38 2 3 OUTPUT BIT 16 OUTPUT BIT 19 OUTPUT BIT 16 3 OUTPUT BIT 18 39 OUTPUT BIT 15 40 2 4 1 OUTPUT BIT 14 V SS OUTPUT BIT 17 5 PLCC44 6 DIP40 1/8 M5450 - M5451 BLOCK DIAGRAM (Figure 1) V DD BRIGTHNESS CONTROL 20 OUTPUT BIT 34 OUTPUT BIT 1 24 18 100kΩ 19 35 OUTPUT BUFFERS LOAD 35 LATCHES DATA ENABLE (M5450) OUTPUT35 (M5451) 23 SERIAL DATA 22 CLOCK 21 35-BIT SHIFT REGISTER 5450-03.EPS RESET 1 Symbol VDD VI VO(off) IO Ptot Tj Value Unit Supply Voltage Parameter – 0.3 to 15 V Input Voltage – 0.3 to 15 V Off State Output Voltage 15 V Output Sink Current 40 mA Total Package Power Dissipation at 25°C at 85°C 1 560 W mW Junction Temperature 150 °C Top Operating Temperature Range – 25 to 85 °C Tstg Storage Temperature Range – 65 to 150 °C Stresses above those listed under "Absolute Maximum Ratings" may causes permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. FUNCTIONAL DESCRIPTION Both the M5450 and the M5451 are specially designed to operate 4 or 5-digit alphanumeric displays with minimal interface with the display and the data source. Serial data transfer from the data source to the display driver is accomplished with 2 signals, serial data and clock. Using a format of a leading "1" followed by the 35 data bits allows data transfer without an additional load signal. The 35 data bits are latched after the 36th bit is complete, thus providing non-multiplexed, direct drive to the display. Outputs change only if the serial data bits differ from the previous time. Display brightness is determined by control of the output current LED displays. 2/8 A 1nF capacitor should be connected to brightness control, pin 19, to prevent possible oscillations. A block diagram is shown in figure 1. For the M5450 a DATA ENABLE is used instead of the 35th output. The DATA ENABLE input is a metal option for the M5450. The output current is typically 20 times greater than the current into pin 19, which is set by an external variable resistor. There is an internal limiting resistor of 400Ω nominal value. Figure 2 shows the input data format. A start bit of logical "1" precedes the 35 bits of data. At the 36th clock a LOAD signal is generated synchronously with the high state of the clock, which loads the 35 bits of the shift registers into the latches. 5450-01.TBL ABSOLUTE MAXIMUM RATINGS M5450 - M5451 At the low state of the clock a RESET signal is generated which clears all the shift registers for the next set of data. The shift registers are static master-slave configurations. There is no clear for the master portion of the first shift register, thus allowing continuous operation. There must be a complete set of 36 clocks or the shift registers will not clear. When power is first applied to the chip an internal power ON reset signal is generated which resets all registers and all latches. The START bit and the first clock return the chip to its normal operation. Bit 1 is the first bit following the start bit and it will appear on Pin 18. A logical "1" at the input will turn on the appropriate LED. Figure 3 shows the timing relationship between Data, Clock and DATA ENABLE. A max clock frequency of 0.5MHz is assumed. For applications where a lesser number of outputs are used, it is possible to either increase the current per output or operate the part at higher than 1V VOUT. The following equation can be used for calculations. Tj = [(VOUT) (ILED) (No. of segments) + (VDD ⋅ 7mA)] (124°C/W) + Tamb where : Tj = junction temperature (150°C max) VOUT = the voltage at the LED driver outputs ILED = the LED current 124°C/W = thermal coefficient of the package Tamb = ambient temperature The above equation was used to plot Figures 4, 5 and 6. STATIC ELECTRICAL CHARACTERISTICS (Tamb within operating range, VDD = 4.75V to 13.2V, VSS = 0V, unless otherwise specified) Parameter VDD Supply Voltage IDD Supply Current VI Input Voltage IB Brightness Input Current (note 2) VB Brightness Input Voltage (pin 19) VO(off) IO fclock IO Notes : 1. 2. 3. 4. Test Conditions Min. Typ. 4.75 Max. 13.2 V 7 mA - 0.3 2.2 VDD - 2 0.8 VDD VDD V V V 0 0.75 mA 3 4.3 V 13.2 V 10 µA 10 4 25 µA mA mA 0.5 MHz ± 20 % VDD = 13.2V Logical "0" Level Logical "1" Level ± 10µA Input Bias 4.75 ≤ VDD ≤ 5.25 VDD > 5.25 Input Current = 750µA, Tamb = 25oC Off State Out. Voltage Out. Sink Current (note 3) Segment OFF Segment ON Input Clock Frequency Output Matching (note 1) VO = 3V VO = 1V (note 4) Brightness In. = 0µA Brightness In. = 100µA Brightness In. = 750µA Unit 0 2 12 2.7 15 0 Output matching is calculated as the percent variation from IMAX + IMIN/2. With a fixed resistor on the brightness input some variation in brightness will occur from one device to another. Absolute maximum for each output should be limited to 40mA. The VO voltage should be regulated by the user. See figures 5 and 6 for allowable VO versus IO operation. 3/8 5450-02.TBL Symbol M5450 - M5451 Figure 2 : Input Data Format 1 36 CLOCK START BIT 1 BIT 34 BIT 35 DATA 5450-04.EPS LOAD (INTERNAL) RESET (INTERNAL) Figure 3 Figure 4 1.0 Ptot (W) 15mA/segment 34 segments VO = 1V CLOCK 0.8 0.6 DATA 300ns (min.) 0.4 DATA ENABLE Figure 5 T amb (˚C) 20 0 80 100 I 0 (mA) VO (V) 105 T amb = 85˚C 2.0 I O (max.) = 40mA 85 65 VO = 1V VO = 1.5V VO = 2V 1.6 45 1.2 0.8 T amb = 85˚C 0.4 T j = 150˚C (max.) 8 12 16 20 24 28 32 5450-07.EPS 4 25 I LED (mA) N˚ Segm. 5 0 4 8 12 16 20 24 28 32 36 40 5450-08.EPS 20 segments 30 segments 34 segments 2.4 4/8 60 Figure 6 2.8 0 40 5450-06.EPS 5450-05.EPS 0.2 100ns (min.) 3.2 SAFE OPERATING AREA M5450 - M5451 TYPICAL APPLICATIONS BASIC ELECTRONICALLY TUNED RADIO OR TV SYSTEM AM FM 34 SEGMENTS M5450 DISPLAY DRIVER ELECTRONIC TUNING CONTROLLER PLL SYNTHESIZER 5450-09.EPS KEYBOARD STATION DETEC. ETC. DUPLEXING 8 DIGITS WITH ONE M5450 V DD V LED . 9 16 . 28 40 V DD V LED . 32 39 . . . . . 24 31 M5450 18 21 22 19 20 1 23 17 CLOCK IN DATA IN 5450-10.EPS V DD BRIGHTNESS CONTROL 5/8 M5450 - M5451 nected diodes is quite stable if the diodes are properly chosen. The total power dissipation of the IC depends, in a first approximation, only on the number of segments activated. POWER DISSIPATION OF THE IC The power dissipation of the IC can be limited using different configurations. a) In the application R must be chosen taking into account the worst operating conditions. b) +V C a) +V C R ID VD R is determined by the maximum number of segments activated VC − VD MAX − VO MIN R= NMAX ⋅ ID The worst case condition for the device is when roughly half of the maximum number of segments are activated. It must be checked that the total power dissipation does not exceed the absolute maximum ratings of the device. In critical cases more resistors can be used in conjunction with groups of segments. In this case the current variation in the single resistor is reduced and Ptot limited. b) In this configuration the drop on the serial con- 6/8 5450-12.EPS c) In this configuration VOUT + VD is constant. The total power dissipation of the IC depends only on the number of segments activated. c) +VC V OUT +V D 5450-13.EPS 5450-11.EPS V OUT M5450 - M5451 I L a1 PACKAGE MECHANICAL DATA 40 PINS - PLASTIC DIP b1 b b2 e E e3 D 21 1 20 a1 b b1 b2 D E e e3 F i L Min. Millimeters Typ. 0.63 0.45 0.23 Max. Min. 0.31 0.009 1.27 2.54 48.26 0.012 2.070 0.657 0.598 0.100 1.900 14.1 4.445 3.3 Max. 0.050 52.58 16.68 15.2 Inches Typ. 0.025 0.018 0.555 DIP40.TBL Dimensions PM-DIP40.EPS F 40 0.175 0.130 7/8 M5450 - M5451 PACKAGE MECHANICAL DATA 44 PINS - PLASTIC CHIP CARRIER C B M M1 6 1 44 2 39 M 38 e3 F1 E e F M1 7 17 29 18 28 d2 A G (Seating Plane Coplanarity) A B C D d1 d2 E e e3 F F1 G M M1 Min. 17.4 16.51 3.65 4.2 2.59 Millimeters Typ. Max. 17.65 16.65 3.7 4.57 2.74 Min. 0.685 0.650 0.144 0.165 0.102 16 0.590 0.68 14.99 D Inches Typ. Max. 0.695 0.656 0.146 0.180 0.108 0.027 1.27 12.7 0.46 0.71 0.630 0.050 0.500 0.018 0.028 0.101 1.16 1.14 0.004 0.046 0.045 Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No licence is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. © 1994 SGS-THOMSON Microelectronics - All Rights Reserved Purchase of I2C Components of SGS-THOMSON Microelectronics, conveys a license under the Philips I2C Patent. Rights to use these components in a I2C system, is granted provided that the system conforms to the I2C Standard Specifications as defined by Philips. SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. 8/8 PLCC44.TBL Dimensions PMPLCC44.EPS d1