HYNIX GM6486

GM6486
GM6486
33 OUTPUT LED DRIVER
General Description
Pin Configuration
The GM6486 is a monolithic MOS integrated circuit
produced with high voltage CMOS technology. It is
available in a 40-pin dual in-line plastic package. A
sin-gle pin controls the LED display brightness by
setting a reference current through a variable
resistor connect-ed to VDD or to a separated supply
of 13.2V maximum.
40 PIN DIP
Features
l 33 Output, 15mA Sink Capability
l Current Generator Outputs (No External
Resistros Required)
l Continous Brightness Control
l Serial Data Input-Output
l External Load Input
l Cascade operation capability
l Wide supply voltage range
l TTL compatibility
4
37
OUT BIT 20
OUT BIT 13
5
36
OUT BIT 21
OUT BIT 12
6
35
OUT BIT 22
OUT BIT 11
7
34
OUT BIT 23
OUT BIT 10
8
33
OUT BIT 24
OUT BIT
9
9
32
OUT BIT 25
OUT BIT
8
10
31
OUT BIT 26
OUT BIT
7
11
30
OUT BIT 27
OUT BIT
6
12
29
OUT BIT 28
OUT BIT
5
13
28
OUT BIT 29
OUT BIT
4
14
27
OUT BIT 30
OUT BIT
3
15
26
OUT BIT 31
OUT BIT
2
16
25
OUT BIT
1
17
24
OUT BIT 32
OUT BIT 33
18
23
19
22
LOAD
DATA IN
20
21
CLOCK IN
GM6486
OUTPUT BIT 33
OUTPUT BIT 1
44 PIN PLCC
33 BIT SHIFT REGISTER
18
DATA
OUT
21
1
VSS
Application
OUT BIT 12
OUT BIT 21
OUT BIT 11
OUT BIT 22
OUT BIT 10
OUT BIT 9
OUT BIT 23
OUT BIT 24
8
OUT BIT
7
OUT BIT
6
OUT BIT
5
OUT BIT
4
OUT BIT 28
OUT BIT 29
OUT BIT
3
OUT BIT 30
OUT BIT
2
OUT BIT 31
GM6486-44
OUT BIT 26
OUT BIT 27
OUT BIT 20
NC
LOAD
OUT BIT 20
DATA IN
CLOCK IN
OUT BIT 1
VDD
BRIGHTNES
CONTROL S
DATA OUT
1
OUT BIT 25
OUT BIT
NC
l Microprocessor Displays
l Industrial control Indicator
l Relay Driver
l Instrumentation Readouts
NC
33 LATCHES
OUT BIT 20
OUTPUT
VSS
33
BUFFES
OUT BIT 19
17
OUT BIT 18
24
OUT BIT170
20
OUT BIT 16
CLOCK
22
OUT BIT 18
OUT BIT 19
OUT BIT 15
SERIAL
DATA
23
38
OUT BIT 14
LOAD
3
NC
750µ
OUT BIT 17
39
Top View
VDD
100KΩ
TYP
40
2
OUT BIT 13
InF
1
DATA OUT
BRIGHTNESS
CONTROL
VDD
Block Diagram
BRIGHTNESS
CONTROL
VSS
OUT BIT 16
OUT BIT 15
OUT BIT 14
GM6486
Absolute Maximum Rating
SYMBOL
VDD
VIN
VO (off )
IO
PARAMETER
RATINGS
Supply Voltage
Input Voltage
Off State Output Voltage
Output Sink Current
Ptot
Total Package Power Dissipation
Tj
Top
Tstg
Junction Temperature
Operating Temperature Range
Storage Temperature Range
UNIT
-0.3 to 15
-0.3 to 15
15
40
1 (at 25 °C )
560 (at 85 °C )
150
-25 to 85
-65 to 150
V
V
V
mA
W
mW
°C
°C
°C
Electrical Characteristics
( Tamb within operating range, VDD =4.75V to 13.2V VSS =0, unless otherwise specified)
SYMBOL
PARAMETER
VDD
Supply Voltage
I DD
VIL
VIH
Ib
Vb
VO (off )
I OH
I OL
IO
Supply Current
Input Voltage
Logical “0” Level
Logical “1” Level
Brightness input current
(Note 1)
Brightness input voltage
(Pin 19)
Off State out. Voltage
Output sink current
(Note 2)
Segment off
Segment on
TEST CONDITION
MIN
TYP MAX UNIT
4.75
VDD =13.2V
All Control Inputs at VSS =0V
±10µA Input Bias
4.75 ≤ VDD ≤ 5.25
VDD >5.25
Input Current=750 µA
Vo = 3V
Vo = 1V (Note 3)
Bright in =0 µA
Bright in =100 µA
Bright in =750 µA
Maximum Segment
Current
2
50
-0.3
2.2
VDD -2
3
0
2
12
2.7
15
13.2
V
1000
µA
0.8
VDD
VDD
V
V
V
0.75
mA
4.3
V
13.2
V
10
µA
10
4
25
µA
40
mA
mA
mA
GM6486
SYMBOL
OM
VOL
VOH
fC
th
tl
t DS
t DH
t DES
Note: 1.
2.
3.
4.
5.
6.
PARAMETER
Output Matching
(Note 4)
Data Output
Logical “0” Level
Logical “1” Level
Clock Input
Frequency
High Time
Low Time
Data Input
Set-up time
Hold time
Data Enable Input
Set-up time
TEST CONDITION
I OUT = 0.5mA
I OUT = 100µA
MIN
MAX
±20
UNIT
%
0.4
VDD
V
V
500
950
950
KHz
ns
ns
300
300
ns
ns
100
ns
VSS
2.4
TYP
(notes 5 and 6)
With a fixed resistor on the brightness input, some variation in brightness will occur from one device
to another.
Absolute maximum for each output should be limited to 40 mA.
The Vo voltage should be regulated by the user. See figures 6 and 7 for allowable Vo versus Io
operation.
Output matching is calculated as the percent variation (lmax+lmin)/2.
AC input waveform specification for test prupose: t r ≤ 20 ns . t f ≤ 20ns .
f=500kHz ± 10% duty cycle
Clock Input rise and fall times must not exceed 300ns.
Functional Description
The GM6486 is specifically designed to operate 4 digit displays with minimal interface with the display and the
data source. Serial data transfer from the data source to the display driver is accomplished with 3 signals, serial
data, clock and load.
The 33 data bits are latched by a positive pulse, thus providing non-multiplexed direct drive to the display.
Outputs change only if the serial data bits differ from the previous time. Display brightness is determined by control of the output current of LED drivers. A 1nF capacitor should be connected to brightness control, pin 19, to
prevent possible oscillation. A block diagram is shown in figure 1.
The output current is typically 20 times greater than the current into pin 19, which is set by an external variable resistor.
There is an internal limiting resistor of 400 Ω nominal value.
Figure 2 and 3 show the input data format. Bit “1” is the first bit into the data input pin and it will appear on pin
17. A logical “1” at the input will turn on the appropriate LED. The LOAD signal latches the 33 bit of the shift
registers into the latches. The data out pin allows for cascading the shift registers for more than 33 output drivers.
When power is first applied to the chip an internal power ON reset signal is generated which resets all registers
and all latches.
The first clock return the chip to its normal operation.
Figure 4 shows the timing relationship between data, clock and load.
A max clock frequency of 0.5MHz is assumed.
For applications where less number of outputs are used, it is possible to either increase the current per output or
operate the part at higher than 1V Vo .
The following equation can be used for calculation.
Tj = [(Vo ) • ( I LED ) • (No. of segments)+(Vdd × 7mA)](124 °C /W)+Tamb
where
Tj = junction temperature (+150 °C max) 124 °C /W=thermal coefficient of package
Vo =the voltage at the LED driver outputs
Temb=ambient temperature
I LED
=the LED current
The above equation was used to plot figure 5, 6 and 7.
3
GM6486
LEADING
CLOCK 1
2
32
LEADING
CLOCK 1
33
CLOCK
BIT 1
BIT 2
BIT 32 BIT 33
BIT 1
DATA
LOAD
reset
Pulse 1
reset
Pulse 2
RESET
(INTERNAL)
• leading clock is necessary after power on and load signal high.
• reset pulse 1: internal pulse that comes after power on—
effective on both shift register and latches
• reset pulse 2: internal pulse that comes load pulse—
effective on shift register only.
Fig. 2. Data Input Format
VDD
CLOCK
300ns MIN
RESET
(INTERNAL)
Fig. 3. Power On Reset
t
r
th
t
f
t
l
t
ds
t
dh
CLOCK
DATA
LOAD
t
des
Fig. 4. Timing Diagram
4
GM6486
Fig. 5
Plot
(W)
Fig. 6
33 SEGMENTS
V0=1V
15mA/SEGMEN
T
0.8
SAFE OPERATING
AREA
0.6
0.4
Vo
Tamb = 85°C
Tj = 150°C(MAX)
2.4
20SEGM
40
60
75
Vo = 1 .5 V
Vo = 1V
Vo = 2 V
45
30SEGM
Tamb( °C ) 0
MAXIo=40mA
35
25
0.6
20
85
55
33SEGM
0
Io
(mA)
65
1.8
1.2
0.2
Fig. 7
4
8
12
15
5
16 20 24 ILED (mA) 0
4
8 12 16 20 24 28 32 N° Se
Typical Applications
Basic electronically turned Ratio or TV system
AM
FM
33 SEGMENT
GM6486
DISPLAY
DRIVER
KEY BOARD
ELECTRONIG
UNIGNG
CONTROLLER
STATION
DETECT ETC.
5
PLL SYNTHESIZER
GM6486
Typical Applications (Continued)
Duplexing 8 Digits with one GM6486
VCC
VDD
VLED
9-15
2-8, 40
VLED
32-39
24-31
GM6486
16 21
22 19
20
1
23
17
CLOCK IN
DATA IN
VDD
BRIGHTNESS
CONTROL
LOAD
Power Dissipations of the IC
The power dissipation of the IC can be limited by using different configulation.
a)
VC
ID
VD
VOUT
6
GM6486
In this application R must be chosen taking into account the worst operating conditions. R is determined by the
maximum number of segment activated.
R=
VC
VDMAX VOMIN
NMax • ID
The worst case condition for the device is when roughly half of the maximum number of segments are activated.
It must be checked that the total power dissipation does not exceed the absolute maximum ratings.
In critical cases more resistors can be used in conjuction with groups of segments. In this case the current
variation in the single resistor is reduced and plot limited.
b)
VC
In this configuration the drop on the serial connected diodes is quite stable if the diodes are properly chosen.
The total power dissipation of the ICs is, in first approximation, depending only on the number of segments
activated.
c)
VC
VOUT+VD
In this configuration VOUT+VD is constant. The total power dissipation of the IC depends only the number of
segments activated.
7