STMICROELECTRONICS M54HC597D

M54HC597
RAD-HARD 8 BIT LATCH/SHIFT REGISTER
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HIGH SPEED:
fMAX = 50 MHz (TYP.) at VCC = 6V
LOW POWER DISSIPATION:
ICC =4µA(MAX.) at TA=25°C
HIGH NOISE IMMUNITY:
VNIH = VNIL = 28% VCC (MIN.)
SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 4mA (MIN)
BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL
WIDE OPERATING VOLTAGE RANGE:
VCC (OPR) = 2V to 6V
PIN AND FUNCTION COMPATIBLE WITH
54 SERIES 597
SPACE GRADE-1: ESA SCC QUALIFIED
50 krad QUALIFIED, 100 krad AVAILABLE ON
REQUEST
NO SEL UNDER HIGH LET HEAVY IONS
IRRADIATION
DEVICE FULLY COMPLIANT WITH
SCC-9306-054
DESCRIPTION
The M54HC597 is an high speed CMOS 8 BIT
PIPO SHIFT REGISTER fabricated with silicon
gate C2MOS technology.
DILC-16
FPC-16
ORDER CODES
PACKAGE
FM
EM
DILC
FPC
M54HC597D
M54HC597K
M54HC597D1
M54HC597K1
This devices comes in a 16-pin package and
consist of an 8-bit storage latch feeding a parallel
in, serial out 8-bit shift register. Both the storage
register and shift register have positive edge
triggered clocks. The shift register also has direct
load (from storage) and clear inputs.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
PIN CONNECTION
June 2004
Rev. 1
1/14
M54HC597
Figure 1: IEC Logic Symbols
Figure 2: Input And Output Equivalent Circuit
Table 1: Pin Description
PIN N°
SYMBOL
NAME AND FUNCTION
9
QH’
10
SCLR
11
SCK
12
RCK
13
SLOAD
10
15, 1, 2, 3, 4,
5, 6, 7
8
SI
Serial Data Outputs
Asynchronous Reset
Input (Active LOW)
Shift Clock Input (LOW to
HIGH Edge-triggered)
Storage Clock Input (LOW
to HIGH Edge-triggered)
Parallel Data Input (Active
Low)
Serial Data Input
16
A to H
Parallel Data Inputs
GND
VCC
Ground (0V)
Positive Supply Voltage
Table 2: Truth Table
INPUTS
OUTPUT
SI
SCK
SCLR
SLOAD
RCK
X
X
X
X
L
H
H
L
X
X
L
H
H
X
H
H
H
X
X
H
H
X
STATE OF S.R. IS NOT CHANGED
X
X
X
X
INPUT DATA ON A ~ H LINE IS STORED INTO INPUT REGISTER
X
X
X
X
STORAGE REGISTER STATE IS NOT CHANGED
X : Don’t Care
2/14
S.R. IS CLEARED TO "L"
INPUT REGISTER DATA IS STORED INTO S.R.
FIRST STAGE OF S.R. BECOMES "L" OTHER STAGES
STORE THE DATA OF PREVIOUS STAGE, RESPECTIVELY
FIRST STAGE OF S.R. BECOMES "H" OTHER STAGES
STORE THE DATA OF PREVIOUS STAGE, RESPECTIVELY
M54HC597
Figure 3: Logic Diagram
This logic diagram has not be used to estimate propagation delays
3/14
M54HC597
Figure 4: Timing Chart
Table 3: Absolute Maximum Ratings
Symbol
VCC
Parameter
Supply Voltage
Value
Unit
-0.5 to +7
V
VI
DC Input Voltage
-0.5 to VCC + 0.5
V
VO
DC Output Voltage
IIK
DC Input Diode Current
-0.5 to VCC + 0.5
± 20
mA
IOK
DC Output Diode Current
± 20
mA
IO
DC Output Current
± 25
mA
ICC or IGND DC VCC or Ground Current
PD
Power Dissipation
Tstg
Storage Temperature
TL
Lead Temperature (10 sec)
V
± 50
mA
300
mW
-65 to +150
°C
265
°C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
4/14
M54HC597
Table 4: Recommended Operating Conditions
Symbol
VCC
Parameter
Supply Voltage
Value
Unit
2 to 6
V
VI
Input Voltage
0 to VCC
V
VO
Output Voltage
0 to VCC
V
Top
Operating Temperature
Input Rise and Fall Time
tr, tf
-55 to 125
°C
VCC = 2.0V
0 to 1000
ns
VCC = 4.5V
0 to 500
ns
VCC = 6.0V
0 to 400
ns
Table 5: DC Specifications
Test Condition
Symbol
VIH
VIL
VOH
VOL
II
ICC
Parameter
High Level Input
Voltage
Low Level Input
Voltage
High Level Output
Voltage
Low Level Output
Voltage
Input Leakage
Current
Quiescent Supply
Current
Value
TA = 25°C
VCC
(V)
Min.
2.0
4.5
6.0
2.0
4.5
6.0
Typ.
Max.
1.5
3.15
4.2
-40 to 85°C
-55 to 125°C
Min.
Min.
Max.
1.5
3.15
4.2
0.5
1.35
1.8
Max.
1.5
3.15
4.2
0.5
1.35
1.8
V
0.5
1.35
1.8
2.0
IO=-20 µA
1.9
2.0
1.9
1.9
4.5
IO=-20 µA
4.4
4.5
4.4
4.4
6.0
IO=-20 µA
5.9
6.0
5.9
5.9
4.5
IO=-4.0 mA
4.18
4.31
4.13
4.10
5.68
Unit
V
V
6.0
IO=-5.2 mA
2.0
IO=20 µA
0.0
0.1
0.1
0.1
4.5
IO=20 µA
0.0
0.1
0.1
0.1
6.0
IO=20 µA
0.0
0.1
0.1
0.1
4.5
IO=4.0 mA
0.17
0.26
0.33
0.40
6.0
IO=5.2 mA
0.18
0.26
0.33
0.40
6.0
VI = VCC or GND
± 0.1
±1
±1
µA
6.0
VI = VCC or GND
4
40
80
µA
5.8
5.63
5.60
V
5/14
M54HC597
Table 6: AC Electrical Characteristics (CL = 50 pF, Input tr = tf = 6ns)
Test Condition
Symbol
Parameter
tTLH tTHL Output Transition
Time
tPLH tPHL Propagation Delay
Time
(SCK - QH’)
tPLH tPHL Propagation Delay
Time
(SCLR - QH’)
tPLH tPHL Propagation Delay
Time
(SLOAD - QH’)
tPLH tPHL Propagation Delay
Time
(RCK- QH’)
fMAX
tW(H)
tW(L)
tW(L)
ts
ts
ts
th
tREM
6/14
Maximum Clock
Frequency
Minimum Pulse
Width (SCK, RCK)
Minimum Pulse
Width (SCLR,
SLOAD)
Minimum Set-up
Time (RCK SLOAD)
Minimum Set-up
Time (SI, SCK)
Minimum Set-up
Time (PI, RCK)
Minimum Hold
Time
Minimum Removal
Time
TA = 25°C
VCC
(V)
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
Value
Min.
Typ.
Max.
75
15
13
145
29
25
175
35
30
175
35
30
210
42
36
6.0
30
35
30
8
7
78
20
16
90
24
20
80
22
18
112
30
24
12
48
50
20
7
4
25
7
5
48
12
10
20
5
4
20
5
4
SLOAD = "L"
12
4
3
-40 to 85°C
-55 to 125°C
Min.
Min.
Max.
95
19
16
180
36
31
220
44
37
220
44
37
265
53
45
4.8
24
28
75
15
13
75
15
13
100
20
17
75
15
13
75
15
13
0
0
0
75
15
13
Max.
115
23
20
220
44
37
265
53
45
265
53
45
315
63
54
4.0
20
24
95
19
16
95
19
16
125
25
21
95
19
16
95
19
16
0
0
0
95
19
16
Unit
ns
ns
ns
ns
ns
MHz
110
22
19
110
22
19
150
30
26
110
22
19
110
22
19
0
0
0
115
23
20
ns
ns
ns
ns
ns
ns
ns
M54HC597
Table 7: Capacitive Characteristics
Test Condition
Symbol
Parameter
VCC
(V)
Value
TA = 25°C
Min.
Typ.
Max.
10
CIN
Input Capacitance
5.0
5
CPD
Power Dissipation
Capacitance (note
1)
5.0
60
-40 to 85°C
-55 to 125°C
Min.
Min.
Max.
10
Unit
Max.
10
pF
pF
1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC
Table 8: Test Circuit
CL = 50pF or equivalent (includes jig and probe capacitance)
RT = ZOUT of pulse generator (typically 50Ω)
Figure 5: Waveform - Minimum Pulse Width, Propagation Delay Time (f=1MHz; 50% duty cycle)
7/14
M54HC597
Figure 6: Waveform - Minimum Pulse Width, Propagation Delay Time (f=1MHz; 50% duty cycle)
Figure 7: Waveform - Minimum Pulse Width And Removal Time (f=1MHz; 50% duty cycle)
8/14
M54HC597
Figure 8: Waveform - Minimum Setup And Hold Time (f=1MHz; 50% duty cycle)
Figure 9: Waveform - Propagation Delay, Minimum Pulse Width, Removal Time
(f=1MHz; 50% duty cycle)
9/14
M54HC597
Figure 10: Waveform - Minimum Setup Time (f=1MHz; 50% duty cycle)
Figure 11: Waveform - Input Waveform (f=1MHz; 50% duty cycle)
10/14
M54HC597
DILC-16 MECHANICAL DATA
mm.
inch
DIM.
MIN.
TYP
MAX.
MIN.
TYP.
MAX.
A
2.1
2.71
0.083
0.107
a1
3.00
3.70
0.118
0.146
a2
0.63
1.14
0.025
B
1.82
2.39
0.072
b
0.40
0.45
0.50
0.016
0.018
0.020
b1
0.20
0.254
0.30
0.008
0.010
0.012
D
20.06
20.32
20.58
0.790
0.800
0.810
E
7.36
7.62
7.87
0.290
0.300
0.310
e
0.88
2.54
0.035
0.045
0.094
0.100
e1
17.65
17.78
17.90
0.695
0.700
0.705
e2
7.62
7.87
8.12
0.300
0.310
0.320
F
7.29
7.49
7.70
0.287
0.295
0.303
I
3.83
0.151
K
10.90
12.1
0.429
0.476
L
1.14
1.5
0.045
0.059
0056437F
11/14
M54HC597
FPC-16 MECHANICAL DATA
mm.
inch
DIM.
MIN.
TYP
MAX.
MIN.
TYP.
MAX.
A
6.75
6.91
7.06
0.266
0.272
0.278
B
9.76
9.94
10.14
0.384
0.392
0.399
C
1.49
1.95
0.059
D
0.102
0.127
0.152
0.004
0.005
0.006
E
8.76
8.89
9.01
0.345
0.350
0.355
F
0.077
1.27
G
0.38
H
6.0
L
18.75
M
0.33
0.050
0.43
0.48
0.015
0.017
0.019
0.237
0.38
N
22.0
0.738
0.43
0.013
0.867
0.015
4.31
0.017
0.170
G
F
D
H
9
16
A
N
L
8
1
H
E
B
12/14
M
C
0016030E
M54HC597
Table 9: Revision History
Date
Revision
01-Jun-2004
1
Description of Changes
First Release
13/14
M54HC597
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