STMICROELECTRONICS SABRE-LL-I

SABRE-LL-I
Combo motor driver
Preliminary Data
Features
■
Configurable device
■
4 full bridges to generate
– Up 2 DC motor drivers and 1 stepper motor
driver
or
– 4 DC motor drivers
■
■
TQFP64 exposed pad
Bridges (1 & 2) additional configurations are
– Super DC
– 2 half bridges
– 1 super half bridge
– 2 switches
– 1 super switch
■
Bridges (3 & 4) additional configurations are:
– Same as bridges 1&2, listed above
– 2 buck regulators (bridge 3)
– 1 super buck regulator
– Battery charger (bridge 4)
Description
■
One variable voltage buck switching regulator
■
One switching regulator controller
■
One linear regulator
■
Bidirectional serial interface
■
Programmable watchdog function
■
Integrated power sequencing and supervisory
functions with fault signaling through serial
interface and external reset pin
■
Thermal shutdown protection with thermal
warning capability
■
Very low power dissipation in shut-down mode
(~35 mW)
Table 1.
Aux features
– Operational amplifiers
– Comparators
– Pass switches
– Multi-channels 9 bit ADC
– GPIOs
S.A.B.Re™ (structured architecture of bridges
and regulators) is a new concept of IC in the
motion & power supply field. ST aim is to follow
the S.A.B.Re specification and to offer to the
customer an IC with a wide number of features,
that can be configured and customized: motor
drivers, regulators, high precision A/D converter,
operational amplifiers and voltage comparators.
The start up configuration can be defined by the
GPIOs and then through the serial interface; a
customization can be done through a metal layer
in order to set more complex functions.
Device summary
Part number
Package
Packing
SABRE-LL-I
TQFP64
Tray
November 2007
Rev 1
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.
1/141
www.st.com
1
Contents
SABRE-LL-I
Contents
1
General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2
S.A.B.Re’s main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3
Global specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4
5
6
7
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3.1
Absolute maximum rating specifications . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.2
Operating ratings specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Internal supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.2
VSupplyInt regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.3
VSupplyInt specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.4
Charge pump regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.5
V3v3 regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.6
V3v3 specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Supervisory system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.2
Power on reset (POR) circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.3
nRESET generation circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.4
nRESET specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.5
Thermal shut down generation circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.6
TSD specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Watchdog circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.2
Watchdog specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Internal clock oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.2
Internal clock specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
SABRE-LL-I
8
9
Contents
Start-up configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8.1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8.2
Operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8.3
Basic device mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
8.4
Slave device mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8.5
Master device mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8.6
Single device mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8.7
Sub-configurations for slave, master or single device modes . . . . . . . . . 29
11
13
8.7.2
Primary regulator mode (KP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8.7.3
Regulators mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
8.7.4
Simple regulator mode (KT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
8.7.5
Bridge+ VEXT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
8.7.6
Secondary regulators mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
10.1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
10.2
Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
10.3
Hibernate mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
10.4
Low power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
10.5
nAWAKE pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Linear main regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
11.1
12
Bridge mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Power sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
9.1
10
8.7.1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Main switching regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
12.1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
12.2
Pulse skipping operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Switching regulator controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
13.1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
13.2
Pulse skipping operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
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Contents
14
15
16
SABRE-LL-I
13.3
Output equivalent circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
13.4
Switching regulator controller specifications . . . . . . . . . . . . . . . . . . . . . . 45
13.5
Switching regulator controller application considerations . . . . . . . . . . . . . 45
Power bridges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
14.1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
14.2
Power bridges operating specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 50
14.3
Possible configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
18
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14.3.2
Parallel configuration (super bridge) . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
14.3.3
Half bridge configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
14.3.4
Switch configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
14.3.5
Bipolar stepper configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
14.3.6
Synchronous buck regulator configuration . . . . . . . . . . . . . . . . . . . . . . . 64
14.3.7
Regulation loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
15.1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
15.2
A2D specification with A2dType=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
15.3
A2D specification with A2dType=1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
15.4
Voltage divider specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Current DAC circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Operational amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
17.1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
17.2
Operational amplifiers specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
17.3
Operational amplifiers used as comparators specifications . . . . . . . . . . . 85
Low voltage power switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
18.1
19
Full bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
AD converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
16.1
17
14.3.1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
General purpose PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
19.1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
19.2
General purpose PWM generators 1 and 2 (AuxPwm1 and AuxPwm2) . 88
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Contents
19.3
20
21
Interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
20.1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
20.2
Interrupt controller monitored signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Digital comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
21.1
22
Programmable PWM generator (GpPwm) . . . . . . . . . . . . . . . . . . . . . . . . 88
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
GPIO pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
22.1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
22.2
GPIO[0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
22.3
GPIO[1] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
22.4
GPIO[2] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
22.5
GPIO[3] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
22.6
GPIO[4] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
22.7
GPIO[5] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
22.8
GPIO[6] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
22.9
GPIO[7] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
22.10 GPIO[8] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
22.11 GPIO[9] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
22.12 GPIO[10] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
22.13 GPIO[11] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
22.14 GPIO[12] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
22.15 GPIO[13] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
22.16 GPIO[14] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
23
Serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
23.1
Read transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
23.2
Write transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
24
Registers list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
25
Schematic samples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
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Contents
26
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Pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
26.1
Pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
27
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
28
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
6/141
SABRE-LL-I
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Absolute maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
IC operating ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
VSupplyInt specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
VPump specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
VSupplyInt specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Power on reset specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Stretch time selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
nRESET circuit specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
TSD circuit specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Watchdog timeout specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Watchdog specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Internal clock specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Possible start-up pins state symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Start-up correspondence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
nAWAKE function specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
System linear regulator operating specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Switching regulator controller PWM specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Main switching regulator PWM specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Main switching regulator current limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Main switching regulator specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Switching regulator controller PWM specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Switching regulator controller PWM specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Switching regulator controller operating specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Switching regulator controller operating specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Switching regulator controller application feedback reference . . . . . . . . . . . . . . . . . . . . . . 46
PWM selection truth for bridge 1 or 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
PWM selection truth for bridge 3 or 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Power bridges operating specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Bridge selection truth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Bridge 3 and 4 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Full bridge truth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Half bridge truth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Switch truth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Stepper specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Sequencer drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Stepper mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Stepper sequencer direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Internal sequencer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Blanking times specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Stepper off time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Stepper fast decay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Switching regulator controller PWM specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Pwm specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Operating specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Battery charger control loop FBRef specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Battery charger control loop CurrRef specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
7/141
List of tables
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
Table 70.
Table 71.
Table 72.
Table 73.
Table 74.
Table 75.
Table 76.
Table 77.
Table 78.
Table 79.
Table 80.
Table 81.
Table 82.
Table 83.
Table 84.
Table 85.
Table 86.
Table 87.
Table 88.
Table 89.
Table 90.
Table 91.
Table 92.
Table 93.
Table 94.
Table 95.
Table 96.
Table 97.
Table 98.
Table 99.
Table 100.
8/141
SABRE-LL-I
Battery charger regulator controller PWM specification . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Battery charger operating specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
ADC truth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Channel addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
ADC sample times when working as a 8-bit ADC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
ADC sample time when working as a 9-bit ADC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
ADC specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
ADC specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Voltage divider specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Current DAC truth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Current DAC specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Configurable 3.3V operational amplifier specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Configurable 3.3V operational amplifier used as comparator specification . . . . . . . . . . . . 85
3.3V low power switch specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Interrupt controller event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Interrupt controller specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Comparison type truth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
DataX selection truth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
GPIO functions description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
GPIO[0] truth. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
GPIO[0] specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
GPIO[1] truth. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
GPIO[1] specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
GPIO[2] truth. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
GPIO[2] specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
GPIO[3] truth. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
GPIO[3] specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
GPIO[4] truth. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
GPIO[4] specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
GPIO[5] truth. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
GPIO[5] specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
GPIO[6] truth. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
GPIO[6] specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
GPIO[7] truth. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
GPIO[7] specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
GPIO[8] truth. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
GPIO[8] specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
GPIO[9] truth. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
GPIO[9] specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
GPIO[10] truth. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
GPIO[10] specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
GPIO[11] truth. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
GPIO[11] specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
GPIO[12] truth. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
GPIO[12] specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
GPIO[13] truth. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
GPIO[13] specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
GPIO[14] truth. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
GPIO[14] specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
SPI interface specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Register address map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
SABRE-LL-I
List of tables
Table 101. Pins configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Table 102. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
9/141
List of figures
SABRE-LL-I
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
Figure 42.
Figure 43.
Figure 44.
Figure 45.
Figure 46.
Figure 47.
Figure 48.
10/141
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
VSupplyInt pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
nReset generation circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Watchdog circuit block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Standby mode function description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
nAWAKE function block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Linear main regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Linear main regulator external bipolar example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Main switching regulator functional blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Switching regulator controller functional blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Switching regulator controller output driving equivalent circuit . . . . . . . . . . . . . . . . . . . . . . 44
H Bridge block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Bridge 1 and 2 PWM selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Super bridge configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Half bridge configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Bipolar stepper configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Regulator block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Internal comparator functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Battery charger control loop block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Li-ion battery charge profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Simple buck regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
A2D block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Current DAC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Configurable 3.3V operational amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Low power switch block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Low power switch block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Digital Comparator block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
GPIO[0] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
GPIO[1] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
GPIO[2] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
GPIO[3] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
GPIO[4] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
GPIO[5] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
GPIO[6] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
GPIO[7] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
GPIO[8] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
GPIO[9] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
GPIO[10] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
GPIO[11] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
GPIO[12] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
GPIO[13] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
GPIO[14] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
SPI read transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
SPI write transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
SPI input timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
SPI output timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Application with 2 DC motors, 1 stepper motor and 3 power supplies . . . . . . . . . . . . . . . 134
Application with 2 DC motors, a battery charger and 5 power supplies . . . . . . . . . . . . . . 135
SABRE-LL-I
Figure 49.
List of figures
TQFP64 mechanical data & package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
11/141
General description
SABRE-LL-I
1
General description
1.1
Overview
S.A.B.Re represents a new concept of IC in motion & power supply field.
The aim that ST followed in defining S.A.B.Re specification was to offer to the customer an
IC with a wide number of features: motor drivers, regulators, high precision A/D converter,
operational amplifiers, voltage comparators and many other circuits can easily be
configured and customized. The device configuration can be defined by programming the IC
via the Serial Interface while a deeper customization can be done through metal layer in
order to set more complex functions.
Block diagram
Note:
12/141
Start Up
config.
Power
sequencing
Int. Ref. Volt
Rsense
Bridge 4
Stepper
circuitry
ADC
SPI
Charge Pump
Analog
Mux
Switching Reg.
controller
S/H
Bridge 3
Batt. Charg.
circuitry
Digital
auxiliary
Current
DAC
OP.Amps
Thermal
Manager
SA B R e
Main Linear
regulator
(2x) 3.3V
Pass
Switch
Osc.
Supervisory
& Reset
Manager
Main Switching
regulator
Bridge 2
Digital
compar.
GPIOs
Bridge 1
Internal
regulators
Figure 1.
See following “S.A.B.Re’s Main features” for a detailed description of possible
configurations.
Rsense
SABRE-LL-I
2
S.A.B.Re’s main features
S.A.B.Re’s main features
S.A.B.Re includes the following circuits:
●
Four widely configurable full bridges:
–
–
●
Bridges 1 and 2:
–
Diagonal RDSon: 0.6Ω typ.
–
Max operative current = 2.5A.
Bridges 3 and 4:
–
Diagonal RDSon: 0.85Ω typ.
–
Max operative current = 1.5A.
Possible configurations for each bridge are the following:
–
Bridge 1:
–
DC motor driver.
–
Super DC (bridge 1 and 2 paralleled form superbridge1).
–
2 independent half bridges.
–
1 super half bridge (bridge 1 side A and bridge 1 side B paralleled form
superhalfbridge1).
–
2 independent switches (high or low side).
–
1 super switch (high or low side).
–
Bridge 2 has the same configurations of bridge 1.
–
Bridge 3 has the same configurations of bridge 1 (bridge 3 and 4 paralleled form
superbridge2) plus the following:
–
–
●
●
½ Stepper motor driver.
–
2 buck regulators (VAUX1_SW, VAUX2_SW).
–
1 Super buck regulator (VAUX1//2_SW).
Bridge 4 has the same configurations of bridge 1 plus the following:
–
½ stepper motor driver.
–
1 super buck regulator (VAUX3_SW).
–
Battery charger.
One buck type switching regulator (VMAIN_SW) with:
–
Output regulated voltage range: 1-5 Volts.
–
Output load current: 3.0 A.
–
Internal output power DMOS.
–
Internal soft start sequence.
–
Internal PWM generation.
–
Switching frequency: ~250kHz.
–
Pulse skipping strategy control.
One switching regulator controller (VEXT_SW) with:
–
Output regulated voltage range: 1-30 Volts.
–
Selectable current limitation.
–
Internal PWM generation.
–
Pulse skipping strategy control.
13/141
S.A.B.Re’s main features
●
One linear regulator (VMAIN_LIN) that can be used to generate low current/low ripple
voltages. This regulator can be used to drive an external bipolar pass transistor to
generate high current/low ripple output voltages.
●
One bidirectional serial interface with address detection so that different ICs can share
the same data bus.
●
Integrated power sequencing and supervisory functions with fault signaling through
serial interface and external reset pin.
●
Fourteen general purpose I/Os that can be used to drive/read internal/external
analog/logic signals.
●
One 8-bit/9-bit A/D converter (100KS/sec @ 9-bit, 200KS/sec @8-bit). It can be used to
measure most of the internal signals, of the input pins and a voltage proportional to IC
temperature.
●
14/141
SABRE-LL-I
–
Current sink DAC:
–
Three output current ranges: up to 0.64/6.4/64 mA.
–
64 (6-bit programmable) available current levels for each range.
–
5V output tolerant.
Two operational amplifiers:
–
3.3V supply, rail to rail input compatibility, internally compensated.
–
They can have all pins externally accessible or can be internally configured as a
buffer o make internal reference voltages available outside of the chip.
–
Unity gain bandwidth > 1MHz.
–
They can also be set as comparators with 3.3V input compatibility and low offset.
●
Two 3.3V pass switches with 1Ω RDSon and short circuit protected.
●
Programmable watchdog function.
●
Thermal shutdown protection with thermal warning capability.
●
Very low power dissipation in “Low Power mode” (~35mW)
●
S.A.B.Re is intended to maximize the use of its components, so when an internal circuit
is not used it could be employed for other applications. Bridge 3, for example, can be
used as a full bridge or to implement two switching regulators with synchronous
rectification: to obtain this flexibility S.A.B.Re includes 2 separate regulation loops for
these regulators; when the bridge is used as a motor driver, the 2 regulation loops can
be redirected on general purpose I/Os to leave the possibility to assembly a switching
regulator by only adding an external FET.
SABRE-LL-I
Global specifications
3
Global specifications
3.1
Absolute maximum rating specifications
The following specifications define the maximum range of voltages or currents for S.A.B.Re.
Stresses above these absolute maximum specifications may cause permanent damage to
the device.
Exposure to absolute maximum ratings for extended periods may affect device reliability.
Table 2.
Absolute maximum rating
Parameter
VSupply_Abs
VGPIO_SPI_Abs
V3V3pin_Abs
Description
Max
Unit
VSupply voltage
40
V
VGPIO_SPI voltage
3.9
V
3.3V pins input voltage
3.9
V
VSupply
V
VSw_Abs
Switching regulators output pin voltage
range
VSw_pulse
Switching regulators min pulsed
voltage
VPump_Abs
Charge pump pins voltage
Junction temperature(2)
Tj_Abs
Test
condition
Min
-1
For less than
500ns
-3
(1)
V
15
V
Storage
-40
190
°C
Operating
0
TSD
°C
1. This value is useful to define the voltage rating for external capacitor to be connected from VPump to
VSupply. VPump is internally generated and can never be supplied by external voltage source nor is intended
to provide voltage to external loads.
2. TSD is the thermal shut down temperature of the device.
3.2
Operating ratings specifications
Table 3.
IC operating ratings
Parameter
VSupply_Op
Description
VSupply voltage range
ISupply_Op
VSupply operative current
IShut_down
VSupply shut down state current
VGPIO_SPI_OP
IVGPIO_SPI_OP
V3v3pin_Op
Tj_Abs
Test
condition
Unit
23
38
V
15
mA
1.5
mA
3.6
V
TBD
mA
-0.3
3.6
V
0
125.
°C
2.4
(2)
3.3V input pins voltage range
Junction temperature
Max
(1)
VGPIO_SPI voltage range
VGPIO_SPI operative current
Min
Operating
1. Operating Supply current is measured with System regulators operating but not loaded.
2. Operating VGPIO_SPI current is measured with all circuits supplied by VGPIO_SPI (GPIO’s, operational
amplifiers and pass switches) enabled but not loaded.
15/141
Internal supplies
SABRE-LL-I
4
Internal supplies
4.1
Overview
S.A.B.Re includes three internal regulators used to provide a regulated voltage to internal
circuits.
The internal regulators are the following:
- VSupplyInt regulator.
- Charge pump regulator.
- V3v3 regulator.
4.2
VSupplyInt regulator
VSupplyInt is the output of an internal regulator used to supply some internal circuits. This
regulator is not intended to provide external current so it must not be used to supply external
loads. An external capacitor must always be connected to this pin (preferably towards
VSupply pin).
Figure 2.
VSupplyInt pin
VsupplyInt
Vsupply
IS_Int_TYP
SABRe
internal
circuits
SABRe
GND
The VSupplyInt pin may also be externally connected to VSupply pin by means of an external
resistor REXT: this allows REXT, particularly when VSupply is at the max values of the
operative supply range, to dissipate power that otherwise would be dissipated inside the
chip. The choice of the optimal resistor depends on the application since it is strictly
depending on both VSupply and the current used inside the chip (that is changing with the
chosen configuration).
16/141
SABRE-LL-I
4.3
Internal supplies
VSupplyInt specifications
Table 4.
VSupplyInt specification
Test
condition
Min
Typ
Max
Unit
VSupplyInt output voltage
(1)
18
19.5
21
V
VSupplyInt operative current
(2)
11
VSupply=32V
IS_Int=12mA(3)
1000
1.5
Ω
100
120
nF
Parameter
VS_Int_RNG
IS_Int_TYP
Description
RExt
External resistor value
CExt
External capacitor
80
mA
1. This value is useful to define the voltage rating for external capacitor to be connected from VSupply to
VSupplyInt.
2. This typical value is only intended to give an extimation of the current consumption when S.A.B.Re is
configured in simple regulators mode (see following Chapter 8.7.4) at the end of the start up sequence and
with no load on regulators. This typical value allows a raw choose of the external resistor but the definitive
choose must be done according to following Note 3).
3. REXT could be chosen by applying this formula: REXT = (VSupply min - VS_Int max)/(IS_Int max). IS_Int max
is depending from the chosen configuration and represents the total current needed by the circuits
connected to this pin.
4.4
Charge pump regulator
S.A.B.Re implements a charge pump regulator to generate a voltage over VSupply.This
voltage is used to drive internal circuits and the external FET driver and cannot be used for
any other purpose.
This circuit is always under the supervisory circuit control, so no regulator can start before
the VPump voltage reaches its undervoltage rising threshold. If VPump voltage falls down
below its under voltage falling threshold, all the regulators will be switched off.
The charge pump circuit is disabled when S.A.B.Re is in “Low Power mode”.
Table 5.
Parameter
4.5
VPump specification
Description
VPump
Regulated Voltage
FPump
VPump clock frequency
Test condition
Min
Typ
Max
Unit
VSupply=32V
VSupply
+10.5
VSupply
+12.5
VSupply
+14.5
V
Fosc = 16MHz typ
Fosc/64
KHz
CFLY
Flying capacitor
100
nF
CBOOST
Boost capacitor
1
µF
V3v3 regulator
V3v3 is the output of an internal regulator used to supply some low voltage internal circuits.
This regulator is not intended to provide external current so it must not be used to supply
external loads. An external capacitor must always be connected from this pin to gnd.
17/141
Internal supplies
4.6
V3v3 specifications
Table 6.
Parameter
18/141
SABRE-LL-I
VSupplyInt specification
Description
V3V3
V3v3 output voltage
CExt
External capacitor
Test condition
Min
Typ
Max
Unit
VSupply=32V
3.15
3.3
3.45
V
80
100
120
nF
SABRE-LL-I
Supervisory system
5
Supervisory system
5.1
Overview
The supervisory circuitry monitors the state of several functions inside S.A.B.Re and resets
the device (and other ICs if connected to nRESET pin) when the monitored functions are
outside their normal range. Supervisory circuitry can be divided into three main blocks:
–
Power on reset (POR) generation circuitry.
–
nRESET (nRST_int) generation circuitry.
–
Thermal shut down (TSD) generation circuitry.
POR circuitry monitors the voltages that S.A.B.Re needs to guarantee its own functionality;
nRESET circuitry controls if S.A.B.Re’s main voltages are inside their normal range; TSD is
the thermal shut down of the chip in case of overheating.
5.2
Power on reset (POR) circuit
Power on reset circuit monitors VSupply, and V3v3 voltages. The purpose of this circuit is to
set the device is in a stable and controlled status until the minimum supply voltages that
guarantee the device functionality are reached. The output signal of this circuit (in the
following indicated as “POR”) becomes active when VSupply or V3v3 go under their falling
threshold.
When POR output signal is active, all functions and all flags inside S.A.B.Re are set in their
reset state; once POR signal comes back from off state (meaning monitored voltages are
above their rising threshold), the power up sequence is re-initialized
.
Table 7.
Power on reset specifications
Parameter
Description
VSupply_POR_valid VSupply voltage for POR valid
5.3
Test condition
Min
InRESET = 1mA
4
VSupply falling
6
VSupply_POR_fall
VSupply POR
falling threshold
tSupply_POR_filt
VSupply POR
filter Time
V3V3_POR_fall
V3v3 POR falling threshold
V3V3 falling
V3V3_POR_rise
V3v3 POR
rising threshold
V3V3 rising
V3V3_POR_hys
t3V3_POR_filt
Typ
Max
Unit
V
9
V
3
µs
2.2
V
2.7
V
V3v3 POR hysteresis
0.5
V
V3v3 PORfilter time
1.5
µs
1.9
nRESET generation circuit
The nRESET circuit monitors VSupply, VSupply_int, VPump, VGPIO_SPI and all system
regulators (VSystem) voltages. The purpose of this circuit is to prevent the device
functionality until the monitored voltages reach their operative value (please note that V3v3
19/141
Supervisory system
SABRE-LL-I
is monitored by POR, so it must be above its minimum value, otherwise nRESET circuit is
not active).
This circuit generates an internal reset signal (in the following indicated as “nRST_int”) that
will also be signaled to external circuits by pulling low the nRESET pin.
The signal nRST_int becomes active in the following cases:
1.
When one of the following voltages is lower than its own under voltage threshold:
–
VSupply and VSupply_int.
–
VPump.
–
VSystem (all switching or linear system regulators voltages).
–
VGPIO_SPI.
2.
When watchdog timer counter (see Chapter 6) elapse the watchdog timeout time (only
if watchdog function is enabled).
3.
When S.A.B.Re is in “Low Power mode”.
4.
When EnExtSoftRst bit in SoftResReg register is at logic level = “1” and a “SoftRes”
command is applied (see SoftResReg register description in Chapter 25).
When an nRST_int event is caused by above cases, the nRESET pin will stay low for a
“stretch” time that starts from the moment that nRST_int signal returns in the operative
state. This stretch time can be selected by setting the ID[1:0] bits in the SampleID register
according to following table:
Table 8.
Stretch time selection
Selected stretch time
ID[1]
ID[0]
Note
Typ
0
0
16ms
0
1
32ms
1
0
48ms
1
1
64ms
Default state
When nRST_int becomes active (logic level = “0”) it sets in their reset state some of the
functions inside S.A.B.Re. The main functions that will be reset by nRST_int signal are the
following:
20/141
–
Serial interface will be reset and will not accept any other command.
–
The bridges 1 and 2 will place their outputs in high impedance and PWM and
direction signals will be reset.
–
Not system regulators will be powered off.
–
AD converter will be powered off.
–
GPIOs will be powered off.
–
Current DAC will be powered off.
–
Operational amplifiers will be powered off.
–
Watchdog count will be reset (while Watchdog flags won’t be reset).
–
Interrupt controller will be powered off.
–
Digital comparator will be powered off.
SABRE-LL-I
Supervisory system
Additionally the system regulators will be powered off but only if the voltage that caused the
nRST_int event is checked before the system regulator in the power up sequence. This
means that:
5.4
–
all system regulators will be powered off if nRST_int is caused by VSupply,
VSupply_int, VPump (and also if V3v3 causes a POR);
–
no one of the system regulators will be powered off if nRST_int is caused by
VGPIO_SPI;
–
only the system regulators that follows the system regulator that caused the
nRST_int in power up sequence will be powered off.
nRESET specifications
Table 9.
nRESET circuit specifications
Parameter
nRST_VOL
Description
nRESET Low level output
voltage
nRST_fall
nRESET fall time
nRST_del
nRESET delay time
VSupply_UV_f
VSupply falling threshold
VSupply_UV_r
VSupply rising threshold
VSupply_UV_hys
Test
condition
Min
Max
Unit
I=10mA
0.4
V
I=1mA
C=50pF(1)
15
ns
(2)
150
ns
18.5
VSupply UV filter time
VS_Int_UV_f
VSupplyInt falling threshold
VS_Int_UV_r
VSupplyInt rising threshold
V
23
VSupply hysteresis
tSupply_UV
Typ
V
2
V
3.5
us
14.0
V
17.5
V
VSupplyInt hysteresis
1.5
V
tS_Int_UV
VSupplyInt UV filter time
3.5
µs
VPump_UV_f
VPump falling threshold
VPump_UV_r
VPump rising threshold
VS_Int_UV_hys
VPump_UV_hys
tPump_UV
VSupply
+7
V
VSupply
+ 9.5
V
VPump hysteresis
1.5
V
VPump UV filter time
3.5
us
VGPIO_SPI_UV_f
VGPIO_SPI falling threshold
1.8
V
VGPIO_SPI_UVr
VGPIO_SPI rising threshold
VGPIO_SPI_hys
VGPIO_SPI hysteresis
250
mV
tGPIO_SPI_UV
VGPIO_SPI UV filter time
3.5
us
2.4
V
1. Measured between 10% and 90% of output voltage transition.
2. Measured from a fault detection to 50% of output voltage transition.
21/141
Supervisory system
SABRE-LL-I
Figure 3.
nReset generation circuit
V Supply
UV comparator
UV Filter
V SupplyInt
V SupplyUV
V SupplyIntUV
UV comparator
Filter
Low Power
Mode
nRST_in
UV Filter
nRESET
pin
V Pump
nRESET
pin Driver
V PumpUV
UV comparator
UV Filter
UV comparator
V SysY
POR
SystemregulatorsUV
UV comparator
UV Filter
to SPI
Note:
22/141
WatchDog
Elapsed
UV Filter
WD_En_nRst
V SysX
nGateCtrl
All regulator voltages included in power up sequence (VSysX – VSysY in Figure 3) will be
considered as nRESET circuit voltages.
SABRE-LL-I
5.5
Supervisory system
Thermal shut down generation circuit
The third component of the supervisory circuit is the thermal shut down generation circuit.
This circuit generates two different flags depending on the IC temperature:
–
the “TSD” flag indicates that the IC temperature is greater than the maximum
allowable temperature.
–
the “Warm” flag, that can be read using serial interface, becomes active at a lower
temperature respect to TSD signal, therefore it can be used to prevent the IC from
reaching over temperature.
When a TSD event occurs, S.A.B.Re will enter in the reset state placing the bridges in high
impedance and turning off all regulators and other circuits until the internal temperature
decreases below the Warm temperature. At this point, S.A.B.Re will restart the power up
sequence and TSD bit will be set and will be readable as soon as S.A.B.Re will come out
from the reset state.
This TSD bit can be reset in three ways:
–
by writing a logic level ‘1’ in the ClearTSD bit in the ICTemp register (see
Chapter 25);
–
by a POR event;
–
by entering in “Low Power Mode”.
The Warm bit, set by S.A.B.Re when IC is working over the warming temperature, can be
read using the SPI interface. Once this bit is set it can be reset in three ways:
–
by writing a logic level ‘1’ in the ClearWarm bit;
–
by a POR event;
–
by entering in “Low Power Mode”.
The thermal sensor voltage can be converted using the internal A/D: this way the
microcontroller can directly measure the IC temperature.
To avoid unwanted commutation especially when temperature is near the thresholds, the
output signal is filtered for both TSD and Warm.
5.6
TSD specifications
Table 10.
TSD circuit specifications
Parameter
TTSD
TWARM
TDIFF
tTSD_FILT
tWARM_FILT
Description
Test
condition
Min
Typ
Max
Unit
Thermal shut down temperature
170
°C
Warming temperature
140
°C
Thermal shut down to warming
difference
30
°C
Thermal shut down filter time
8
us
Warming filter time
8
us
23/141
Watchdog circuit
SABRE-LL-I
6
Watchdog circuit
6.1
Overview
The Watchdog timer can be used to reset S.A.B.Re if it is not serviced by the firmware that
can periodically write at logic level “1’ the ClrWDog bit in the WatchDogStatus register.
This circuit is disabled by default; firmware can enable it by setting at logic level ‘1’ the
WDEnable bit in the WatchDogCfg register.
When the Watchdog timeout event happens, S.A.B.Re sets to ‘1’ a latched bit WDTimeOut
in theWatchDogStatus register that can be read using SPI interface; once this bit is set it
can be cleared in three ways:
–
by writing a ‘1’ in the WDClear bit in the WatchDogStatus register.
–
by writing a ‘1’ in the SoftReset bit in the WatchDogStatus register.
–
by a POR event.
The Watchdog function includes also a warning bit WDWarning to indicate, via serial
interface or via the circuit called Interrupt Controller (see Chapter 21) that the watchdog is
near to its timeout; this bit is asserted to logic level “1” exactly one watch dog clock period
(WD_Tclk) before the watchdog timeout happens. Firmware can enable the WDTimeOut
signal to cause an “nRst_int” event by setting to logic ‘1’ the WDEnnRst bit.
To SPI
WD_req_nRst
To nRSTint
generation circuit
WD_En_nRst
WDdelay[3:0]
WD_clk Watchdog counter
WDTimeOut
Frequency divider
WDWarning
Fosc
WDEnable
Watchdog circuit block diagram
ClrWDog
Figure 4.
The watchdog timeout has an imprecision of maximum one WD_Tclk. The effective
programmed WD time is changed in the register only when the watchdog circuit is serviced
by firmware with ClrWDog bit. At this time the watchdog timer is reset and the new value of
the WD delay value is loaded.
The watchdog timer can be programmed to generate different timeouts using the
WDdelay[3:0] bits in the WatchDogCfg register according to following table:
24/141
SABRE-LL-I
Watchdog circuit
Table 11.
Watchdog timeout specifications
WD timeout
WDdelay[3:0]
Typ
6.2
0000
8*WD_Tclk
0001
9*WD_Tclk
0010
10*WD_Tclk
0011
11*WD_Tclk
0100
12*WD_Tclk
0101
13*WD_Tclk
0110
14*WD_Tclk
0111
15*WD_Tclk
1000
16*WD_Tclk
1001
17*WD_Tclk
1010
18*WD_Tclk
1011
19*WD_Tclk
1100
20*WD_Tclk
1101
21*WD_Tclk
1110
22*WD_Tclk
1111
23*WD_Tclk
Watchdog specifications
Table 12.
Parameter
WD_Tclk
Watchdog specifications
Description
Watchdog clock period
Test condition
Min
Typ
Tosc * 222
Max
Unit
s
25/141
Internal clock oscillator
SABRE-LL-I
7
Internal clock oscillator
7.1
Overview
S.A.B.Re includes a free running oscillator that does not require any external components.
This circuit is used to generate the time base needed to generate the internal timings; the
typical frequency is 16MHz.
The oscillator circuit starts as soon as the IC exits from the power on reset condition and it is
stopped only when in “Low Power mode”.
7.2
Internal clock specifications
Table 13.
Parameter
26/141
Internal clock specifications
Description
Fosc
Oscillator frequency
Tosc
Oscillator period
Test condition
Min
Typ
Max
Unit
V3V3 =3.3V
14.4
16
17.6
MHz
1/Fosc
SABRE-LL-I
Start-up configurations
8
Start-up configurations
8.1
Overview
S.A.B.Re start-up configuration is selected by setting in different states the GPIO[0],
GPIO[3] and GPIO[4] pins. Each of these is a three state input pin and is able to distinguish
among the following situations:
Table 14.
Possible start-up pins state symbol
Pin condition
State symbol
Shorted to ground
0
Shorted to V3v3 pin
1
Floating
Z
Note: “Shorted” means: R≤1KOhm; “Z” means: R≥10KOhm, C≤200pF
8.2
Operation modes
When VSupply voltage is applied to S.A.B.Re, the internal regulator V3v3, used to supply the
logic circuits inside the device, starts its functionality. When it reaches its final value,
S.A.B.Re enables the GPIO[0] pin state read circuitry, and, after a time TpinSample, it will
sample the GPIO[0] state. If it is found to be in high impedance, S.A.B.Re does not consider
GPIO[3] and GPIO[4] pins state and starts its “Basic device” mode sequence. If GPIO[0] is
found to be connected to ground or to V3v3, S.A.B.Re checks the state of GPIO[3] and
GPIO[4] pins to select its start-up configuration.
The possible configurations can be classified in four “Major” modes:
1.
Basic device.
2.
Slave device.
3.
Master device.
4.
Single device.
Hereafter is reported the correspondence table between GPIO[X] state and S.A.B.Re
configurations.
27/141
Start-up configurations
Table 15.
SABRE-LL-I
Start-up correspondence
Pin state(1)
Major mode
Minor mode(2)
GPIO[0]
GPIO[3]
GPIO[4]
Z
X
X
0
0
0
Bridge
0
0
Z
Primary regulator
0
0
1
Basic
Regulators
Single
0
Z
0
Simple regulator
0
Z
Z
Bridge + VEXT
0
Z
1
Secondary Regulators
0
1
0
Bridge
0
1
Z
Primary regulator
0
1
1
Regulators
Master
1
0
0
Simple regulator
1
0
Z
Bridge + VEXT
1
0
1
Secondary Regulators
1
Z
0
Bridge
1
Z
Z
Primary regulator
1
Z
1
Regulators
Slave
1
1
0
Simple regulator
1
1
Z
Bridge + VEXT
1
1
1
Secondary Regulators.
1. “X” means “don’t care”.
2. The description of these modes is in the following paragraph 9.7.
8.3
Basic device mode
The basic device mode is selected by leaving the GPIO[0] pin floating. In this mode
S.A.B.Re doesn’t use GPIO[3] and GPIO[4] as configuration pins, leaving them free for
other uses.
When in this mode the regulators included in the start up sequence (except VMAIN_SW) are
considered as system regulators and they start in the following sequence:
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1.
Auxiliary switching regulator1 (VAUX1_SW).
2.
Auxiliary switching regulator2 (VAUX2_SW).
3.
Main linear regulator (VMAIN_LIN).
4.
Main switching regulator (VMAIN_SW) (Not system regulator).
SABRE-LL-I
8.4
Start-up configurations
Slave device mode
In slave device mode, S.A.B.Re consider the nAWAKE pin as an input enable. Since this is
now a digital pin, the current pull up source inside the nAWAKE circuit is disabled.
At the startup, if the nAWAKE pin is found to be low for a period higher than tAWAKEFILT
seconds, S.A.B.Re enters directly in the “Low Power mode”; when nAWAKE pin is pulled
high for a period higher than tAWAKEFILT seconds, S.A.B.Re begins its start up procedure.
8.5
Master device mode
In master device mode, S.A.B.Re begins its start up procedure without waiting for any
external enable signal and it uses GPIO[5] pin to drive the nAWAKE pin of Slave devices.
During the whole start up time, it forces its GPIO[5] pin at logic level “0” in order to maintain
all slave devices in “Low Power mode” as previously described. When start up operations
are completed, S.A.B.Re forces the GPIO[5] output to logic level “1” to enable the slave
devices and keeps GPIO[5] output at high level until it senses an under-voltage on any of its
System regulators. If firmware writes in the PwrCtrl register to set Master S.A.B.Re in “Low
Power mode” it immediately forces GPIO[5] output to logic level “0” to force the slave
devices to enter in “Low Power mode”, then it waits for TMASTWAIT time and it starts its “Low
Power mode” sequence.
8.6
Single device mode
In single device mode, the device behaves similarly to master device mode but:
8.7
1.
It doesn’t use the GPIO[5] pin to drive slave devices.
2.
It doesn’t wait for TMASTWAIT before entering in “Low Power mode”.
Sub-configurations for slave, master or single device modes
Each slave, master or single device modes can be divided in other minor modes depending
on the start-up sequence needed for S.A.B.Re internal regulators.
Unless otherwise specified, in all the following modes the regulators included in the start up
sequence are considered system regulators and they start in the sequence indicated.
8.7.1
Bridge mode
In this configuration bridges 3 and 4 are not used as regulators and therefore can be
configured by the firmware in any of their possible bridge modes.
When in this mode the power-up sequence is:
8.7.2
1.
Main switching regulator (VMAIN_SW).
2.
Main linear regulator (VMAIN_LIN).
Primary regulator mode (KP)
In this configuration bridge 4 can be configured by firmware while bridge 3 is configured as
two separate synchronous switching regulators. The last regulator in the sequence
(VAUX2_SW).is not considered a system regulator.
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Start-up configurations
SABRE-LL-I
When in this mode the power-up sequence is:
8.7.3
1.
Auxiliary switching regulator1 (VAUX1_SW).
2.
Main switching regulator (VMAIN_SW) together with main linear regulator (VMAIN_LIN).
3.
Auxiliary switching regulator2 (VAUX2_SW) (Not system regulator).
Regulators mode
In this configuration bridge 4 can be configured by firmware while bridge 3 is configured as
two separate synchronous switching regulators, but the start up sequence is different
previous one.
When in this mode the power-up sequence is:
8.7.4
1.
Main switching regulator (VMAIN_SW).
2.
Auxiliary switching regulator1 (VAUX1_SW)
3.
Auxiliary switching regulator2 (VAUX2_SW)
Simple regulator mode (KT)
Also in this configuration Bridge 4 can be configured by firmware while Bridge3 is configured
as two separate synchronous switching regulators. The last regulator in the sequence
(VMAIN_SW).is not considered a system regulator.
When in this mode the power-up sequence is:
8.7.5
1.
Auxiliary switching regulator1 (VAUX1_SW).
2.
Auxiliary switching regulator2 (VAUX2_SW)
3.
Main linear regulator (VMAIN_LIN)
4.
Main switching regulator (VMAIN_SW) (not system regulator).
Bridge+ VEXT mode
In this configuration bridges 3 and 4 are not used as regulators and the regulator obtained
using the switching regulator controller (VEXT) is included in start-up.
When in this mode the power-up sequence is:
8.7.6
1.
Main switching regulator (VMAIN_SW).
2.
Switching regulator controller regulator (VEXT).
3.
Main linear regulator (VMAIN_LIN).
Secondary regulators mode
In this configuration, bridge 3 is configured as a single synchronous switching regulator
using its two half bridges in parallel (VAUX_(1//2)SW).
When in this mode the power-up sequence is:
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1.
Main switching regulator (VMAIN_SW).
2.
Auxiliary switching regulator (VAUX(1//2)_SW).
3.
Main linear regulator (VMAIN_LIN).
SABRE-LL-I
Power sequencing
9
Power sequencing
9.1
Overview
As soon as VSupply and VSupplyInt are above their power on reset level, S.A.B.Re will start
the charge pump circuit; once VPump voltage reaches its under voltage rising threshold,
S.A.B.Re begins a sequence that starts the regulators considered system regulators.
A regulator is considered a System regulator if:
–
It has to start in on state without any user action.
–
It is included in the power-up sequence.
–
Its under-voltage event is considered by S.A.B.Re as an error condition to be
signaled through nRESET pin.
Once VSupply and VSupplyInt, VPump and all the system regulators are over their under
voltage rising threshold, S.A.B.Re enters in the normal operating state, that will release
nRESET pin and will wait for SPI commands.
S.A.B.Re will reduce the noise introduced in the system by switching out of phase all its
power circuits (switching regulators, bridges and charge pump).
The S.A.B.Re's startup sequence of operation is the following:
–
start V3v3 internal linear regulator
–
sample startup configuration
–
wait enable if slave device
–
start charge pump
–
start system regulators (see order in Section 8.7)
–
send enable to slave device, if master
–
wait until VGPIO_SPI becomes ok
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Power saving modes
SABRE-LL-I
10
Power saving modes
10.1
Overview
Saving power is very important for today platforms: S.A.B.Re implements different functions
to achieve different levels of power saving.
Sections here below describe these different power saving modes.
10.2
Standby mode
Almost all low voltage circuitry inside S.A.B.Re are powered by V3v3 internal regulator; this
regulator is a linear regulator powered by VSupplyInt. This means that all the current provided
by V3v3 regulator is directly coming from VSupplyInt and therefore the total power
consumption is:
Low voltage power = VSupply* IV3v3.
because VSupplyInt is feeded by VSupply, directly or with a resistor in series.
This power could be reduced by using a switching buck regulator to supply V3v3: in this
case, assuming the buck regulator efficiency near to 100%, the dissipated power would
become:
Low voltage power ≈ 3.3V * IV3v3.
To achieve this result there is the need to switch off the internal V3v3 linear regulator and to
use an additional pin to provide a 3.3V supply to internal circuits. S.A.B.Re can do this by
using the low voltage switch implemented on GPIO6 pin. This switch internally connects
VGPIOSpi voltage to GPIO6 output so, by externally connecting GPIO6 to V3v3 pin, the
VGPIOSpi voltage can be provided to low voltage circuitry inside S.A.B.Re.
Figure 5.
Standby mode function description
Power Switch 1
VSupplyInt
StdByMode
3.3 V
1.9 V
0
+
1
GPIO6
External
connection
3.3V
-
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V3v3
Regulator
VGPIOSpi
SABRE-LL-I
Power saving modes
The StdByMode bit used to switch off V3v3 and switch on the power switch can be set to ‘1’
by writing the standby command in the StdByMode register. S.A.B.Re exits standby mode if
a reset event happens or “Low Power mode” is selected.
Because all internal low voltage circuitry powered by V3v3 are designed to work with a 3.3V
voltage rail, when the standby mode is used, VGPIOSpi is requested to be at 3.3V.
10.3
Hibernate mode
S.A.B.Re’s hibernate mode allows the firmware to switch off some (or all) selected System
Regulators leaving in on state only those necessary to resume S.A.B.Re to operative
condition when waked-up by an external signal.
Hibernate mode is selected when the firmware writes the command word in the
HibernateCmd register. When in hibernate mode S.A.B.Re will force regulators in the state
(on/off) selected by the firmware by writing in the HibernateCmd register and will force
nRESET pin low.
The exiting from hibernate mode is achieved by forcing at low level nAWAKE pin (or GPIO5
pin if S.A.B.Re is in Slave mode); S.A.B.Re will also exit from hibernate mode if an
undervoltage event happens on VSupply, VSupplyInt, VPump or V3v3.
When the exit from hibernate mode is due to an external command, S.A.B.Re sets to ‘1’ the
bit HibModeLth in the HibernateStatus register.
10.4
Low power mode
When in normal operating mode, the microcontroller can place S.A.B.Re in “Low Power
mode”.
In this condition S.A.B.Re sets all bridges outputs in high impedance, powers down all
regulators (including system regulators and charge pump) and disables almost all its circuits
including internal clock reducing as much as possible power consumption.
The only circuits that remain active are:
–
V3V3 internal regulator.
–
nAWAKE pin current pull-up.
–
nRESET pin that will be pulled low.
–
POR circuit.
The entering in low power mode is obtained in different ways depending if S.A.B.Re is
configured as slave device or not. When S.A.B.Re is configured as slave device the low
power mode is directly controlled by nAWAKE pin that acts as an enable: if this pin is low for
a time longer then tAWAKEFILT, Low Power mode is entered; if this pin is high S.A.B.Re exits
from Low Power mode.
In all other start-up configurations, Low Power mode is entered by writing a Low Power
mode command in the PowerModeControl register; once S.A.B.Re is in Low Power mode it
starts checking the nAWAKE pin status: if it is found low for a time longer than tAWAKEFILT,
S.A.B.Re exits from Low Power mode and restarts its startup sequence. When the
nAWAKE pin is externally pulled low, the “AWAKE” event is stored and it is readable
through SPI. S.A.B.Re will also exit from Low Power mode if a POR event is found.
Note:
When in “Low power mode” VSupply is monitored only for its power on reset level.
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Power saving modes
10.5
SABRE-LL-I
nAWAKE pin
At the start up, before S.A.B.Re has identified the required operation mode (see Chapter 8),
a current sink IINP is always active to pull down nAWAKE pin. As soon as the operation
mode (basic, slave, master or single device) is detected, the functionality of nAWAKE pin
will be different.
If S.A.B.Re is not configured as Slave device a current source IOUT will be active on this
pin, while the current sink IINP will be disabled. If S.A.B.Re is configured as a Slave device,
the current sink IINP will be active until nAWAKE pin is detected high for the first time; after
that both current sources IINP and IOUT will be disabled and the nAWAKE pin can be
considered as a digital input.
Here below is reported the nAWAKE pin simplified schematic.
Figure 6.
nAWAKE function block diagram
V 3v3
SlaveMode
I OUT
AWAKE_req
AWAKE
nAWAKE seen high
for the first time after
start up.
Table 16.
Parameter
nAWAKE function specifications
Description
VIL
nAWAKE logic low threshold
VIH
nAWAKE logic high threshold
VHYS
nAWAKE input hysteresys
IOUT
nAWAKE pin output current
IINP
tAWAKEFILT
I INP
nAWAKE pin input current
Test condition
Typ
Max
Unit
0.8
V
1.6
V
0.25
nAWAKE=0V(1)
nAWAKE=0.8V
Filter time
1. Current is defined to be positive when flowing into the pin.
34/141
Min
)
V
- 0.72
-2
mA
0.2
0.4
mA
(1
1.2
ns
SABRE-LL-I
Linear main regulator
11
Linear main regulator
11.1
Overview
The linear main regulator is directly powered by VSupply voltage and it is one of the
regulators that S.A.B.Re could consider as a system regulator. This means that the voltage
generated by this regulator is not used to power any internal circuit, but S.A.B.Re will check
that the feedback voltage VLINmain_FB is in the good value range before enabling all its
internal functions. When an under-voltage event (with a duration longer than period
Tlinear_uv defined by the deglitch filter) is detected during normal operation, S.A.B.Re will
enter in reset state and it will signal this event to the microcontroller by pulling low the
nRESET pin and disabling most of its internal blocks.
Here are summarized the primary features of the regulator:
–
Regulated output voltage from 0.8V to VSupply-2V with a maximum load of 10mA.
–
Band gap generated internal reference voltage.
–
Short circuit protected (output current is clamped to 22mA typ).
–
Under voltage signal (both continuous and latched) accessible through serial
interface.
–
Low power dissipation mode.
The internal series element is a P-channel MOS device. The voltage regulator will regulate
its output so that feedback pin equals VLINmain_FB, therefore the regulated voltage can be
calculated using the formula:
VLINmain_OUT = VLINmain_ref *(Ra+Rb)/Rb
Figure 7.
Linear main regulator
V supply
Body Diode
V LINmain_OUT
Driver
Cc
Ra
+
V LINmain_FB
-
V LINmain_ref
Rb
To extend the output current capability this regulator can be used as a controller for an
external active component able to provide higher current (i.e. a Darlington device); the
external power element allows the handling of an higher current since it dissipates the
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Linear main regulator
SABRE-LL-I
power externally (the power dissipated by a linear driver supplied at VSupply and regulating a
voltage VLINmain_OUT with an output current IOUT is about: Pd= (VSupply-VLINmain_OUT)*IOUT.
Figure 8.
Linear main regulator external bipolar example
V supply
Body Diode
VLINmain_OUT
Driver
Cc
Cload
Ra
+
VLINmain_FB
-
VLINmain_Ref
Rb
Whichever configuration is used (regulator or controller), a ceramic capacitor must be
connected on the output pin towards ground to guarantee the stability of the regulator; the
value of this capacitance is in the range of 100nF to 1µF depending on the regulated
voltage.
When this regulator is disabled, the whole circuit is switched off and the current
consumption is reduced to a very low level both from V3v3 and from VSupply. When in this
condition, the output pin is pulled low by an internal switch.
Table 17.
System linear regulator operating specifications
Parameter
VLINmain_OUT
Vdrop
IPD
36/141
Description
Output pin
voltage range
Drop out voltage
Internal switch pull
down current
Test condition
Min
(1)
0
Vdrop=
Vsupply-VLINmain_OUT
2
Linear Main Regulator
disabled;
VLINmain_OUT=1V
Typ
Max
Unit
VSupply
V
V
3
VLINmain_FB
Feedback pin voltage
range
VLINmain_Ref
Feedback reference
voltage
0.776
ILINmain_Ref
Feedback pin input
current
-2
0
0.8
mA
3.6
V
0.824
V
2
µA
SABRE-LL-I
Linear main regulator
Table 17.
System linear regulator operating specifications (continued)
Parameter
IoutLinMax
Ishort
∆Vout/Vo
∆Vout/∆VSupply
Vloop_acc
Description
Maximum Output
current
Output short
circuit current
Load regulation
Line regulation
Test condition
Min
Regulated voltage =
Vsupply-2V
10
VLINmain_OUT =0V,
VLINmain_FB =0V
12
Typ
Max
mA
24
mA
0 ≤ Iload ≤ IoutLinMax(2)
(2)
Iload =10mA
Loop voltage accuracy
Unit
0.8
%
0.2
%
±2.5
%
VuvFall
Under voltage
falling threshold
(3)
84.5
87
89.5
%
VuvRise
Under voltage
rising threshold
(3)
90.5
93
95.5
%
Vuvhys
Under voltage
hysteresis
(3)
tprim_uv
Under voltage
deglitch filter
CC
Compensation
capacitance
VLINmain_OUT =0.8V
0.8V<VLINmain_OUT < 2.5V
2.5V=VLINmain_OUT ≤ 5V
VLINmain_OUT > 5V
6
%
5
us
1
0.68
0.33
0.1
µF
1. The external components connected to the pin must be chosen to avoid that the voltage exceeds this
operative range.
2. Load regulation is calculated at a fixed junction temperature using short load pulses covering all the load
current range. This is to avoid change on output voltage due to heating effect.
3. Undervoltage rising and falling thresholds are intended as a percentage of feedback pin voltage
(VLINmain_Ref).
37/141
Main switching regulator
SABRE-LL-I
12
Main switching regulator
12.1
Overview
Main switching regulator is an asynchronous switching regulator intended to be the source
of the main voltage in the system. It implements a soft start strategy and could be a system
regulator so even if its output voltage VMAIN_SW is not used to power any internal circuit,
S.A.B.Re will check that it is in the good value range before enabling all its internal
functions. When S.A.B.Re detects a system regulator under-voltage event with a duration
longer than the period defined by the deglitch filter (Tprim_uv), it will enter in reset state
signaling this event to the microcontroller by pulling low the nRESET pin and disabling most
of its internal block (e.g. bridges, GPIOs, …).
The output voltage will be externally set by a divider network connected to feedback pin. To
reduce as much as possible the regulation voltage error S.A.B.Re has the possibility to
choose between four feedback voltage references (and, as a consequence, four undervoltage thresholds) using the serial interface. The feedback reference voltage selection is
made by writing the SelFBRef bits in the MainSwCfg register according to the table here
below:
Table 18.
Switching regulator controller PWM specification
MainSwCfg register
Reference voltage (VFBREF)
Unit
SelFBref[1]
SelFBref[0]
Min
Typ
Max
0
0
0.776
0.8
0.824
V
0
1
0.97
1
1.03
V
1
0
2.425
2.5
2.575
V
1
1
2.910
3
3.09
V
Comments
Default state
Reference voltage range can be changed by using a metal layer change in order to adapt
them to customer system.
Here after are summarized the primary features of this regulator:
–
Internal power switch.
–
Soft start circuitry to limit inrush current flow from primary supply.
–
Internally generated PWM (250kHz switching frequency).
–
Nonlinear pulse skipping control.
–
Protected against load short circuit.
–
Cycle by cycle current limiting using internal current sensor.
–
Under voltage signal (both continuous and latched) accessible through SPI.
When S.A.B.Re is in “Low Power mode”, this regulator will be disabled.
In order to save external components and power when using two or more S.A.B.Re IC’s on
the same board, the primary switching regulator can be disabled by serial interface. Care
must be paid using this function because an under-voltage on this regulator, as previously
seen, will be read as a fault condition by S.A.B.Re.
38/141
SABRE-LL-I
12.2
Main switching regulator
Pulse skipping operation
Pulse skipping is a well known, non linear, control strategy used in switching regulators.
In this technique (see Figure 9) the feedback comparator output is sampled at the beginning
of each switching cycle. At this time, if the sampled value shows that output voltage is lower
than requested one, the complete PWM duty cycle is applied to power switch; otherwise no
PWM is applied and the switching cycle is skipped. Once PWM is applied to power element
only a current limit event can disable the power switch before the whole duty cycle is
finished.
Figure 9.
Main switching regulator functional blocks
VSupply
Current Sense
Charge pump Voltage
High Side
Driver
VSWmain_SW
La
Ra
C
Voltage
From Central Logic
Loop Control
Control
Logic
+
VSWmain_FB
Rb
Regulator Freq
Regulator Ref
Under voltage flag
Filter
To Central Logic
+
Under voltage
Threshold
In pulse skipping control the duty cycle must be chosen by the user depending on supply
voltage and output regulated voltage. Therefore the switching regulator has 4 possible duty
cycles that can be changed by writing the VmainSwSelPWM bits in the MainSwCfg register
according to following table.
Table 19.
Main switching regulator PWM specification
MainSwCfg register
Duty cycle value
VmainSwSelPWM[1:0]
Typical
00
12%
01
15%
10
26%
11
63.5%
Comments
Default state
Adjustable duty cycles can be changed by a metal layer change in order to adapt it to
customer system. The only limitation is that all regulators share the same duty cycle bus, so
any modification must consider all regulators duty cycles.
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Main switching regulator
SABRE-LL-I
The output current is limited to a value that can be set by means of selilimit bit in the
MainSwCfg register according to following table:
Table 20.
Main switching regulator current limit
SelIlimit
Current limit (min)
Comments
0
3.3A
Default state
1
2.3A
Table 21.
Parameter
Main switching regulator specifications
Description
Test condition
Min
(1)
Max
Unit
-1
Vsupply
V
Output leakage current
Tjunction = 125°C
-40
+40
µA
IQlp
Output leakage current in
“Low Power Mode”
VSupply = 36V
Tjunction = 125°C
-15
+5
µA
IQfb
Feedback pin current
Tjunction = 125°C
-10
+0
µA
Vout
Output voltage range
(2)
0.8
5
V
Iload
Output load current
VSupply = 36V
0.002
3
A
RonH
Internal high side RDson
0.55
O
Vloop
Loop voltage accuracy
VregR
Output voltage ripple
(RMS)
VuvFall
Under voltage falling
threshold
(4)
84.5
87
89.5
%
VuvRise
Under voltage rising
threshold
(4)
90.5
93
95.5
%
Vuvhys
Under voltage hysteresys
6
%
tprim_uv
Under voltage deglitch
filter
5
us
Ilimit
Current limit protection
VMAIN_SW Output pin voltage range
IQ
tdeglitch
Iload=1A
Tjunction = 125°C
±3%
L =150u,
C=330µF/ESR=0.54Ω
28
mVRMS
(3)
SelIlimit =”0”
SelIlimit =”1”
Current limit deglitch time
3.3
2.3
5
3.5
TBD
TBD
50
A
A
ns
tI_lim
Current limit response time
In normal operating
mode (no UV)(5)
650
ns
tI_limUV
Current limit response time
in UV condition.
When in
Under Voltage(6)
400
ns
tr
Switching output rise time
VSupply = 36V, Resistive
load to gnd = 422 Ω(7)
5
30
ns
tf
Switching output fall time
VSupply = 36V, Resistive
load to gnd = 10 Ω(7)
5
30
ns
FregPwm
40/141
Typ
Operating frequency
Fosc/64
kHz
SABRE-LL-I
Main switching regulator
1. The external components connected to the pin must be chosen to avoid that the voltage exceeds this
operative range.
2. The regulated voltage can be calculated using the formula: VMAIN_SW = VFBREF *(Ra+Rb)/Rb.
3. The choice of proper values for L and C depends from the application.
4. Undervoltage rising and falling thresholds are intended as a percentage of feedback pin voltage
(VSW_main_FB).
5. This condition is intended to simulate an extra current on output.
6. This condition is intended to simulate a short circuit on output.
7. Rise time is measured between 10% and 90% of supply voltage.
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Switching regulator controller
SABRE-LL-I
13
Switching regulator controller
13.1
Overview
This circuit controls an external FET to implement a switching buck regulator using a non
linear pulse skipping control with internally generated PWM signal.
The output voltage will be externally set by a divider network connected on feedback pin. To
reduce as much as possible the regulation voltage error S.A.B.Re has the possibility to
switch between four regulator feedback voltage references (and, as a consequence, four
under-voltage thresholds) using serial interface. The feedback reference voltage is selected
by writing the SelFBRef bits in the SwCtrCfg register according to the following table.
Table 22.
Switching regulator controller PWM specification
SwCtrCfg register
Reference voltage (VFBREF)
Unit
SelFBref[1]
SelFBref[0]
Min
Typ
Max
0
0
0.776
0.8
0.824
V
0
1
0.970
1
1.030
V
1
0
2.425
2.5
2.575
V
1
1
2.910
3
3.09
V
Comments
Default state
Adjustable feedback voltages can be changed using a metal layer change in order to adapt
it to customer system.
This regulator is switched off when S.A.B.Re is powered up for the first time and can be
enabled using S.A.B.Re’s SPI interface.
Here after are summarized the main features of the regulator:
42/141
–
Soft start circuitry to limit inrush current flow from primary supply.
–
Changeable feedback reference voltage
–
Internally generated PWM (250kHz switching frequency).
–
Nonlinear pulse skipping control.
–
Protected against load short circuit.
–
Cycle by cycle current limiting using internal current sensor.
–
Under voltage signal (both continuous and latched) accessible through SPI.
SABRE-LL-I
Switching regulator controller
Figure 10. Switching regulator controller functional blocks
V supply
Rsense
CurrentSense
V SWDRW_sns
Charge pump Voltage
N-CH Fet
Driver
V SWDRV_gate
V SWDRV
La
Ra
SW
V out
Voltage
C
Loop Control
Control
Logic
From Central Logic
+
SelFBRef[1:0]
V SWDRV
FB
Regulator Freq
Rb
Analog Mux
Vref = 3 V
Vref = 3V
Vref=0.8V
VFBRef
Vref=0.8V
undervoltage flag
+
Filter
To Central Logic
Analog Mux
SelFBRef
Uv Threshold 1
Uv Threshold 2
13.2
Under voltage
Threshold
Pulse skipping operation
Pulse skipping strategy has already been explained on main switching regulator section.
This regulator has 4 possible PWM duty cycles that can be changed writing in the
SelSwCtrPWM bits in the SwCtrCfg register using SPI.
Table 23.
Switching regulator controller PWM specification
SwCtrCfg register
Duty cycle value
SelSwCtrPWM[1:0]
Typical
00
9%
01
12%
10
22.5%
11
58%
Comments
Default state
Adjustable duty cycles can be changed using a metal layer change in order to adapt it to
customer system. The only limitation is that all regulators share the same duty cycle bus, so
any modification must consider all regulators needed duty cycles.
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Switching regulator controller
13.3
SABRE-LL-I
Output equivalent circuit
The switching regulator controller output driving stage can be represented with an
equivalent circuit as in the figure below:
Figure 11. Switching regulator controller output driving equivalent circuit
VPUMP
I SOURCE
Source command
Tsink
V SWDRV_gate
Sink pulse command
RSUSTAIN
Sink command
I SINK
V SWDRV_SW
As can be seen from the above figure, the external switch gate is charged with a current
generator ISOURCE and it is discharged towards ground with a current generator ISINK that is
applied for a TSINK pulse while an equivalent resistor RSUSTAIN is connected between gate
and source until the sink command is present.
The table here below lists the values of the above mentioned parameters:
Table 24.
Parameter
ISOURCE
Description
Source current
ISINK
Sink current
tSINK
Sink discharge pulse time
RSUSTAIN
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Switching regulator controller operating specification
Gate-source sustain
resistance
Test condition
Min Typ
VPump=VSupply+12V
VSWCTR_GATE=0V
25
VSWCTR_GATE = VSupply
20
(VSWCTR_GATE - VSWCTR_SRC)
= 0.2V
Max
Unit
50
mA
mA
600
ns
650
Ω
SABRE-LL-I
13.4
Switching regulator controller
Switching regulator controller specifications
Table 25.
Parameter
Switching regulator controller operating specification
Description
VSWDRV_SW
VSWDRV_SW pin voltage
range
VSWDRV_GAT
Gate drive pin voltage
Max
Uni
t
-1
VSupply
V
0
VPump
V
VSupply
-3V
VSupply
V
Test condition
Min
(1)
Typ
E
VSWDRV_SNS Sense pin voltage
Vvgs_ext
Gate to source voltage for
ext FET
V
VPump
Output
leakage current
VSupply = 36V,
Tjunction = 125°C
-15
+15
µA
Output leakage current in
“Low Power Mode”
VSupply = 36V,
Tjunction = 125°C
-5
+5
µA
VSWDRV_FB
VSWDRV_FB pin current
VSupply = 36V,
Tjunction = 125°C
-10
+10
µA
Vloop
Loop voltage accuracy
IQ
IQlp
±3%
VuvFall(1)
Under voltage falling
threshold
84.5
87
89.5
%
VuvRise(1)
Under voltage rising
threshold
90.5
93
95.5
%
Vuvhys(1)
Under voltage hysteresys
6
%
tprim_uv
Under voltage deglitch filter
5
us
Vovc
tdeglitch
Over current threshold
voltage
250
Current limit deglitch time
50
300
350
mV
ns
tI_lim
Current limit response time
In normal operating
mode (no UV)(2)
900
ns
tI_limUV
Current Limit response time
in UV condition.
When in
Under Voltage(3)
550
ns
FregPwm
Operating frequency
Fosc/6
4
kHz
1. Under voltage rising and falling thresholds are referred to feedback pin voltage.
2. This condition is intended to simulate an extra current on output.
3. This condition is intended to simulate a short circuit on output.
13.5
Switching regulator controller application considerations
This controller can implement a step-down switching regulator used to provide a regulated
voltage in the range 0.8V – 32V. Such kind of variation could be managed by considering
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Switching regulator controller
SABRE-LL-I
some constraints in the application and particularly by choosing the correct feedback
reference voltage as indicated in the following table:
Table 26.
Switching regulator controller application feedback reference
Output regulated voltage range
Feedback voltage reference
0.8V ≤ Vout < 5V
0.8V - 1V
5V ≤ Vout ≤ 32V
2.5V - 3V
Typical application can be considered the following, supposing the external mosfet type
STD12NF06L:
–
Max DC current load = 3A
–
Typ Over current threshold = 3A * 1.5 = 4.5A
–
L = 150 µH
–
C = 220-330 µF
In this conditions the step-down regulator will result over-load protected, short-circuit
protected over all the regulated voltage range and the VSupply range.
Other application configurations could be evaluated before being implemented.
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SABRE-LL-I
Power bridges
14
Power bridges
14.1
Overview
S.A.B.Re includes four H bridge power outputs (each one made by two independent half
bridges) that are configurable in several different configurations.
Each half bridge is protected against: over-current, over-temperature and short circuit to
ground, to supply or across the load. When an over current event occurs, all outputs are
turned off (after a filter time), and the over current bit is stored in the internal status register
that can be read through SPI.
Positive and negative voltage spikes, which occur when switching inductive loads, are
limited by integrated freewheeling diodes (see Figure 12).
Figure 12. H Bridge block diagram
High side Driver
High side Driver
Control Logic
Control Logic
Low side Driver
Low side Driver
During the start up procedure the bridges are in high impedance and after that they can be
enabled through SPI. When a fault condition happens, i.e. an over-temperature event, the
bridges return in their start-up condition and they need to be re-enabled from the micro
controller.
The bridges can use PWM signals internally generated or externally provided (supplied
through the GPIO pins). Internally generated PWM signals will run at approximately
31.25kHz with a duty cycle that, through serial interface, can be programmed and
incremented in steps of 1/(512*Fosc). To reduce the peak current requested from supply
voltage when all bridges are switching, the four internally generated PWM signals are outof-phase.
Each half bridge will use the PWM signal selected by the respective
MtrXSelPWMSideY[1:0] (X stands for 1, 2, 3 or 4; Y stands for A or B) bits in the SPI, but if
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Power bridges
SABRE-LL-I
two half bridges are configured as a full bridge, only the PWM signal chosen for side A will
be used to drive the resulting H bridge.
More in detail the PWM selection truth table will be as describe in the following tables:
Table 27.
PWM selection truth for bridge 1 or 2
Selected PWM(1)
MtrXSelPWMSideY [1] MtrXSelPWMSideY [0]
0
0
MotorXPWM (Configurable by means of MtrXCfg
register).
0
1
AuxXPWM (Configurable by means of
AuxPwmXCtrl register).
1
0
ExtPWM1 (from GPIO 9 input)
1
1
ExtPWM2 (from GPIO 10 input)
1. In this table X stands for 1 or 2, Y stands for A or B.
Table 28.
PWM selection truth for bridge 3 or 4
MtrXSelPWMSideY [1] MtrXSelPWMSideY [0]
Selected PWM(1)
0
0
MotorXPWM (Configurable by means of
MtrXCfg register).
0
1
AuxXPWM (Configurable by means of
AuxPwmXCtrl register).
1
0
ExtPWM3 (from GPIO 2 input)
1
1
ExtPWM4 (from GPIO 11 input)
1. In this table X stands for 3 or 4, Y stands for A or B.
Here below is reported a block diagram representing the possible PWM choices for each
S.A.B.Re half bridges. The figure is related only to bridges 1 and 2, but it could be assumed
to be valid also for bridges 3 and 4, with few differences due to different possible
configurations of these last drivers.
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SABRE-LL-I
Power bridges
Figure 13. Bridge 1 and 2 PWM selection
00 Motor1 PWM
01 Aux1PWM
10 ExtPWM1
Motor 1 side A
Logic Table
11 ExtPWM2
Mtr1_2Parallel
Side A Power Section
Mtr1SelPWMSideA [1:0]
Mtr1SelPWMSideB [1:0]
01Aux1PWM
10ExtPWM1
11ExtPWM2
Motor 1 sideB
Logic Table
Bridge 1
Side B Power Section
Mtr1Tablel[1:0]
00 Motor1 PWM
Mtr1_2Parallel
Mtr2SelPWMSideA [1:0]
Motor 2 side A
Logic Table
Side A Power Section
Motor 2 sideB
Logic Table
Side B Power Section
Mtr2Tablel[1:0]
00 Motor2 PWM
01Aux2Pwm
10ExtPwm1
11ExtPwm2
Mtr2SelPWMSideA [1:0]
Mtr1_2Parallel
Mtr2Tablel[1:0]
00 Motor2 PWM
01 Aux2Pwm
10 ExtPwm1
11 ExtPwm2
Bridge 2
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Power bridges
14.2
SABRE-LL-I
Power bridges operating specifications
Table 29.
Parameter
Description
Test condition
RON_1_2
Bridge 1 and 2 diagonal Ron
I = 1.4A, VSupply = 36V,
Tjunction = 125°C
1.0
Ω
RON_3_4
Bridge 3 and 4 diagonal Ron
I = 1A, VSupply = 36V,
Tjunction = 125°C
1.5
Ω
IMax
Bridge 1 and 2 max operative
current
2.5
A
IMax
Bridge 3 and 4 max operative
current
1.5
A
Idss
Output leakage current.
Tjunction = 125°C
-50
+50
µA
IQlp
Output leakage current in
“Low Power Mode”
VSupply = 36V,
Tjunction = 125°C
-10
+10
µA
Low side current protection
for bridges 1 & 2(1)
MtrXSideYILimSel[1:0]=00
MtrXSideYILimSel[1:0]=01
MtrXSideYILimSel[1:0]=10
MtrXSideYILimSel[1:0]=11(2)
0.6
1.4
2.4
2.4
1.6
2.6
3.6
3.6
A
IprotH_1&2
High side current protection
for bridges 1 & 2(1)
MtrXSideYILimSel[1:0]=00
MtrXSideYILimSel[1:0]=01
MtrXSideYILimSel[1:0]=10
MtrXSideYILimSel[1:0]=11(2)
0.7
1.5
2.5
2.5
1.7
2.7
3.7
3.7
A
Iprot_3
Low side current protection
for bridges 3 & 4(1)
MtrXSideYILimSel[1:0]=11(3)(4) 1.55
2.5
A
Iprot_4
High side current protection
for bridges 3 & 4(1)
MtrXSideYILimSel[1:0]=11(3)(4)
1.6
2.5
A
2
5
us
IprotL_1&2
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Power bridges operating specifications
tfilter
Current limit
filter time
tdelay
Current limit
delay time
Min
Typ
Max Unit
5
us
60
120
240
480
ns
ns
ns
ns
toc_off
Over current off time
MtrXIlimitOffTimeY[1:0]=00
MtrXIlimitOffTimeY[1:0]=01
MtrXIlimitOffTimeY[1:0]=10
MtrXIlimitOffTimeY[1:0]=11(5)
tr1_2
Output rise time
bridges 1 &2
VSupply = 36V, Resistive load
between outputs:
R= 25 Ohm(6)
100
250
ns
tr3_4
Output rise time
bridges 3 & 4
VSupply = 36V, Resistive load
between outputs:
R= 36 Ohm(6)
50
200
ns
tf1_2
Output fall time
bridges 1 & 2
VSupply = 36V, Resistive load
between outputs:
R= 25 Ohm(6)
100
250
ns
SABRE-LL-I
Power bridges
Table 29.
Power bridges operating specifications (continued)
Parameter
Description
Output fall time
bridges 3 & 4
tf3_4
Test condition
Min
Typ
Max Unit
VSupply = 36V, Resistive load
between outputs:
R= 36 Ohm(6)
50
250
ns
tdeadRise
Anti crossover rising dead
time
100
450
ns
tdeadFall
Anti crossover falling dead
time
100
450
ns
Fpwm
Operating frequency
Fosc
/512
kHz
tresp
Delay from PWM to output
transition
500
ns
1. The current protection values must be intended as a protection for the chip and not as a continuous current
limitation. The protection is performed by switching off the output bridge when current reaches values
higher than the Iprot max. No protection could be guaranteed for values in the middle range between
Ioperative max and Iprot.
2. In this cell X stands for 1 or 2, Y stands for A or B
3. In this cell X stands for 3 or 4, Y stands for A or B
4. The current protection thresholds for Bridge 3 and 4 are not selectable so only the max current value
(MtrXSideYILimSel[1:0]= 11) is available.
5. Over Current Off time can be configured using SPI.
6. Rise and fall time are measured between 10% and 90% of supply voltage. With device in full bridge
configuration (resistive load between outputs).
14.3
Possible configurations
The selection of the bridge configuration is done through SPI, by writing the MtrXTable[1:0]
bits in the MtrXCfg register. The table below shows the correspondence between
MtrXTable[1:0] bits and the bridge configuration.
Table 30.
Bridge selection truth
MtrXTable[1]
MtrXTable[0]
Bridge truth
0
0
Full bridge configuration
0
1
High or low side switch configuration
1
0
Half bridge configuration
1
1
High or low side switch configuration
Bridge 1 & 2 can be paralleled by means of Mtr1_2Parallel bit in the Mtr1_2Cfg register:
Bridge 1 and 2 paralleled will form superbridge1, bridge X side A and bridge X side B
paralleled form SuperHalfBridgeX or SuperSwitchX.
Bridge 3 & 4 can be configured by means of Mtr3_4CfgTable[1:0] bits in the Mtr3_4Cfg
register according to following table:
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Power bridges
SABRE-LL-I
Table 31.
Bridge 3 and 4 configuration
Mtr3_4CfgTable[1]
Mtr3_4CfgTable[0]
Bridge 3 and 4 configuration
0
0
Two independent bridges
0
1
Two bridges in parallel
1
0
Stepper motor
1
1
Stepper motor
The possible configurations for the bridges are described in the following:
14.3.1
Full bridge
When in full bridge configuration, the drivers will behave according to the following truth
table:
Table 32.
Full bridge truth
TSD
nRESET
Low
power
mode
Enable
1
X
X
X
X
X
0
0
X
X
X
0
1
1
X
0
1
0
0
1
0
Current MtrXCtrl MtrXCtrl
limit
SideA
SideB
PWM
OUT+
OUT-
X
X
Z
Z
X
X
X
Z
Z
X
X
X
X
Z
Z
0
X
X
X
X
Z
Z
0
1
1
X
X
X
Z
Z
1
0
1
0
0
0
X
0
0
0
1
0
1
0
0
1
0
1
1
0
1
0
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
1
1
0
1
0
1
0
1
0
1
1
0
0
1
0
1
0
1
1
X
1
1
Note: When “Low Power mode” is active, the bridges will enter in low power state and will reduce its biasing
thus contributing to the power saving.
When a current limit event occurs this event will be latched and the bridges will remain in high
impedance state for the toff time.
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SABRE-LL-I
14.3.2
Power bridges
Parallel configuration (super bridge)
Bridges 1, 2, 3 and 4 can be configured to be used two by two (1 plus 2, 3 plus 4) as one
super bridge thus enabling the driving of loads (motors) requiring high currents. In this
configuration the half bridges will be paralleled and will work as one phase of the superbridge just created: the two phases + will become phase + of the newly created superbridge while the two phases - will become phase –.
Figure 14. Super bridge configuration
Parallel Full Bridge
Super Bridge
Bridge 2 (4)
Bridge 1 (3)
PH
PH
PH
PH
+
-
-
+
M
When this configuration is chosen for bridges 1 (3) and 2 (4), the resulting bridge will use the
driving logic of bridge 1 (3) so for programming it must be used the bridge 1 (3) control and
status bits (direction, PWM, ...): i.e. the used PWM signal will be chosen by
Mtr1SideAPwmSel[1:0] (Mtr3SideAPwmSel[1:0]) bits in SPI.
If the bridges are not configured to be used in parallel, each side of the bridge will use the
PWM selected by the respective MtrXPWMYSel[1:0] bits in the SPI, but if one of the two
drivers is configured as a full bridge only one of the two selected PWM will be used to drive
the motor and this is the PWM chosen for side A.
In order to avoid any problem coming from different propagation times of PWM signals the
anti-crossover dead times are slightly increased when the bridges are paralleled.
14.3.3
Half bridge configuration
Each bridge can be configured to be used as 2 independent half bridges or as 1 super half
bridge (see Figure 15). It is also possible to parallel more than one bridge and use all of
them as a single super half bridge.
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Power bridges
SABRE-LL-I
Figure 15. Half bridge configuration
V Supply
V pump
High side
Driver
DCX Phase output
Control Signals
Fault
From SPI
Signals
Control
Logic
Low side
Driver
In this case each half bridge will behave according to the following truth table.
Table 33.
Half bridge truth
TSD
nReset
Low
power
mode
Enable
Current
limit
MtrXCtrl
SideA/B
PWM
OUT
1
X
X
X
X
X
X
Z
0
0
X
X
X
X
X
Z
0
1
1
X
X
X
X
Z
0
1
0
0
X
X
X
Z
0
1
0
1
0
0
0
Z
0
1
0
1
0
0
1
0
0
1
0
1
0
1
0
Z
0
1
0
1
0
1
1
1
0
1
0
1
1
X
X
Z
Note: When “Low Power mode” bit is active the bridges will reduce its biasing thus contributing to the power
saving.
When a current limit event occurs this event will be latched and the bridges will remain in high
impedance state for the toff time.
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SABRE-LL-I
14.3.4
Power bridges
Switch configuration
Each bridge can be configured to be used as 2 independent switches that connects the
output to supply or to ground. It is also possible to parallel the two switches and use them as
a single super switch.
All resulting switches will behave according to the following truth table.
Table 34.
Switch truth
TSD
nReset
Low
power
mode
Enable
Current
limit
MtrXCtrl
SideA/B
PWM
OUT
1
X
X
X
X
X
X
Z
0
0
X
X
X
X
X
Z
0
1
1
X
X
X
X
Z
0
1
0
0
X
X
X
Z
0
1
0
1
0
0
X
Z
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
0
1
0
1
1
X
X
Z
Note: When “Low Power mode” bit is active the bridge will reduce its biasing thus contributing to the whole
power saving.
When a current limit event occurs this event will be latched and the bridge will remain in high impedance
state for the toff time.
14.3.5
Bipolar stepper configuration
The bridges 3 and 4 can be configured to be used as a micro-stepping, bidirectional driver
for bipolar stepper motors.
The primary features of the driver are the following:
–
Internal PWM current control.
–
Micro stepping.
–
Fast, mixed and slow current decay modes.
Each H-bridge is controlled with a fixed and selectable off-time PWM current-control circuit
that limits the load current to a value set by choosing VSTEPREF voltage by means of the
internal DAC and an the external RSENSE value.
The max current level could be calculated using the formula:
IMAX=VSTEPREF/RSENSE
To obtain the best current profile, the user can choose three different current decay modes:
slow, fast and mixed. Initially, during Ton, a diagonal pair of source and sink power MOS is
enabled and current flows through the motor winding and the sense resistor. When the
voltage across the sense resistor reaches the programmed DAC output voltage, the control
logic will change the status of the bridge according to the selected decay mode (slow, fast or
mixed). In slow decay mode the current is recirculated through the path including both high
side power MOS for the whole toff time. In fast decay mode the current is recirculated
through the high and low side power MOS opposite respect to those forcing current to
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Power bridges
SABRE-LL-I
increase. Mixed decay mode is a selectable mix of the previous two modes (fast decay
followed by slow decay) and allows the user to find the best trade off between load current
ripple and fast current levels transition. Additionally, by setting the
SeqMixedOnlyInDecreasingPh bit in the StpCfg1 register, the user can choose to apply the
fast decay percentage in mixed mode always or only when the current is decreasing (i.e
from 90° to 180° and from 270° to 360° of the sinusoidal wave).
By using SPI interface the user can choose:
56/141
●
Control type (external firmware control, half step, normal drive, wave drive, micro-step).
●
Up to 16 current levels (quasi-sinusoidal increments) for each bridge.
●
Current direction.
●
Decay mode.
●
Blanking time.
●
Off time (32 values from 2µs to 64µs).
●
Percentage of fast decay respect to toff (when in mixed decay mode).
SABRE-LL-I
Power bridges
Figure 16. Bipolar stepper configuration
DC3_PHDC3SENSE
V supply
DC3_PH+
Stepper
Motor
VRefA
DC4 PH-
Supply
PH-
Supply
PH+
PH-
PH+
DC4 PH+
Sense
Sense
Bridge Driver
- Control Logic
- Toff generation
- DAC reference
selection
Bridge Driver
VRefB
Ref1
V STEPREF
Ref2
DC4SENSE
VRefA
StepperDACPhA
SelStepRef
StepperDACPhB
VRefB
The operating characteristics remain the same (when applicable) already seen in the power
bridges operating specifications with the addition of the following:
Table 35.
Parameter
Stepper specifications
Description
VSTEPREF
Reference voltage
Sense_off
Sense comparator offset
Test condition
SelStepRef =0
SelStepRef =1
Min
Typ
Max
Unit
0.480 0.50
0.720 0.75
0.520
0.780
V
12
mV
-12
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Power bridges
SABRE-LL-I
Using the StepCtrlMode[2:0] bits in StepCfg1 register, S.A.B.Re can be programmed to
internally generate the stepping levels. In these cases and depending on the StepFromGpio
bit in the StpCfg1 register the Stepper driver will move to next step each time the StepCmd
bit is set at logic level “1” or at each pulse transition longer than ~1µs externally applied on
GPIO12 (StepReq signal), according to following table:
Table 36.
Sequencer drive
StepFromGpio
Sequencer driven by
0
StepCmd bit in StepCmd register.
1
GPIO12 input pin.
The allowable control modes are as follows:
1.
Stepping sequence left to external microcontroller: in this mode the current level in
each motor winding is set by the microcontroller via the serial interface.
2.
Full step: in this mode the electrical angle will change by 90° steps at each StepReq
signal transition. There are two possibilities:
–
Normal step (two phases on): in normal step mode both windings are energized
simultaneously and the current will be alternately reversed. The resulting electrical
angles will be 45°, 135°, 225° and 315°.
–
Wave drive (one phase on): In wave drive mode each winding is alternately
energized and reversed. The resulting electrical angles will be 90°, 180° and 270°
and 360°.
3.
Half step: in this mode, one motor winding is energized and then two windings
alternately so the electrical angles the motor will do when rotating in clockwise direction
and using the same current limit in both the phases are: 45°, 90°, 135°, 180°, 225°,
270°, 315° and 360°.
4.
Microstepping: in this mode the current in each motor winding has a quasi sinusoidal
profile. The increment between each step is obtained at each transition of StepCmd bit
in StepCmd register. The difference between each step could be chosen (4, 8 or 16
levels for each phase) according to following table:
Table 37.
Stepper mode
StepCtrlMode[2:0]
Control mode
Description
000 or 111
No Control
001
Half Step
010
Normal Step
Full step (two phases on)
011
Wave Drive
Full step (one phase on)
100
1/4 Step
Four micro steps
101
1/8 Step
Eight micro steps
110
1/16 Step
Sixteen micro steps
Stepping sequence control left to the external
controller
Half step
Note: When in 1/16 step mode, the best phase approximation of sinusoidal wave, is obtained by repeating the
“F” step as follows: 0, 1, 2, 3, … , D, E, F, F, F, E, D, … , 3, 2, 1, 0
When internal stepping sequence generation is used, the stepping direction is set by the
StepDir bit according to the following table.
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Power bridges
Table 38.
Stepper sequencer direction
StepDir
Direction
0
Counter Clockwise (CCW)
1
Clockwise (CW)
Note: It is intended as clockwise the sequence that forces a clockwise rotation of the versors representing the
current module and phase.
An internal DAC is used to digitally control the output regulated current. The available
values are chosen to provide a quasi sinusoidal profile of the current. The current limit in
each phase is decided by PhADAC[3:0] bits for phase A and PhBDAC[3:0] bits for phase B.
The table below describes the relation between the value programmed in the stepper DAC
and the current level:
Table 39.
DAC
Phase Current ratio respect to IMAX
PhXDAC [3:0]
Min
0000
Typ
Max
Unit
(Hi-Z)
0001
7.8
9.8
11.8
% of IMAX
0010
17.5
19.5
21.5
% of IMAX
0011
27.0
29.0
31.0
% of IMAX
0100
36.3
38.3
40.3
% of IMAX
0101
45.1
47.1
49.1
% of IMAX
0110
53.6
55.6
57.6
% of IMAX
0111
61.4
63.4
65.4
% of IMAX
1000
68.7
70.7
72.7
% of IMAX
1001
75.3
77.3
79.3
% of IMAX
1010
81.1
83.1
85.1
% of IMAX
1011
86.2
88.2
90.2
% of IMAX
1100
90.4
92.4
94.4
% of IMAX
1101
93.7
95.7
97.7
% of IMAX
1110
96.5
98.1
99.7
% of IMAX
1111
IMAX
Note: The Min and Max values are guaranteed by testing the percentage of VSTEPREF that allows the
commuatation of the Rsense comparator.
IMAX=VSTEPREF/ RSENSE.
To obtain the best phase approximation of a sinusoidal wave, the user needs to repeat the final (100%)
value. So the full values sequence should be as follows: 0, 1, 2, 3 … D, E, F, F, F, E, D … 3, 2, 1, 0.
Even if the total spread shows overlapping between current steps, the monotonicity is guaranteed by
design.
59/141
Power bridges
SABRE-LL-I
When the internal sequencer the minimum angle resolution is nominally 5.625°, so
depending on the control mode chosen, the selectable steps are the following:
Table 40.
Internal sequencer
Typical output
current (% of IMAX )
Control mode
Half
step
Full step
(2 phases
on)
1
1
Full step
(1 phase
on)
1/4
step
1
1/8
step
1
2
2
3
4
2
1
3
5
6
4
7
8
3
2
5
9
10
6
11
12
4
2
7
13
14
60/141
1/16
step
Resulting
electrical
angle
Phase A
Phase B
(sin)
(cos)
Electrical
degrees
1
70.7
70.7
45°
2
77.3
63.4
50.6°
3
83.1
55.6
56.2°
4
88.2
47.1
61.9°
5
92.4
38.3
67.5°
6
95.7
29.0
73.1°
7
98.1
19.5
78.8°
8
100
9.8
84.4°
9
100
HiZ
90°
10
100
-9.8
95.6°
11
98.1
-19.5
101.2°
12
95.7
-29.0
106.9°
13
92.4
-38.3
112.5°
14
88.2
-47.1
118.1°
15
83.1
-55.6
123.8°
16
77.3
-63.4
129.4°
17
70.7
-70.7
135°
18
63.4
-77.3
140.6°
19
55.6
-83.1
146.2°
20
47.1
-88.2
151.9°
21
38.3
-92.4
157.5°
22
29.0
-95.7
163.1°
23
19.5
-98.1
168.8°
24
9.8
-100
174.4°
25
HiZ
-100
180°
26
-9.8
-100
185.6°
27
-19.5
-98.1
191.2°
28
-29.0
-95.7
196.9°
SABRE-LL-I
Power bridges
Table 40.
Internal sequencer (continued)
Typical output
current (% of IMAX )
Control mode
Half
step
Full step
(2 phases
on)
Full step
(1 phase
on)
1/4
step
8
1/8
step
15
16
3
5
9
17
18
10
19
20
6
3
11
21
22
12
23
24
7
4
13
25
26
14
27
28
8
4
15
29
30
1/16
step
Resulting
electrical
angle
Phase A
Phase B
(sin)
(cos)
Electrical
degrees
29
-38.3
-92.4
202.5°
30
-47.1
-88.2
208.1°
31
-55.6
-83.1
213.8°
32
-63.4
-77.3
219.4°
33
-70.7
-70.7
225°
34
-77.3
-63.4
230.6°
35
-83.1
-55.6
236.2°
36
-88.2
-47.1
241.9°
37
-92.4
-38.3
247.5°
38
-95.7
-29.0
253.1°
39
-98.1
-19.5
258.8°
40
-100
-9.8
264.4°
41
-100
HiZ
270°
42
-100
9.8
275.6°
43
-98.1
19.5
281.2°
44
-95.7
29.0
286.9°
45
-92.4
38.3
292.5°
46
-88.2
47.1
298.1°
47
-83.1
55.6
303.8°
48
-77.3
63.4
309.4°
49
-70.7
70.7
315°
50
-63.4
77.3
320.6°
51
-55.6
83.1
326.2°
52
-47.1
88.2
331.9°
53
-38.3
92.4
337.5°
54
-29.0
95.7
343.1°
55
-19.5
98.1
348.8°
56
-9.8
100
354.4°
57
HiZ
100
360°/0°
58
9.8
100
5.6°
59
19.5
98.1
11.2°
61/141
Power bridges
SABRE-LL-I
Table 40.
Internal sequencer (continued)
Full step
(2 phases
on)
Half
step
Full step
(1 phase
on)
Resulting
electrical
Typical output
current (% of IMAX )
Control mode
1/4
step
1/8
step
16
31
32
1/16
step
angle
Phase A
Phase B
(sin)
(cos)
Electrical
degrees
60
29.0
95.7
16.9°
61
38.3
92.4
22.5°
62
47.1
88.2
28.1°
63
55.6
83.1
33.8°
64
63.4
77.3
39.4°
The voltage spikes on Rsense could be filtered by selecting an appropriate blanking time on
the output of Current sense comparator. The Blanking time selection is made by using the
StepBlkTime[1:0] bits in the StpCfg1 register, according to following table:
Table 41.
Blanking times specification
Blanking time
StepBlkTime[1]
StepBlkTime[0]
Min
Typ
Max
Unit
Comments
Default value
0
0
0.6
0.95
1.2
us
0
1
0.95
1.4
1.85
us
1
0
1.5
2.25
3
us
1
1
3
4.25
5.5
us
The stepper driver toff time could be programmed by means of the StepOffTime[4:0] bits in
StpCfg1 register:
Table 42.
Stepper off time
Off time
StepOffTime[4:0]
Unit
Typ
62/141
00000
2
us
00001
4
us
00010
6
us
00011
8
us
00100
10
us
00101
12
us
00110
14
us
00111
16
us
01000
18
us
SABRE-LL-I
Power bridges
Table 42.
Stepper off time (continued)
Off time
StepOffTime[4:0]
Unit
Typ
01001
20
us
01010
22
us
01011
24
us
01100
26
us
01101
28
us
01110
30
us
01111
32
us
10000
34
us
10001
36
us
10010
38
us
10011
40
us
10100
42
us
10101
44
us
10110
46
us
10111
48
us
11000
50
us
11001
52
us
11010
54
us
11011
56
us
11100
58
us
11101
60
us
11110
62
us
11111
64
us
By means of MixDecPhA[4:0] and MixDecPhB[4:0] in StepCfg2 register, the percentage of
Toff time during which each phase will stay in fast decay mode could be programmed
according to following table:
63/141
Power bridges
Table 43.
SABRE-LL-I
Stepper fast decay
MixDecPhX[4:0]
Fast decay percentage
during toff
Unit
Typ
14.3.6
00000
0
%
00001
6.25
%
00010
12.5
%
00011
18.75
%
00100
25
%
00101
31.25
%
00110
37.6
%
00111
43.75
%
01000
50
%
01001
56.25
%
01010
62.5
%
01011
68.75
%
01100
75
%
01101
81.25
%
01110
87.5
%
01111
93.75
%
1xxxx
100
%
Synchronous buck regulator configuration
Bridge 3 can be configured to be used as 2 independent synchronous buck regulators or as
a single high current synchronous buck regulator using GPIOs pins in order to close the
voltage loop. The resulting regulator(s) will implement a non linear, pulse skipping, control
loop using an internally generated PWM signal. The voltage will be set externally with a
divider network and PWM duty cycle that can be programmed in order to ensure a proper
regulation.
The regulator will be enabled/disabled using serial interface and will implement a soft start
strategy similar to that used by primary switching regulator.
64/141
SABRE-LL-I
Power bridges
Here after are summarized the primary features of the regulator(s):
–
Synchronous rectification
–
Automatic low side disabling when current in the inductance reaches 0 to optimize
efficiency at low load
–
Pulse skipping control
–
Internally generated PWM
–
Cycle by cycle current limiting using internal current sensor
–
Protected against load short circuit
–
Soft start circuitry
–
Under voltage signal (both continuous and latched) accessible through serial
interface.
Figure 17. Regulator block diagram
V supply
CurrentSense
Charge pump Voltage
High Side
Driver
Half Bridge OUT
La
V out
Ra
Low Side
Driver
From Central Logic
C
Bridge Sense
Control
Logic
Voltage
Loop Control
Vref=3V
Regulator Freq
N.C.
N.C.
+
GPIO USED as FB
Rb
Regulator Ref
Vref= 0.8V
SelFBRef
Obtained using spare analog
/digital blocks
To Central Logic
Filter
+
Under voltage
Threshold
Depending on the load current, there could be the necessity to add a Schottky diode on
output to reduce internal thermal dissipation. This diode must be placed near to the pin and
must be fast recovery and low series resistance type.
For detail about pulse skipping please refer to main switching regulator paragraph.
The output voltage will be externally set by a divider network connected on feedback pin. To
reduce as much as possible the regulation voltage error S.A.B.Re has the possibility to
switch between four regulator feedback voltage references (and, as a consequence, four
under-voltage thresholds) using serial interface. The feedback reference voltage is selected
65/141
Power bridges
SABRE-LL-I
by writing the SelFBRef[1:0] bits in the Aux1SwCfg or Aux2SwCfg registers according to the
following table:
Table 44.
Switching regulator controller PWM specification
SelFBRef[1:0]
Reference voltage (VFBREF)
Comments
SelFBref[1]
SelFBref[0]
Min
Typ
Max
Unit
0
0
0.776
0.8
0.824
V
0
1
0.970
1
1.030
V
Default voltage for AUX1
1
0
2.425
2.5
2.575
V
Default voltage for AUX2
1
1
2.910
3
3.09
V
The switching regulators have four possible PWM duty cycles that can be changed using
SPI according to following table:
Table 45.
Pwm specification
AuxXPWMTable[1:0]
Typical duty cycle value
Comments
00
10%
01
13%
Default state for AUX1
10
24%
Default state for AUX2
11
61%
The operating characteristics remain the same (when applicable) already seen in the
Section 15.2 with the addition of the following:
Table 46.
66/141
Operating specification
Parameter
Description
Test condition
Min
VAUX_SW
Output pin voltage range
(1)
Typ
Max
Unit
-1
VSupply
V
IQ
Output leakage current
Tjunction = 125°C
-50
+50
µA
IQlp
Output leakage current
in “Low Power Mode”
VSupply = 36V Tjunction =
125°C
-10
+10
µA
IQfb
GPIO feedback pin
current
Tjunction = 125°C
0V≤Feedback ≤ 3V
-10
+10
µA
Vout
Output voltage range
VSupply = 36V(2)
0.8
30
V
Iload
Output load current
VSupply = 36V
0.002
1.5
A
RonH
Internal high/low side
RDSon
0.8
Ω
Vloop
Loop voltage accuracy
VregR
Output voltage ripple
(RMS)
L = TBD, C =
TBD/ESR=TBD mΩ(3)
VuvFall
Under voltage falling
threshold
(4)
84.5
87
89.5
%
VuvRise
Under voltage rising
threshold
(4)
90.5
93
95.5
%
Tjunction = 125°C
Iload=1A
±3%
TBD
mVRMS
SABRE-LL-I
Power bridges
Table 46.
Operating specification (continued)
Parameter
Description
Vuvhys
Under voltage hysteresis
6
%
taux_uv
Under voltage deglitch
filter
5
µs
Ilimit
Current limit protection
1.6
Current limit deglitch
time
50
tdeglitch
Test condition
Min
Typ
Max
2.5
Unit
A
ns
tI_lim
Current limit response
time
In normal operating
mode (no UV)(5)
700
ns
tI_limUV
Current limit response
time in UV condition.
When in Under
Voltage(6)
500
ns
tr
Switching output rise
time
VSupply = 36V, Resistive
load to gnd: R=422 Ω(7)
5
30
ns
tf
Switching output fall time
VSupply = 36V, Resistive
load to gnd = 10 Ω(7)
10
50
ns
tdead
Crossover dead time
100
ns
FregPwm
Operating frequency
Fosc/64
kHz
1. The external components connected to the pin must be chosen to avoid that the voltage exceeds this
operative range.
2. The regulated voltage can be calculated using the formula: VMAIN_SW = VFBREF *(Ra+Rb)/Rb.
3. The choice of proper values for L and C depends from the application.
4. Undervoltage rising and falling thresholds are intended as a percentage of feedback pin voltage
(VSW_main_FB).
5. This condition is intended to simulate an extra current on output.
6. This condition is intended to simulate a short circuit on output.
7. Rise time is measured between 10% and 90% of supply voltage.
14.3.7
Regulation loop
As seen before S.A.B.Re contains 2 regulation loops for switching regulators that are used
when bridge 3 is used as a regulator. These loops are assembled using internal
comparators and filters similar to that used in main switching regulator.
When bridge 3 is not used for this purpose or when only one regulation loop is needed, the
control loop is available on a GPIO output thus enabling the customer to assembly a basic
buck switching regulator using an external Power FET. The comparators used in the above
mentioned regulation loops are general purpose low voltage (3.3 V) comparators; when the
relative regulation loop is not used they can be accessed as shown in the diagram here
below:
67/141
Power bridges
SABRE-LL-I
Figure 18. Internal comparator functional block diagram
GPIOx
GPIOy
GPIOy
DECODE
LOGIC
GPIOyMode
+
-
GPIOxMode
GPIOx
DECODE
LOGIC
V 3v3
GPIOz
GPIOz Value From SP
GPIOzMod
e
GPIOz
DECODE
LOGIC
GPIOz Logic
Driver
The functionality of this circuit is obtained by using the bridge 4 output stage. This circuit is
powered directly from VSupply and it is intended to be used as a battery charger or a
switching regulator.
The control loop block diagram is shown in the following figure:
Figure 19. Battery charger control loop block diagram
SABRE
IREF_FB
COMP_I
VREF_FB
DIFF
AMPLI
COMP_V
PULSE SKIPPING
BURST
CONTROL LOGIC
PEAK CURRENT
MODE CONTROL
LOGIC
DC4_plus
PWM
Ilimit
BRIDGE 4
PARALLELED
POWER
STAGE
TO
LOAD
DC4_minus
FBRef
SelFBRef<1:0>
CurrRef
SelCurrRef<1:0>
The battery charger control loop implements an asynchronous switching regulator intended
to be used as a constant voltage/constant current programmable source.
68/141
SABRE-LL-I
Power bridges
When used as a simple switching regulator, it could be a system regulator depending on
startup configurations
When a system regulator under-voltage event is detected S.A.B.Re will enter in reset state
signaling this event to the microcontroller by pulling low the nRESET pin and disabling most
of its internal blocks.
Battery charger regulator application (CC-CV).
When the control loop is intended to be used as a battery charger, the Aux3BatteryCharge
bit must be written in the Aux3SwCfg1 register. This is because in this case the
undervoltage event that will be sure present when charging a battery (see next battery
charger profile) will not be considered during start up sequence.
Voltage regulation
The regulated output voltage will be externally set by a resistor divider network connected to
VREF_FB pin. S.A.B.Re has the possibility to choose between four voltage references (and,
as a consequence, four under-voltage thresholds) using the serial interface. The feedback
reference voltage selection is made by writing the SelFBRef[1:0] bits in the Aux3SwCfg1
register according to the table here below:
Table 47.
Battery charger control loop FBRef specification
Aux3SwCfg1
Reference voltage (FBRef)
Comments
SelFBref[1]
SelFBref[0]
Min
Typ
Max
Unit
0
0
1.370
1.412
1.455
V
0
1
1.746
1.8
1.854
V
1
0
2.079
2.143
2.207
V
1
1
2.425
2.5
2.575
V
Default state
Reference voltages values can be changed using a metal layer change in order to adapt
them to customer system.
The first, second and third reference voltage has been chosen to regulate 3.3V, 4.2V and
5V with the same resistor divider network, such that the commutation between different
regulated voltages can be done on the fly in the application.
Current regulation
The regulation of the output current can be done externally, by using a sense resistor
connected in series on the path that provides current to the load. By using an external
differential amplifier the customer can set the desired V=f(I) characteristic, and therefore the
regulated current: the voltage provided at the IREF_FB pin will be compared to the internal
reference. S.A.B.Re has the possibility to choose between four voltage references using the
serial interface, writing the SelCurrRef[1:0] bits in the Aux3SwCfg1 register according to the
following the table:
69/141
Power bridges
SABRE-LL-I
Table 48.
Battery charger control loop CurrRef specification
Aux3SwCfg1
Reference voltage (CurrRef)
Comments
SelCurrRef[1] SelCurrRef[0]
Min
Typ
Max
Unit
0
0
0.873
0.900
0.927
V
0
1
1.394
1.437
1.480
V
1
0
1.746
1.8
1.854
V
1
1
2.182
2.25
2.318
V
Default state
Adjustable reference voltages values can be changed using a metal layer change in order to
adapt them to customer system.
Regardless of the CurrRef voltage, if the IREF_FB pin remains below the chosen threshold,
the internal current limitation will work (see DC motor paragraph, Bridge4 Ilimit).
Battery charge profile
The battery charge profile can be chosen by fixing the desired CurrRef and FBRef internal
reference voltages and by choosing the desired V=f(I) trans-characteristic of the external
differential amplifier.
The following is a typical Li-Ion battery charge profile:
Figure 20. Li-ion battery charge profile
Voltage or Current
Veochrg
Blue=Battery Voltage
FBRef depending
Vchrg
Ichrg
CurrRef depending
Red=Battery Current
Iprechrg
Ieochrg
Time
Precharge
phase
70/141
Rapid charge
phase
Constant V.
phase
End Of Charge
SABRE-LL-I
Power bridges
Simple buck regulator application
The battery charge loop control can be used to implement a buck type switching regulator.
The regulated output voltage will be externally set by a resistor divider network connected to
VREF_FB pin, as already described in voltage regulation section, and the current protection
will be the one implemented internally in the Bridge4 section.
Figure 21. Simple buck regulator
SABRE
IREF_FB
VREF_FB
COMP_I
COMP_V
PULSE SKIPPING
BURST
CONTROL LOGIC
PEAK CURRENT
MODE CONTROL
LOGIC
DC4_plus
PWM
Ilimit
BRIDGE 4
PARALLELED
POWER
STAGE
TO
LOAD
DC4_minus
FBRef
SelFBRef<1:0>
CurrRef
SelCurrRef<1:0>
When this control loop is intended to be used as a simple buck regulator, the proper
Aux3BatteryCharge bit must be written in the Aux3SwCfg1 register.
The regulator will also implement a soft start strategy.
When S.A.B.Re “Low Power mode” is enabled this regulator will be disabled.
Here after are summarized the primary features of the regulator:
–
Internal power switch.
–
Nonlinear pulse skipping control.
–
Internally generated PWM (250 KHz switching frequency).
–
Cycle by cycle current limiting using internal current sensor/ external current
sense differential amplifier.
–
Protected against load short circuit.
–
Soft start circuitry to limit inrush current flow from primary supply.
–
Under voltage signal (both continuous and latched) accessible through SPI.
–
Over temperature protection.
71/141
Power bridges
SABRE-LL-I
In pulse skipping control PWM the duty cycle must be decided by the user depending on
supply voltage and regulated voltage.
Therefore the switching regulator has 4 possible PWM duty cycles that can be changed
writing in the Aux3PWMTable[1:0] bits in the Aux3SwCfg1 register according to the
following table.
Table 49.
Battery charger regulator controller PWM specification
Aux3PWMTable [1:0]
Typical duty cycle value
00
10%
01
13%
10
24%
11
61%
Comments
Default state
Adjustable duty cycles can be changed using a metal layer change in order to adapt it to
customer system. The only limitation is that ALL regulators share the same duty cycle bus,
so any modification must consider ALL regulators needed duty cycles.
AUX3 Control loop parameters specifications
The following table assumes that DC4_PLUS and DC4_MINUS pins are externally shorted
together.
Table 50.
Parameter
Test condition
Min
Max
Unit
(1)
-1
VSupply
V
Output leakage
current
Tjunction = 125°C
-100
+100
µA
IQlp
Output leakage
current in
“Low Power Mode”
VSupply = 36V
Tjunction = 125°C
-20
+20
µA
IQfb
GPIo feedback pin
current
Tjunction = 125°C
0V=Feedback=3V
-10
+10
µA
Vout
Output voltage range
VSupply = 36V(2)
1.412
30
V
Iload
Output load current
VSupply = 36V
0.002
3
A
RonH
Internal high/low side
RDson
0.4
Ω
Vloop
Loop voltage
accuracy
VregR
Output voltage ripple
(RMS)
L = TBD, C =
TBD,ESR=TBD mΩ(3)
VuvFall
Under voltage falling
threshold
(4)
84.5
87
89.5
%
VuvRise
Under voltage rising
threshold
(4)
90.5
93
95.5
%
VAUX_SW
IQ
72/141
Battery charger operating specification
Description
Output pin voltage
range
Typ
Tjunction = 125°C
Iload=1.5A
±3%
TBD
mVRMS
SABRE-LL-I
Power bridges
Table 50.
Parameter
Battery charger operating specification (continued)
Description
Test condition
Min
Typ
Max
Unit
Vuvhys
Under voltage
hysteresis
6
%
taux_uv
Under voltage
deglitch filter
5
µs
Current limit
protection
3.1
tdeglitch
Current limit deglitch
time
50
tI_lim
Current limit response
time
In normal operating
mode (no UV)(5)
700
ns
tI_limUV
Current limit response
time in UV condition.
When in Under
Voltage(6)
500
ns
tr
Switching output rise
time
VSupply = 36V, Resistive
load to gnd = 422 Ω(7)
5
30
ns
tf
Switching output fall
time
VSupply = 36V, Resistive
load to gnd = 10 Ω(6)
10
50
ns
tdead
Crossover dead time
100
ns
FregPwm
Operating frequency
Fosc/64
kHz
Ilimit
5.3
A
ns
1. The external components connected to the pin must be chosen to avoid that the voltage exceeds this
operative range.
2. The regulated voltage can be calculated using the formula: VMAIN_SW = VFBREF *(Ra+Rb)/Rb.
3. The choice of proper values for L and C depends from the application.
4. Undervoltage rising and falling thresholds are intended as a percentage of feedback pin voltage
(VSW_main_FB).
5. This condition is intended to simulate an extra current on output.
6. This condition is intended to simulate a short circuit on output.
7. Rise time is measured between 10% and 90% of supply voltage.
73/141
AD converter
SABRE-LL-I
15
AD converter
15.1
Overview
S.A.B.Re integrates and makes accessible via SPI a general purpose multi-input channel
3.3V analog to digital converter (ADC).
The ADC can be configured to be used as:
–
8-bit resolution ADC.
–
9-bit resolution ADC.
The result of the conversion will always be a 9-bit word; the difference between the two
configurations is that, to speed up the conversion, the resolution is reduced when the ADC
is used in the 8-bit resolution mode.
The ADC is seen at software level as a 2 channel ADC with different programmable sample
times; a finite state machine will sample the requests done through the SPI interface on both
the channel and will execute them in sequence.
When used as 8-bit resolution the ADC can achieve a higher throughput and, if the
minimum sample time is used, one conversion is completed in t = 5.5µs. When used as 9-bit
resolution ADC the circuit is slower and the minimum sample times are disabled. In that
case the conversion will be completed in a time t= 10 µs
The use of ADC type must be decided at the start-up by writing in the one time
programmable ADC configuration register; no A/D conversion will be enabled if this register
is not set from last power-up sequence.
This ADC can be used to measure some external pins as well as some S.A.B.Re’s internal
voltages. The converter is based on a cyclic architecture with an internal sample-and-hold
circuit. Sample time can be changed using serial interface to enable good measure of higher
impedance sources.
74/141
SABRE-LL-I
AD converter
Sample Time
1
SampleTime
0
Figure 22. A2D block diagram
Analog Mux
V supply
V pump
V 3v3
VLINmain
VSWmain
S&H
FB
FB
SWDRV_FB
GPio[13:0]
V psw
CurrDac
A2DType1
To SPI
A2DType0
Conversion
Done 0
Conversion
Done 1
Conversion
Result
A2DEnabl
Conversion
Address 1
Conversion
Address 0
Selected
A2DType
A2D
Temp Senso
The A2D system is enabled by setting the A2DEnable bit to ‘1’ in the A2DControl register.
The A2DType bit in the A2DConfigX registers selects the A2D active configuration (8-bit
resolution or 9-bit) according to the following truth table:
Table 51.
ADC truth
A2DEnable
A2DType0/1
A2D operation
0
X
Disabled
1
0
ADC working as a 8-bit ADC
1
1
ADC working as a 9-bit ADC
The multiplexer channel to be converted can be chosen by writing the A2DChannel1[4:0] or
A2DChannel2[4:0] bits in the A2DConfigX register; the channel addresses table is reported
in the following table.
75/141
AD converter
Table 52.
SABRE-LL-I
Channel addresses
A2DChannelX[4:0] (bin.)
Converted channel
Note
00000
VSupply scaled
See voltage divider specification.
00001
VSupplyInt scaled
See voltage divider specification.
00010
Vref_2_5V
00011
Temp Sensor1
Temperature sensor1
00100
Temp Sensor2
Temperature sensor2
00101
V3v3 scaled
See voltage divider specification.
0011X
Not used
01000
Not used
01001
GPIO[0]
01010
GPIO[1]
01011
GPIO[2]
01100
GPIO[3]
01101
GPIO[4]
01110
GPIO[5]
01111
GPIO[6]
10000
GPIO[7]
10001
GPIO[8] clamp
10010
GPIO[9]
10011
GPIO[10]
10100
GPIO[11]
10101
GPIO[12]
10110
GPIO[13]
10111
GPIO[14]
11000
MuxRefOpAmp1
11001
MuxRefOpAmp2
11010
OutStripStepperPhA
11011
OutStripStepperPhB
11100
Not used
11101
ST reserved
References AUX1 switching reg.
11110
ST reserved
0.8V reference voltage
11111
ST reserved
1.65V reference voltage
See current DAC circuit
The sample time can be changed by modifying the A2DSampleX[2:0] bits in the
A2DConfigX register; depending on which is the A2DType bit, the available sample times
are reported in the following tables.
76/141
SABRE-LL-I
AD converter
Table 53.
ADC sample times when working as a 8-bit ADC
Sample time
A2DSampleX[2:0] (binary)
Table 54.
Typ
Unit
000
16*Tosc
µs
001
32*Tosc
µs
010
64*Tosc
µs
011
128*Tosc
µs
100
256*Tosc
µs
101
512*Tosc
µs
110
1024*Tosc
µs
111
2048*Tosc
µs
ADC sample time when working as a 9-bit ADC
Sample time
A2DSampleX[2:0] (binary)
Typ
Unit
000
32*Tosc
µs
001
64*Tosc
µs
010
128*Tosc
µs
011
256*Tosc
µs
100
512*Tosc
µs
101
1024*Tosc
µs
110
2048*Tosc
µs
111
4096*Tosc
µs
A conversion on channel 1 can be triggered by writing a logic ‘1’ in the A2DTrig1 bit in the
A2DConfigX register and a conversion on channel 2 can be triggered writing a logic ‘1’ in the
A2DTrig2 bit in the same register. While a request on a channel is pending but not yet
completed S.A.B.Re will force to logic ‘0’ the corresponding A2DdoneX bit in the
A2DResultX registers and S.A.B.Re will not accept other conversion request on that
channel.
Continuous conversion on one channel can be accomplished by setting to logic ‘1’ the
A2DcontinuousX bit in the A2DConfigX register. When A2DcontinuousX bit is set, other
conversions can be accomplished on the other channel; these conversions will be inserted
between two conversions of the other channel and the end of the conversion will be
signaled using A2DdoneX bit. Of course when a channel is in continuous mode its sample
time and channel address cannot be changed.
Continuous conversions on both 2 channels can be also accomplished by setting to logic ‘1’
the A2Dcontinuous1 and A2Dcontinuous2 bits; the conversions are made in sequence.
77/141
AD converter
15.2
SABRE-LL-I
A2D specification with A2dType=0
Table 55.
Parameter
ADC specification
Description
Test condition
Min
0
IMR
Measurement range
A2dType = 0
INL
Integral non-linearity
DNL
OE
OEDrift
GE
GEDrift
tconv
Cin
Differential non-linearity
Offset error
Offset error drift
Gain error
Gain error drift
Typ
Max Unit(1)
V3v3
V
A2dType = 0(2)(3)
±1
LSB
0(4)(3)
±1
LSB
(5)
±4
LSB
A2dType = 0 over time
and temperature
±3
LSB
A2dType = 0(6)
±4
LSB
A2dType = 0 over time
and temperature
±4
LSB
5.5
µs
A2dType =
A2dType = 0
Minimum conversion time
Resolution
(7)
Input capacitance
(8)
8
bits
4
pF
1. The definition of LSB for this table is LSB=IMRmax/(27.5-1).
2. Integral Non Linearity error (INL) is defined as the maximum distance between any point of the ADC
characteristic and the “best straight line” approximating the ADC transfer curve.
3. The ADC ensures monotonic characteristic and no missing codes.
4. Differential nonlinearity error (DNL) is defined as the difference between an actual step width and the ideal
width value of 1 LSB.
5. Offset error (OE) is the deviation of the first code transition (000...000 to 000...001) from the ideal (i.e. GND
+ 0.5 LSB).
6. Gain error (GE) is the deviation of the last code transition (111...110 to 111...111) from the ideal (V3v3 0.5 LSB), after adjusting for offset error.
7. Please note that the result of the conversion will always be a 9-bit word: to speed up the conversion, the
resolution is reduced when the ADC is used in the 8- bit resolution mode.
8. Actual input capacitance depends on the pin that must be converted.
78/141
SABRE-LL-I
15.3
AD converter
A2D specification with A2dType=1
Table 56.
Parameter
ADC specification
Description
Test condition
Min
0
Typ
Max
Unit(1)
V3v3
V
IMR
Measurement range
A2dType = 1
INL
Integral non-linearity
A2dType = 1(2)(3)
±1
LSB
1(4)(3)
±1
LSB
(5)
±4
LSB
A2dType = 1 over time
and temperature
±3
LSB
Gain error
A2dType = 1(6)
±4
LSB
Gain error drift
A2dType = 1
over time and
temperature
±4
LSB
10
µs
DNL
OE
OEDrift
GE
GEDrift
tconv
Differential Non-Linearity
A2dType =
Offset error
Offset error drift
A2dType = 1
Minimum conversion time
Resolution
Cin
9
bits
(7)
Input capacitance
4
pF
9
1. The definition of LSB for this table is LSB=IMRmax/(2 -1).
2. Integral non linearity error (INL) is defined as the maximum distance between any point of the ADC
characteristic and the “best straight line” approximating the ADC transfer curve.
3. The ADC ensures monotonic characteristic and no missing codes.
4. Differential nonlinearity error (DNL) is defined as the difference between an actual step width and the ideal
width value of 1 LSB.
5. Offset error (OE) is the deviation of the first code transition (000...000 to 000...001) from the ideal (i.e. GND
+ 0.5 LSB).
6. Gain error (GE) is the deviation of the last code transition (111...110 to 111...111) from the ideal (V3v3 0.5 LSB), after adjusting for offset error.
7. Actual input capacitance depends on the pin that must be converted.
15.4
Voltage divider specifications
As can be seen in the A2D block diagram, in order to report some voltages in the A2D
working range, they are scaled with a resistor divider before the conversion.
Here below are reported the resistor voltage divider specifications:
Table 57.
Parameter
RSupply_ratio
RSupplyInt_rati
o
Rv3v3_ratio
Voltage divider specification
Description
Notes
Min
Typ
Max
VSupply divider ratio
-10%
1/15
+10%
VSupply Int divider ratio
-10%
1/15
+10%
V3v3 divider ratio
-10%
1/2
-10%
Unit
79/141
Current DAC circuit
SABRE-LL-I
16
Current DAC circuit
16.1
Overview
S.A.B.Re includes a multiple range 6-bit current sink DAC. The LSB value of this DAC can
be selected using the DacRange[1:0] bits in the CurrDacCtrl register.
The output of this circuit is connected to GPIO[8] that is a 5V tolerant pin. The value of this
pin can be converted using ADC. The pin value can be scaled before being converted by
enabling the internal resistor divider connected to this pin. If the current sunk by resistor
divider is not acceptable the pin voltage can be converted without scaling its value. When
the conversion without scaling resistor is chosen a clamping connection is used to avoid
voltage compatibility of the pin to the ADC system. The clamping circuit will sink a typical
current of half microampere from the pin during the sampling time.
Figure 23. Current DAC block diagram
Va3
Reference Current
Generator
DacRange[1:0]
EnDac
Current Sink
DAC
DacValue[5:0]
DacRange[1:0]
Gpio[8]
RCurrDac
Clamp circuit
Gpio8 Clamp
(to ADC)
EnDac
A2DChannel1[4:0] Combinatorial
Address
Recognized
Mask
A2DChannel2[4:0] Combinatorial
Address
Recognized
Mask
EnDacScale
Gpio[8] Digital Driver
The circuit is enabled by setting to logic ‘1’ the EnDac bit in the CurrDacCtrl register then the
desired sunk current value is chosen by changing the value of the DacValue[5:0] bits in the
80/141
SABRE-LL-I
Current DAC circuit
same register being DacValue[0] the least significant bit and DacValue[5] the most
significant bit.
The current DAC has three possible current ranges that can be selected using the
DacRange[1:0] bits in the CurrDacCtrl register . The DAC range selection table is shown
here below:
Table 58.
Current DAC truth
DacRange[1]
DacRange[0]
LSB typical current
ILSB typ
Full scale typical
current IFULL typ
0
0
Disabled
Disabled
0
1
10 µA
0.63 mA
1
0
100 µA
6.3 mA
1
1
1 mA
63 mA
By changing LSB current value, all steps will change following this relation:
Istep(N) = N * ILSB
where N is the value of DacValue[5:0] bits.
Table 59.
Current DAC specification
Parameter
Description
Test condition
Min
VR
Pin voltage operative range
(1)
IOUT_OFF
Output off leakage current
Typ
Max
Unit
0.7
5.5
V
DacValue[5:0] = 000000
-1
+1
µA
IFULL_ERR_01 Full scale current error
DacRange[1:0] =01
DacValue[5:0] = 111111
-10
10
% of
IFULL typ
IFULL_ERR_10 Full scale current error
DacRange[1:0] =10
DacValue[5:0] = 111111
-13
13
% of
IFULL typ
IFULL_ERR_11 Full scale current error
DacRange[1:0] =11
DacValue[5:0] = 111111
-12
12
% of
IFULL typ
INL10_11
Integral non-linearity for 10
and 11 ranges
±2
LSB
DNL10_11
Differential non-linearity for
10 and 11 ranges
±2
LSB
INL01
Integral non-linearity for 01
range
±1
LSB
DNL01
Differential non-linearity for
01 range
±1
LSB
+25%
kΩ
RCurrDac_res
Gpio[8] divider total
resistance
-25%
RCurrDac_ratio Gpio[8] divider ratio
tset
Settling time
45
-2.5% 3/5 +2.5%
(2)
5
µs
1. All parameters are guaranteed in the range between VOL and VR Max.
2. Measured from DacValue[5:0] change in SPI interface.
81/141
Operational amplifiers
17
Operational amplifiers
17.1
Overview
SABRE-LL-I
S.A.B.Re contains two rail to rail output, high bandwidth internally compensated operational
amplifiers supplied by VGPIO_SPI pin. The operative supply range is 3.3V±4.5%
Each operational amplifier can have all pin accessible or, to save pins, can be internally
configured as a buffer. They can also be used as comparators; to do that the user must
disable internal compensation by writing a logic level “1” in the OpXCompMode bit in the
OpAmpXCtrl register.
Here below are reported the block diagrams of the two operational amplifiers
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SABRE-LL-I
Operational amplifiers
Figure 24. Configurable 3.3V operational amplifiers
GPIO[11]
Op1Ref[1:0]
Op1EnIntRef
Op1PlusRef
V GPIO_SPI
Op1EnPlusPin
Op1CompMode
To A/D System
GPIO[9]
+
OpAmp 1
-
GPIO[10]
EnOp1
EnOp2
Op1BufConf
Op1EnMinusPin
Op2BufConf
Op2EnMinusPin
+-
GPIO[13]
+-
GPIO[12]
Op2CompMode
Op2EnPlusPin
V GPIO_SPI
Op2PlusRef
Op2EnIntRef
Op2Ref[1:0]
GPIO[14]
Note:
Op1EnPlusRef and Op2EnPlusRef cannot be used to drive external pin so the user must be
sure not to enable the path between one of these voltage references and the external pin.
The operational amplifiers are capable to drive a capacitive load in buffer configuration up to
a maximum of 100pF; for higher capacitance it is necessary to add resistive loads to
increase the OP output current, and/or to add a low resistor (10 Ohm) in series to the load
capacitance.
The table here below describes the main operational amplifier parameters.
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Operational amplifiers
17.2
SABRE-LL-I
Operational amplifiers specifications
Table 60.
Parameter
Configurable 3.3V operational amplifier specification
(Note: VGPIO_SPI=3.3V unless otherwise specified)
Description
Min
Typ
Max
Unit
VGPIO_SPI
Supply voltage range
3.15
3.45
V
VICM
Input common mode
voltage range
0
VGPIO_SP
V
VOUT_MAX
VOp1PlusRef
VOp1PlusRef
Output voltage
CMRR
I
Iload =± 1mA
0.1
3.2
V
Operational amplifier 1
reference voltage
Op1Ref[1:0]=00
Op1Ref[1:0]=01
Op1Ref[1:0]=10
Op1Ref[1:0]=11
0.970 1
1.600 1.65
1.940 2
2.425 2.5
1.030
1.700
2.060
2.575
V
Operational amplifier 2
reference voltage
Op2Ref[1:0]=00
Op2Ref[1:0]=01
Op2Ref[1:0]=10
Op2Ref[1:0]=11
0.970 1
1.600 1.65
1.940 2
2.425 2.05
1.030
1.700
2.060
2.575
V
Open loop gain
VICM=1.65V
Iload= 0mA
90
Common mode
rejection ratio
PSRR
Iload= ±6mA
VICM=1.65V(1)
dB
105
dB
90
dB
I in _offs
Input offset current
150
nA
I in _bias
Input bias current
500
nA
V in _offs
Input offset voltage
5
mV
GBWP
Gain bandwidth
product
Cload=100pF VICM=1.65V
Rload=330 Ohm to VGPIO_SPI
Iout
Output current
Vout=1.65V
Ishort_max
Slew
-5
Short circuit current
Slew rate
1. VICM is the input common mode voltage.
84/141
Test condition
Iload= 0
CLOAD=100pF
2
MHz
10
mA
12
20
mA
1.3
1.75
V/µs
SABRE-LL-I
17.3
Operational amplifiers
Operational amplifiers used as comparators specifications
To use the operational amplifiers as comparators the user must disable internal
compensation writing a logic one in the OpXDisComp bit in the OpAmpXCtrl register.
Table 61.
Parameter
Configurable 3.3V operational amplifier used as comparator specification
(Note: VGPIO_SPI=3.3V unless otherwise specified)
Description
Test condition
Min
Typ
Max
Unit
VGPIO_SPI
Supply voltage range
3.15
3.45
V
VICM
Input Common Mode
Voltage Range
0
VGPIO_SPI
V
0.3
2.9
V
VOUT_MAX
Output voltage
Iload =± 10mA
Iin _offs
Input offset current
150
nA
Iin _bias
Input bias current
500
nA
Vin _offs
Input offset voltage
-5
5
mV
Ishort_max
Short circuit current
12
tPHL
Output falling delay
VCM = 1.65V
∆ Vi = -/+ 20mV
CLOAD=100pF(1)(2)
1
µs
tFALL
Fall time
VCM = 1.65V
∆ Vi = -/+ 20mV
CLOAD=100pF(1)(2)
0.4
µs
tPLH
Output rising delay
VCM = 1.65V
∆ Vi = -/+ 20mV
CLOAD=100pF(1)(2)
0.5
µs
tRISE
Rise time
VCM = 1.65V
∆ Vi = -/+ 20mV
CLOAD=100pF(1)(2)
0.4
µs
20
mA
1. ∆Vi is the differential voltage applied to input pins across the common voltage VCM.
2. Measured between 50% of input and output signal.
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Low voltage power switches
SABRE-LL-I
18
Low voltage power switches
18.1
Overview
Low voltage power switches are analog switches designed to operate from a single +2.4V to
+3.6V VGPIO_SPI supply. They are intended to provide and remove power supply to low
voltage devices. When switched on, they connect the VGPIO_SPI pin to their output pin
(GPIO[6] for low voltage power switch 1 or GPIO[7] for low voltage power switch 2) thus
powering the device connected to it. The turning on and off of each switch can be controlled
through serial interface.
S.A.B.Re provides a total of 2 low voltage power switches, each of them has current
limitation to minimum 150mA to limit inrush current when charging a capacitive load. When
the limit current has been reached, for more than a Tfilter time, then a flag is activated; this
flag is latched in the central logic and can be cleared by the firmware. Please note that, in
case of capacitive load, the current limit is reached the first time the low power switch is
turned on: therefore the user will find a limit flag that must be cleared.
The 2 low voltage power switches can be externally paralleled to obtain a single super low
voltage power switch. Low voltage pass switches sink current IPASS needed for their
functionality from pin VGPIO_SPI, they never inject current on this pin.
Figure 25. Low power switch block diagram
EnLowVSw[x]
LowVSwIlim[x]
To SPI
Driving
Circuit
V GPIO_SP
GPIO[6] (LPS 1)
or
GPIO[7] (LPS 2)
Current
Limit
Sensor
S
LowVSwIlimLth[x]
86/141
R
ClrLowVrSwLth
Reset Stat
GPIO[6]/GPIO[7]
Driver
SABRE-LL-I
Low voltage power switches
Table 62.
Parameter
VPSW
3.3V low power switch specification
Description
Input voltage range
VOUT_MAX
Output voltage
RDSON
On resistance
ILIMIT
tdeglitch
Test condition
Min
Typ
2.4
Iload=100mA
Current limit
150
Current limit deglitch
time
50
250
Max
Unit
3.6
V
VGPIO_SPI
V
1
O
350
mA
ns
tI_lim
Current limit response
time
650
ns
CLOAD
Max load capacitance
2.5
µF
tON
On delay
VGPIO_SPI=3.3V
ILOAD=1mA
CLOAD=100pF(1)
650
ns
tOFF
Off delay
VGPIO_SPI=3.3V
ILOAD=1mA
CLOAD=100pF(1)
450
ns
1. Time measured from change in SPI interface to 50% of external pin transition.
87/141
General purpose PWM
SABRE-LL-I
19
General purpose PWM
19.1
Overview
S.A.B.Re includes three general purpose PWM generators that can be redirected on GPIO
pins (see Chapter 23). Two of these generators (Aux_PWM_1 and Aux_PWM_2) work with
a fixed period FOSC/512 and have a programmable duty cycle; the other one (GP_PWM)
has a programmable base time clock and a programmable time for both high and low levels.
19.2
General purpose PWM generators 1 and 2 (AuxPwm1 and
AuxPwm2)
The Duty cycle of these PWM generators can be changed by writing the AuxPwmXCtrl bits
(where X can be 1 or 2) in the AuxPwm1Ctrl and AuxPwm2Ctrl registers. Their positive duty
cycle will change according to the equation:
PWM_X_DUTY = AuxPwmXCtrl [ 9:0 ]/512
According to this equation a programmed “0” value will cause a 0% duty cycle (output
always at logic level 0).
19.3
Programmable PWM generator (GpPwm)
GpPWM has a programmable base clock that can be changed by programming the
GpPwmBase[6:0] bits in the GpPwmBase register. The clock will change according to the
equation:
PWM_BASE_PERIOD = ( GpPwmBase [ 6:0 ] + 1 ) × Tosc
The high and low level duration (expressed in base clock periods), can be programmed
writing the GpPwmHigh[7:0] and GpPwmLow[7:0] bits in the GpPwmCtrl register so they will
change according to following equations:
High_level_Time = GpPwmHigh [ 7:0 ] × PWM_BASE_PERIOD
Low_level_Time = GpPwmLow [ 7:0 ] × PWM_BASE_PERIOD
The resulting period of the PWM will be:
Period = ( GpPwmHigh [ 7:0 ] + GpPwmLow [ 7:0 ] ) + PWM_BASE_PERIOD
and the positive duty cycle will result:
High_level_Time
GpPwmHigh [ 7:0 ]
- = -------------------------------------------------------------------------------------------------------DutyCycle = ---------------------------------------------------------------------------------------------High_level_Time + Low_level_Time
GpPwmHigh [ 7:0 ] + GpPwmLow [ 7:0 ]
A programmed value of 0 in GpPwmHigh[7:0] and GpPwmLow[7:0] bits will force the PWM
generator output to be always at logic level “0”.
88/141
SABRE-LL-I
Interrupt controller
20
Interrupt controller
20.1
Overview
S.A.B.Re contains one programmable interrupt controller that can be used to advice the
firmware, through the serial interface, when a certain event happens inside the IC. The
output of the interrupt circuit can be also redirected on a GPIO pin therefore the event can
be signaled directly to the external circuits.
Figure 26. Low power switch block diagram
EnIntCtrl
Disable Pulse DisableSignals
Generation logic
Pulse
Generator
To Gpio
IntCtrlPolarity
Enable signal
s
Decode logic
Monitored signals
DisableMonitor
EnIntCtrlPulse
IntCtrlAutoDisable
EnIntCtrlPulse
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Interrupt controller
20.2
SABRE-LL-I
Interrupt controller monitored signal
The table here below contains the events that can be monitored by the interrupt controller.
Table 63.
Interrupt controller event
Event
Event description
Mtr1Fault
Bridge 1 fault (Ilimit event)
Mtr2Fault
Bridge 2 fault (Ilimit event)
Mtr3Fault
Bridge 3 fault (Ilimit event)
Mtr4Fault
Bridge 4 fault (Ilimit event)
nAWAKE
nAWAKE pin low
SwRegCtrl Ilimit
Switching regulator controller Ilimit event.
VMainSW Ilimit
Main switching regulator Ilimit event.
LowPowSw 1
Low voltage power switch 1 Ilimit event.
LowPowSw 2
Low voltage power switch 2 Ilimit event
Warm
Notes
Warming event
WDWarn
Watch dog warning event
WD
Watch dog event
DigCmp
Digital comparator
ADCDone1
ADC conversion done 1
(1)
ADCDone2
ADC conversion done 2
(1)
Vloop1Ilim
AUX1 Ilimit event.
1. This event is disabled if the related ADC channel is configured in continuous mode.
Any event detection can be enabled and disabled by setting at logic level 1 the relative
enable bit in the interrupt controller configuration register (IntCrtlCfg).
The interrupt controller can be programmed to give a pulse when a monitored event
happens or to continuously maintaining the output active until the interrupt condition is
finished.
When programmed to signal the enabled events by giving pulses, the interrupt controller
can be configured to disable the event that caused the interrupt request until the firmware
re-enables it writing the relative bit in the control register (IntCrtlCtrl) or to continue to
monitor the event.
The GPIO output of this circuit can be programmed to be active high or active low.
Table 64.
Parameter
90/141
Interrupt controller specification
Description
tPULSE
Pulse duration
tINTFILT
Filter time
Test condition
Min
Typ
Max
Unit
16*Tosc
µs
200
ns
SABRE-LL-I
Digital comparator
21
Digital comparator
21.1
Overview
S.A.B.Re includes one digital comparator that can be used to signal, through serial
interface, that a channel converted by the ADC is greater, greater-equal, lesser, lesser
equal, or equal than a fixed value set by serial interface or than the value converted by the
other ADC channel.
This circuit can be used to monitor the temperature of the IC advising the firmware when it
reaches a certain value decided by the firmware by setting one ADC channel to do
continuous conversions of the temperature sensor.
The circuit operation can be enabled or disabled changing the EnDigCmp bit in the
configuration register DigCmpCfg. By setting the DigCmpUpdate[1:0] bits in the
configuration register, the comparator can be programmed to update its output in one of the
following ways:
●
DigCmpUpdate[1:0]=00
–
●
–
●
Each time a conversion is performed on ADC channel 0.
DigCmpUpdate[1:0]=10
–
●
Continuously (each clock).
DigCmpUpdate[1:0]=01
Each time a conversion is performed on ADC channel 1.
DigCmpUpdate[1:0]=11
–
ADC state machine driven.
When the last option is selected, the digital comparator will update its output in two different
ways depending on the configuration of the ADC converter. If ADC converter is configured
to do continuous conversions on both channels, the output of the comparator will be
updated when the double conversion is completed. If ADC converter is not configured to do
continuous conversions on both channels, the output of the comparator will be updated
each time a conversion is completed.
The comparator output can be digitally filtered so that the programmed condition has to be
found for three consecutive checks before to be signaled.
The picture here below is a block representation of the comparator.
91/141
Digital comparator
SABRE-LL-I
DigCmpValue[9:0]
A2DDone1
Logic ‘1’
DigCmpSelCh0[1]
A2DDone0
Figure 27. Digital Comparator block diagram
ADC FSM
Update
Signal
DigCmpUpdate[1:0]
A2DResult0[8:0]
Three check
s
filter
A2DResult1[8:0]
DigCmpSelCh0[0]
CmpOut
Data0[9:0]
DigCmpSelCh1[0]
COMPARATOR
SelCmpType[1:0]
EnDigCmp
Data1[9:0]
DigCmpSelCh1[1]
Here below is reported the comparison type truth table:
Table 65.
Comparison type truth
EnDigCmp
SelCmpType[1]
SelCmpType[0]
Comparison type
0
X
X
Disabled
1
0
0
Data0[9:0] ≤1³1÷Data1[9:0]
1
0
1
Data0[9:0] = Data1[9:0]
1
1
0
Data0[9:0] > Data1[9:0]
1
1
1
Data0[9:0] ≤= Data1[9:0]
Here below is reported the Data0/Data1 selection truth table:
Table 66.
92/141
DataX selection truth
DigCmpSelChX[1]
DigCmpSelChX[0]
DataX[9:0]
0
X
DigCmpValue[9:0]
1
0
A2DResult1[8:0]
1
1
A2DResult1[8:0]
SABRE-LL-I
GPIO pins
22
GPIO pins
22.1
Overview
Some of the pins of S.A.B.Re are indicated as GPIO (General Purpose I/O). These pins can
be configured to be used in different ways depending on customer application. All GPIOs
can be used as digital input/output pins with digital value settable/readable using serial
interface or as analog input pins that can be converted using the A2D system. Some of the
pins can be used for special purposes: i.e. two of them can be used to access to the pass
switch function, other two are used as feedback pins for the auxiliary synchronous switching
regulators.
All input Schmitt triggers and output circuitry used for start-up purposes are powered by the
internally generated V3v3, while the digital output buffers are powered by VGPIO_SPI pin. To
ensure independency between V3v3 and VGPIO_SPI the GPIOs output drivers are open-drain
driver or the high side MOS is in back-to-back configuration to avoid the presence of the
body diode between output and supply (all back-to-back drivers can be customized to
become open-drain drivers with a metal change).
All digital output signals can be inverted before being provided on the relative GPIO pins.
Here below is reported the table with GPIO functions:
Table 67.
GPIO functions description
Function(1)
Pin
Name
Input
Output
Notes
Special
Analog
Digital
Analog
Digital
- SPI IN
- SPI OUT
- Interrupt ctrl.
- AuxPwm1
- AuxPwm2
Start-up
Open drain
configuration
output
pin
Open drain
output
GPIO[0]
- ADC input
GPIO[1]
- ADC input
- Comp1 In- Vaux1 F.B.
- SPI IN
- SPI OUT
- Interrupt ctrl.
- AuxPwm1
- AuxPwm2
GPIO[2]
- ADC input
- Comp2 In- Vaux2 F.B.
- SPI IN
- IN PWM
- SPI OUT
- Interrupt ctrl.
- AuxPwm2
- AuxPwm3
Open drain
output
GPIO[3]
- ADC input
- SPI IN
- SPI OUT
- AuxPwm2
- AuxGpPwm3
Start-up
Open drain
configuration
output
pin
- SPI IN
- SPI OUT
- Interrupt ctrl.
- AuxPwm1
- AuxPwm3
Start-up
configuration Open drain
output
pin
GPIO[4]
- ADC input
93/141
GPIO pins
Table 67.
SABRE-LL-I
GPIO functions description (continued)
Function(1)
Pin
Name
Input
GPIO[6]
GPIO[7]
- ADC input
- ADC input
- ADC input
Digital
Analog
- SPI IN
- SPI IN
- Low Pow Sw 1
- SPI OUT
- A2DGpo
- AuxPwm2
- Comp2 out
Full driver
connected to
VGPIO_SPI
- Low Pow Sw 2
- SPI OUT
- AuxPwm1
- AuxPwm3
- Comp1 out
Full driver
connected to
VGPIO_SPI
- CurrDAC
- SPI OUT
- AuxPwm1
- AuxPwm3
- Comp2 out
- SPI IN
- SPI IN(2)
- ADC input
GPIO[9]
- SPI IN
- ADC input
- ID 1
- OpAmp1 in+
- IN PWM
- SPI IN
- ADC input
GPIO[10]
- ID 2
- OpAmp1 in- IN PWM
GPIO[11] - ADC input
94/141
Digital
- SPI OUT
- Reg. loop 1
- Comp1 out
- AuxPwm3
GPIO[8]
GPIO[12]
Notes
Special
Analog
GPIO[5]
Output
- SPI IN
- IN PWM
- ADC input
- SPI IN
- OpAmp2 in+ - STEP_REQ
- OpAmp1 Out
Slave
Control
5 volt input
tolerant
Full driver BB
powered by
V3v3
Open drain
output
- SPI OUT
- Interrupt contr.
- AuxPwm1
- Reg. loop 3
Full driver
connected to
VGPIO_SPI
- SPI OUT
- Interrupt ctrl.
- AuxPwm2
- AuxPwm3
Full driver
connected to
VGPIO_SPI
- SPI OUT
- A2DGpo
- AuxPwm1
- AuxPwm2
Full driver
connected to
VGPIO_SPI
- SPI OUT
- Interrupt ctrl
- Comp2 out
- Reg. loop 2
Full driver BB
(can be
powered by
V3v3 with a
metal change)
SABRE-LL-I
Table 67.
GPIO pins
GPIO functions description (continued)
Function(1)
Pin
Name
Input
Output
Notes
Special
Analog
Digital
Analog
Digital
- ADC input
GPIO[13]
- SPI IN
- OpAmp2 in-
- SPI OUT
- AuxPwm1
- Reg. loop 3
- AuxPwm3
Full driver
connected to
VGPIO_SPI
GPIO[14] - ADC input
- SPI OUT
- Interrupt ctrl.
- AuxPwm2
- AuxPwm3
Full driver
connected to
VGPIO_SPI
- SPI IN
- OpAmp2 Out
1. In the above table the following abbreviations were used.
2. Gpio[8] input Schmitt trigger is disabled by default (after a reset) to be able to read the digital value from this pin it needs to
be enabled writing a logic ‘1’ in the EnGpio8DigIn in CurrDacCtrl register.
Table 68.
Abbreviations
Abbreviation
ADC input
Meaning
Input to the ADC system.
SPI IN
Digital state of this pin is readable through SPI.
SPI OUT
Digital state of this pin can be set through SPI.
BB
Back to back high side driver.
Comp1 IN -
This pin can be used as minus input for comparator 1.
Comp2 IN -
This pin can be used as minus input for comparator 2.
Vaux1 FB
This pin can be used as feedback input for AUX1 regulator obtained by
using bridge 3.
A2DGpo
This pin can be used to carry out the A2DGpo value related to the ADC
conversion S.A.B.Re is doing.
Reg. Loop 3
This pin can be used as output of the regulation loop used by AUX3
regulator obtained by using bridge 4.
STEP_REQ
This pin can be used to request a stepper sequencer evolution step.
Interrupt Ctrl
This pin can be used to carry out the interrupt controller circuit output.
Vaux2 FB
This pin can be used as feedback pin by AUX2 regulator obtained by
using bridge 3
IN PWM
This pin can be used to provide an external PWM to bridges.
Reg. Loop 1
This pin can be used as output of the regulation loop used by AUX1
regulator.
Comp1 OUT
This pin can be used as output of the comparator 1.
AuxPwm1
Low Volt. Pow. Sw. 1
This pin can be used to carry out the PWM generated by AuxPwm1 circuit.
This pin can be used as output of low voltage power switch 1.
95/141
GPIO pins
SABRE-LL-I
Table 68.
Abbreviations (continued)
Abbreviation
Meaning
Reg. Loop 2
This pin can be used as output of the regulation loop used by AUX2
regulator.
Comp2 OUT
This pin can be used as output of the comparator 2.
AuxPwm2
Low Volt. Pow. Sw. 2
Reg. Loop 3
This pin can be used to carry out the PWM generated by AuxPwm2 circuit.
This pin can be used as output of low voltage power switch 2.
This pin can be used as output of the regulation loop used by AUX3
regulator.
AuxPwm3
This pin can be used to carry out the PWM generated by AuxPwm3 circuit.
CurrDAC
This pin can be used to carry out the output of the current DAC circuit.
AuxPwm4
This pin can be used to carry out the PWM generated by AuxPwm4 circuit.
OpAmp1 in+
This pin can be used as operational amplifier 1 non-inverting input.
OpAmp1 in-
This pin can be used as operational amplifier 1 inverting input.
OpAmp1 Out
This pin can be used as operational amplifier 1 output.
OpAmp2 in+
This pin can be used as operational amplifier 2 non-inverting input.
OpAmp2 in-
This pin can be used as operational amplifier 2 inverting input.
OpAmp2 Out
This pin can be used as operational amplifier 2 output.
ID 1
This pin is used to determine the SPI ID1 bit value.
ID 2
This pin is used to determine the SPI ID2 bit value.
Slave Control
This pin is used as slave control when the IC is configured as master.
Hereafter are reported the detailed specifications for each GPIO.
To enable the functionality of the GPIO as output pin, the relative GpioOutEnable[14:0] bit
must be enabled in GpioOutEnable register.
Each GPIO could be configured by setting the appropriate GpioXMode[2:0] in the GpioCtrlX
register.
96/141
SABRE-LL-I
22.2
GPIO pins
GPIO[0]
The GPIO[0] truth table is (for the abbreviation list please refer to Table 68):
Table 69.
GPIO[0] truth
GPIO[0] SPI BITS
State at
StartUp
Function
Note
X
Detection of StartUp config
See
Chapter 8
X
X
HiZ (SPI_IN)
0
0
0
SPI OUT
(1)
1
0
0
1
InterruptCtrl
(1)
0
1
0
1
0
AuxPwm1
(1)
0
1
0
1
1
AuxPwm2
(1)
0
1
1
0
0
SPI OUT inverted
(1)
0
1
1
0
1
InterruptCtrl inverted
(1)
0
1
1
1
0
AuxPwm1 inverted
(1)
0
1
1
1
1
AuxPwm2 inverted
(1)
GpioOut
Enable [0]
Mode[2]
Mode[1]
Mode[0]
1
X
X
X
0
0
X
0
1
0
1. In all configurations in which GPIO[0] is enabled as output:
a) the GPIO[0] pin can be always used as an analog input to the ADC system (ADC function) by writing its
address in the A2DChannelX[4:0] in the A2DConfigX register and starting a conversion;
b) the GPIO[0] pin can be always used as a digital input so its value can be always read through SPI
interface (SPI_IN function);
c) the GPIO[0] pin is an open drain output.
97/141
GPIO pins
SABRE-LL-I
Figure 28. GPIO[0] block diagram
V 3v3
To Serial Interface
To ADC
V 3v3
To Control Logic
Start-up pin State
Detect circuit
V 3v3
From Serial
Interface
V 3v3
Logic Decode
EnStartUpDtc
From Power Up
FSM
Table 70.
Parameter
GPIO[0] Driver
GPIO[0] specification
Description
VIH
High level input voltage
VIL
Low level input voltage
VHYS
Input voltage hysteresis
VOL
Low level output voltage
ILEAKAGE
Test condition
Load capacitance
tDELAY
Delay from serial write to pin
Low
Typ
Max
0.22
IOUT = 15mA
0 ≤Vout ≤ V3v3
CLOAD =50 pF(1)
-1
Unit
V
0.8
Leakage current
CLOAD
Min
1.6
1. Measured between nSS rising edge and 50% of Vout.
98/141
GPIO[0]
V
V
0.4
V
1
µA
200
pF
500
ns
SABRE-LL-I
22.3
GPIO pins
GPIO[1]
The GPIO[1] truth table is (for the abbreviation list please refer to Table 68):
Table 71.
GPIO[1] truth
AUX1Enable
or
AUX1System
GPIO[1] SPI BITS
Function
Note
X
AUX1 FB
(1)
X
X
HiZ (SPI_IN)
1
X
X
Comp1 IN -
(2)
1
0
0
0
SPI OUT
(2)
0
1
0
0
1
AuxPwm1
(2)
0
1
0
1
0
AuxPwm2
(2)
0
1
0
1
1
InterruptCtrl
(2)
0
1
1
0
0
SPI OUT inverted
(2)
0
1
1
0
1
AuxPwm1 inverted
(2)
0
1
1
1
0
AuxPwm2inverted
(2)
0
1
1
1
1
IntCtrlinverted
(2)
GpioOut
Enable [1]
Mode[2]
Mode[1]
Mode[0]
1
X
X
X
0
0
0
0
0
0
1. AUX1Enable or AUX1System bit =1 represent the case in which AUX1 is used as a System or Not System
regulator.
2. In all configurations in which GPIO[1] is enabled as output:
a) the GPIO[1] pin can be always used as an analog input to the ADC system (ADC function) by writing
its address in the A2DChannelX[4:0] in the A2DConfigX register and starting a conversion;
b) the GPIO[1] pin can be always used as a digital input so its value can be always read through SPI
interface (SPI_IN function);
c) the GPIO[1] pin is an open drain output.
99/141
GPIO pins
SABRE-LL-I
Figure 29. GPIO[1] block diagram
V 3v3
To Serial Interface
To ADC
To AUX1 Feedback
comparator
GPIO[1]
V 3v3
From Serial
Interface
V 3v3
Logic Decode
Gpio[1] Driver
Table 72.
Parameter
GPIO[1] specification
Description
Test condition
VIH
High level input voltage
VIL
Low level input voltage
VHYS
Input voltage hysteresis
VOL
Low level output voltage
IOUT = 15mA
Leakage current
0 ≤Vout ≤ V3v3
ILEAKAGE
tDELAY
Delay from serial write to
pin low
Typ
Max
1.6
0.22
CLOAD =50 pF(1)
-1
Unit
V
0.8
1. Measured between nSS rising edge and 50% of Vout.
100/141
Min
V
V
0.4
V
1
µA
500
ns
SABRE-LL-I
22.4
GPIO pins
GPIO[2]
The GPIO[2] truth table is (for the abbreviation list please refer to Table 68):
Table 73.
GPIO[2] truth
AUX2Enable
or
AUX2System
GPIO[1] SPI BITS
Function
Note
X
AUX2 FB
(1)
X
X
HiZ (SPI_IN)
1
X
X
Comp1 IN -
(2)
1
0
0
0
SPI OUT
(2)
0
1
0
0
1
AuxPwm2
(2)
0
1
0
1
0
AuxPwm3
(2)
0
1
0
1
1
InterruptCtrl
(2)
0
1
1
0
0
SPI OUT inverted
(2)
0
1
1
0
1
AuxPwm2 inverted
(2)
0
1
1
1
0
AuxPwm3 inverted
(2)
0
1
1
1
1
IntCtrlinverted
(2)
GpioOut
Enable [1]
Mode[2]
Mode[1]
Mode[0]
1
X
X
X
0
0
0
0
0
0
1. AUX2Enable or AUX2System bit =1 represent the case in which AUX1 is used as a System or Not System
regulator.
2. In all configurations in which GPIO[2] is enabled as output:
a) the GPIO[2] pin can be always used as an analog input to the ADC system (ADC function) by writing
its address in the A2DChannelX[4:0] in the A2DConfigX register and starting a conversion;
b) the GPIO[2] pin can be always used as a digital input so its value can be always read through SPI
interface (SPI_IN function);
c) please note that GPIO[2] output is directly connected to ExtPWM3 input for Bridge 3 or 4 and therefore
particular care must be taken in order to avoid wrong PWM signals when ExtPWM3 is selected for
bridge 3 or 4;
d) the GPIO[2] pin is an open drain output.
101/141
GPIO pins
SABRE-LL-I
Figure 30. GPIO[2] block diagram
V 3v3
To ExtPWM3
To Serial Interface
To ADC
To AUX2 Feedback
comparator
GPIO[2]
V 3v3
From Serial
Interface
V 3v3
Logic Decode
Gpio[2] Driver
Table 74.
Parameter
GPIO[2] specification
Description
VIH
High level input voltage
VIL
Low level input voltage
VHYS
Input voltage hysteresis
VOL
Low level output voltage
ILEAKAGE
tDELAY
Leakage current
Delay from serial write to
pin low
Test condition
Typ
Max
1.6
0.22
IOUT = 15mA
0 ≤ Vout ≤ V3v3
CLOAD =50 pF(1)
-1
Unit
V
0.8
1. Measured between nSS rising edge and 50% of Vout.
102/141
Min
V
V
0.4
V
1
µA
500
ns
SABRE-LL-I
22.5
GPIO pins
GPIO[3]
The GPIO[3] truth table is (for the abbreviation list please refer to Table 68):
Table 75.
GPIO[3] truth
GPIO[3] SPI BITS
State at
StartUp
Function
Note
X
Detection of StartUp config
See
Chapter 8
X
X
HiZ (SPI_IN)
0
0
0
SPI OUT
(1)
1
0
0
1
AuxPwm1
(1)
0
1
0
1
0
AuxPwm2
(1)
0
1
0
1
1
AuxPwm2
(1)
0
1
1
0
0
SPI OUT inverted
(1)
0
1
1
0
1
AuxPwm1 inverted
(1)
0
1
1
1
0
AuxPwm2 inverted
(1)
0
1
1
1
1
AuxPwm3 inverted
(1)
GpioOut
Enable [3]
Mode[2]
1
X
X
X
0
0
X
0
1
0
Mode[1] Mode[0]
1. In all configurations in which GPIO[3] is enabled as output:
a) the GPIO[3] pin can be always used as an analog input to the ADC system (ADC function) by writing its
address in the A2DChannelX[4:0] in the A2DConfigX register and starting a conversion;
b) the GPIO[3] pin can be always used as a digital input so its value can be always read through SPI
interface (SPI_IN function);
c) the GPIO[3] pin is an open drain output.
103/141
GPIO pins
SABRE-LL-I
Figure 31. GPIO[3] block diagram
V 3v3
To Serial Interface
To ADC
V 3v3
Start-up pin State
Detect circuit
To Control Logic
GPIO[3]
V 3v3
V 3v3
From Serial
Interface
Logic Decode
EnStartUpDtc
From Power Up
FSM
Table 76.
Parameter
Gpio[3] Driver
GPIO[3] specification
Description
Test condition
VIH
High level input voltage
VIL
Low level input voltage
VHYS
Input voltage hysteresis
VOL
Low level output voltage
IOUT = 15mA
Leakage current
0 ≤Vout ≤ V3v3
ILEAKAGE
CLOAD
Load capacitance
tDELAY
Delay from serial write to pin
low
Typ
Max
1.6
0.22
CLOAD =50 pF(1)
-1
Unit
V
0.8
1. Measured between nSS rising edge and 50% of Vout.
104/141
Min
V
V
0.4
V
1
µA
200
pF
500
ns
SABRE-LL-I
22.6
GPIO pins
GPIO[4]
The GPIO[4] truth table is (for the abbreviation list please refer to Table 68):
Table 77.
GPIO[4] truth
GPIO[4] SPI BITS
State at
StartUp
Function
Note
X
Detection of StartUp config
See
Chapter 8
X
X
HiZ (SPI_IN)
0
0
0
SPI OUT
(1)
1
0
0
1
Interrupt Ctrl
(1)
0
1
0
1
0
AuxPwm1
(1)
0
1
0
1
1
AuxPwm3
(1)
0
1
1
0
0
SPI OUT inverted
(1)
0
1
1
0
1
Interrupt Ctrl
(1)
0
1
1
1
0
AuxPwm1 inverted
(1)
0
1
1
1
1
AuxPwm3 inverted
(1)
GpioOut
Enable [4]
Mode[2]
Mode[1]
Mode[0]
1
X
X
X
0
0
X
0
1
0
1. In all configurations in which GPIO[4] is enabled as output:
a) the GPIO[4] pin can be always used as an analog input to the ADC system (ADC function) by writing its
address in the A2DChannelX[4:0] in the A2DConfigX register and starting a conversion;
b) the GPIO[4] pin can be always used as a digital input so its value can be always read through SPI
interface (SPI_IN function);
c) the GPIO[4] pin is an open drain output.
105/141
GPIO pins
SABRE-LL-I
Figure 32. GPIO[4] block diagram
V 3v3
To Serial Interface
To ADC
V 3v3
Start-up pin State
Detect circuit
To Control Logic
From Serial
Interface
Logic Decode
EnStartUpDtc
From PowerUp
FSM
Table 78.
Parameter
Gpio[4] Driver
GPIO[4] specification
Description
Test condition
VIH
High level input voltage
VIL
Low level input voltage
VHYS
Input voltage hysteresis
VOL
Low level output voltage
IOUT = 15mA
Leakage current
0 ≤Vout ≤ V3v3
ILEAKAGE
CLOAD
tDELAY
Delay from serial write to pin low
Min
Typ
Max
1.6
0.22
CLOAD =50
pF(1)
-1
Unit
V
0.8
Load capacitance
1. Measured between nSS rising edge and 50% of Vout.
106/141
GPIO[4]
V 3v3
V 3v3
V
V
0.4
V
1
µA
200
pF
500
ns
SABRE-LL-I
22.7
GPIO pins
GPIO[5]
The GPIO[5] truth table is (for the abbreviation list please refer to Table 68):
Figure 33. GPIO[5] block diagram
To internal Logic & SPI
V 3v3
To ADC
V 3V3
V 3v3
From Control
logic
GPIO[5]
Logic Decode
Back to Back
Driver
Table 79.
GPIO[5] truth
AUX1
system
Master(1)
and
Vloop1
external(2)
GPIO[5] SPI BITS
GpioOut
enable[5]
Function
Note
Mode[2] Mode[1] Mode[0]
1
X
X
X
X
X
Slave control
0
1
X
X
X
X
Reg Loop1 OUT
0
0
0
X
X
X
HiZ (SPI_IN)
0
0
1
0
0
0
SPI OUT
(3)
0
0
1
0
0
1
Comp1OUT
(3)
0
0
1
0
1
0
Reg Loop1 OUT
(3)
0
0
1
0
1
1
AuxPwm3
(3)
0
0
1
1
0
0
SPI OUT inverted
(3)
0
0
1
1
0
1
Comp1OUT inverted
(3)
0
0
1
1
1
0
Reg Loop1 OUT
inverted
(3)
0
0
1
1
1
1
AuxPwm3 inverted
(3)
(3)
1. Master bit is at logic level “1” when S.A.B.Re is used as a master device (seeChapter 8)
107/141
GPIO pins
SABRE-LL-I
2. This bit is at logic level “1” if AUX1 regulator is a system regulator but its power stage is externally realized
(and therefore the regulation loop is not used to drive bridge 3). In this case Vloop1IsSys bit will be at logic
level “1”, while Vloop1OnMtr3SideA and Vloop1OnMtr3SideB bits will be at logic level “0” in
CoreConfigReg register.
3. In all configurations in which GPIO[5] is enabled as output:
a) the GPIO[5] pin can be always used as an analog input to the ADC system (ADC function) by writing its
address in the A2DChannelX[4:0] in the A2DConfigX register and starting a conversion;
b) the GPIO[5] pin can be always used as a digital input so its value can be always read through SPI
interface (SPI_IN function);
c) the GPIO[5] pin is a rail to rail, back to back output supplied by V3v3.
Table 80.
Parameter
GPIO[5] specification
Description
Min
VIH
High level input voltage
VIL
Low level input voltage
VHYS
Input voltage hysteresis
VOL
Low level output voltage
IOUT = 15mA
VOH
High level output voltage
IOUT = 5mA
2.75
0 ≤Vout ≤ V3v3
-1
ILEAKAGE
tDELAY
Leakage current
Delay from serial write to pin low
1. Measured between nSS rising edge and 50% of Vout.
108/141
Test condition
Typ
Max
1.6
V
0.8
0.22
CLOAD =50
pF(1)
Unit
V
V
0.4
V
V
1
µA
500
ns
SABRE-LL-I
22.8
GPIO pins
GPIO[6]
The GPIO[6] truth table is (for the abbreviation list please refer to Table 68):
Table 81.
GPIO[6] truth
GPIO[6] SPI BITS
StdByMode
AEnLow
VSw[1]
GpioOut
Mode[2] Mode[1] Mode[0]
enable[6]
Function
Note
1
X
X
X
X
X
Low Volt. Pow. Sw. 1
0
1
X
X
X
X
Low Volt. Pow. Sw. 1
0
0
0
X
X
X
HiZ (SPI_IN)
0
0
1
0
0
0
SPI OUT
(2)
0
0
1
0
0
1
A2DGpo
(2)
0
0
1
0
1
0
AuxPwm2
(2)
0
0
1
0
1
1
Comp2OUT
(2)
0
0
1
1
0
0
A2DGpo inverted
(2)
0
0
1
1
0
1
AuxGpPwm2 inverted
(2)
0
0
1
1
1
1
Comp2OUT inverted
(2)
(1)
1. When EnLowVSw[1]= ‘1’ the GpioOutEnable[6] bit is forced to 0.
2. In all configurations in which GPIO[6] is enabled as output:
a) the GPIO[6] pin can be always used as an analog input to the ADC system (ADC function) by writing its
address in the A2DChannelX[4:0] in the A2DConfigX register and starting a conversion;
b) the GPIO[6] pin can be always used as a digital input so its value can be always read through SPI
interface (SPI_IN function);
c) the GPIO[6] pin is a rail to rail output supplied by VGPIO_SPI.
109/141
GPIO pins
SABRE-LL-I
Figure 34. GPIO[6] block diagram
V GPIO_SPI
Power Switch 1
To internal
Logic & SPI
V 3v3
V 3v3
From Serial
Interface
EnPass1
To ADC
V 3v3
GPIO[6]
Logic Decode
Stand By mode
Gpio[6] Driver
Table 82.
Parameter
GPIO[6] specification
Description
VIH
High level input voltage
VIL
Low level input voltage
VHYS
Input voltage hysteresis
VOL
Low level output voltage
IOUT = 15mA
Leakage current
0 ≤Vout ≤ V3v3
ILEAKAGE
tDELAY
Delay from serial write to pin low
1. Measured between nSS rising edge and 50% of Vout.
110/141
Test condition
Min
Typ
Max
1.6
V
0.8
0.22
CLOAD =50 pF(1)
-1
Unit
V
V
0.4
V
1
µA
500
ns
SABRE-LL-I
22.9
GPIO pins
GPIO[7]
The GPIO[7] truth table is (for the abbreviation list please refer to Table 68):
Table 83.
GPIO[7] truth
GPIO[7] SPI BITS
EnLowVSw[2]
GpioOut
enable[7]
Function
Note
(1)
Mode[2] Mode[1] Mode[0]
1
X
X
X
X
Low Volt. Pow. Sw. 2
0
0
X
X
X
HiZ (SPI_IN)
0
1
0
0
0
SPI OUT
(2)
0
1
0
0
1
AuxPwm1
(2)
0
1
0
1
0
AuxPwm3
(2)
0
1
0
1
1
Comp1OUT
(2)
0
1
1
0
0
AuxPwm1 inverted
(2)
0
1
1
0
1
AuxPwm3 inverted
(2)
0
1
1
1
1
Comp1OUT inverted
(2)
1. When EnLowVSw[2] = ‘1’ the GpioOutEnable[7] bit is forced to 0.
2. In all configurations in which GPIO[7] is enabled as output:
a) the GPIO[7] pin can be always used as an analog input to the ADC system (ADC function) by writing
its address in the A2DChannelX[4:0] in the A2DConfigX register and starting a conversion;
b) the GPIO[7] pin can be always used as a digital input so its value can be always read through SPI
interface (SPI_IN function);
c) the GPIO[7] pin is a rail to rail output supplied by VGPIO_SPI.
111/141
GPIO pins
SABRE-LL-I
Figure 35. GPIO[7] block diagram
V GPIO_SPI
Power Switch 2
To internal
Logic & SPI
V 3v3
EnPass2
To ADC
V 3v3
From Serial
Interface
Table 84.
Parameter
GPIO[7]
Logic Decode
GPIO[7] specification
Description
Test condition
Min
VIH
High level input voltage
VIL
Low level input voltage
VHYS
Input voltage hysteresis
VOL
Low level output voltage
IOUT = 15mA,
VGPIO_SPI = 3.15V
VOH
High level output voltage
IOUT = 15mA,
VGPIO_SPI = 3.15V
2.75
0 ≤Vout ≤ VGPIO_SPI,
VGPIO_SPI = 3.15V
-1
ILEAKAGE
tDELAY
Leakage current
Delay from serial write to pin low
1. Measured between nSS rising edge and 50% of Vout.
112/141
V GPIO_SPI
Typ
Max
1.6
V
0.8
0.22
CLOAD =50 pF(1)
Unit
V
V
0.4
V
V
1
µA
500
ns
SABRE-LL-I
22.10
GPIO pins
GPIO[8]
The GPIO[8] truth table is (for the abbreviation list please refer to Table 68):
Table 85.
GPIO[8] truth
GPIO[8] SPI BITS
Function (2)
Note
X
CurrDAC
(3)
X
X
HiZ (SPI_IN)
(4)
0
0
0
SPI OUT
(4)
1
0
0
1
AuxPwm1
(4)
0
1
0
1
0
AuxPwm3
(4)
0
1
0
1
1
Comp2OUT
(4)
0
1
1
0
0
AuxPwm1
inverted
(4)
0
1
1
0
1
AuxPwm3
inverted
(4)
0
1
1
1
1
Comp2OUT inverted
(4)
EnDac
(1)
GpioOut
enable[8]
Mode[2]
Mode[1]
Mode[0]
1
X
X
X
0
0
X
0
1
0
1. The EnDAC bit in the CurrDacCtrl register enables the Current DAC (seeChapter 17)
2. This pin is 5 volt input tolerant.
3. When EnDAC = ‘1’ the GpioOutEnable[8] bit is forced to 0. The current DAC circuit is directly connected to
GPIO[8] pin so as soon as it is enabled it will sink current from pin.
4. The GPIO[8] pin can be always used as a digital input so its value can be always read through SPI
interface (SPI_IN function). To avoid affecting the precision of CurrDAC when this is used to sink very low
currents, it is necessary to enable the digital input functionality of GPIO[8]. Therefore to read their values
through SPI interface (SPI_IN function), it is necessary to enable the EnGpio8DigIn bit in the CurrDacCtrl
register.
113/141
GPIO pins
SABRE-LL-I
Figure 36. GPIO[8] block diagram
V 3v3
To internal Logic & SPI
EnGpio8DigIn
To ADC
V 3v3
V 3v3
From Serial
Interface
Logic Decode
GPIO[8]
Gpio[8] Driver
From Serial
Interface
Table 86.
Parameter
Current Sink
Circuit
GPIO[8] specification
Description
VIH
High level input voltage
VIL
Low level input voltage
VHYS
Input voltage hysteresis
VOL
Low level output voltage
Min
Typ
Max
1.6
V
0.8
0.22
IOUT = 15mA,
Unit
V
V
0.4
V
ILEAK_0
Leakage current
EnGpio8DigIn=0,
0 ≤ Vout ≤ 5V
-1
1
µA
ILEAK_1
Leakage current
EnGpio8DigIn=1,
0 ≤ Vout ≤ 5V
-1
5
µA
A/D path absorbed current
ADChannelX[4:0]
=10001 and
bit EnDacScale=0
-1
1
µA
500
ns
IAD
tDELAY
Delay from serial write to pin low
1. Measured between nSS rising edge and 50% of Vout.
114/141
Test condition
CLOAD =50 pF(1)
SABRE-LL-I
22.11
GPIO pins
GPIO[9]
The GPIO[9] truth table is (for the abbreviation list please refer to Table 68):
Table 87.
GPIO[9] truth
GPIO[9] SPI BITS
(1)
Function (2)
Note
X
OpAmp1 in+
(3)
X
X
HiZ (SPI_IN)
0
0
0
SPI OUT
(4)
1
0
0
1
Interrupt Ctrl
(4)
0
1
0
1
0
AuxPwm2
(4)
0
1
0
1
1
Reg Loop 3
(4)
0
1
1
0
0
Interrupt Ctrl inverted
(4)
0
1
1
0
1
AuxPwm2 inverted
(4)
0
1
1
1
1
Reg Loop 3 inverted
(4)
Op1EnPlusPin
GpioOut
enable[9]
Mode[2]
Mode[1]
Mode[0]
1
X
X
X
0
0
X
0
1
0
1. The Op1EnPlusPin bit in the OpAmp1Ctrl register enables the connection of the positive input of Op1 to
GPIO[9] pin.
2. The GPIO[9] pin is used by the system when firmware requires the ID read action (Chapter 25)
3. When Op1EnPlusPin = ‘1’ the GpioOutEnable[9] bit is forced to 0.
4. In all configurations in which GPIO[9] is enabled as output:
a) the GPIO[9] pin can be always used as an analog input to the ADC system (ADC function) by writing its
address in the A2DChannelX[4:0] in the A2DConfigX register and starting a conversion;
b) the GPIO[9] pin can be always used as a digital input so its value can be always read through SPI
interface (SPI_IN function);
c) please note that GPIO[9] output is directly connected to ExtPWM1 input for Bridge 1 or 2 and therefore
particular care must be taken in order to avoid wrong PWM signals when ExtPWM1 is selected for
bridge 1 or 2;
d) the GPIO[9] pin is a rail to rail output supplied by VGPIO_SPI.
115/141
GPIO pins
SABRE-LL-I
Figure 37. GPIO[9] block diagram
To internal Logic & SPI
ID1
V 3v3
Pin State Sample
Circuit
SampleID
To ADC
GPIO[9]
V GPIO_SPI
V 3v3
From SPI
Logic Decode
Gpio[9] Driver
To OpAmp1 In+
Table 88.
Parameter
GPIO[9] specification
Description
Test condition
VIH
High level input voltage
VIL
Low level input voltage
VHYS
Input voltage hysteresis
VOL
Low level output voltage
IOUT = 15mA,
VGPIO_SPI = 3.15V
VOH
High level output voltage
IOUT = 15mA,
VGPIO_SPI = 3.15V
2.75
0 ≤Vout ≤ VGPIO_SPI,
VGPIO_SPI = 3.15V
-1
ILEAKAGE
tDELAY
Leakage current
Typ
Max
1.6
0.22
Delay from serial write to pin low
CLOAD =50 pF(1)
Unit
V
0.8
1. Measured between nSS rising edge and 50% of Vout.
116/141
Min
V
V
0.4
V
V
1
µA
500
ns
SABRE-LL-I
22.12
GPIO pins
GPIO[10]
The GPIO[10] truth table is (for the abbreviation list please refer to Table 68):
Table 89.
GPIO[10] truth
GPIO[10] SPI BITS
(1)
Function (2)
Note
X
OpAmp1 in-
(3)
X
X
HiZ (SPI_IN)
0
0
0
SPI OUT
(4)
1
0
0
1
Interrupt Ctrl
(4)
0
1
0
1
0
AuxPwm2
(4)
0
1
0
1
1
AuxPwm3
(4)
0
1
1
0
0
Interrupt Ctrl inverted
(4)
0
1
1
0
1
AuxPwm2 inverted
(4)
0
1
0
0
0
AuxPwm3 inverted
(4)
Op1EnPlusPin
GpioOut
enable[10]
Mode[2]
Mode[1]
Mode[0]
1
X
X
X
0
0
X
0
1
0
1. The Op1EnMinusPin bit in the OpAmp1Ctrl register enables the connection of the positive input of Op1 to
GPIO[10] pin.
2. The GPIO[10] pin is used by the system when firmware requires the ID read action (Chapter 25)
3. When Op1EnPlusPin = ‘1’ the GpioOutEnable[10] bit is forced to 0.
4. In all configurations in which GPIO[10] is enabled as output:
a) the GPIO[10] pin can be always used as an analog input to the ADC system (ADC function) by writing
its address in the A2DChannelX[4:0] in the A2DConfigX register and starting a conversion;
b) the GPIO[10] pin can be always used as a digital input so its value can be always read through SPI
interface (SPI_IN function);
c) please note that GPIO[10] output is directly connected to ExtPWM2 input for bridge 1 or 2 and
therefore particular care must be taken in order to avoid wrong PWM signals when ExtPWM2 is
selected for bridge 1 or 2;
d) the GPIO[10] pin is a rail to rail output supplied by VGPIO_SPI.
117/141
GPIO pins
SABRE-LL-I
Figure 38. GPIO[10] block diagram
To internal Logic & SPI
ID2
V 3v3
Pin State Sample
Circuit
SampleID
To ADC
GPIO[10]
V GPIO_SPI
V 3v3
From SPI
Logic Decode
Gpio[10] Driver
To OpAmp1 In-
Table 90.
Parameter
GPIO[10] specification
Description
Test condition
VIH
High level input voltage
VIL
Low level input voltage
VHYS
Input voltage hysteresis
VOL
Low level output voltage
IOUT = 15mA,
VGPIO_SPI = 3.15V
VOH
High level output voltage
IOUT = 15mA,
VGPIO_SPI = 3.15V
2.75
0 ≤Vout ≤ VGPIO_SPI,
VGPIO_SPI = 3.15V
-1
ILEAKAGE
tDELAY
Leakage current
Typ
Max
1.6
0.22
Delay from serial write to pin low
CLOAD =50 pF(1)
Unit
V
0.8
1. Measured between nSS rising edge and 50% of Vout.
118/141
Min
V
V
0.4
V
V
1
µA
500
ns
SABRE-LL-I
22.13
GPIO pins
GPIO[11]
The GPIO[11] truth table is (for the abbreviation list please refer to Table 68):
Table 91.
GPIO[11] truth
GPIO[11] SPI BITS
EnOpl
(1)
Function
Note
X
OpAmp1 Out
(2)
X
X
HiZ (SPI_IN)
0
0
0
SPI OUT
(3)
1
0
0
1
A2DGpo
(3)
0
1
0
1
0
AuxPwm1
(3)
0
1
0
1
1
AuxPwm2
(3)
0
1
1
0
0
SPI OUT inverted
(3)
0
1
1
0
1
A2DGpo inverted
(3)
0
1
1
1
0
AuxPwm1 inverted
(3)
0
1
1
1
1
AuxPwm2 inverted
(3)
GpioOut
enable[11]
Mode[2]
Mode[1]
Mode[0]
1
X
X
X
0
0
X
0
1
0
1. The EnOp1 bit in the OpAmp1Ctrl register enables the operational amplifier 1.
2. When EnOp1 = ‘1’ the GpioOutEnable[11] bit is forced to 0.
3. In all configurations in which GPIO[11] is enabled as output:
a) the GPIO[11] pin can be always used as an analog input to the ADC system (ADC function) by writing
its address in the A2DChannelX[4:0] in the A2DConfigX register and starting a conversion;
b) the GPIO[11] pin can be always used as a digital input so its value can be always read through SPI
interface (SPI_IN function);
c) please note that GPIO[11] output is directly connected to ExtPWM4 input for bridge 3 or 4 and
therefore particular care must be taken in order to avoid wrong PWM signals when ExtPWM4 is
selected for bridge 3 or 4;
d) the GPIO[11] pin is a rail to rail output supplied by VGPIO_SPI.
119/141
GPIO pins
SABRE-LL-I
Figure 39. GPIO[11] block diagram
To internal Logic & SPI
V 3v3
To ADC
V GPIO_SPI
V 3v3
GPIO[11]
From Central
Logic
Logic Decode
OpAmp 1
Table 92.
Parameter
GPIO[11] specification
Description
Test condition
VIH
High level input voltage
VIL
Low level input voltage
VHYS
Input voltage hysteresis
VOL
Low level output voltage
IOUT = 15mA,
VGPIO_SPI = 3.15V
VOH
High level Output voltage
IOUT = -15mA,
VGPIO_SPI = 3.15V
2.75
0 ≤Vout ≤ VGPIO_SPI,
VGPIO_SPI = 3.15V
-1
ILEAKAGE
tDELAY
Leakage current
Typ
Max
1.6
0.22
Delay from serial write to pin low
CLOAD =50 pF(1)
Unit
V
0.8
1. Measured between nSS rising edge and 50% of Vout.
120/141
Min
V
V
0.4
V
V
1
µA
500
ns
SABRE-LL-I
22.14
GPIO pins
GPIO[12]
The GPIO[12] truth table is (for the abbreviation list please refer to Table 68):
Table 93.
GPIO[12] truth
GPIO[12] SPI BITS
AUX2enable
or
Op2En
AUX2syste
m (1)
PlusPin
1
X
X
X
X
X
RegLoop2
0
1
X
X
X
X
OpAmp2 in+
0
0
0
X
X
X
HiZ (SPI_IN)
0
0
1
0
0
0
SPI OUT
(3)
0
0
1
0
0
1
Interrupt Ctrl
(3)
0
0
1
0
1
0
Comp2OUT
(3)
0
0
1
0
1
1
RegLoop2
(3)
0
0
1
1
0
0
Interrupt Ctrl inverted
(3)
0
0
1
1
0
1
Comp2OUT inverted
(3)
0
0
1
1
1
1
RegLoop2 inverted
(3)
Function
GpioOut
Mode[2] Mode[1] Mode[0]
enable[12]
Note
(2)
1. AUX2Enable or AUX2System bit =1 represent the case in which AUX2 is used as a regulator (system or
not system).
2. When Op2EnPlusPin = ‘1’ the GpioOutEnable[11] bit is forced to 0.
3. In all configurations in which GPIO[12] is enabled as output:
a) the GPIO[12] pin can be always used as an analog input to the ADC system (ADC function) by writing
its address in the A2DChannelX[4:0] in the A2DConfigX register and starting a conversion;
b) the GPIO[12] pin can be always used as a digital input so its value can be always read through SPI
interface (SPI_IN function);
c) please note that GPIO[12] output is directly connected to StepCmd input for stepper driver and
therefore particular care must be taken in order to avoid wrong PWM signals when StepCmd is
selected for stepper driver (STEP_REQUEST function)
d) the GPIO[12] pin is a rail to rail, back to back output supplied by VGPIO_SPI.
121/141
GPIO pins
SABRE-LL-I
Figure 40. GPIO[12] block diagram
To internal Logic & SPI
V 3v3
To ADC
V 3v3
From SPI
Logic Decode
To OpAmp2 In+
Table 94.
Parameter
Back to Back
Driver
GPIO[12] specification
Description
Test condition
Min
VIH
High level input voltage
VIL
Low level input voltage
VHYS
Input voltage hysteresis
VOL
Low level output voltage
IOUT = 15mA,
VGPIO_SPI = 3.15V
VOH
High level output voltage
IOUT = 15mA,
VGPIO_SPI = 3.15V
2.75
0 ≤Vout ≤ VGPIO_SPI,
VGPIO_SPI = 3.15V
-1
ILEAKAGE
tDELAY
Leakage current
Delay from Serial Write to pin Low
1. Measured between nSS rising edge and 50% of Vout.
122/141
GPIO[12]
V GPIO_SPI
Typ
Max
1.6
V
0.8
0.22
CLOAD =50 pF (1)
Unit
V
V
0.4
V
V
1
µA
500
ns
SABRE-LL-I
22.15
GPIO pins
GPIO[13]
The GPIO[13] truth table is (for the abbreviation list please refer to Table 68):
Table 95.
GPIO[13] truth
GPIO[13] SPI BITS
Op2En
Function
Note
X
OpAmp2 in-
(2)
X
X
HiZ (SPI_IN)
0
0
0
SPI OUT
(3)
1
0
0
1
AuxPwm1
(3)
0
1
0
1
0
Reg Loop 3
(3)
0
1
0
1
1
AuxPwm3
(3)
0
1
1
0
0
AuxPwm1 inverted
(3)
0
1
1
0
1
Reg Loop 3 inverted
(3)
0
1
1
1
1
AuxPwm3 inverted
(3)
mimusPin(1)
GpioOut
enable[13]
Mode[2]
Mode[1]
Mode[0]
1
X
X
X
0
0
X
0
1
0
1. The Op2EnMinusPin bit in the OpAmp2Ctrl register enables the connection of the positive input of Op1 to
GPIO[13] pin.
2. When Op2EnMinusPin = ‘1’ the GpioOutEnable[13] bit is forced to 0.
3. In all configurations in which GPIO[9] is enabled as output:
a) the GPIO[13] pin can be always used as an analog input to the ADC system (ADC function) by writing
its address in the A2DChannelX[4:0] in the A2DConfigX register and starting a conversion;
b) the GPIO[13] pin can be always used as a digital input so its value can be always read through SPI
interface (SPI_IN function);
c) the GPIO[13] pin is a rail to rail output supplied by VGPIO_SPI.
123/141
GPIO pins
SABRE-LL-I
Figure 41. GPIO[13] block diagram
To internal Logic &SPI
V 3v3
To ADC
V 3v3
From SPI
GPIO[13]
V GPIO_SP
Logic Decode
Gpio[13] Driver
To OpAmp2 In-
Table 96.
Parameter
GPIO[13] specification
Description
Min
VIH
High level input voltage
VIL
Low level input voltage
VHYS
Input voltage hysteresis
VOL
Low level output voltage
IOUT = 15mA,
VGPIO_SPI = 3.15V
VOH
High level output voltage
IOUT = 15mA,
VGPIO_SPI = 3.15V
2.75
0 ≤Vout ≤ VGPIO_SPI,
VGPIO_SPI = 3.15V
-1
ILEAKAGE
tDELAY
Leakage current
Delay from serial write to pin low
1. Measured between nSS rising edge and 50% of Vout.
124/141
Test condition
Typ
Max
1.6
V
0.8
0.22
CLOAD =50 pF(1)
Unit
V
V
0.4
V
V
1
µA
500
ns
SABRE-LL-I
22.16
GPIO pins
GPIO[14]
The GPIO[14] truth table is (for the abbreviation list please refer to Table 68):
Table 97.
GPIO[14] truth
GPIO[14] SPI BITS
EnOp2
(1)
Function
Note
X
OpAmp2 Out
(2)
X
X
HiZ (SPI_IN)
0
0
0
SPI OUT
(3)
1
0
0
1
Interrupt Ctrl
(3)
0
1
0
1
0
AuxPwm2
(3)
0
1
0
1
1
AuxPwm3
(3)
0
1
1
0
0
SPI OUT inverted
(3)
0
1
1
0
1
Interrupt Ctrl inverted
(3)
0
1
1
1
0
AuxPwm2 inverted
(3)
0
1
1
1
1
AuxPwm3 inverted
(3)
GpioOut
enable[14]
Mode[2]
Mode[1]
Mode[0]
1
X
X
X
0
0
X
0
1
0
1. The EnOp2 bit in the OpAmp2Ctrl register enables the operational amplifier 2.
2. When EnOp2 = ‘1’ the GpioOutEnable[14] bit is forced to 0.
3. In all configurations in which GPIO[14] is enabled as output:
a) the GPIO[14] pin can be always used as an analog input to the ADC system (ADC function) by writing
its address in the A2DChannelX[4:0] in the A2DConfigX register and starting a conversion;
b) the GPIO[14] pin can be always used as a digital input so its value can be always read through SPI
interface (SPI_IN function);
c) the GPIO[14] pin is a rail to rail output supplied by VGPIO_SPI.
125/141
GPIO pins
SABRE-LL-I
Figure 42. GPIO[14] block diagram
V 3v3
To internal Logic & SPI
To ADC
V GPIO_SP
V 3v3
GPIO[14]
From Central
Logic
Logic Decode
Gpio[14] Driver
OpAmp 2
Table 98.
Parameter
GPIO[14] specification
Description
Test condition
VIH
High level input voltage
VIL
Low level input voltage
VHYS
Input voltage hysteresis
VOL
Low level output voltage
IOUT = 15mA,
VGPIO_SPI = 3.15V
VOH
High level output voltage
IOUT = 15mA,
VGPIO_SPI = 3.15V
2.75
0 ≤Vout ≤ VGPIO_SPI,
VGPIO_SPI = 3.15V
-1
ILEAKAGE
tDELAY
Leakage current
Typ
Max
1.6
0.22
Delay from serial write to pin low
CLOAD =50 pF(1)
Unit
V
0.8
1. Measured between nSS rising edge and 50% of Vout.
126/141
Min
V
V
0.4
V
V
1
µA
500
ns
SABRE-LL-I
23
Serial interface
Serial interface
S.A.B.Re can communicate with an external microprocessor by using an integrated slave
SPI (Serial Protocol Interface). Through this interface almost all S.A.B.Re functionalities can
be controlled and all the ICs can be seen as a register map made by 128 register of 16-bit
each.
The SPI is a simple industry standard communications interface commonly used in
embedded systems and it has the following four I/O pins:
–
Miso (master input slave output)
–
Mosi (Master Output Slave Input)
–
sclk (serial clock [controlled by the master])
–
nSS (slave select active low [controlled by the master])
The “Miso” (master in, slave out) signal carries synchronous data from the slave to the
master device. The mosi (master out, slave in) signal carries synchronous data from the
master to the slave device. The sclk signal is driven by the master, synchronizing all data
transfers. Each SPI slave device has one nSS signal that is an active-low slave input/master
output pin. Slave devices do not respond to transactions unless their nSS input signal is
driven low. Master device interfacing with multiple SPI slave devices has an nSS signal for
each slave device.
S.A.B.Re will maintain its miso pin in high impedance until it does not recognize its address
in serial frame.
23.1
Read transaction
A read transaction (see Figure 43) is always started by the master device that lowers the
nSS pin. The other bits are then sent on the mosi pin with this order:
1.
7-bit representing the address of the register that must be read (MSB first [A6…A0]);
2.
2-bit that must be “10” for a read transaction;
3.
2-bit representing S.A.B.Re IC address;
4.
1-bit reserved for future use that must be set at “0”.
At this point the data stored in the register at the selected address will be shifted out on the
miso pin.
The read operation is terminated by raising the signal on nSS pin.
127/141
Serial interface
SABRE-LL-I
Figure 43. SPI read transaction
nSS
sclk
Register
Address field
mosi
A6
Data Field
A0
High Impedance
miso
23.2
Control IC
Field address
D15
D0
Write transaction
A write transaction (see Figure 44) is always started by the master lowering the signal on
nSS pin. The other bits are then sent on the mosi pin with this order:
1.
7-bit representing the address of the register that must be written (MSB first [A6…A0]);
2.
2-bit that must be “01” for a read transaction;
3.
2-bit representing S.A.B.Re IC address;
4.
1-bit reserved for future use that must be set at “0”.
The data to be written (MSB first D15…D0) are then read from mosi pin. The length of data
field can be 16 or 20 bits, but only the first 16-bit are accepted as valid data. Data is latched
on rising edge of the nSS line.
Figure 44. SPI write transaction
nSS
sclk
Control IC
Field addres
Register
Address field
mosi
miso
A6
A0
Data Field
D15
D0
High Impedance
The SPI input and output timing definitions are shown in the following tables:
128/141
SABRE-LL-I
Serial interface
Figure 45. SPI input timing diagram
T nss
T sclk
setup
T nss
period
hold
T nss
min
V IH
V IL
nSS
T sclk
hig
T sclk
low
sclk
V IH
V IL
mosi
V IH
V IL
T mosi
T mosi
setup
hold
T sclk
rise
T sclk
fall
Figure 46. SPI output timing diagram
T nss
T sclk
setup
period
T nss
hold
T nss
min
V IH
V IL
nSS
T sclk
high
T sclk
low
V IH
V IL
sclk
mosi
T sclk
rise
T sclk
fall
miso
V OH
V OL
T miso
valid
T miso
disable
129/141
Serial interface
SABRE-LL-I
Table 99.
Parameter
SPI interface specifications
(Note: VGPIO_SPI=3.3V unless otherwise specified)
Description
Test condition
VIH
High level input voltage
VIL
Low level input voltage
(1)
Input voltage hysteresis
(1)
VHYS
VOH
VOL
tsclk_period
High level output voltage
Low level output voltage
Typ
Max
1.6
0.22
IOUT = -10mA,
IOUT = 10mA,
V
0.8
(2)
SCLK period
V
V
2.75
(2)
Unit
V
0.4
62.5
V
ns
tsclk_rise
SCLK rise time
2
ns
tsclk_fall
SCLK fall time
2
ns
tsclk_high
SCLK high time
20
ns
tsclk_low
SCLK low time
20
ns
tnss_setup
nSS setup time
10
ns
tnss_hold
nSS hold time
10
ns
tnss_min
nSS high minimum time
30
ns
tmosi_setup
Mosi setup time
10
ns
tmosi_hold
Mosi hold time
10
ns
tmiso_rise
tmiso_fall
tmiso_valid
tmiso_disable
CLOAD
Miso rise time
Miso fall time
CLOAD
=50pF(3)
9
ns
(3)
9
ns
CLOAD=50pF
Miso valid from clock low
0
15
ns
Miso disable time
0
15
ns
200
pF
Miso maximum load
1. Specification applies to nSS, sclk and mosi pins.
2. Current is considered to be positive when flowing towards the IC
3. These times are measured at the pin output between specified VOH and VOL.
130/141
Min
SABRE-LL-I
24
Registers list
Registers list
Many of the S.A.B.Re functionalities are controlled or can be supervised by accessing to the
relative register through serial interface. All these registers can be seen from the user
(microcontroller) point of view as a register table. Each register is one word wide (16-bit)
and can be read using a 7-bit address
Table 100. Register address map
Address[6:0]
(binary)
Name
Comment
Address[6:0]
(binary)
Name
000_0000
DevName
Read only
100_0000
AuxPwm1Ctrl
000_0001
CoreConfigReg
100_0001
AuxPwm2Ctrl
000_0010
ICTemp
100_0010
GpPwm3Base
000_0011
ICStatus
100_0011
GpPwm3Ctrl
000_0100
EnTestRegs
100_0100
000_0101
SampleID
100_0101
000_0110
WatchDogCfg
100_0110
IntCtrlCfg
000_0111
WatchDogStatus
100_0111
IntCtrlCtrl
000_1000
SoftResReg
100_1000
DigCmpCfg
000_1001
100_1001
DigCmpValue
000_1010
100_1010
000_1011
100_1011
000_1100
HibernateStatus
100_1100
000_1101
HibernateCmd
100_1101
000_1110
100_1110
000_1111
Mtr1_2PwrCtrl
100_1111
001_0000
MainVSwCfg
101_0000
A2DControl
101_0001
A2DConfig1
101_0010
A2DResult1
101_0011
A2DConfig2
101_0100
A2DResult2
001_0001
001_0010
MainlinCfg
001_0011
001_0100
SwCtrCfg
001_0101
101_0101
001_0110
101_0110
001_0111
101_0111
001_1000
Comment
StdByMode
101_1000
GpioOutEnable
001_1001
101_1001
GpioCtrl1
001_1010
101_1010
GpioCtrl2
001_1011
101_1011
GpioCtrl3
131/141
Registers list
SABRE-LL-I
Table 100. Register address map (continued)
Address[6:0]
(binary)
Address[6:0]
(binary)
Name
Comment
001_1100
101_1100
GpioPadVal
Read only
001_1101
101_1101
GpioOutVal
001_1110
101_1110
001_1111
101_1111
Name
010_0000
Mtrs1_2Cfg
110_0000
010_0001
Mtr1Cfg
110_0001
010_0010
Mtr1Ctrl
110_0010
010_0011
Mtr1Limit
110_0011
010_0100
Mtr2Cfg
110_0100
OpAmpCtrl1
010_0101
Mtr2Ctrl
110_0101
OpAmpCtrl2
010_0110
Mtr2Limit
110_0110
010_0111
LowVSwitchCtrl
110_0111
010_1000
Mtrs3_4Cfg
110_1000
010_1001
Mtr3Cfg
110_1001
010_1010
Mtr3Ctrl
110_1010
010_1011
Mtr3ILimit
110_1011
010_1100
Mtr4Cfg
110_1100
010_1101
Mtr4Ctrl
110_1101
010_1110
Mtr4ILimit
110_1110
010_1111
110_1111
011_0000
StpCfg1
111_0000
011_0001
StpCfg2
111_0001
011_0010
StpCtrl
111_0010
011_0011
StpCmd
111_0011
011_0100
StpTest
111_0100
011_0101
Aux1SwCfg
111_0101
011_0110
Aux2SwCfg
111_0110
011_0111
Aux3SwCfg1
111_0111
011_1000
Aux3SwCfg2
111_1000
011_1001
Power Mode
Control
111_1001
011_1010
111_1010
011_1011
111_1011
REV_MFCT
111_1100
RESERVED
011_1100
132/141
Comment
CurrDacCtrl
SABRE-LL-I
Registers list
Table 100. Register address map (continued)
Address[6:0]
(binary)
Address[6:0]
(binary)
Name
011_1101
111_1101
RESERVED
011_1110
111_1110
RESERVED
011_1111
111_1111
RESERVED
Name
Comment
Comment
133/141
nRESET
JP7
1
2
3
2
JP1
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
LED
SCLK
D2
R39
Open
330
LED
1
RESET
AWAKE
R3
R11
R41
1K
R40
560
R10
4.7K
R13
1
2
D5
Gpio5
nSS
MISO
MOSI
J7
LED
4.7K
VSWMAIN
GND
3.3V 2.5A
D1
R2
nSS
100nF
C29
1
Master
4.7K
R1
Q3
BC846B
CON17X2
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
J10
nRESET
MISO
MOSI
SCLK
Slave
Vsupply
nAWAKE
J8
CON5X2
1 2
3 4
5 6
7 8
9 10
J1
VLINMAIN
GND
1.2V 0.5A
nSS
1
2
3
2
4.7K
330
C28
330nF
+
JP9
+
R9
4.7K
4.7K
R6
C1
1uF
C16
680uF 50V
C5
680nF
Close on Master
AWAKE
C27
10uF 10V
R18
1K
R36
2.2K
+3_3VS
Q4
BSP51
+3_3VS
R38
Open
LED
330
1
1
1
V3v 3
Q2
BC846B
1
C4
1uF
Vsupply
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
3
2
3
2
3
2
C6
100nF
nAWAKE
R7
4.7K
SCLK
Gpio8
MISO
MOSI
33uH 3A Coilcraf t DO5010H-333MLD
+3_3VS
L1
C12
100pF
C13
100nF
+
C25
470uF 16V
D3
STPS3L60U
D4
R12
JP4
JP3
JP2
Start up configuration
V3v 3
R17
R16
R15
73
72
71
70
J2
3
2
1K
1K
1K
nSS
Gpio0
Gpio1
Gpio2
DC2_plus
Vsupply
MISO
MOSI
VLINmain_FB
VLINmain_OUT
Gpio8
VSWmain_SW
Vsupply
VSWmain_FB
VREF_FB
IREF_FB
SCLK
Vsupply
DC4_plus
DC4_plus
JP12
R23
2.2
JP11
R22
1
Gpio12
Gpio13
Gpio14
TAB
TAB
TAB
TAB
Gpio3
Gpio4
3.9
R24
JP13
3.9
R25
JP14
2.2
R26
JP15
R20
R19
1K
1K
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
1
R27
JP16
+3_3VS
TAB
TAB
TAB
TAB
TAB
DC1_plus
Vsupply
CPL
CPH
Vpump
VSWDRV_gate
VSWDRV_SW
Gpio6
VGPIO_SPI
Gpio7
Vsupply Int
V3v 3
nRESET
Vsupply
DC3_plus
DC3_plus
U1
SABRe
JP8
Gpio8
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
DC2_plus
nSS
Gpio0
Gpio1
Gpio2
DC2_minus
DC2_minus
GND2
GND1
DC1_minus
DC1_minus
Gpio3
Gpio4
VSWDRV_FB
VSWDRV_sns
DC1_plus
DC4_sense
nAWAKE
Gpio12
Gpio13
Gpio14
DC4_minus
DC4_minus
DC4_sense
DC3_sense
DC3_minus
DC3_minus
Gpio11
Gpio10
Gpio9
Gpio5
DC3_sense
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
Gpio11
Gpio10
Gpio9
Gpio5
134/141
3
2
3
2
JP6
JP5
1
1
C9
V3v 3
Device ID
C11
1uF 1210
C3
Gpio6
+3_3VS
Gpio7
100nF
C7
1nF
1nF
100nF
100nF
Vsupply
ID2
ID1
100nF
C8
nRESET
1
R14
1K
LED
D6
CON3
1
2
3
GND
2.2K
R37
R5 4.7K
R8
4.7K
+
1nF
C22
1nF
C23
RESET
C26
330uF 25V
L2
1nF
C21
1
2
J6
Gpio13
Gpio14
Gpio6
Gpio7
Gpio11
Gpio12
Gpio1
Gpio2
R21
1K
R43
22K
Phase B
Phase A
Stepper
C15
100pF
1
2
1nF J5
C24
C14
100nF
100nF
C31
+3_3VS
33uH 4.5A Coilcraf t DO5040H-333MLD
Q5
STD12NF06L
R42
0.047 1W
Vsupply
+3_3VS
D7
6CWQ06
DC2_plus
DC2_minus
DC1_plus
DC1_minus
Q1
BC846B
100nF
C10
1
2
J4
C2
1uF
C17
C18
1nF J3
1nF
1
2
C20
C19
3
R44
39K
1
2
J9
VSWDRV
GND
12V 3A
CON10
1
2
3
4
5
6
7
8
9
10
J11
25
2
Vsupply
GND
Schematic samples
SABRE-LL-I
Schematic samples
Figure 47. Application with 2 DC motors, 1 stepper motor and 3 power supplies
BATTERY +
GND
12V 1.5A max
D3
BZX284C15
1
2
C32
100pF
C22
22uF 16V
J10
+
1
R14
4.7K 1W
R24
10K
R19
10K
C23
100nF
J8
+Vop
Q4
BSP51
1
R15
1K
R11
560
R45
1K
R48
330
1
Q9
R44 2.2K
BC857B
1
GREEN330
LED
1
R38
4.7K
R37
ES3B
J5
4.7K
330
Q2
BSP51
-
+
0.1 1W
R25
150K 0.1%
R28
150K 0.1%
C5
10pF
R23
10K 0.1%
R20
10K 0.1%
R17
LED
GREEN
D8
+
C21
1uF
MISO
MOSI
SCLK
Gpio8
1
1
1
+
JP9
Close on Master
AWAKE
D16
Y ELLOW LED
Charge in progress
C27
470uF 16V
R43
1K
R31
4.7K
4.7K
R29
C28
100nF
L4
V3v 3
R3
R2
R1
1K
1K
1K
DC2_plus
Vsupply
MISO
MOSI
VLINmain_FB
VLINmain_OUT
Gpio8
VSWmain_SW
Vsupply
VSWmain_FB
VREF_FB
IREF_FB
SCLK
Vsupply
DC4_plus
DC4_plus
V3v 3
D6
STPS3L60U
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
3
2
3
2
3
2
Q5
BC846B
1
33uH 2A Coilcraf t DO3316P-333MLD
C20
470uF 63V
C15
680nF
Vsupply
JP3
JP2
JP1
Start up configuration
LED
GREEN
33uH 3A Coilcraf t DO5010H-333MLD
+3_3VS
L1
C6
C7
100pF
100nF
+
C8
470uF 16V
D1
STPS3L60U
D10
10K 1W
R32
C19
10uF 10V
R7
1K
R5
2.2K
330
R35
Vsupply
2
3
U2A
LM358
+
+3_3VS
1
2
1
2
+3_3VS
J2
C18
330nF
VSWMAIN
GND
3.3V 3A
R34
R33
Vsupply
GND
D12
Gpio5
LED
GREEN
nSS
D9
D5
1
2
Master
JP5
Q6
BC846B
3
2
Slave
RESET
VLINMAIN
GND
1.2V 0.5A
nRESET
MISO
MOSI
SCLK
nAWAKE
CON10A
1 2
3 4
5 6
7 8
9 10
J7
CON34A
AWAKE
MISO
MOSI
SCLK
nSS
D17
RED LED
Disconnect the battery
Vsupply
nSS
nRESET
JP4
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
4
2
3
3
2
2
3
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
8
4
73
72
71
70
TAB
TAB
TAB
TAB
nSS
Gpio0
Gpio1
Gpio2
C14
100nF
R26
4.7K
nAWAKE
Gpio12
Gpio13
Gpio14
1K
R49
R22
R18
+3_3VS
TAB
TAB
TAB
TAB
TAB
DC1_plus
Vsupply
CPL
CPH
Vpump
VSWDRV_gate
VSWDRV_SW
Gpio6
VGPIO_SPI
Gpio7
Vsupply Int
V3v 3
nRESET
Vsupply
DC3_plus
DC3_plus
6
5
1K
1K
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
-
+
1
4.7K
R6
LM358
7
U2B
JP7
JP6
+Vop
3
2
3
2
1
C17
V3v 3
Device ID
C16
1uF
Gpio6
+3_3VS
Gpio7
100nF
ID2
ID1
100nF
100nF
D13
R36
2.2K
LED
GREEN
4.7K
RESET
+
+
C25
100nF
C29
470uF 16V
+
C30
100nF
Gpio2
C31
100pF
L5
33uH 2A Coilcraf t DO3316P-333MLD
C24
470uF 16V
R30
1K
R27
1K
Gpio1
C26
100pF
270
1K
1
2
J11
1
2
J9
LED
GREEN
1
1
2
J6
CON8
1
2
3
4
5
6
7
8
J12
D14
R9
1K
D15
LED
GREEN
R42
680
R21
1K
R16
820
R41
C11
100pF
R40
+3_3VS
C10
100pF
L3
33uH 2A Coilcraf t DO3316P-333MLD
R12
R13
4.7K
R39
680
C9
330uF 25V
L2
R8
15K
Gpio6
Gpio7
Gpio8
Gpio11
Gpio12
+3_3VS
D11
CON3
1
2
3
JP8
33uH 4.5A Coilcraf t DO5040H-333MLD
Q1
STD12NF06L
R4
0.047 1W
ResetOn
RED LED
1
R10
1K
+3_3VS
D2
6CWQ06
Vsupply
D4
STPS1L60U
Q3
BC846B
nRESET
DC2_plus
DC2_minus
DC1_plus
DC1_minus
D7
STPS1L60U
1
2
J4
Vsupply
1nF
1nF
C13
C4
C3
1nF J3
1nF
1
2
C2
C1
C12
D21
LED
GREEN
10K 1W
R47
D20
LED
RED
U1
SABRe
D19
LED
RED
R46
10K 1W
D18
LED
GREEN
3
2
Gpio3
Gpio4
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
DC2_plus
nSS
Gpio0
Gpio1
Gpio2
DC2_minus
DC2_minus
GND2
GND1
DC1_minus
DC1_minus
Gpio3
Gpio4
VSWDRV_FB
VSWDRV_sns
DC1_plus
DC4_sense
nAWAKE
Gpio12
Gpio13
Gpio14
DC4_minus
DC4_minus
DC4_sense
DC3_sense
DC3_minus
DC3_minus
Gpio11
Gpio10
Gpio9
Gpio5
DC3_sense
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
Gpio11
Gpio10
Gpio9
Gpio5
VSWDC3GND
5V 1A
VDC3+
GND
1.8V 1A
Q7
BC846B
VSWDRV
GND
12.8V
3A
3
2
To PractiSpin
J1
3
2
8
4
SABRE-LL-I
Schematic samples
Figure 48. Application with 2 DC motors, a battery charger and 5 power supplies
135/141
Pin list
SABRE-LL-I
26
Pin list
26.1
Pin list
Table 101. Pins configuration
Pin #
Pin name
1
DC1_PLUS
2
VSWDRV_SNS Switching regulator controller sense
Bridge 1 phase “plus” output
Switching regulator controller feedback
Type
Output
Analog input
Analog input
3
VSWDRV_FB
4
GPIO4
General purpose I/O
Analog In/Out - CMOS bi-dir
5
GPIO3
General purpose I/O
Analog In/Out - CMOS bi-dir
6
DC1_MINUS Bridge 1 phase “minus” output
Output
7
DC1_MINUS Bridge 1 phase “minus” output
Output
8
9
GND1
GND2
(1)(2)(3)
Power/digital
bridge2(1)(2)(3)
Power/digital
Ground pin for bridge1
Ground pin for
10
DC2_MINUS Bridge 2 phase “minus” output
Output
11
DC2_MINUS Bridge 2 phase “minus” output
Output
12
GPIO2
General purpose I/O
Analog In/Out - CMOS bi-dir
13
GPIO1
General purpose I/O
Analog In/Out - CMOS bi-dir
14
GPIO0
General purpose I/O
Analog Input - CMOS input
15
nSS
16
DC2_PLUS
Bridge 2 phase “plus” output
Output
17
DC2_PLUS
Bridge 2 phase “plus” output
Output
18
VSupply
Main voltage supply
19
MISO
SPI serial data output
20
MOSI
SPI serial data input
CMOS input
21
VLINmain_FB
Linear main regulator feedback
Analog input
22
136/141
Description
SPI chip select pin
VLINmain_OUT Linear main regulator output
23
GPIO 8
24
VSWmain_SW
25
VSupply
26
VSWmain_FB
27
General purpose I/O
CMOS input
Power input
CMOS output
Power output
Analog In/Out - CMOS bi-dir
Main switching regulator switching output
Power output
Main voltage supply
Power Input
Main switching regulator feedback pin
Analog input
VREF_FB
Regulator voltage feedback
Analog input
28
IREF_FB
Regulator current feedback
Analog input
29
SCLK
SPI input clock pin
CMOS input
30
VSupply
Main voltage supply
Power input
31
DC4_PLUS
Bridge 4 phase “plus” output
Output
SABRE-LL-I
Pin list
Table 101. Pins configuration (continued)
Pin #
Pin name
32
N.C.
33
Description
Type
Not connected
DC4_SENSE Bridge 4 sense output(4)
Output
34
nAWAKE
Device wake up
35
GPIO12
General purpose I/O
Analog In/Out - CMOS bi-dir
36
GPIO13
General purpose I/O
Analog In/Out - CMOS bi-dir
37
GPIO14
General purpose I/O
Analog In/Out - CMOS bi-dir
38
N.C.
39
CMOS input
Not connected
DC4_MINUS Bridge 4 phase “minus” output
Output
40
DC4_SENSE Bridge 4 sense output
(4)
Output
41
DC3_SENSE Bridge 3 sense output(4)
Output
42
DC3_MINUS Bridge 3 phase “minus” output
Output
43
N.C.
44
GPIO11
General purpose I/O
Analog In/Out - CMOS bi-dir
45
GPIO10
General purpose I/O
Analog In/Out - CMOS bi-dir
46
GPIO9
General purpose I/O
Analog In/Out - CMOS bi-dir
47
GPIO5
General purpose I/O
48
Not connected
DC3_SENSE Bridge 3 sense output
Analog In/Out - CMOS bi-dir
(4)
49
N.C.
50
DC3_PLUS
51
VSupply
52
nRESET
53
V3v3
54
VSupplyInt
55
GPIO7
56
VGPIO_SPI
57
GPIO6
58
VSWDRV_SW
Switching regulator controller source input
59
VSWDRV_GAT
Switching driver gate drive pin
Output
Not connected
Bridge 3 phase “plus” output
Main voltage supply
Output
Power input
Open drain system reset pin
CMOS Input/output
Internal 3.3 volt regulator
Power Input/output
Internal voltage supply
General purpose I/O
Low voltage pins power supply
General purpose I/O
Power Input
Analog In/Out - CMOS bi-dir
Power input
Analog In/Out - CMOS bi-dir
Power input
Analog output
E
60
VPump
Charge pump voltage
Power Input/output
61
CPH
Charge pump high switch pin
Power Input/output
62
CPL
Charge pump low switch pin
Power Input/output
63
VSupply
64
DC1_plus
Bridge 1 phase “plus” output
GND_PAD
(1)(2)(3)
E_Pad
Main voltage supply
Power input
Output
137/141
Pin list
SABRE-LL-I
1. These pins must be connected all together to a unique PCB ground.
2. Bridges1 and 2 have 2 ground pads: one is bonded to the relative ground pin (GND1 or GND2) and the
other is connected to exposed pad (E_Pad) ground ring. This makes the bond wires testing possible by
forcing a current between E-Pad and GND1 or GND2 pins and using the other pin as sense pin to measure
the resistance of E-Pad bonding. (N.B: grounds of two bridges are internally connected together).
3. The analog ground is connected to exposed pad E-Pad.
4. The pin must be tied to ground if bridge is not used as a stepper motor.
138/141
SABRE-LL-I
27
Package information
Package information
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a lead-free second level interconnect. The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label.
ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
Figure 49. TQFP64 mechanical data & package dimensions
mm
inch
DIM.
MIN.
TYP.
A
MAX.
MIN.
TYP.
1.20
A1
0.05
A2
0.95
b
0.17
c
0.09
D
11.80
D1
9.80
D2
2.00
D3
MAX.
0.0472
0.15
0.002
1.00
1.05
0.0374 0.0393 0.0413
0.22
0.27
0.0066 0.0086 0.0086
0.20
0.0035
12.00
12.20
0.464
0.472
0.480
10.00
10.20
0.386
0.394
0.401
0.006
0.0078
0.787
7.50
0.295
E
11.80
12.00
12.20
0.464
0.472
0.480
E1
9.80
10.00
10.20
0.386
0.394
0.401
E2
2.00
0.787
E3
7.50
0.295
e
0.50
0.0197
L
0.45
L1
k
ccc
0.60
0.75
0.0177 0.0236 0.0295
1.00
0˚
OUTLINE AND
MECHANICAL DATA
3.5˚
0.0393
7˚
0.080
0˚
3.5˚
7˚
TQFP64 (10x10x1.0mm)
Exposed Pad Down
0.0031
7278840 B
139/141
Revision history
28
SABRE-LL-I
Revision history
Table 102. Document revision history
140/141
Date
Revision
14-Nov-2007
1
Changes
Initial release.
SABRE-LL-I
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