STMICROELECTRONICS L6460

L6460
SPI configurable stepper and DC multi motor driver
Features
■
Operating supply voltage from 13 V to 38 V
■
4 full bridge driver configurable in multi-motor
application to drive:
– 2 DC and 1 stepper motor
– 4 DC motor
■
Bridge 1 and 2 (RDSon = 0.60 Ω) can be
configured to work as:
– Dual full bridge driver
– Super DC driver
– 2 half bridge driver
– 1 super half bridge
– 2 power switches
– 1 super power switch
■
TQFP64 exposed pad
■
Bridge 3 and 4 (RDSon = 0.85 Ω) can be
configured to work as:
– Same as bridges 1 and 2, listed above
– Stepper motor driver: up to 1/16
microstepping
– 2 buck regulators (bridge 3)
– 1 super buck regulator
– Battery charger (bridge 4)
■
Power supply management
– One switching buck regulator
– One switching regulator controller
– One linear regulator
– One battery charger
■
Fully protected through
– Thermal warning and shutdown
– Overcurrent protection
– Undervoltage lock-out
■
SPI interface
■
Programmable watchdog function
■
Integrated power sequencing and supervisory
functions with fault signaling through serial
interface and external reset pin
■
Auxiliary features
– Multi-channels 9 bit ADC
– 2 operational amplifiers
– Digital comparator
– 2 low voltage power switches
– 3 general purpose PWM generators
– 14 GPIOs
Description
The L6460 is optimized to control and drive multimotor system providing a unique level of
integration in term of control, power and auxiliary
features. Thanks to the high configurability L6460
can be customized to drive different motor
architectures and to optimize the number of
embedded features, such as the voltage
regulators, the high precision A/D converter, the
operational amplifier and the voltage
comparators. The possibility to drive
simultaneously stepper and DC motor makes
L6460 the ideal solution for all the application
featuring multi motors.
Table 1.
Device summary
Order code
Package
L6460
Packing
Tray
TQFP64
L6460TR
Tape and reel
Very low power dissipation in shut-down mode
(~35 mW)
July 2010
Doc ID 17713 Rev 1
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www.st.com
139
Contents
L6460
Contents
1
General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.2
Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.3
Pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2
L6460’s main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4
5
3.1
Absolute maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.2
Operating ratings specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Internal supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.1
VSupplyInt regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.2
Charge pump regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.3
V3v3 regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Supervisory system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.1
Power on reset (POR) circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.2
nRESET generation circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.3
Thermal shut down generation circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6
Watchdog circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7
Internal clock oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
8
Start-up configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2/139
8.1
Operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
8.2
Basic device mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
8.3
Slave device mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
8.4
Master device mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
8.5
Single device mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
8.6
Sub-configurations for slave, master or single device modes . . . . . . . . . 41
Doc ID 17713 Rev 1
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Contents
8.6.1
Bridge mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
8.6.2
Primary regulator mode (KP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
8.6.3
Regulators mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
8.6.4
Simple regulator mode (KT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
8.6.5
Bridge + VEXT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
8.6.6
Secondary regulators mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
9
Power sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
10
Power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
10.1
Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
10.2
Hibernate mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
10.3
Low power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
10.4
nAWAKE pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
11
Linear main regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
12
Main switching regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
12.1
13
14
Switching regulator controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
13.1
Pulse skipping operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
13.2
Output equivalent circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
13.3
Switching regulator controller application considerations . . . . . . . . . . . . . 54
Power bridges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
14.1
15
Pulse skipping operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Possible configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
14.1.1
Full bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
14.1.2
Parallel configuration (super bridge) . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
14.1.3
Half bridge configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
14.1.4
Switch configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
14.1.5
Bipolar stepper configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
14.1.6
Synchronous buck regulator configuration (Bridge 3) . . . . . . . . . . . . . . 73
14.1.7
Regulation loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
14.1.8
Battery charger or switching regulator (Bridge 4) . . . . . . . . . . . . . . . . . 76
AD converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
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Contents
L6460
15.1
Voltage divider specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
16
Current DAC circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
17
Operational amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
18
Low voltage power switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
19
General purpose PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
19.1
General purpose PWM generators 1 and 2 (AuxPwm1 and AuxPwm2) . 90
19.2
Programmable PWM generator (GpPwm) . . . . . . . . . . . . . . . . . . . . . . . . 90
20
Interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
21
Digital comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
22
GPIO pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
22.1
GPIO[0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
22.2
GPIO[1] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
22.3
GPIO[2] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
22.4
GPIO[3] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
22.5
GPIO[4] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
22.6
GPIO[5] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
22.7
GPIO[6] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
22.8
GPIO[7] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
22.9
GPIO[8] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
22.10 GPIO[9] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
22.11 GPIO[10] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
22.12 GPIO[11] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
22.13 GPIO[12] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
22.14 GPIO[13] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
22.15 GPIO[14] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
23
4/139
Serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
23.1
Read transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
23.2
Write transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Doc ID 17713 Rev 1
L6460
Contents
24
Registers list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
25
Schematic examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
26
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
27
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
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List of tables
L6460
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
Table 49.
6/139
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pins configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
IC operating ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Stretch time selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Watchdog timeout specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Possible start-up pins state symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Start-up correspondence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Main switching regulator PWM specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Main switching regulator current limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Switching regulator controller PWM specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Switching regulator controller application: feedback reference. . . . . . . . . . . . . . . . . . . . . . 54
PWM selection truth table for bridge 1 or 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
PWM selection truth table for bridge 3 or 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Bridge selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Bridge 3 and 4 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Full bridge truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Half bridge truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Switch truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Sequencer driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Stepper driving mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Stepper sequencer direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Internal sequencer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Stepper off time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Stepper fast decay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
PWM specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Battery charger regulator controller PWM specification . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
ADC truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Channel addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
ADC sample times when working as a 8-bit ADC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
ADC sample time when working as a 9-bit ADC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Voltage divider specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Current DAC truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Interrupt controller event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Comparison type truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
DataX selection truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
GPIO functions description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
GPIO[0] truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
GPIO[1] truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
GPIO[2] truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
GPIO[3] truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
GPIO[4] truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
GPIO[5] truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
GPIO[6] truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
GPIO[7] truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
GPIO[8] truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Doc ID 17713 Rev 1
L6460
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
List of tables
GPIO[9] truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
GPIO[10] truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
GPIO[11] truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
GPIO[12] truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
GPIO[13] truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
GPIO[14] truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Register address map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Doc ID 17713 Rev 1
7/139
List of figures
L6460
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
Figure 42.
8/139
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
VSupplyInt pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Charge pump block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
nReset generation circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Watchdog circuit block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Standby mode function description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
nAWAKE function block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Linear main regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Linear main regulator with external bipolar for high current . . . . . . . . . . . . . . . . . . . . . . . . 49
Main switching regulator functional blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Switching regulator controller functional blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Switching regulator controller output driving: equivalent circuit . . . . . . . . . . . . . . . . . . . . . 54
H Bridge block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Bridge 1 and 2 PWM selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Super bridge configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Half bridge configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Bipolar stepper configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Regulator block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Internal comparator functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Battery charger control loop block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Li-ion battery charge profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Simple buck regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
A2D block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Current DAC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Configurable 3.3 V operational amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Low power switch block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Interrupt controller diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Digital comparator block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
GPIO[0] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
GPIO[1] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
GPIO[2] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
GPIO[3] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
GPIO[4] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
GPIO[5] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
GPIO[6] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
GPIO[7] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
GPIO[8] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
GPIO[9] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
GPIO[10] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
GPIO[11] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
GPIO[12] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Doc ID 17713 Rev 1
L6460
Figure 43.
Figure 44.
Figure 45.
Figure 46.
Figure 47.
Figure 48.
Figure 49.
Figure 50.
Figure 51.
List of figures
GPIO[13] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
GPIO[14] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
SPI read transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
SPI write transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
SPI input timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
SPI output timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Application with 2 DC motors, 1 stepper motor and 3 power supplies . . . . . . . . . . . . . . . 135
Application with 2 DC motors, a battery charger and 5 power supplies . . . . . . . . . . . . . . 136
TQFP64 mechanical data an package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Doc ID 17713 Rev 1
9/139
General description
L6460
1
General description
1.1
Overview
L6460 offers the possibility to control and power multi motor systems, through the
management of simultaneous driving of stepper and DC motor. A number of features can be
configured through the digital interface (SPI), including 3 voltage regulators, 1 high precision
A/D converter, 2 operational amplifiers and 14 configurable GPIOs.
The high flexibility allows the possibility to configure two, one full or half bridge to work as
power stage featuring additional voltage buck regulators.
'0)/
'0)/
'0)/
'0)/
'0)/
'0)/
'0)/
'0)/
'0)/
'0)/
'0)/
'0)/
'0)/
6'0)/?30)
'0)/
Block diagram
'0)/
Figure 1.
63UPPLY)NT #0(
'0)/S
#0,
60UMP
#HARGE
PUMP
63UPPLY
63UPPLY
60UMP
60UMP
X
/P!MP S
#URRENT
$!#
07'ENERATORS
X
3WITCH
$#?-).53
4HERMAL
-ANAGER
N2%3%4
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-58
3UPERVISORY
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-ANAGER
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)NT6OLTAGE2EFERENCE
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63UPPLY
60UMP
60UMP
7$
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2EGISTERS
(3 $#X?-).53
3TEPPER-OTOR
-ANAGER
$#$#
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$#?-).53
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60UMP
60UMP
N33
3#,+
63UPPLY
(3 $#X?0,53
$#?0,53
-/3)
60UMP
63UPPLY
60UMP
63UPPLY
63UPPLY
66
60UMP
)NTERNAL
2EGULATOR
-AIN
3WITCHING
2EGULATOR
-AIN
,INEAR
2EGULATOR
3WITCHING
2EGULATOR
#ONTROLLER
$#?3%.3%
63UPPLY
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2EGOLATION
,OOP
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Note:
10/139
)2%&?&"
62%&?&"
637$26?&"
637$26?37
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6,).MAIN?&"
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637MAIN?&"
%?0!$
637MAIN?37
$#?3%.3%
See following Chapter 2 for a detailed description of possible configurations.
Doc ID 17713 Rev 1
L6460
Pin connection
DC1_PLUS
1
VSWDRV_SNS
2
VSWDRV_FB
VSWDRV_SW
GPIO6
VGPIO_SPI
GPIO7
VSupplyInt
60
59
58
57
56
55
54
N.C.
VSWDRV_GATE
61
DC3_PLUS
VPump
62
VSupply
CPH
63
V3V3
CPL
64
nRESET
VSupply
Pin connection
DC1_PLUS
Figure 2.
53
52
51
50
49
48
DC3_SENSE
47
GPIO5
3
46
GPIO9
GPIO4
4
45
GPIO10
GND_PAD
GPIO3
5
44
GPIO11
DC1_MINUS
6
43
N.C.
DC1_MINUS
7
42
DC3_MINUS
GND1
8
41
DC3_SENSE
36
GPIO13
14
35
GPIO12
nSS
15
34
nAWAKE
DC2_PLUS
16
33
DC4_SENSE
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
N.C.
13
GPIO0
DC4_PLUS
GPIO1
VSupply
GPIO14
SCLK
37
IREF_FB
12
VREF_FB
GPIO2
VSWmain_FB
N.C.
VSupply
38
VSWmain_SW
11
GPIO8
DC2_MINUS
VLINmain_OUT
DC4_MINUS
VLINmain_FB
DC4_SENSE
39
MOSI
40
10
MISO
GND2
VSupply
9
DC2_MINUS
DC2_PLUS
1.2
General description
Doc ID 17713 Rev 1
11/139
General description
1.3
Pin list
Table 2.
Pins configuration
Pin #
Pin name
1
DC1_PLUS
2
VSWDRV_SNS Switching regulator controller sense
Description
Bridge 1 phase “plus” output
Type
Output
Analog input
3
VSWDRV_FB
4
GPIO4
General purpose I/O
Analog In/Out - CMOS bi-dir
5
GPIO3
General purpose I/O
Analog In/Out - CMOS bi-dir
Switching regulator controller feedback
Analog input
6
DC1_MINUS Bridge 1 phase “minus” output
Output
7
DC1_MINUS Bridge 1 phase “minus” output
Output
8
9
GND1
GND2
(1)(2)(3)
Power/digital
bridge2(1)(2)(3)
Power/digital
Ground pin for bridge1
Ground pin for
10
DC2_MINUS Bridge 2 phase “minus” output
Output
11
DC2_MINUS Bridge 2 phase “minus” output
Output
12
GPIO2
General purpose I/O
Analog In/Out - CMOS bi-dir
13
GPIO1
General purpose I/O
Analog In/Out - CMOS bi-dir
14
GPIO0
General purpose I/O
Analog Input - CMOS input
15
nSS
16
DC2_PLUS
Bridge 2 phase “plus” output
Output
17
DC2_PLUS
Bridge 2 phase “plus” output
Output
18
VSupply
Main voltage supply
19
MISO
SPI serial data output
20
MOSI
SPI serial data input
CMOS input
21
VLINmain_FB
Linear main regulator feedback
Analog input
22
SPI chip select pin
VLINmain_OUT Linear main regulator output
23
GPIO 8
24
VSWmain_SW
25
VSupply
26
VSWmain_FB
27
General purpose I/O
CMOS input
Power input
CMOS output
Power output
Analog In/Out - CMOS bi-dir
Main switching regulator switching output
Power output
Main voltage supply
Power Input
Main switching regulator feedback pin
Analog input
VREF_FB
Regulator voltage feedback
Analog input
28
IREF_FB
Regulator current feedback
Analog input
29
SCLK
SPI input clock pin
CMOS input
30
VSupply
Main voltage supply
Power input
31
DC4_PLUS
32
N.C.
33
34
12/139
L6460
Bridge 4 phase “plus” output
Not connected
DC4_SENSE Bridge 4 sense output(4)
nAWAKE
Output
Device wake up
Doc ID 17713 Rev 1
Output
CMOS input
L6460
General description
Table 2.
Pins configuration (continued)
Pin #
Pin name
Description
Type
35
GPIO12
General purpose I/O
Analog In/Out - CMOS bi-dir
36
GPIO13
General purpose I/O
Analog In/Out - CMOS bi-dir
37
GPIO14
General purpose I/O
Analog In/Out - CMOS bi-dir
38
N.C.
Not connected
39
DC4_MINUS Bridge 4 phase “minus” output
Output
40
DC4_SENSE Bridge 4 sense output(4)
Output
41
DC3_SENSE Bridge 3 sense output
(4)
Output
42
DC3_MINUS Bridge 3 phase “minus” output
Output
43
N.C.
44
GPIO11
General purpose I/O
Analog In/Out - CMOS bi-dir
45
GPIO10
General purpose I/O
Analog In/Out - CMOS bi-dir
46
GPIO9
General purpose I/O
Analog In/Out - CMOS bi-dir
47
GPIO5
General purpose I/O
Analog In/Out - CMOS bi-dir
48
DC3_SENSE Bridge 3 sense output(4)
49
N.C.
50
DC3_PLUS
51
VSupply
52
nRESET
53
V3v3
54
VSupplyInt
55
GPIO7
56
VGPIO_SPI
57
GPIO6
58
VSWDRV_SW
59
Not connected
Output
Not connected
Bridge 3 phase “plus” output
Main voltage supply
Output
Power input
Open drain system reset pin
CMOS Input/output
Internal 3.3 volt regulator
Power Input/output
Internal voltage supply
General purpose I/O
Low voltage pins power supply
General purpose I/O
Switching regulator controller source input
VSWDRV_GATE Switching driver gate drive pin
Power Input
Analog In/Out - CMOS bi-dir
Power input
Analog In/Out - CMOS bi-dir
Power input
Analog output
Charge pump voltage
Power Input/output
CPH
Charge pump high switch pin
Power Input/output
62
CPL
Charge pump low switch pin
Power Input/output
63
VSupply
64
DC1_plus
Bridge 1 phase “plus” output
GND_PAD
(1)(2)(3)
60
VPump
61
E_Pad
Main voltage supply
Power input
Output
1. These pins must be connected all together to a unique PCB ground.
2. Bridges1 and 2 have 2 ground pads: one is bonded to the relative ground pin (GND1 or GND2) and the
other is connected to exposed pad (E_Pad) ground ring. This makes the bond wires testing possible by
forcing a current between E-Pad and GND1 or GND2 pins and using the other pin as sense pin to measure
the resistance of E-Pad bonding. (N.B: grounds of two bridges are internally connected together).
3. The analog ground is connected to exposed pad E-Pad.
4. The pin must be tied to ground if bridge is not used as a stepper motor.
Doc ID 17713 Rev 1
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L6460’s main features
2
L6460
L6460’s main features
L6460 includes the following circuits:
●
Four widely configurable full bridges:
–
–
●
●
14/139
Diagonal RDSon: 0.6 Ω typ.
–
Max operative current = 2.5 A.
Bridges 3 and 4:
–
Diagonal RDSon: 0.85 Ω typ.
–
Max operative current = 1.5 A.
Bridge 1:
–
DC motor driver.
–
Super DC (bridge 1 and 2 paralleled form superbridge1).
–
2 independent half bridges.
–
1 super half bridge (bridge 1 side A and bridge 1 side B paralleled form
superhalfbridge1).
–
2 independent switches (high or low side).
–
1 super switch (high or low side).
–
Bridge 2 has the same configurations of bridge 1.
–
Bridge 3 has the same configurations of bridge 1 (bridge 3 and 4 paralleled form
superbridge2) plus the following:
–
●
–
Possible configurations for each bridge are the following:
–
●
Bridges 1 and 2:
–
½ stepper motor driver.
–
2 buck regulators (VAUX1_SW, VAUX2_SW).
–
1 Super buck regulator (VAUX1//2_SW).
Bridge 4 has the same configurations of bridge 1 plus the following:
–
½ stepper motor driver.
–
1 super buck regulator (VAUX3_SW).
–
Battery charger.
One buck type switching regulator (VSWmain) with:
–
Output regulated voltage range: 1-5 Volts.
–
Output load current: 3.0 A.
–
Internal output power DMOS.
–
Internal soft start sequence.
–
Internal PWM generation.
–
Switching frequency: ~250 kHz.
–
Pulse skipping strategy control.
One switching regulator controller (VSWDRV) with:
–
Output regulated voltage range: 1-30 Volts.
–
Selectable current limitation.
–
Internal PWM generation.
–
Pulse skipping strategy control.
One linear regulator (VLINmain) that can be used to generate low current/low ripple
Doc ID 17713 Rev 1
L6460
L6460’s main features
voltages. This regulator can be used to drive an external bipolar pass transistor to
generate high current/low ripple output voltages.
●
One bidirectional serial interface with address detection so that different ICs can share
the same data bus.
●
Integrated power sequencing and supervisory functions with fault signaling through
serial interface and external reset pin.
●
Fourteen general purpose I/Os that can be used to drive/read internal/external
analog/logic signals.
●
One 8-bit/9-bit A/D converter (100 kS/s @ 9-bit, 200 kS/s @8-bit). It can be used to
measure most of the internal signals, of the input pins and a voltage proportional to IC
temperature.
●
–
Current sink DAC:
–
Three output current ranges: up to 0.64/6.4/64 mA.
–
64 (6-bit programmable) available current levels for each range.
–
5 V output tolerant.
Two operational amplifiers:
–
3.3 V supply, rail to rail input compatibility, internally compensated.
–
They can have all pins externally accessible or can be internally configured as a
buffer o make internal reference voltages available outside of the chip.
–
Unity gain bandwidth > 1 MHz.
–
They can also be set as comparators with 3.3 V input compatibility and low offset.
●
Two 3.3 V pass switches with 1 Ω RDSon and short circuit protected.
●
Programmable watchdog function.
●
Thermal shutdown protection with thermal warning capability.
●
Very low power dissipation in “low power mode” (~35 mW)
L6460 is intended to maximize the use of its components, so when an internal circuit is not
used it could be employed for other applications. Bridge 3, for example, can be used as a full
bridge or to implement two switching regulators with synchronous rectification: to obtain this
flexibility L6460 includes 2 separate regulation loops for these regulators; when the bridge is
used as a motor driver, the 2 regulation loops can be redirected on general purpose I/Os to
leave the possibility to assembly a switching regulator by only adding an external FET.
Doc ID 17713 Rev 1
15/139
Electrical specifications
L6460
3
Electrical specifications
3.1
Absolute maximum rating
The following specifications define the maximum range of voltages or currents for L6460.
Stresses above these absolute maximum specifications may cause permanent damage to
the device. Exposure to absolute maximum ratings for extended periods may affect device
reliability.
Table 3.
Absolute maximum ratings
Parameter
VSupply
VGPIO_SPI
Test
condition
Description
Max
Unit
VSupply voltage
40
V
VGPIO_SPI voltage
3.9
V
-0.3
3.9
V
-1
VSupply
V
V3V3 voltage
V3V3pin
Switching regulators output pin voltage
range
VSW
VSW_pulse
VPump
Switching regulators min pulsed
voltage
tpulse <
500ns
Charge pump voltage
(1)
Junction temperature(2)
TJ
Min
-3
V
15
V
Storage
-40
190
°C
Operating
-40
TSD
°C
1. This value is useful to define the voltage rating for external capacitor to be connected from VPump to
VSupply. VPump is internally generated and can never be supplied by external voltage source nor is intended
to provide voltage to external loads.
2. TSD is the thermal shut down temperature of the device.
3.2
Operating ratings specifications
Table 4.
IC operating ratings
Parameter
VSupply
ISupply
VSupply operative current
VSupply shut down state current
VGPIO_SPI
VGPIO_SPI voltage range
IVGPIO_SPI
VGPIO_SPI operative current
V3v3
3.3V input pin voltage range
VLINmain_FB
16/139
VSupply voltage range
IShut_down
VLINmain_OUT
Test
condition
Description
Output pin voltage range
Output pin voltage range
VSWDRV_SW
VSWDRV_SW pin voltage range
Doc ID 17713 Rev 1
Max
Unit
13 (1)
38
V
15
mA
1.5
mA
3.6
V
0.4
mA
3.6
V
0
VSupply
V
0
3.6
V
-1
Vsupply
V
-1
VSupply
V
(2)
2.4
(3)
(4)
Feedback pin voltage range
VSWmain_SW
Min
(4)
(4)
L6460
Electrical specifications
Table 4.
IC operating ratings
Parameter
Description
VSWDRV_GATE
Gate drive pin voltage
VSWDRV_SNS
Sense pin voltage
TJ
Junction temperature
Test
condition
Operating
Min
Max
Unit
0
VPump
V
VSupply
VSupply
-3V
V
-40
125
°C
1. For Vsupply lower than 21 V an external resistor between Vsupply and Vsupply Int pins are required.
For Vsupply lower than 15 V external diodes for charge pump are required.
2. Operating supply current is measured with system regulators operating but not loaded.
3. Operating VGPIO_SPI current is measured with all circuits supplied by VGPIO_SPI (GPIO’s, operational
amplifiers and pass switches) enabled but not loaded.
4. The external components connected to the pin must be chosen to avoid that the voltage exceeds this
operative range.
3.3
Electrical characteristics
Table 5.
Electrical characteristics
Parameter
Description
Test condition
Min
Typ
Max
Unit
18
19.5
21
V
VSupplyInt regulator
VS_Int
IS_Int
VSupplyInt output voltage
(1)
VSupplyInt operative current
(2)
11
mA
VSupply VSupply VSupply
+ 10.5 +12.5 + 14.5
V
FOSC/6
4
kHz
Charge pump VPump
VPump
Charge pump voltage
VSupply=32V
FPump
VPump clock frequency
FOSC = 16MHz typ
V3v3 output voltage
VSupply=32V
V3V3 regulator
V3V3
3.15
3.3
3.45
V
Power on reset
VSupply_POR_valid VSupply voltage for POR valid
InRESET = 1mA
4
VSupply falling
6
VSupply_POR_fall
VSupply POR falling threshold
tSupply_POR_filt
VSupply POR filter Time
V3V3_POR_fall
V3v3 POR falling threshold
V3V3 falling
V3V3_POR_rise
V3v3 POR rising threshold
V3V3 rising
V3V3_POR_hys
t3V3_POR_filt
V
8
V
3
µs
2.2
V
2.7
V
V3v3 POR hysteresis
0.5
V
V3v3 POR filter time
1.5
µs
1.9
nRESET circuit
VnRST_L
nRESET low level output
voltage
I=10mA
Doc ID 17713 Rev 1
0.4
V
17/139
Electrical specifications
Table 5.
L6460
Electrical characteristics (continued)
Parameter
Description
Test condition
tnRST_fall
nRESET fall time
I=1mA
C=50pF(3)
tnRST_del
nRESET delay time
(4)
Min
Typ
Max
Unit
15
ns
150
ns
VSupply_UV_f
VSupply falling threshold
10.2
11
11.8
V
VSupply_UV_r
VSupply rising threshold
10.5
11.5
12.5
V
VSupply hysteresis
0.3
0.5
0.7
V
VSupply_UV_hys
tSupply_UV
VSupply UV filter time
VS_Int_UV_f
VSupplyInt falling threshold
9.7
10.7
11.7
V
VS_Int_UV_r
VSupplyInt rising threshold
10.6
11.4
12.2
V
VSupplyInt hysteresis
0.4
0.7
1
V
VS_Int_UV_hys
3.5
µs
tS_Int_UV
VSupplyInt UV filter time
3.5
µs
VPump_UV_f
VPump falling threshold
VSupply VSupply VSupply
+7
+ 7.5
+8
V
VPump_UV_r
VPump rising threshold
VSupply VSupply VSupply
+ 7.5
+8
+ 8.5
V
VPump_UV_hys
tPump_UV
VPump hysteresis
0.3
VPump UV filter time
VGPIO_SPI_UV_f
VGPIO_SPI falling threshold
VGPIO_SPI_UV_r
VGPIO_SPI rising threshold
1.8
200
0.5
0.7
V
3.5
µs
2
V
2.2
2.4
V
250
300
mV
VGPIO_SPI_hys
VGPIO_SPI hysteresis
tGPIO_SPI_UV
VGPIO_SPI UV filter time
3.5
µs
Thermal shut down
temperature
170
°C
Warming temperature
140
°C
Thermal shut down to warming
difference
30
°C
Thermal shut down filter time
8
µs
Warming filter time
8
µs
Tosc *
222
s
TSD circuit
TTSD
TWARM
TDIFF
tTSD_FILT
tWARM_FILT
Watchdog
WD_Tclk
Watchdog clock period
Internal clock
Fosc
Oscillator frequency
V3V3 = 3.3 V
14.1
16
17.6
MHz
0.8
V
nAWAKE function
VIL
18/139
nAWAKE low logic level
voltage
Doc ID 17713 Rev 1
L6460
Electrical specifications
Table 5.
Electrical characteristics (continued)
Parameter
Description
VIH
nAWAKE high logic level
voltage
VHYS
nAWAKE input hysteresis
IOUT
nAWAKE pin output current
IINP
tAWAKEFILT
Test condition
Min
Typ
Max
1.6
V
0.25
nAWAKE=0V(5)
nAWAKE pin input current
nAWAKE=0.8V
(5)
Unit
V
-0.72
-2
mA
0.2
0.4
mA
Filter time
μs
1.2
Main linear regulator
Vdrop
IPD
Drop out voltage
Vdrop=
Vsupply-VLINmain_OUT
Internal switch pull down
current
Linear Main Regulator
disabled; VLINmain_OUT=1V
2
3
VLINmain_Ref
Feedback reference voltage
0.776
ILINmain_Ref
Feedback pin input current
-2
IoutLINMax
Ishort
ΔVout/Vo
ΔVout/ΔVSupply
Vloop_acc
VLIN_UV_f
VLIN_UV_r
VLIN_UV_hys
tprim_uv
Maximum output current
VLINmain_OUT= Vsupply-2V
10
Output short
circuit current
VLINmain_OUT =0V,
VLINmain_FB =0V
12
Load regulation
0 ≤ Iload ≤ IoutLINMax(6)
Line regulation
Iload
V
0.8
0.824
V
2
µA
mA
24
=10mA(6)
Loop voltage accuracy
mA
32
mA
0.8
%
0.2
%
±2.5
%
Undervoltage falling threshold
(7)
84.5
87
89.5
%
Undervoltage rising threshold
(7)
90.5
93
95.5
%
Undervoltage hysteresis
6
%
Under voltage deglitch filter
5
µs
Main switching regulator
SelFBref = ‘00’
VFBREF
IQ
IQ_LP
ISWmain_FB
VSWmain_OUT
Iload
RDSonHS
0.776
0.8
0.824
V
0.97
1
1.03
V
SelFBref = ‘10’
2.425
2.5
2.575
V
SelFBref = ‘11’
2.91
3
3.09
V
Output leakage current
Tjunction = 125°C
-40
+40
µA
Output leakage current in
“low power mode”
VSupply = 36V
Tjunction = 125°C
-15
+15
µA
VSWmain_FB pin current
Tjunction = 125°C
-10
+10
µA
Output voltage range
(9)
0.8
5
V
Maximum output load current
VSupply = 36V
0.002
3
A
Internal high side RDSon
Iload=1A
Tjunction = 125°C
0.95
Ω
SelFBref = ‘01’
Main switching regulator
feedback reference voltage
(8)
Doc ID 17713 Rev 1
0.33
19/139
Electrical specifications
Table 5.
L6460
Electrical characteristics (continued)
Parameter
Vloop
Description
Test condition
Min
Loop voltage accuracy
Typ
Max
Unit
±3%
VSW_UV_f
Under voltage falling threshold (10)
84.5
87
89.5
%
VSW_UV_r
(10)
90.5
93
95.5
%
VSW_UV_hys
tprim_uv
Ilimit
tdeglitch
Under voltage rising threshold
Under voltage hysteresis
6
%
Under voltage deglitch filter
5
µs
5
3.5
A
A
SelIlimit =”0”
SelIlimit =”1”
Current limit protection
Current limit deglitch time
3.3
2.3
50
ns
Current limit response time
Normal operating mode (no
UV)(11)
450
650
ns
Current limit response time in
UV condition
UV condition (12)
200
400
ns
tr
Switching output rise time
VSupply = 36V,
RLOAD = 422 Ω(13)
5
30
ns
tf
Switching output fall time
VSupply = 36V,
RLOAD = 10 Ω(13)
5
30
ns
tI_lim
tI_limUV
FSW_PWM
Operating frequency
Fosc/6
4
kHz
VPump
V
Switching regulator controller
VGS_ext
Gate to source voltage for
external FET
ISOURCE
Source current
VPump=VSupply+12V
VSWCTR_GATE=0V
25
ISINK
Sink current
VSWCTR_GATE = VSupply
20
tSINK
Sink discharge pulse time
RSUSTAIN
IQ
IQ_LP
VFBREF
mA
mA
600
ns
650
Ω
Gate-source sustain
resistance
(VSWCTR_GATE VSWCTR_SRC) = 0.2V
Output
leakage current
VSupply = 36V,
Tjunction = 125°C
-40
+40
µA
Output leakage current in
“Low Power Mode”
VSupply = 36V,
Tjunction = 125°C
-5
+5
µA
SelFBref = ‘00’ (8)
0.776
0.8
0.824
V
SelFBref = ‘01’
0.97
1
1.03
V
SelFBref = ‘10’
2.425
2.5
2.575
V
SelFBref = ‘11’
2.91
3
3.09
V
VSupply = 36V,
Tjunction = 125°C
-10
+10
µA
Switching regulator feedback
controller feedback reference
voltage
ISWDRV_FB
VSWDRV_FB pin current
Vloop
Loop voltage accuracy
20/139
50
±3%
Doc ID 17713 Rev 1
L6460
Electrical specifications
Table 5.
Electrical characteristics (continued)
Parameter
Description
Test condition
VSWD_UV_f
Under voltage falling threshold
(14)
VSWD_UV_r
Under voltage rising threshold
(14)
VSWD_UV_hys
tprim_uv
Vovc
tdeglitch
tI_lim
tI_limUV
FSWD_PWM
Min
Typ
Max
Unit
84.5
87
89.5
%
90.5
93
95.5
%
Under voltage hysteresis
6
%
Under voltage deglitch filter
5
µs
Over current threshold voltage
250
Current limit deglitch time
50
300
350
mV
ns
Current limit response time
Normal operating mode (no
UV) (11)
500
900
ns
Current Limit response time in
UV condition.
UV condition (12)
380
550
ns
Operating frequency
Fosc/64
kHz
Power bridges
RDSon1_2
Bridge 1 and 2 diagonal RDSon
I = 1.4A, VSupply = 36V,
Tjunction = 125°C
0.6
1.1
Ω
RDSon3_4
Bridge 3 and 4 diagonal RDSon
I = 1A, VSupply = 36V,
Tjunction = 125°C
0.85
1.65
Ω
IMAX1_2
Bridge 1 and 2 operative rms
current
2.5
A
IMAX3_4
Bridge 3 and 4 operative rms
current
1.5
A
Idss
IQ_LP
IOC_LS1_2
Output leakage current.
Tjunction = 125°C
-50
+50
µA
Output leakage current in “low
power mode”
VSupply = 36V,
Tjunction = 125°C
-10
+10
µA
MtrXSideYILimSel[1:0]=00
MtrXSideYILimSel[1:0]=01
Low side current protection for
MtrXSideYILimSel[1:0]=10
(15)
bridges 1 and 2
MtrXSideYILimSel[1:0]=11
0.6
1.4
2.4
2.4
1
2
3
3
1.6
2.6
3.6
3.6
0.7
1.5
2.5
2.5
1
2
3
3
1.7
2.7
3.7
3.7
A
(16)
IOC_HS1_2
MtrXSideYILimSel[1:0]=00
MtrXSideYILimSel[1:0]=01
High side current protection for
MtrXSideYILimSel[1:0]=10
(15)
bridges 1 and 2
MtrXSideYILimSel[1:0]=11(1
A
6)
IOC_LS3_4
Low side current protection for MtrXSideYILimSel[1:0]=11
(17)(18)
bridges 3 and 4(15)
1.55
2.5
A
IOC_HS3_4
High side current protection for MtrXSideYILimSel[1:0]=11(1
7)(18)
bridges 3 and 4(15)
1.6
2.5
A
2
5
μs
tfilter
Current limit
filter time
Doc ID 17713 Rev 1
21/139
Electrical specifications
Table 5.
Electrical characteristics (continued)
Parameter
tdelay
tOC_off
L6460
Description
Test condition
Min
Current limit
delay time
MtrXIlimitOffTimeY[1:0]=00
MtrXIlimitOffTimeY[1:0]=01
MtrXIlimitOffTimeY[1:0]=10
MtrXIlimitOffTimeY[1:0]=11
Over current Off time
(19)
Typ
Max
Unit
5
μs
60
120
240
480
µs
µs
µs
µs
tr1_2
Output rise time
bridges 1 and 2
VSupply = 36V, resistive load
between outputs:
R= 25 Ω(20)
100
180
250
ns
tr3_4
Output rise time
bridges 3 and 4
VSupply = 36V, resistive load
between outputs:
R= 36 Ω(20)
50
100
200
ns
tf1_2
Output fall time
bridges 1 and 2
VSupply = 36V, resistive load
between outputs:
R= 25 Ω(20)
100
180
250
ns
tf3_4
Output fall time
bridges 3 and 4
VSupply = 36V, resistive load
between outputs:
R= 36 Ω(20)
50
125
250
ns
tdeadRise
Anti crossover rising dead time
100
300
450
ns
tdeadFall
Anti crossover falling dead
time
100
300
450
ns
FPWM
tresp
Operating frequency
Delay from PWM to output
transition
Fosc/51
2
kHz
500
ns
Bipolar stepper circuitry
VSTEPREF
Voffset
Reference voltage
Sense comparator offset
0.50
0.75
-12
(8)
0.52
0.78
V
12
mV
0.65
0.95
1.25
µs
StepBlkTime = ‘01’
1
1.45
1.9
µs
StepBlkTime = ‘10’
1.5
2.25
3
µs
StepBlkTime = ‘11’
3
4.25
5.5
µs
Output pin voltage range
(DC3x)
(26)
-1
VSupply
V
Output leakage current
Tjunction = 125°C
-50
+50
µA
Output leakage current in “Low VSupply = 36V
Power Mode”
Tjunction = 125°C
-10
+10
µA
StepBlkTime = ‘00’
tblk
0.48
0.72
SelStepRef =0
SelStepRef =1
Blanking time
Synchronous buck regulator (bridge 3)
VAUX_SW
IQ
IQLP
22/139
Doc ID 17713 Rev 1
L6460
Electrical specifications
Table 5.
Electrical characteristics (continued)
Parameter
Description
Test condition
Min
Typ
Max
Unit
0.776
0.8
0.824
V
0.97
1
1.03
V
2.425
2.5
2.575
V
SelFBRef = ‘11’
2.91
3
3.09
V
GPIO feedback pin current
Tjunction = 125°C
0V≤Feedback ≤ 3V
-15
15
µA
Vout
Output voltage range
VSupply = 36V(23)
0.8
30
V
Iload
Output load current
VSupply = 36V
0.002
1.5
A
Internal high/low side RDSon
Tjunction = 125°C; Iload=1A
0.8
Ω
SelFBRef = ‘00’
VFBREF
IGPIO_FB
RDSonHS
Vloop
SelFBRef = ‘01’ (21)
Synchronous buck regulator
feedback reference voltage
SelFBRef = ‘10’
±3%
VREG_UV_f
Under voltage falling threshold
VREG_UV_r
Under voltage rising threshold
(24)
taux_UV
Ilimit
tdeglitch
0.6
Loop voltage accuracy
(24)
VREG_UV_hys
(22)
84.5
87
89.5
%
90.5
93
95.5
%
Under voltage hysteresis
6
%
Under voltage deglitch filter
5
µs
Current limit protection
1.6
Current limit deglitch time
50
2.5
A
ns
Current limit response time
Normal operating mode
(no UV) (11)
480
700
ns
Current limit response time in
UV condition.
UV condition (12)
350
500
ns
tr
Switching output rise time
VSupply = 36V,
RLOAD = 422 Ω(25)
5
30
ns
tf
Switching output fall time
VSupply = 36V,
RLOAD = 10 Ω (23)
10
50
ns
tI_lim
tI_limUV
tdead
Crossover dead time
100
ns
FREGPWM
Operating frequency
Fosc/64
kHz
Battery charger (Bridge 4)
VAUX3_SW
IQ
VFBRef
Output pin voltage range
(DC4x)
(26)
Output leakage current
Battery charger control loop
feedback reference voltage
-1
VSupply
V
Tjunction = 125°C
-100
+100
µA
SelFBRef = ‘00’
1.37
1.412
1.455
V
1.746
1.8
1.854
V
SelFBRef = ‘10’
2.079
2.143
2.207
V
SelFBRef = ‘11’
2.425
2.5
2.575
V
SelFBRef = ‘01’
(8)
Doc ID 17713 Rev 1
23/139
Electrical specifications
Table 5.
L6460
Electrical characteristics (continued)
Parameter
Description
Test condition
Min
Typ
Max
Unit
0.873
0.9
0.927
V
SelCurrRef = ‘01’
1.394
1.437
1.48
V
SelCurrRef = ‘10’
1.746
1.8
1.854
V
SelCurrRef = ‘11’
2.182
2.25
2.318
V
(27)
1.412
30
V
0.002
3
A
0.4
Ω
SelCurrRef = ‘00’
VCurrRef
Battery charger control loop
feedback reference current
Vout
Output voltage range
VSupply = 36V
Iload
Output load current
VSupply = 36V
RDSon
Internal high/low side RDSon
Tjunction = 125°C;
ILOAD = 1.5A
Vloop
Loop voltage accuracy
(8)
0.3
±3%
VBC_UV_f
Under voltage falling threshold (28)
84.5
87
89.5
%
VBC_UV_r
(28)
90.5
93
95.5
%
VBC_UV_hys
taux_UV
Ilimit
tdeglitch
Under voltage rising threshold
Under voltage hysteresis
6
%
Under voltage deglitch filter
5
µs
Current limit protection
3.2
Current limit deglitch time
50
5
A
ns
Current limit response time
Normal operating mode
(no UV) (11)
480
700
ns
Current limit response time in
UV condition.
UV condition (12)
350
500
ns
tr
Switching output rise time
VSupply = 36V,
RLOAD = 422 Ω (25)
5
30
ns
tf
Switching output fall time
VSupply = 36V,
RLOAD = 10 Ω (25)
10
50
ns
tI_lim
tI_limUV
tdead
Crossover dead time
100
ns
FBCPWM
Operating frequency
Fosc/64
kHz
ADC with A2DType=0 (29)
IMR
INL
Measurement range
Integral non-linearity
V3v3
V
(30)(31)
0
±2
LSB
0(32)(31)
±2
LSB
A2dType = 0
DNL
Differential non-linearity
A2dType =
OE
Offset error
A2dType = 0(33)
±4
LSB
Offset error drift
A2dType = 0 over time
and temperature
±3
LSB
Gain error
A2dType = 0(34)
±4
LSB
Gain error drift
A2dType = 0 over time
and temperature
±4
LSB
55
µs
OEDrift
GE
GEDrift
tconv
Minimum conversion time
Resolution
24/139
A2dType = 0
(35)
Doc ID 17713 Rev 1
8
bits
L6460
Electrical specifications
Table 5.
Electrical characteristics (continued)
Parameter
Cin
Description
Test condition
Min
Typ
(36)
Input sampling capacitance
Max
Unit
4
pF
ADC with A2DType=1 (37)
IMR
INL
Measurement range
A2dType = 1
Integral non-linearity
V3v3
V
A2dType = 1
(30)(31)
0
±1
LSB
(32)(31)
±1
LSB
DNL
Differential Non-Linearity
A2dType = 1
OE
Offset error
A2dType = 1 (33)
±4
LSB
Offset error drift
A2dType = 1 over time and
temperature
±3
LSB
Gain error
A2dType = 1 (34)
±4
LSB
Gain error drift
A2dType = 1
over time and temperature
±4
LSB
10
µs
OEDrift
GE
GEDrift
tconv
Minimum conversion time
Resolution
9
Input sampling capacitance
(36)
VR
Pin voltage operative range
(GPIO8)
(38)
IOUT_OFF
Output off leakage current
IFULL_ERR
Full scale current error
Cin
bits
4
pF
0.7
5.5
V
DacValue[5:0] = 000000
-1
+1
µA
DacRange[1:0] =xx
DacValue[5:0] = 111111
-15
+15
% of
IFULL
Current DAC
typ
INL10_11
Integral non-linearity for 10
and 11 ranges
±2
LSB
DNL10_11
Differential non-linearity for 10
and 11 ranges
±2
LSB
INL01
Integral non-linearity for 01
range
±1
LSB
DNL01
Differential non-linearity for 01
range
±1
LSB
RCurrDac_res
Gpio[8] divider total resistance
45
RCurrDac_ratio
Gpio[8] divider ratio
3/5
tset
kΩ
Settling time
(39)
5
µs
3.45
V
V
Operational amplifier (40)
VGPIO_SPI
Operational amplifier supply
voltage range
3.15
VICM
Input common mode voltage
range
0
VGPIO_
0.1
3.2
VOUT_MAX
Output voltage
ILOAD =± 1mA
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3.3
SPI
V
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Electrical specifications
Table 5.
L6460
Electrical characteristics (continued)
Parameter
VOp1PlusRef
VOp2PlusRef
Avd
Description
Test condition
Operational amplifier 1 and 2
reference voltage
OpxRef[1:0]=00
OpxRef[1:0]=01
OpxRef[1:0]=10
OpxRef[1:0]=11
Open loop gain
VICM=1.65V
ILOAD= 0mA
Min
Typ
Max
Unit
0.97
1.6
1.94
2.425
1
1.65
2
2.5
1.03
1.7
2.06
2.575
V
90
CMRR
Common mode rejection ratio
PSRR
Power supply rejection ratio
I in _offs
Input offset current
-150
150
nA
I in _bias
Input bias current
-500
500
nA
V in _offs
Input offset voltage
-5
5
mV
GBWP
Gain bandwidth product
Cload=100pF VICM=1.65V
Rload=330 Ω to VGPIO_SPI
Output current
Vout=1.65V
Iout
Ishort_max
SR
80
dB
ILOAD= ±6mA
VICM=1.65V
Short circuit current
Slew rate
Iload= 0
CLOAD=100pF
110
dB
90
dB
2
MHz
10
mA
12
20
mA
1.3
1.75
V/µs
Operational amplifier used as comparator (40) (41)
VOUT_MAX
Output voltage
Iload =± 10mA
tOFF
Turn off propagation delay
VCM = 1.65V
Δ Vi = -/+ 20mV
CLOAD=100pF (42)(43)
tFALL
Fall time
tON
tRISE
0.3
2.9
V
0.6
1
µs
VCM = 1.65V
Δ Vi = -/+ 20mV
CLOAD=100pF (42)(43)
0.15
0.4
µs
Turn on propagation delay
VCM = 1.65V
Δ Vi = -/+ 20mV
CLOAD=100pF (42)(43)
0.25
0.5
µs
Rise time
VCM = 1.65V
Δ Vi = -/+ 20mV
CLOAD=100pF (42)(43)
0.2
0.4
µs
3.6
V
VGPIO_
V
Low power switch
VPSW
VOUT_MAX
Input voltage range
2.4
Output voltage
SPI
RDSon
Switch RDSon resistance
ILIMIT
Current limit
150
Current limit deglitch time
50
tdeglitch
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Iload=100mA
Doc ID 17713 Rev 1
0.6
1
Ω
250
350
mA
ns
L6460
Electrical specifications
Table 5.
Electrical characteristics (continued)
Parameter
tI_lim
CLOAD
Description
Test condition
Min
Typ
Max
Unit
Current limit response time
650
ns
Max load capacitance
2.5
µF
tON
Turn on propagation delay
VGPIO_SPI=3.3V ILOAD=1mA
CLOAD=100pF(44)
450
650
ns
tOFF
Turn off propagation delay
VGPIO_SPI=3.3V
ILOAD=1mA
CLOAD=100pF(44)
250
450
ns
Interrupt controller
tPULSE
Pulse duration
tINTFILT
Filter time
16*Tosc
µs
200
ns
GPIO[0], GPIO[1], GPIO[2], GPIO[3], GPIO[4], GPIO[6]
VIH
High level input voltage
VIL
Low level input voltage
VHYS
Input voltage hysteresis
VOL
Low level output voltage
IOUT = 15mA
Leakage current
0 ≤ Vout ≤ V3v3
Delay from serial write to pin
Low
CLOAD =50 pF(45)
ILEAKAGE
tDELAY
1.6
V
0.8
0.15
0.22
-1
V
V
0.5
V
1
µA
500
ns
GPIO[5], GPIO[7], GPIO[9], GPIO[10], GPIO[11], GPIO[12], GPIO[13], GPIO[14]
VIH
High level input voltage
VIL
Low level input voltage
VHYS
Input voltage hysteresis
VOL
Low level output voltage
IOUT = 15mA
VOH
High level output voltage
IOUT = 5mA
Leakage current
0 ≤Vout ≤ V3v3
Delay from serial write to pin
low
CLOAD =50 pF(45)
ILEAKAGE
tDELAY
1.6
V
0.8
0.15
0.22
V
V
0.5
2.75
V
V
-1
1
µA
500
ns
GPIO[8]
VIH
High level input voltage
1.6
VIL
Low level input voltage
VHYS
Input voltage hysteresis
VOL
Low level output voltage
IOUT = 15mA,
ILEAK_0
Leakage current
EnGpio8DigIn=0,
0 ≤ Vout ≤ 5V
ILEAK_1
Leakage current
EnGpio8DigIn=1,
0 ≤ Vout ≤ 5V
V
0.8
0.13
Doc ID 17713 Rev 1
0.22
V
V
0.4
V
-1
1
µA
-1
5
µA
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Electrical specifications
Table 5.
L6460
Electrical characteristics (continued)
Parameter
Description
Test condition
A/D path absorbed current
ADChannelX[4:0]
=10001 and
bit EnDacScale=0
Delay from serial write to pin
low
CLOAD =50 pF(45)
VIH
High level input voltage
(46)
VIL
Low level input voltage
(46)
Input voltage hysteresis
(46)
IAD
tDELAY
Min
Typ
Max
Unit
1
µA
500
ns
-1
SPI interface (40)
VHYS
VOH
VOL
tSCLK
High level output voltage
Low level output voltage
1.6
V
0.8
0.15
IOUT =
-10mA,(47)
IOUT =
10mA,(47)
SCLK period
0.22
V
V
2.75
V
0.4
62.5
V
ns
tSCLK_rise
SCLK rise time
2
ns
tSCLK_fall
SCLK fall time
2
ns
tSCLK_high
SCLK high time
20
ns
tSCLK_low
SCLK low time
20
ns
tnSS_setup
nSS setup time
10
ns
tnSS_hold
nSS hold time
10
ns
tnSS_min
nSS high minimum time
30
ns
tMOSI_setup
MOSI setup time
10
ns
tMOSI_hold
MOSI hold time
10
ns
tMISO_rise
tMISO_fall
tMISO_valid
tMISO_disable
CLOAD
MISO rise time
MISO fall time
CLOAD=50pF(48)
CLOAD=50pF
(48)
9
ns
9
ns
MISO valid from clock low
0
15
ns
MISO disable time
0
15
ns
200
pF
MOSI maximum load
1. This value is useful to define the voltage rating for external capacitor to be connected from VSupply to VSupplyInt.
2. This typical value is only intended to give an estimation of the current consumption when L6460 is configured in simple
regulators mode (see following Chapter 8.6.4) at the end of the start up sequence and with no load on regulators. This
typical value allows a raw choose of the external resistor but the definitive choose must be done according to the
recommendations on Chapter 4.1).
3. Measured between 10% and 90% of output voltage transition.
4. Measured from a fault detection to 50% of output voltage transition.
5. Current is defined to be positive when flowing into the pin.
6. Load regulation is calculated at a fixed junction temperature using short load pulses covering all the load current range. This
is to avoid change on output voltage due to heating effect.
7. Undervoltage rising and falling thresholds are intended as a percentage of feedback pin voltage (VLINmain_FB).
8. Default state.
9. The regulated voltage can be calculated using the formula: VSWmain_OUT = VFBREF *(Ra+Rb)/Rb.
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L6460
Electrical specifications
10. Undervoltage rising and falling thresholds are intended as a percentage of feedback pin voltage (VSW_main_FB).
11. This condition is intended to simulate an extra current on output.
12. This condition is intended to simulate a short circuit on output.
13. Rise and fall time are measured between 10% and 90% VSWmain output voltage.
14. Undervoltage rising and falling thresholds are intended as a percentage of feedback pin voltage (VSWDRV_FB).
15. The current protection values must be intended as a protection for the chip and not as a continuous current limitation. The
protection is performed by switching off the output bridge when current reaches values higher than the IOC max. No
protection could be guaranteed for values in the middle range between IMAX and IOC
16. In this cell X stands for 1 or 2, Y stands for A or B
17. In this cell X stands for 3 or 4, Y stands for A or B
18. The current protection thresholds for Bridge 3 and 4 are not selectable so only the max current value
(MtrXSideYILimSel[1:0]= 11) is available.
19. Overcurrent Off time can be configured using SPI.
20. Rise and fall time are measured between 10% and 90% of DC output voltage. With device in full bridge configuration
(resistive load between outputs).
21. Default state for Aux1
22. Default state for Aux2
23. The regulated voltage can be calculated using the formula: VAUX_SW = VFBREF *(Ra+Rb)/Rb.
24. Undervoltage rising and falling thresholds are intended as a percentage of feedback pin voltage (GPIO1 and/or GPIO2)
25. Rise and fall time is measured between 10% and 90% of output voltage.
26. The external components connected to the pin must be chosen to avoid that the voltage exceeds this operative range.
27. The regulated voltage can be calculated using the formula: VAUX3_SW = VFBREF *(Ra+Rb)/Rb.
28. Undervoltage rising and falling thresholds are intended as a percentage of feedback pin voltage (VREF_FB).
29. The definition of LSB for this table is LSB=IMRmax/(27.5-1).
30. Integral Non Linearity error (INL) is defined as the maximum distance between any point of the ADC characteristic and the
“best straight line” approximating the ADC transfer curve.
31. The ADC ensures monotonic characteristic and no missing codes.
32. Differential nonlinearity error (DNL) is defined as the difference between an actual step width and the ideal width value of 1
LSB.
33. Offset error (OE) is the deviation of the first code transition (000...000 to 000...001) from the ideal (i.e. GND + 0.5 LSB).
34. Gain error (GE) is the deviation of the last code transition (111...110 to 111...111) from the ideal (V3v3 - 0.5 LSB), after
adjusting for offset error.
35. Please note that the result of the conversion will always be a 9-bit word: to speed up the conversion, the resolution is
reduced when the ADC is used in the 8- bit resolution mode.
36. Actual input capacitance depends on the pin that must be converted.
37. The definition of LSB for this table is LSB=IMRmax/(29-1).
38. All parameters are guaranteed in the range between VOL and VR Max.
39. Measured from DacValue[5:0] change in SPI interface.
40. VGPIO_SPI = 3.3 V unless otherwise specified
41. In this section reports the operational amplifier parameters that change when used as comparator.
42. ΔVi is the differential voltage applied to input pins across the common voltage VCM.
43. Measured between 50% of input and output signal.
44. Time measured from change in SPI interface to 50% of external pin transition.
45. Measured between nSS rising edge and 50% of Vout.
46. Specification applies to nSS, SCLK and MOSI pins.
47. Current is considered to be positive when flowing towards the IC
48. These times are measured at the pin output between specified VOH and VOL.
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Internal supplies
4
L6460
Internal supplies
L6460 includes three internal regulators used to provide a regulated voltage to internal
circuits.
The internal regulators are the following:
- VSupplyInt regulator.
- Charge pump regulator.
- V3v3 regulator.
4.1
VSupplyInt regulator
VSupplyInt is the output of an internal regulator used to supply some internal circuits. This
regulator is not intended to provide external current so it must not be used to supply external
loads. An external capacitor must always be connected to this pin (preferably towards
VSupply pin), recommended value is in the range 80 ÷ 120 nF.
Figure 3.
VSupplyInt pin
Vsupply
VsupplyInt
IS_Int_TYP
L6460
internal
circuits
L6460
GND
The VSupplyInt pin may also be externally connected to VSupply pin by means of an external
resistor REXT: this allows REXT, particularly when VSupply is at the max values of the
operative supply range, to dissipate power that otherwise would be dissipated inside the
chip. The choice of the optimal resistor depends on the application since it is strictly
depending on both VSupply and the current used inside the chip (that is changing with the
chosen configuration).
REXT could be chosen by applying this formula: REXT = (VSupply min - VS_Int max)/(IS_Int max).
IS_Int max is depending from the chosen configuration and represents the total current needed
by the circuits connected to this pin.
For example, with VSupply = 32 V and IS_Int = 12 mA a typical resistor value is 1 kΩ.
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L6460
4.2
Internal supplies
Charge pump regulator
L6460 implements a charge pump regulator to generate a voltage over VSupply.This voltage
is used to drive internal circuits and the external FET driver and cannot be used for any
other purpose.
This circuit is always under the supervisory circuit control, so no regulator can start before
the VPump voltage reaches its undervoltage rising threshold. If VPump voltage falls down
below its under voltage falling threshold, all the regulators will be switched off.
The charge pump circuit is disabled when L6460 is in “low power mode”.
Figure 4.
Charge pump block diagram
VSupplyInt
VSupply
CBOOST
VPump
CPH
for VSupply lower than 15V,
external diodes are required
CFLY
EnVPump
M2
CPL
Driver
M1
+
CLKBOOST
Ref
An example of capacitors value is: CFLY = 100 nF and CBOOST = 1 µF
4.3
V3v3 regulator
V3v3 is the output of an internal regulator used to supply some low voltage internal circuits.
This regulator is not intended to provide external current so it must not be used to supply
external loads. An external capacitor must always be connected from this pin to GND,
recommended value is in the range 80 ÷ 120 nF.
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Supervisory system
5
L6460
Supervisory system
The supervisory circuitry monitors the state of several functions inside L6460 and resets the
device (and other ICs if connected to nRESET pin) when the monitored functions are
outside their normal range. Supervisory circuitry can be divided into three main blocks:
–
Power on reset (POR) generation circuitry.
–
nRESET (nRST_int) generation circuitry.
–
Thermal shut down (TSD) generation circuitry.
POR circuitry monitors the voltages that L6460 needs to guarantee its own functionality;
nRESET circuitry controls if L6460’s main voltages are inside the normal range; TSD is the
thermal shut down of the chip in case of overheating.
5.1
Power on reset (POR) circuit
Power on reset circuit monitors VSupply, and V3V3 voltages. The purpose of this circuit is to
set the device is in a stable and controlled status until the minimum supply voltages that
guarantee the device functionality are reached. The output signal of this circuit (in the
following indicated as “POR”) becomes active when VSupply or V3V3 go under their falling
threshold.
When POR output signal is active, all functions and all flags inside L6460 are set in their
reset state; once POR signal comes back from off state (meaning monitored voltages are
above their rising threshold), the power up sequence is re-initialized.
5.2
nRESET generation circuit
The nRESET circuit monitors VSupply, VSupplyInt, VPump, VGPIO_SPI and all system regulators
(VSystem) voltages. The purpose of this circuit is to prevent the device functionality until the
monitored voltages reach their operative value (please note that V3v3 is monitored by POR,
so it must be above its minimum value, otherwise nRESET circuit is not active).
This circuit generates an internal reset signal (in the following indicated as “nRST_int”) that
will also be signaled to external circuits by pulling low the nRESET pin.
The signal nRST_int becomes active in the following cases:
1.
When one of the following voltages is lower than its own under voltage threshold:
–
VSupply and VSupplyInt.
–
VPump.
–
VSystem (all switching or linear system regulators voltages).
–
VGPIO_SPI.
2.
When watchdog timer counter (see Chapter 6) elapse the watchdog timeout time (only
if watchdog function is enabled).
3.
When L6460 is in “Low Power mode”.
4.
When EnExtSoftRst bit in SoftResReg register is at logic level = “1” and a “SoftRes”
command is applied (see SoftResReg register description in Chapter 25).
When an nRST_int event is caused by above cases, the nRESET pin will stay low for a
“stretch” time that starts from the moment that nRST_int signal returns in the operative
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L6460
Supervisory system
state. This stretch time can be selected by setting the ID[1:0] bits in the SampleID register
according to following table.
Table 6.
Stretch time selection
Selected stretch time
ID[1]
ID[0]
Note
Typ
0
0
16ms
0
1
32ms
1
0
48ms
1
1
64ms
Default state
When nRST_int becomes active (logic level = “0”) it sets in their reset state some of the
functions inside L6460. The main functions that will be reset by nRST_int signal are the
following:
–
Serial interface will be reset and will not accept any other command.
–
The bridges 1 and 2 will place their outputs in high impedance and PWM and
direction signals will be reset.
–
AD converter will be powered off.
–
GPIOs will be powered off.
–
Current DAC will be powered off.
–
Operational amplifiers will be powered off.
–
Watchdog count will be reset (while Watchdog flags won’t be reset).
–
Interrupt controller will be powered off.
–
Digital comparator will be powered off.
Additionally the system regulators will be powered off but only if the voltage that caused the
nRST_int event is checked before the system regulator in the power up sequence. This
means that:
–
all system regulators will be powered off if nRST_int is caused by VSupply,
VSupplyInt, VPump (and also if V3v3 causes a POR);
–
no one of the system regulators will be powered off if nRST_int is caused by
VGPIO_SPI;
–
only the system regulators that follows the system regulator that caused the
nRST_int in power up sequence will be powered off.
Doc ID 17713 Rev 1
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Supervisory system
L6460
Figure 5.
nReset generation circuit
V Supply
UV comparator
UV Filter
V SupplyInt
V SupplyUV
V SupplyIntUV
UV comparator
Filter
Low Power
Mode
t nRST_int
UV Filter
nRESET
pin
V Pump
nRESET
pin Driver
V PumpUV
UV comparator
UV Filter
UV comparator
V SysY
POR
SystemregulatorsUV
UV comparator
UV Filter
to SPI
Note:
34/139
WatchDog
Elapsed
UV Filter
WD_En_nRst
V SysX
nGateCtrl
All regulator voltages included in power up sequence (VSysX – VSysY in Figure 5) will be
considered as nRESET circuit voltages.
Doc ID 17713 Rev 1
L6460
5.3
Supervisory system
Thermal shut down generation circuit
The third component of the supervisory circuit is the thermal shut down generation circuit.
This circuit generates two different flags depending on the IC temperature:
–
the “TSD” flag indicates that the IC temperature is greater than the maximum
allowable temperature.
–
the “Warm” flag, that can be read using serial interface, becomes active at a lower
temperature respect to TSD signal, therefore it can be used to prevent the IC from
reaching over temperature.
When a TSD event occurs, L6460 will enter in the reset state placing the bridges in high
impedance and turning off all regulators and other circuits until the internal temperature
decreases below the Warm temperature. At this point, L6460 will restart the power up
sequence and TSD bit will be set and will be readable as soon as L6460 will come out from
the reset state.
This TSD bit can be reset in three ways:
–
by writing a logic level ‘1’ in the ClearTSD bit in the ICTemp register (see
Chapter 24);
–
by a POR event;
–
by entering in “Low Power Mode”.
The Warm bit, set by L6460 when IC is working over the warming temperature, can be read
using the SPI interface. Once this bit is set it can be reset in three ways:
–
by writing a logic level ‘1’ in the ClearWarm bit;
–
by a POR event;
–
by entering in “Low Power Mode”.
The thermal sensor voltage can be converted using the internal A/D: this way the
microcontroller can directly measure the IC temperature.
To avoid unwanted commutation especially when temperature is near the thresholds, the
output signal is filtered for both TSD and Warm.
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Watchdog circuit
6
L6460
Watchdog circuit
The Watchdog timer can be used to reset L6460 if it is not serviced by the firmware that can
periodically write at logic level “1’ the ClrWDog bit in the WatchDogStatus register.
This circuit is disabled by default; firmware can enable it by setting at logic level ‘1’ the
WDEnable bit in the WatchDogCfg register.
When the Watchdog timeout event happens, L6460 sets to ‘1’ a latched bit WDTimeOut in
theWatchDogStatus register that can be read using SPI interface; once this bit is set it can
be cleared in three ways:
–
by writing a ‘1’ in the WDClear bit in the WatchDogStatus register.
–
by writing a ‘1’ in the SoftReset bit in the WatchDogStatus register.
–
by a POR event.
The Watchdog function includes also a warning bit WDWarning to indicate, via serial
interface or via the circuit called Interrupt Controller (see Chapter 21) that the watchdog is
near to its timeout; this bit is asserted to logic level “1” exactly one watch dog clock period
(WD_Tclk) before the watchdog timeout happens. Firmware can enable the WDTimeOut
signal to cause an “nRst_int” event by setting to logic ‘1’ the WDEnnRst bit.
To SPI
WD_req_nRst
To nRSTint
generation circuit
WD_En_nRst
WDdelay[3:0]
WD_clk Watchdog counter
WDTimeOut
Frequency divider
WDWarning
Fosc
WDEnable
Watchdog circuit block diagram
ClrWDog
Figure 6.
The watchdog timeout has an imprecision of maximum one WD_Tclk. The effective
programmed WD time is changed in the register only when the watchdog circuit is serviced
by firmware with ClrWDog bit. At this time the watchdog timer is reset and the new value of
the WD delay value is loaded.
The watchdog timer can be programmed to generate different timeouts using the
WDdelay[3:0] bits in the WatchDogCfg register according to following table.
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L6460
Watchdog circuit
Table 7.
Watchdog timeout specifications
WD timeout
WDdelay[3:0]
Typ
0000
8*WD_Tclk
0001
9*WD_Tclk
0010
10*WD_Tclk
0011
11*WD_Tclk
0100
12*WD_Tclk
0101
13*WD_Tclk
0110
14*WD_Tclk
0111
15*WD_Tclk
1000
16*WD_Tclk
1001
17*WD_Tclk
1010
18*WD_Tclk
1011
19*WD_Tclk
1100
20*WD_Tclk
1101
21*WD_Tclk
1110
22*WD_Tclk
1111
23*WD_Tclk
Doc ID 17713 Rev 1
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Internal clock oscillator
7
L6460
Internal clock oscillator
L6460 includes a free running oscillator that does not require any external components.
This circuit is used to generate the time base needed to generate the internal timings; the
typical frequency is 16 MHz.
The oscillator circuit starts as soon as the IC exits from the power on reset condition and it is
stopped only when in “low power mode”.
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L6460
8
Start-up configurations
Start-up configurations
L6460 start-up configuration is selected by setting in different states the GPIO[0], GPIO[3]
and GPIO[4] pins. Each of these is a three state input pin and is able to distinguish among
the following situations:
Table 8.
Possible start-up pins state symbol
Pin condition
State symbol
Shorted to ground
0
Shorted to V3v3 pin
1
Floating
Z
Note:
“Shorted” means: R≤1KOhm; “Z” means: R≥10KOhm, C≤200pF
8.1
Operation modes
When VSupply voltage is applied to L6460, the internal regulator V3v3, used to supply the
logic circuits inside the device, starts its functionality. When it reaches its final value, L6460
enables the GPIO[0] pin state read circuitry, and, after a time TpinSample, it will sample the
GPIO[0] state. If it is found to be in high impedance, L6460 does not consider GPIO[3] and
GPIO[4] pins state and starts its “Basic device” mode sequence. If GPIO[0] is found to be
connected to ground or to V3v3, L6460 checks the state of GPIO[3] and GPIO[4] pins to
select its start-up configuration.
The possible configurations can be classified in four “Major” modes:
1.
Basic device.
2.
Slave device.
3.
Master device.
4.
Single device.
Hereafter is reported the correspondence table between GPIO[X] state and L6460
configurations.
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Start-up configurations
Table 9.
L6460
Start-up correspondence
Pin state(1)
Minor mode(2)
Major mode
GPIO[0]
GPIO[3]
GPIO[4]
Z
X
X
0
0
0
Bridge
0
0
Z
Primary regulator
0
0
1
Basic
Regulators
Single
0
Z
0
Simple regulator
0
Z
Z
Bridge + VEXT (3)
0
Z
1
Secondary regulators
0
1
0
Bridge
0
1
Z
Primary regulator
0
1
1
Regulators
Master
1
0
0
Simple regulator
1
0
Z
Bridge + VEXT (3)
1
0
1
Secondary regulators
1
Z
0
Bridge
1
Z
Z
Primary regulator
1
Z
1
Regulators
Slave
1
1
0
Simple regulator
1
1
Z
Bridge + VEXT (3)
1
1
1
Secondary regulators.
1. “X” means “don’t care”.
2. The description of these modes is in the following Chapter 8.6
3. VEXT is the regulator output voltage obtained using the switching regulator controller with external FET.
8.2
Basic device mode
The basic device mode is selected by leaving the GPIO[0] pin floating. In this mode L6460
doesn’t use GPIO[3] and GPIO[4] as configuration pins, leaving them free for other uses.
When in this mode the regulators included in the start up sequence (except VSWmain) are
considered as system regulators and they start in the following sequence:
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1.
Auxiliary switching regulator1 (VAUX1_SW).
2.
Auxiliary switching regulator2 (VAUX2_SW).
3.
Main linear regulator (VSWmain).
4.
Main switching regulator (VSWmain) (Not system regulator).
Doc ID 17713 Rev 1
L6460
8.3
Start-up configurations
Slave device mode
In slave device mode, L6460 consider the nAWAKE pin as an input enable. Since this is now
a digital pin, the current pull up source inside the nAWAKE circuit is disabled.
At the startup, if the nAWAKE pin is found to be low for a period higher than tAWAKEFILT,
L6460 enters directly in the “Low Power mode”; when nAWAKE pin is pulled high for a
period higher than tAWAKEFILT, L6460 begins its start up procedure.
8.4
Master device mode
In master device mode, L6460 begins its start up procedure without waiting for any external
enable signal and it uses GPIO[5] pin to drive the nAWAKE pin of Slave devices.
During the whole start up time, it forces its GPIO[5] pin at logic level “0” in order to maintain
all slave devices in “Low Power mode” as previously described. When start up operations
are completed, L6460 forces the GPIO[5] output to logic level “1” to enable the slave devices
and keeps GPIO[5] output at high level until it senses an under-voltage on any of its System
regulators. If firmware writes in the PwrCtrl register to set Master L6460 in “Low Power
mode” it immediately forces GPIO[5] output to logic level “0” to force the slave devices to
enter in “Low Power mode”, then it waits for TMASTWAIT time and it starts its “Low Power
mode” sequence.
8.5
Single device mode
In single device mode, the device behaves similarly to master device mode but:
8.6
1.
It doesn’t use the GPIO[5] pin to drive slave devices.
2.
It doesn’t wait for TMASTWAIT before entering in “Low Power mode”.
Sub-configurations for slave, master or single device modes
Each slave, master or single device modes can be divided in other minor modes depending
on the start-up sequence needed for L6460 internal regulators.
Unless otherwise specified, in all the following modes the regulators included in the start up
sequence are considered system regulators and they start in the sequence indicated.
8.6.1
Bridge mode
In this configuration bridges 3 and 4 are not used as regulators and therefore can be
configured by the firmware in any of their possible bridge modes.
When in this mode the power-up sequence is:
1.
Main switching regulator (VSWmain).
2.
Main linear regulator (VLINmain).
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Start-up configurations
8.6.2
L6460
Primary regulator mode (KP)
In this configuration bridge 4 can be configured by firmware while bridge 3 is configured as
two separate synchronous switching regulators. The last regulator in the sequence
(VAUX2_SW) is not considered a system regulator.
When in this mode the power-up sequence is:
8.6.3
1.
Auxiliary switching regulator1 (VAUX1_SW).
2.
Main switching regulator (VSWmain) together with main linear regulator (VLINmain).
3.
Auxiliary switching regulator2 (VAUX2_SW) (Not system regulator).
Regulators mode
In this configuration bridge 4 can be configured by firmware while bridge 3 is configured as
two separate synchronous switching regulators, but the start up sequence is different
previous one.
When in this mode the power-up sequence is:
8.6.4
1.
Main switching regulator (VSWmain).
2.
Auxiliary switching regulator1 (VAUX1_SW)
3.
Auxiliary switching regulator2 (VAUX2_SW)
Simple regulator mode (KT)
Also in this configuration bridge 4 can be configured by firmware while bridge 3 is configured
as two separate synchronous switching regulators. The last regulator in the sequence
(VSWmain) is not considered a system regulator.
When in this mode the power-up sequence is:
1.
8.6.5
Auxiliary switching regulator1 (VAUX1_SW).
2.
Auxiliary switching regulator2 (VAUX2_SW)
3.
Main linear regulator (VLINmain)
4.
Main switching regulator (VSWmain) (not system regulator).
Bridge + VEXT mode
In this configuration bridges 3 and 4 are not used as regulators and the regulator obtained
using the switching regulator controller (VSWDRV) is included in start-up.
When in this mode the power-up sequence is:
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1.
Main switching regulator (VSWmain).
2.
Switching regulator controller regulator (VSWDRV).
3.
Main linear regulator (VLINmain).
Doc ID 17713 Rev 1
L6460
8.6.6
Start-up configurations
Secondary regulators mode
In this configuration, bridge 3 is configured as a single synchronous switching regulator
using its two half bridges in parallel (VAUX_(1//2)SW).
When in this mode the power-up sequence is:
1.
Main switching regulator (VSWmain).
2.
Auxiliary switching regulator (VAUX(1//2)_SW).
3.
Main linear regulator (VLINmain).
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Power sequencing
9
L6460
Power sequencing
As soon as VSupply and VSupplyInt are above their power on reset level, L6460 will start the
charge pump circuit; once VPump voltage reaches its under voltage rising threshold, L6460
begins a sequence that starts the regulators considered system regulators.
A regulator is considered a System regulator if:
–
It has to start in on state without any user action.
–
It is included in the power-up sequence.
–
Its under-voltage event is considered by L6460 as an error condition to be
signaled through nRESET pin.
Once VSupply and VSupplyInt, VPump and all the system regulators are over their under
voltage rising threshold, L6460 enters in the normal operating state, that will release
nRESET pin and will wait for SPI commands.
L6460 will reduce the noise introduced in the system by switching out of phase all its power
circuits (switching regulators, bridges and charge pump).
The L6460's startup sequence of operation is the following:
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–
start V3v3 internal linear regulator
–
sample startup configuration
–
wait enable if slave device
–
start charge pump
–
start system regulators (see order in Section 8.6)
–
if master send enable to slave device
–
wait until VGPIO_SPI becomes ok
Doc ID 17713 Rev 1
L6460
10
Power saving modes
Power saving modes
Saving power is very important for today platforms: L6460 implements different functions to
achieve different levels of power saving. Sections here below describe these different power
saving modes.
Standby mode
Almost all low voltage circuitry inside L6460 are powered by V3v3 internal regulator; this
regulator is a linear regulator powered by VSupplyInt. This means that all the current provided
by V3v3 regulator is directly coming from VSupplyInt and therefore the total power
consumption is:
Low voltage power = VSupply* IV3v3.
because VSupplyInt is feeded by VSupply, directly or with a resistor in series.
This power could be reduced by using a switching buck regulator to supply V3v3: in this
case, assuming the buck regulator efficiency near to 100%, the dissipated power would
become:
Low voltage power ≈ 3.3V * IV3v3.
To achieve this result there is the need to switch off the internal V3v3 linear regulator and to
use an additional pin to provide a 3.3 V supply to internal circuits. L6460 can do this by
using the low voltage switch implemented on GPIO6 pin. This switch internally connects
VGPIO_SPI voltage to GPIO6 output so, by externally connecting GPIO6 to V3v3 pin, the
VGPIO_SPI voltage can be provided to low voltage circuitry inside L6460.
Figure 7.
Standby mode function description
VSupplyInt
Power Switch 1
10.1
StdByMode
3.3 V
1.9 V
0
+
V3v3
Regulator
1
VGPIOSpi
GPIO6
External
connection
3.3V
-
The StdByMode bit used to switch off V3v3 and switch on the power switch can be set to ‘1’
by writing the standby command in the StdByMode register. L6460 exits standby mode if a
reset event happens or “Low Power mode” is selected.
Because all internal low voltage circuitry powered by V3v3 are designed to work with a 3.3V
voltage rail, when the standby mode is used, VGPIO_SPI is requested to be at 3.3V.
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Power saving modes
10.2
L6460
Hibernate mode
L6460’s hibernate mode allows the firmware to switch off some (or all) selected System
Regulators leaving in on state only those necessary to resume L6460 to operative condition
when waked-up by an external signal.
Hibernate mode is selected when the firmware writes the command word in the
HibernateCmd register. When in hibernate mode L6460 will force regulators in the state
(on/off) selected by the firmware by writing in the HibernateCmd register and will force
nRESET pin low.
The exiting from hibernate mode is achieved by forcing at low level nAWAKE pin (or GPIO5
pin if L6460 is in Slave mode); L6460 will also exit from hibernate mode if an undervoltage
event happens on VSupply, VSupplyInt, VPump or V3v3.
When the exit from hibernate mode is due to an external command, L6460 sets to ‘1’ the bit
HibModeLth in the HibernateStatus register.
10.3
Low power mode
When in normal operating mode, the microcontroller can place L6460 in “Low Power mode”.
In this condition L6460 sets all bridges outputs in high impedance, powers down all
regulators (including system regulators and charge pump) and disables almost all its circuits
including internal clock reducing as much as possible power consumption.
The only circuits that remain active are:
–
V3V3 internal regulator.
–
nAWAKE pin current pull-up.
–
nRESET pin that will be pulled low.
–
POR circuit.
The entering in low power mode is obtained in different ways depending if L6460 is
configured as slave device or not. When L6460 is configured as slave device the low power
mode is directly controlled by nAWAKE pin that acts as an enable: if this pin is low for a time
longer then tAWAKEFILT, Low Power mode is entered; if this pin is high L6460 exits from Low
Power mode.
In all other start-up configurations, Low Power mode is entered by writing a Low Power
mode command in the PowerModeControl register; once L6460 is in Low Power mode it
starts checking the nAWAKE pin status: if it is found low for a time longer than tAWAKEFILT,
L6460 exits from Low Power mode and restarts its startup sequence. When the nAWAKE
pin is externally pulled low, the “AWAKE” event is stored and it is readable through SPI.
L6460 will also exit from Low Power mode if a POR event is found.
Note:
When in “Low power mode” VSupply is monitored only for its power on reset level.
10.4
nAWAKE pin
At the start up, before L6460 has identified the required operation mode (see Chapter 8), a
current sink IINP is always active to pull down nAWAKE pin. As soon as the operation mode
(basic, slave, master or single device) is detected, the functionality of nAWAKE pin will be
different.
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Doc ID 17713 Rev 1
L6460
Power saving modes
If L6460 is not configured as slave device a current source IOUT will be active on this pin,
while the current sink IINP will be disabled. If L6460 is configured as a Slave device, the
current sink IINP will be active until nAWAKE pin is detected high for the first time; after that
both current sources IINP and IOUT will be disabled and the nAWAKE pin can be considered
as a digital input.
Here below is reported the nAWAKE pin simplified schematic.
Figure 8.
nAWAKE function block diagram
V 3v3
SlaveMode
I OUT
AWAKE_req
AWAKE
nAWAKE seen high
for the first time after
start up.
I INP
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Linear main regulator
11
L6460
Linear main regulator
The linear main regulator is directly powered by VSupply voltage and it is one of the
regulators that L6460 could consider as a system regulator. This means that the voltage
generated by this regulator is not used to power any internal circuit, but L6460 will check
that the feedback voltage VLINmain_FB is in the good value range before enabling all its
internal functions. When an under-voltage event (with a duration longer than period tprim_uv
defined by the deglitch filter) is detected during normal operation, L6460 will enter in reset
state and it will signal this event to the microcontroller by pulling low the nRESET pin and
disabling most of its internal blocks.
Here are summarized the primary features of the regulator:
–
Regulated output voltage from 0.8V to VSupply-2V with a maximum load of 10mA.
–
Band gap generated internal reference voltage.
–
Short circuit protected (output current is clamped to 22mA typ).
–
Under voltage signal (both continuous and latched) accessible through serial
interface.
–
Low power dissipation mode.
The internal series element is a P-channel MOS device. The voltage regulator will regulate
its output so that feedback pin equals VLINmain_FB, therefore the regulated voltage can be
calculated using the formula:
VLINmain_OUT = VLINmain_ref *(Ra+Rb)/Rb
Figure 9.
Linear main regulator
V supply
Body Diode
V LINmain_OUT
Driver
Cc
Ra
+
V LINmain_FB
-
V LINmain_ref
Rb
To extend the output current capability this regulator can be used as a controller for an
external active component able to provide higher current (i.e. a Darlington device); the
external power element allows the handling of an higher current since it dissipates the
power externally (the power dissipated by a linear driver supplied at VSupply and regulating a
voltage VLINmain_OUT with an output current IOUT is about: Pd= (VSupply-VLINmain_OUT)*IOUT.
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Doc ID 17713 Rev 1
L6460
Linear main regulator
Figure 10. Linear main regulator with external bipolar for high current
V supply
Body Diode
Driver
VLINmain_OUT
Cload
+
Ra
VLINmain_FB
-
VLINmain_Ref
Rb
Whichever configuration is used (regulator or controller), a ceramic capacitor must be
connected on the output pin towards ground to guarantee the stability of the regulator; the
value of this capacitance is in the range of 100 nF to 1 µF depending on the regulated
voltage;
●
VLINmain_OUT = 0.8 V --> 1 µF
●
0.8V< VLINmain_OUT < 2.5 V --> 0.68 µF
●
2.5V= VLINmain_OUT 5 V --> 0.33 µF
●
VLINmain_OUT > 5 V --> 0.1 F
When this regulator is disabled, the whole circuit is switched off and the current
consumption is reduced to a very low level both from V3v3 and from VSupply. When in this
condition, the output pin is pulled low by an internal switch.
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Main switching regulator
12
L6460
Main switching regulator
Main switching regulator is an asynchronous switching regulator intended to be the source
of the main voltage in the system. It implements a soft start strategy and could be a system
regulator so even if its output voltage VSWmain is not used to power any internal circuit,
L6460 will check that it is in the good value range before enabling all its internal functions.
When L6460 detects a system regulator under-voltage event with a duration longer than the
period defined by the deglitch filter (tprim_uv), it will enter in reset state signaling this event to
the microcontroller by pulling low the nRESET pin and disabling most of its internal block
(e.g. bridges, GPIOs, …).
The output voltage will be externally set by a divider network connected to feedback pin. To
reduce as much as possible the regulation voltage error L6460 has the possibility to choose
between four feedback voltage references (and, as a consequence, four under-voltage
thresholds) using the serial interface. The feedback reference voltage selection is made by
writing the SelFBRef bits in the MainSwCfg register.
Here after are summarized the primary features of this regulator:
–
Internal power switch.
–
Soft start circuitry to limit inrush current flow from primary supply.
–
Internally generated PWM (250 kHz switching frequency).
–
Nonlinear pulse skipping control.
–
Protected against load short circuit.
–
Cycle by cycle current limiting using internal current sensor.
–
Under voltage signal (both continuous and latched) accessible through SPI.
When L6460 is in “low power mode”, this regulator will be disabled.
In order to save external components and power when using two or more L6460 IC’s on the
same board, the primary switching regulator can be disabled by serial interface. Care must
be paid using this function because an under-voltage on this regulator, as previously seen,
will be read as a fault condition by L6460.
12.1
Pulse skipping operation
Pulse skipping is a well known, non linear, control strategy used in switching regulators.
In this technique (see Figure 11) the feedback comparator output is sampled at the
beginning of each switching cycle. At this time, if the sampled value shows that output
voltage is lower than requested one, the complete PWM duty cycle is applied to power
switch; otherwise no PWM is applied and the switching cycle is skipped. Once PWM is
applied to power element only a current limit event can disable the power switch before the
whole duty cycle is finished.
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Doc ID 17713 Rev 1
L6460
Main switching regulator
Figure 11. Main switching regulator functional blocks
VSupply
Current Sense
Charge pump Voltage
High Side
Driver
VSWmain_SW
La
Ra
C
Voltage
Loop Control
Control
Logic
From Central Logic
+
VSWmain_FB
Rb
Regulator Freq
Regulator Ref
Under voltage flag
Filter
To Central Logic
+
Under voltage
Threshold
In pulse skipping control the duty cycle must be chosen by the user depending on supply
voltage and output regulated voltage. Therefore the switching regulator has 4 possible duty
cycles that can be changed by writing the VmainSwSelPWM bits in the MainSwCfg register
according to following Table 10.
Table 10.
Main switching regulator PWM specification
MainSwCfg register
Duty cycle value
VmainSwSelPWM[1:0]
Typical
00
12%
01
15%
10
26%
11
63.5%
Comments
Default state
The output current is limited to a value that can be set by means of SelIlimit bit in the
MainSwCfg register according to following Table 11.
Table 11.
Main switching regulator current limit
SelIlimit
Current limit (min)
Comments
0
3.3A
Default state
1
2.3A
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Switching regulator controller
13
L6460
Switching regulator controller
This circuit controls an external FET to implement a switching buck regulator using a non
linear pulse skipping control with internally generated PWM signal.
The output voltage will be externally set by a divider network connected on feedback pin. To
reduce as much as possible the regulation voltage error L6460 has the possibility to switch
between four regulator feedback voltage references (and, as a consequence, four undervoltage thresholds) using serial interface. The feedback reference voltage is selected by
writing the SelFBRef bits in the SwCtrCfg.
This regulator is switched off when L6460 is powered up for the first time and can be
enabled using L6460’s SPI interface.
Here after are summarized the main features of the regulator:
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–
Soft start circuitry to limit inrush current flow from primary supply.
–
Changeable feedback reference voltage
–
Internally generated PWM (250 kHz switching frequency).
–
Nonlinear pulse skipping control.
–
Protected against load short circuit.
–
Cycle by cycle current limiting using internal current sensor.
–
Under voltage signal (both continuous and latched) accessible through SPI.
Doc ID 17713 Rev 1
L6460
Switching regulator controller
Figure 12. Switching regulator controller functional blocks
V supply
Rsense
CurrentSense
V SWDRW_sns
Charge pump Voltage
N-CH Fet
Driver
V SWDRV_gate
V SWDRV
La
Ra
SW
V out
Voltage
C
Loop Control
Control
Logic
From Central Logic
+
SelFBRef[1:0]
V SWDRV
FB
Regulator Freq
Rb
Analog Mux
Vref = 3 V
Vref = 3V
Vref=0.8V
VFBRef
Vref=0.8V
undervoltage flag
+
Filter
To Central Logic
Analog Mux
SelFBRef
Uv Threshold 1
Uv Threshold 2
13.1
Under voltage
Threshold
Pulse skipping operation
Pulse skipping strategy has already been explained on main switching regulator section.
This regulator has 4 possible PWM duty cycles that can be changed writing in the
SelSwCtrPWM bits in the SwCtrCfg register using SPI.
Table 12.
Switching regulator controller PWM specification
SwCtrCfg register
Duty cycle value
SelSwCtrPWM[1:0]
Typical
00
9%
01
12%
10
22.5%
11
58%
Comments
Doc ID 17713 Rev 1
Default state
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Switching regulator controller
13.2
L6460
Output equivalent circuit
The switching regulator controller output driving stage can be represented with an
equivalent circuit as in the Figure 13:
Figure 13. Switching regulator controller output driving: equivalent circuit
VPUMP
I SOURCE
Source command
Tsink
V SWDRV_gate
Sink pulse command
RSUSTAIN
Sink command
I SINK
V SWDRV_SW
As can be seen from the above figure, the external switch gate is charged with a current
generator ISOURCE and it is discharged towards ground with a current generator ISINK that is
applied for a TSINK pulse while an equivalent resistor RSUSTAIN is connected between gate
and source until the sink command is present.
13.3
Switching regulator controller application considerations
This controller can implement a step-down switching regulator used to provide a regulated
voltage in the range 0.8 V – 32 V. Such kind of variation could be managed by considering
some constraints in the application and particularly by choosing the correct feedback
reference voltage as indicated in the Table 13.
Table 13.
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Switching regulator controller application: feedback reference
Output regulated voltage range
Feedback voltage reference
0.8V ≤ Vout < 5V
0.8V - 1V
5V ≤ Vout ≤ 32V
2.5V - 3V
Doc ID 17713 Rev 1
L6460
Switching regulator controller
An example of application can be considered the following, supposing the external mosfet
type STD12NF06L:
–
Max DC current load = 3 A
–
Typ Over current threshold = 3 A * 1.5 = 4.5 A
–
L = 150 µH
–
C = 220-330 µF
In this conditions the step-down regulator will result over-load protected, short-circuit
protected over all the regulated voltage range and the VSupply range.
Other application configurations could be evaluated before being implemented.
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Power bridges
14
L6460
Power bridges
L6460 includes four H bridge power outputs (each one made by two independent half
bridges) that are configurable in several different configurations.
Each half bridge is protected against: over-current, over-temperature and short circuit to
ground, to supply or across the load. When an over current event occurs, all outputs are
turned off (after a filter time), and the over current bit is stored in the internal status register
that can be read through SPI.
Positive and negative voltage spikes, which occur when switching inductive loads, are
limited by integrated freewheeling diodes (see Figure 14).
Figure 14. H Bridge block diagram
7TVQQMZ
(IGHSIDE
$RIVER
(IGHSIDE
$RIVER
#ONTROL,OGIC
#ONTROL,OGIC
,OWSIDE
$RIVER
,OWSIDE
$RIVER
(/%
PS
4&/4&
During the start up procedure the bridges are in high impedance and after that they can be
enabled through SPI. When a fault condition happens, i.e. an over-temperature event, the
bridges return in their start-up condition and they need to be re-enabled from the micro
controller.
The bridges can use PWM signals internally generated or externally provided (supplied
through the GPIO pins). Internally generated PWM signals will run at approximately
31.25kHz with a duty cycle that, through serial interface, can be programmed and
incremented in steps of 1/(512*Fosc). To reduce the peak current requested from supply
voltage when all bridges are switching, the four internally generated PWM signals are outof-phase.
Each half bridge will use the PWM signal selected by the respective
MtrXSelPWMSideY[1:0] (X stands for 1, 2, 3 or 4; Y stands for A or B) bits in the SPI, but if
two half bridges are configured as a full bridge, only the PWM signal chosen for side A will
be used to drive the resulting H bridge.
More in detail the PWM selection truth table will be as describe in the following tables:
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L6460
Power bridges
Table 14.
PWM selection truth table for bridge 1 or 2
Selected PWM(1)
MtrXSelPWMSideY [1] MtrXSelPWMSideY [0]
0
0
MotorXPWM (Configurable by means of MtrXCfg
register).
0
1
AuxXPWM (Configurable by means of
AuxPwmXCtrl register).
1
0
ExtPWM1 (from GPIO 9 input)
1
1
ExtPWM2 (from GPIO 10 input)
1. In this table X stands for 1 or 2, Y stands for A or B.
Table 15.
PWM selection truth table for bridge 3 or 4
MtrXSelPWMSideY [1] MtrXSelPWMSideY [0]
Selected PWM(1)
0
0
MotorXPWM (Configurable by means of
MtrXCfg register).
0
1
AuxXPWM (Configurable by means of
AuxPwmXCtrl register).
1
0
ExtPWM3 (from GPIO 2 input)
1
1
ExtPWM4 (from GPIO 11 input)
1. In this table X stands for 3 or 4, Y stands for A or B.
In Figure 15 is reported a block diagram representing the possible PWM choices for each
L6460 half bridges. The figure is related only to bridges 1 and 2, but it could be assumed to
be valid also for bridges 3 and 4, with few differences due to different possible configurations
of these last drivers.
Doc ID 17713 Rev 1
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Power bridges
L6460
Figure 15. Bridge 1 and 2 PWM selection
00 Motor1 PWM
01 Aux1PWM
10 ExtPWM1
Motor 1 side A
Logic Table
11 ExtPWM2
Mtr1_2Parallel
Side A Power Section
Mtr1SelPWMSide A[1:0]
Mtr1SelPWMSideB [1:0]
01Aux1PWM
10ExtPWM1
11ExtPWM2
Motor 1 sideB
Logic Table
Bridge1
Side B Power Section
Mtr1Tablel[1:0]
00 Motor1 PWM
Mtr1_2Parallel
Mtr2SelPWMSideA[1:0]
Motor 2 side A
Logic Table
Side A Power Section
Motor 2 sideB
Logic Table
Side B Power Section
Mtr2Tablel[1:0]
00 Motor2 PWM
01Aux2Pwm
10ExtPwm1
11ExtPwm2
Mtr2SelPWMSide B [1:0]
Mtr1_2Parallel
Mtr2Tablel[1:0]
00 Motor2 PWM
01 Aux2Pwm
10 ExtPwm1
11 ExtPwm2
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Bridge 2
Doc ID 17713 Rev 1
L6460
14.1
Power bridges
Possible configurations
The selection of the bridge configuration is done through SPI, by writing the MtrXTable[1:0]
bits in the MtrXCfg register. The table below shows the correspondence between
MtrXTable[1:0] bits and the bridge configuration.
Table 16.
Bridge selection
MtrXTable[1]
MtrXTable[0]
Bridge configuration
0
0
Full bridge
0
1
High or low side switch
1
0
Half bridge
1
1
High or low side switch
Bridge 1 & 2 can be paralleled by means of Mtr1_2Parallel bit in the Mtr1_2Cfg register:
Bridge 1 and 2 paralleled will form superbridge1, bridge X side A and bridge X side B
paralleled form SuperHalfBridgeX or SuperSwitchX.
Bridge 3 & 4 can be configured by means of Mtr3_4CfgTable[1:0] bits in the Mtr3_4Cfg
register according to following table:
Table 17.
Bridge 3 and 4 configuration
Mtr3_4CfgTable[1]
Mtr3_4CfgTable[0]
Bridge 3 and 4 configuration
0
0
Two independent bridges
0
1
Two bridges in parallel
1
0
Stepper motor
1
1
Stepper motor
The possible configurations for the bridges are described in the following.
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Power bridges
14.1.1
L6460
Full bridge
When in full bridge configuration, the drivers will behave according to the following truth
table:
Table 18.
Note:
Full bridge truth table
TSD
nRESET
Low
power
mode
Enable
1
X
X
X
X
X
0
0
X
X
X
0
1
1
X
0
1
0
0
1
0
Current MtrXCtrl MtrXCtrl
limit
SideA
SideB
PWM
OUT+
OUT-
X
X
Z
Z
X
X
X
Z
Z
X
X
X
X
Z
Z
0
X
X
X
X
Z
Z
0
1
1
X
X
X
Z
Z
1
0
1
0
0
0
X
0
0
0
1
0
1
0
0
1
0
1
1
0
1
0
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
1
1
0
1
0
1
0
1
0
1
1
0
0
1
0
1
0
1
1
X
1
1
Note: When “low power mode” is active, the bridges will enter in low power state and will
reduce its biasing thus contributing to the power saving.
When a current limit event occurs this event will be latched and the bridges will remain in
high impedance state for the off time.
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Doc ID 17713 Rev 1
L6460
14.1.2
Power bridges
Parallel configuration (super bridge)
Bridges 1, 2, 3 and 4 can be configured to be used two by two (1 plus 2, 3 plus 4) as one
super bridge thus enabling the driving of loads (motors) requiring high currents. In this
configuration the half bridges will be paralleled and will work as one phase of the superbridge just created: the two phases + will become phase + of the newly created superbridge while the two phases - will become phase –.
Figure 16. Super bridge configuration
Parallel Full Bridge
Super Bridge
Bridge 2 (4)
Bridge 1 (3)
PH
PH
PH
PH
+
-
-
+
M
When this configuration is chosen for bridges 1 (3) and 2 (4), the resulting bridge will use the
driving logic of bridge 1 (3) so for programming it must be used the bridge 1 (3) control and
status bits (direction, PWM, ...): i.e. the used PWM signal will be chosen by
Mtr1SideAPwmSel[1:0] (Mtr3SideAPwmSel[1:0]) bits in SPI.
If the bridges are not configured to be used in parallel, each side of the bridge will use the
PWM selected by the respective MtrXPWMYSel[1:0] bits in the SPI, but if one of the two
drivers is configured as a full bridge only one of the two selected PWM will be used to drive
the motor and this is the PWM chosen for side A.
In order to avoid any problem coming from different propagation times of PWM signals the
anti-crossover dead times are slightly increased when the bridges are paralleled.
14.1.3
Half bridge configuration
Each bridge can be configured to be used as 2 independent half bridges or as 1 super half
bridge (see Figure 17). It is also possible to parallel more than one bridge and use all of
them as a single super half bridge.
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Power bridges
L6460
Figure 17. Half bridge configuration
V Supply
V pump
High side
Driver
DCX Phase output
Control Signals
Control
Logic
Low side
Driver
Signals
Fault
From SPI
In this case each half bridge will behave according to the following truth table.
Table 19.
Note:
Half bridge truth table
TSD
nReset
Low
power
mode
Enable
Current
limit
MtrXCtrl
SideA/B
PWM
OUT
1
X
X
X
X
X
X
Z
0
0
X
X
X
X
X
Z
0
1
1
X
X
X
X
Z
0
1
0
0
X
X
X
Z
0
1
0
1
0
0
0
Z
0
1
0
1
0
0
1
0
0
1
0
1
0
1
0
Z
0
1
0
1
0
1
1
1
0
1
0
1
1
X
X
Z
When “low power mode” bit is active the bridges will reduce its biasing thus contributing to
the power saving.
When a current limit event occurs this event will be latched and the bridges will remain in
high impedance state for the off time.
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Doc ID 17713 Rev 1
L6460
14.1.4
Power bridges
Switch configuration
Each bridge can be configured to be used as 2 independent switches that connects the
output to supply or to ground. It is also possible to parallel the two switches and use them as
a single super switch.
All resulting switches will behave according to the following truth table.
Table 20.
Note:
Switch truth table
TSD
nReset
Low
power
mode
Enable
Current
limit
MtrXCtrl
SideA/B
PWM
OUT
1
X
X
X
X
X
X
Z
0
0
X
X
X
X
X
Z
0
1
1
X
X
X
X
Z
0
1
0
0
X
X
X
Z
0
1
0
1
0
0
X
Z
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
0
1
0
1
1
X
X
Z
When “low power mode” bit is active the bridge will reduce its biasing thus contributing to the
whole power saving.
When a current limit event occurs this event will be latched and the bridge will remain in high
impedance state for the toff time.
14.1.5
Bipolar stepper configuration
The bridges 3 and 4 can be configured to be used as a micro-stepping, bidirectional driver
for bipolar stepper motors.
The primary features of the driver are the following:
–
Internal PWM current control.
–
Micro stepping.
–
Fast, mixed and slow current decay modes.
Each H-bridge is controlled with a fixed and selectable off-time PWM current control circuit
that limits the load current to a value set by choosing VSTEPREF voltage by means of the
internal DAC and an the external RSENSE value.
The max current level could be calculated using the formula:
IMAX=VSTEPREF/RSENSE
To obtain the best current profile, the user can choose three different current decay modes:
slow, fast and mixed. Initially, during Ton, a diagonal pair of source and sink power MOS is
enabled and current flows through the motor winding and the sense resistor. When the
voltage across the sense resistor reaches the programmed DAC output voltage, the control
logic will change the status of the bridge according to the selected decay mode (slow, fast or
mixed). In slow decay mode the current is recirculated through the path including both high
Doc ID 17713 Rev 1
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Power bridges
L6460
side power MOS for the whole off time. In fast decay mode the current is recirculated
through the high and low side power MOS opposite respect to those forcing current to
increase. Mixed decay mode is a selectable mix of the previous two modes (fast decay
followed by slow decay) and allows the user to find the best trade off between load current
ripple and fast current levels transition. Additionally, by setting the
SeqMixedOnlyInDecreasingPh bit in the StpCfg1 register, the user can choose to apply the
fast decay percentage in mixed mode always or only when the current is decreasing (i.e
from 90° to 180° and from 270° to 360° of the sinusoidal wave).
By using SPI interface the user can choose:
64/139
●
Control type (external firmware control, half step, normal drive, wave drive, micro-step).
●
Up to 16 current levels (quasi-sinusoidal increments) for each bridge.
●
Current direction.
●
Decay mode.
●
Blanking time.
●
Off time (32 values from 2µs to 64µs).
●
Percentage of fast decay respect to toff (when in mixed decay mode).
Doc ID 17713 Rev 1
L6460
Power bridges
Figure 18. Bipolar stepper configuration
DC3_PHDC3SENSE
V supply
DC3_PH+
Stepper
Motor
VRefA
DC4 PH-
Supply
PH-
Supply
PH+
PH-
PH+
DC4 PH+
Sense
Sense
Bridge Driver
- Control Logic
- Toff generation
- DAC reference
selection
Bridge Driver
VRefB
Ref1
V STEPREF
Ref2
DC4SENSE
VRefA
StepperDACPhA
SelStepRef
StepperDACPhB
VRefB
Using the StepCtrlMode[2:0] bits in StepCfg1 register, L6460 can be programmed to
internally generate the stepping levels. In these cases and depending on the StepFromGpio
bit in the StpCfg1 register the Stepper driver will move to next step each time the StepCmd
bit is set at logic level “1” or at each pulse transition longer than ~1µs externally applied on
GPIO12 (StepReq signal), according to Table 21.
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Power bridges
L6460
Table 21.
Sequencer driver
StepFromGpio
Sequencer driver
0
StepCmd bit in StepCmd register.
1
GPIO12 input pin.
The allowable control modes are as follows:
1.
Stepping sequence left to external microcontroller: in this mode the current level in
each motor winding is set by the microcontroller via the serial interface.
2.
Full step: in this mode the electrical angle will change by 90° steps at each StepReq
signal transition. There are two possibilities:
–
Normal step (two phases on): in normal step mode both windings are energized
simultaneously and the current will be alternately reversed. The resulting electrical
angles will be 45°, 135°, 225° and 315°.
–
Wave drive (one phase on): In wave drive mode each winding is alternately
energized and reversed. The resulting electrical angles will be 90°, 180° and 270°
and 360°.
3.
Half step: in this mode, one motor winding is energized and then two windings
alternately so the electrical angles the motor will do when rotating in clockwise direction
and using the same current limit in both the phases are: 45°, 90°, 135°, 180°, 225°,
270°, 315° and 360°.
4.
Microstepping: in this mode the current in each motor winding has a quasi sinusoidal
profile. The increment between each step is obtained at each transition of StepCmd bit
in StepCmd register. The difference between each step could be chosen (4, 8 or 16
levels for each phase) according to following table:
Table 22.
Note:
Stepper driving mode
StepCtrlMode[2:0]
Control mode
Description
000 or 111
No Control
001
Half Step
010
Normal Step
Full step (two phases on)
011
Wave Drive
Full step (one phase on)
100
1/4 Step
Four micro steps
101
1/8 Step
Eight micro steps
110
1/16 Step
Sixteen micro steps
Stepping sequence control left to the external
controller
Half step
When in 1/16 step mode, the best phase approximation of sinusoidal wave, is obtained by
repeating the “F” step as follows: 0, 1, 2, 3, … , D, E, F, F, F, E, D, … , 3, 2, 1, 0
When internal stepping sequence generation is used, the stepping direction is set by the
StepDir bit according to the Table 23.
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Doc ID 17713 Rev 1
L6460
Power bridges
Table 23.
Note:
Stepper sequencer direction
StepDir
Direction
0
Counter clockwise (CCW)
1
Clockwise (CW)
It is intended as clockwise the sequence that forces a clockwise rotation of the versors
representing the current module and phase.
Doc ID 17713 Rev 1
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Power bridges
L6460
An internal DAC is used to digitally control the output regulated current. The available values
are chosen to provide a quasi sinusoidal profile of the current. The current limit in each
phase is decided by PhADAC[3:0] bits for phase A and PhBDAC[3:0] bits for phase B. The
table below describes the relation between the value programmed in the stepper DAC and
the current level.
Table 24.
DAC
Phase current ratio respect to IMAX
PhXDAC [3:0]
Min
0000
Note:
Typ
Max
Unit
(Hi-Z)
0001
-
9.8
-
% of IMAX
0010
-
19.5
-
% of IMAX
0011
-
29.0
-
% of IMAX
0100
-
38.3
-
% of IMAX
0101
-
47.1
-
% of IMAX
0110
-
55.6
-
% of IMAX
0111
-
63.4
-
% of IMAX
1000
-
70.7
-
% of IMAX
1001
-
77.3
-
% of IMAX
1010
-
83.1
-
% of IMAX
1011
-
88.2
-
% of IMAX
1100
-
92.4
-
% of IMAX
1101
-
95.7
-
% of IMAX
1110
-
98.1
-
% of IMAX
1111
-
IMAX
-
The min and max values are guaranteed by testing the percentage of VSTEPREF that
allows the commutation of the Rsense comparator.
IMAX=VSTEPREF/ RSENSE.
To obtain the best phase approximation of a sinusoidal wave, the user needs to repeat the
final (100%) value. So the full values sequence should be as follows: 0, 1, 2, 3 … D, E, F, F,
F, E, D … 3, 2, 1, 0.
Even if the total spread shows overlapping between current steps, the monotonicity is
guaranteed by design.
When the internal sequencer the minimum angle resolution is nominally 5.625°, so
depending on the control mode chosen, the selectable steps are Table 25.
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Doc ID 17713 Rev 1
L6460
Power bridges
Table 25.
Internal sequencer
Typical output
current (% of IMAX)
Control mode
Half
step
Full step
(2 phases
on)
1
1
Full step
(1 phase
on)
1/4
step
1/8
step
1/16
step
Phase A
(sin)
Phase B
(cos)
Electrical
degrees
1
1
1
70.7
70.7
45°
2
77.3
63.4
50.6°
3
83.1
55.6
56.2°
4
88.2
47.1
61.9°
5
92.4
38.3
67.5°
6
95.7
29.0
73.1°
7
98.1
19.5
78.8°
8
100
9.8
84.4°
9
100
HiZ
90°
10
100
-9.8
95.6°
11
98.1
-19.5
101.2°
12
95.7
-29.0
106.9°
13
92.4
-38.3
112.5°
14
88.2
-47.1
118.1°
15
83.1
-55.6
123.8°
16
77.3
-63.4
129.4°
17
70.7
-70.7
135°
18
63.4
-77.3
140.6°
19
55.6
-83.1
146.2°
20
47.1
-88.2
151.9°
21
38.3
-92.4
157.5°
22
29.0
-95.7
163.1°
23
19.5
-98.1
168.8°
24
9.8
-100
174.4°
25
HiZ
-100
180°
26
-9.8
-100
185.6°
27
-19.5
-98.1
191.2°
28
-29.0
-95.7
196.9°
29
-38.3
-92.4
202.5°
30
-47.1
-88.2
208.1°
31
-55.6
-83.1
213.8°
2
2
3
4
2
1
3
5
6
4
7
8
3
2
5
9
10
6
11
12
4
2
Resulting
electrical
angle
7
13
14
8
15
16
Doc ID 17713 Rev 1
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Power bridges
L6460
Table 25.
Internal sequencer (continued)
Typical output
current (% of IMAX)
Control mode
Half
step
Full step
(2 phases
on)
Full step
(1 phase
on)
1/4
step
1/8
step
3
5
9
17
18
10
19
20
6
3
11
21
22
12
23
24
7
4
13
25
26
14
27
28
8
4
15
29
30
16
70/139
31
Doc ID 17713 Rev 1
Resulting
electrical
angle
1/16
step
Phase A
(sin)
Phase B
(cos)
Electrical
degrees
32
-63.4
-77.3
219.4°
33
-70.7
-70.7
225°
34
-77.3
-63.4
230.6°
35
-83.1
-55.6
236.2°
36
-88.2
-47.1
241.9°
37
-92.4
-38.3
247.5°
38
-95.7
-29.0
253.1°
39
-98.1
-19.5
258.8°
40
-100
-9.8
264.4°
41
-100
HiZ
270°
42
-100
9.8
275.6°
43
-98.1
19.5
281.2°
44
-95.7
29.0
286.9°
45
-92.4
38.3
292.5°
46
-88.2
47.1
298.1°
47
-83.1
55.6
303.8°
48
-77.3
63.4
309.4°
49
-70.7
70.7
315°
50
-63.4
77.3
320.6°
51
-55.6
83.1
326.2°
52
-47.1
88.2
331.9°
53
-38.3
92.4
337.5°
54
-29.0
95.7
343.1°
55
-19.5
98.1
348.8°
56
-9.8
100
354.4°
57
HiZ
100
360°/0°
58
9.8
100
5.6°
59
19.5
98.1
11.2°
60
29.0
95.7
16.9°
61
38.3
92.4
22.5°
62
47.1
88.2
28.1°
L6460
Power bridges
Table 25.
Internal sequencer (continued)
Half
step
Full step
(2 phases
on)
Full step
(1 phase
on)
1/4
step
Resulting
electrical
angle
Typical output
current (% of IMAX)
Control mode
1/8
step
1/16
step
Phase A
(sin)
Phase B
(cos)
Electrical
degrees
32
63
55.6
83.1
33.8°
64
63.4
77.3
39.4°
The voltage spikes on Rsense could be filtered by selecting an appropriate blanking time on
the output of current sense comparator. The Blanking time selection is made by using the
StepBlkTime[1:0] bits in the StpCfg1 register.
The stepper driver off time could be programmed by means of the StepOffTime[4:0] bits in
StpCfg1 register.
Table 26.
Stepper off time
Off time
StepOffTime[4:0]
Unit
Typ
00000
2
µs
00001
4
µs
00010
6
µs
00011
8
µs
00100
10
µs
00101
12
µs
00110
14
µs
00111
16
µs
01000
18
µs
01001
20
µs
01010
22
µs
01011
24
µs
01100
26
µs
01101
28
µs
01110
30
µs
01111
32
µs
10000
34
µs
10001
36
µs
10010
38
µs
10011
40
µs
Doc ID 17713 Rev 1
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Power bridges
Table 26.
L6460
Stepper off time (continued)
Off time
StepOffTime[4:0]
Unit
Typ
10100
42
µs
10101
44
µs
10110
46
µs
10111
48
µs
11000
50
µs
11001
52
µs
11010
54
µs
11011
56
µs
11100
58
µs
11101
60
µs
11110
62
µs
11111
64
µs
By means of MixDecPhA[4:0] and MixDecPhB[4:0] in StepCfg2 register, the percentage of
off time during which each phase will stay in fast decay mode could be programmed
according to Table 28.
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Doc ID 17713 Rev 1
L6460
Power bridges
Table 27.
Stepper fast decay
MixDecPhX[4:0]
Fast decay percentage
during off time
Unit
Typ
14.1.6
00000
0
%
00001
6.25
%
00010
12.5
%
00011
18.75
%
00100
25
%
00101
31.25
%
00110
37.6
%
00111
43.75
%
01000
50
%
01001
56.25
%
01010
62.5
%
01011
68.75
%
01100
75
%
01101
81.25
%
01110
87.5
%
01111
93.75
%
1xxxx
100
%
Synchronous buck regulator configuration (Bridge 3)
Bridge 3 can be configured to be used as 2 independent synchronous buck regulators or as
a single high current synchronous buck regulator using GPIOs pins in order to close the
voltage loop. The resulting regulator(s) will implement a non linear, pulse skipping, control
loop using an internally generated PWM signal. The voltage will be set externally with a
divider network and PWM duty cycle that can be programmed in order to ensure a proper
regulation.
The regulator will be enabled/disabled using serial interface and will implement a soft start
strategy similar to that used by primary switching regulator.
Doc ID 17713 Rev 1
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Power bridges
L6460
Here after are summarized the primary features of the regulator(s):
–
Synchronous rectification
–
Automatic low side disabling when current in the inductance reaches 0 to optimize
efficiency at low load
–
Pulse skipping control
–
Internally generated PWM
–
Cycle by cycle current limiting using internal current sensor
–
Protected against load short circuit
–
Soft start circuitry
–
Under voltage signal (both continuous and latched) accessible through serial
interface.
Figure 19. Regulator block diagram
V supply
CurrentSense
Charge pump Voltage
High Side
Driver
Half Bridge OUT
La
V out
Ra
Low Side
Driver
From Central Logic
C
Bridge Sense
Control
Logic
Voltage
Loop Control
+
Vref=3V
Regulator Freq
N.C.
N.C.
GPIO USED as FB
Rb
Regulator Ref
Vref= 0.8V
SelFBRef
Obtained using spare analo g/dig ital blocks
To Central Logic
Filter
+
Under voltage
Threshold
Depending on the load current, there could be the necessity to add a Schottky diode on
output to reduce internal thermal dissipation. This diode must be placed near to the pin and
must be fast recovery and low series resistance type.
For detail about pulse skipping please refer to main switching regulator Section 13.3 on
page 54.
The output voltage will be externally set by a divider network connected on feedback pin. To
reduce as much as possible the regulation voltage error L6460 has the possibility to switch
between four regulator feedback voltage references (and, as a consequence, four under-
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L6460
Power bridges
voltage thresholds) using serial interface. The feedback reference voltage is selected by
writing the SelFBRef[1:0] bits in the Aux1SwCfg or Aux2SwCfg registers.
The switching regulators have four possible PWM duty cycles that can be changed using
SPI according to Table 28.
Table 28.
AuxXPWMTable[1:0]
Typical duty cycle value
00
10%
01
13%
Default state for AUX1
10
24%
Default state for AUX2
11
61%
Comments
Regulation loop
As seen before L6460 contains 2 regulation loops for switching regulators that are used
when bridge 3 is used as a regulator. These loops are assembled using internal
comparators and filters similar to that used in main switching regulator.
When bridge 3 is not used for this purpose or when only one regulation loop is needed, the
control loop is available on a GPIO output thus enabling the customer to assembly a basic
buck switching regulator using an external Power FET. The comparators used in the above
mentioned regulation loops are general purpose low voltage (3.3 V) comparators; when the
relative regulation loop is not used they can be accessed as shown in the Figure 20.
Figure 20. Internal comparator functional block diagram
GPIOx
GPIOy
GPIOx
DECODE
LOGIC
GPIOy
DECODE
LOGIC
-
GPIOxMode
14.1.7
PWM specification
GPIOyMode
+
V 3v3
GPIOz
GPIOz Value From SPI
GPIOzMod
e
GPIOz
DECODE
LOGIC
Doc ID 17713 Rev 1
GPIOz Logic
Driver
75/139
Power bridges
14.1.8
L6460
Battery charger or switching regulator (Bridge 4)
The functionality of this circuit is obtained by using the bridge 4 output stage. This circuit is
powered directly from VSupply and it is intended to be used as a battery charger or a
switching regulator.
The control loop block diagram is shown in the Figure 21.
Figure 21. Battery charger control loop block diagram
L6460
IREF_FB
COMP_I
VREF_FB
DIFF
AMPLI
COMP_V
PULSE SKIPPING
BURST
CONTROL LOGIC
PEAK CURRENT
MODE CONTROL
LOGIC
DC4_plus
PWM
Ilimit
BRIDGE 4
PARALLELED
POWER
STAGE
TO
LOAD
DC4_minus
FBRef
SelFBRef<1:0>
CurrRef
SelCurrRef<1:0>
The battery charger control loop implements an asynchronous switching regulator intended
to be used as a constant voltage/constant current programmable source.
When used as a simple switching regulator, it could be a system regulator depending on
startup configurations
When a system regulator under-voltage event is detected L6460 will enter in reset state
signaling this event to the microcontroller by pulling low the nRESET pin and disabling most
of its internal blocks.
When the control loop is intended to be used as a battery charger, the Aux3BatteryCharge
bit must be written in the Aux3SwCfg1 register. This is because in this case the
undervoltage event that will be sure present when charging a battery (see battery charger
profile in Figure 22) will not be considered during start up sequence.
The regulated output voltage will be externally set by a resistor divider network connected to
VREF_FB pin. L6460 has the possibility to choose between four voltage references (and, as a
consequence, four under-voltage thresholds) using the serial interface. The feedback
reference voltage selection is made by writing the SelFBRef[1:0] bits in the Aux3SwCfg1
register.
The regulation of the output current can be done externally, by using a sense resistor
connected in series on the path that provides current to the load. By using an external
differential amplifier the customer can set the desired V = f(I) characteristic, and therefore
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Doc ID 17713 Rev 1
L6460
Power bridges
the regulated current: the voltage provided at the IREF_FB pin will be compared to the
internal reference. L6460 has the possibility to choose between four voltage references
using the serial interface, writing the SelCurrRef[1:0] bits in the Aux3SwCfg1 register.
Regardless of the CurrRef voltage, if the IREF_FB pin remains below the chosen threshold,
the internal current limitation will work (typical Ilimit current 4A).
The battery charge profile can be chosen by fixing the desired CurrRef and FBRef internal
reference voltages and by choosing the desired V = f(I) trans-characteristic of the external
differential amplifier.
In the Figure 22 is shown a typical Li-Ion battery charge profile.
Figure 22. Li-ion battery charge profile
Voltage or Current
Veochrg
Blue=Battery Voltage
FBRef depending
Vchrg
Ichrg
CurrRef depending
Red=Battery Current
Iprechrg
Ieochrg
Time
Precharge
phase
Rapid charge
phase
Constant V.
phase
End Of Charge
The battery charge loop control can be used to implement a buck type switching regulator.
The regulated output voltage will be externally set by a resistor divider network connected to
VREF_FB pin, as already described and the current protection will be the one implemented
internally in the Bridge4 section.
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Power bridges
L6460
Figure 23. Simple buck regulator
L6460
IREF_FB
COMP_I
VREF_FB
COMP_V
PULSE SKIPPING
BURST
CONTROL LOGIC
PEAK CURRENT
MODE CONTROL
LOGIC
DC4_plus
PWM
Ilimit
BRIDGE 4
PARALLELED
POWER
STAGE
TO
LOAD
DC4_minus
FBRef
SelFBRef<1:0>
CurrRef
SelCurrRef<1:0>
When this control loop is intended to be used as a simple buck regulator, the proper
Aux3BatteryCharge bit must be written in the Aux3SwCfg1 register.
The regulator will also implement a soft start strategy.
When L6460 “low power mode” is enabled this regulator will be disabled.
Here after are summarized the primary features of the regulator:
–
Internal power switch.
–
Nonlinear pulse skipping control.
–
Internally generated PWM (250 KHz switching frequency).
–
Cycle by cycle current limiting using internal current sensor/ external current
sense differential amplifier.
–
Protected against load short circuit.
–
Soft start circuitry to limit inrush current flow from primary supply.
–
Under voltage signal (both continuous and latched) accessible through SPI.
–
Over temperature protection.
In pulse skipping control PWM the duty cycle must be decided by the user depending on
supply voltage and regulated voltage.
Therefore the switching regulator has 4 possible PWM duty cycles that can be changed
writing in the Aux3PWMTable[1:0] bits in the Aux3SwCfg1 register according to the
Table 31.
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L6460
Power bridges
Table 29.
Battery charger regulator controller PWM specification
Aux3PWMTable [1:0]
Typical duty cycle value
00
10%
01
13%
10
24%
11
61%
Doc ID 17713 Rev 1
Comments
Default state
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AD converter
15
L6460
AD converter
L6460 integrates and makes accessible via SPI a general purpose multi-input channel 3.3V
analog to digital converter (ADC).
The ADC can be configured to be used as:
●
8-bit resolution ADC.
●
9-bit resolution ADC.
The result of the conversion will always be a 9-bit word; the difference between the two
configurations is that, to speed up the conversion, the resolution is reduced when the ADC
is used in the 8-bit resolution mode.
The ADC is seen at software level as a 2 channel ADC with different programmable sample
times; a finite state machine will sample the requests done through the SPI interface on both
the channel and will execute them in sequence.
When used as 8-bit resolution the ADC can achieve a higher throughput and, if the minimum
sample time is used, one conversion is completed in t = 5.5 µs. When used as 9-bit
resolution ADC the circuit is slower and the minimum sample times are disabled. In that
case the conversion will be completed in a time t= 10 µs.
The use of ADC type must be decided at the start-up by writing in the one time
programmable ADC configuration register; no A/D conversion will be enabled if this register
is not set from last power-up sequence.
This ADC can be used to measure some external pins as well as some L6460’s internal
voltages. The converter is based on a cyclic architecture with an internal sample-and-hold
circuit. Sample time can be changed using serial interface to enable good measure of higher
impedance sources.
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Doc ID 17713 Rev 1
L6460
AD converter
Analog Mux
V supply
V pump
Sample Time 1
Sample Time 0
Figure 24. A2D block diagram
V3v3
VLINmain FB
VSWmain FB
VSWDRV_F
B
S&H
GPIO[0:14]
RefOpAmpX
OutStripStepperPHX
Current DAC
Conversion
Address 1
A2DType 1
A2DType 0
Conversion
Done 0
Conversion
Done 1
Conversion
Result
A2DEnable
Conversion
Address 0
Selected
A2DType
A2D
Temp Sensors
To SPI
The A2D system is enabled by setting the A2DEnable bit to ‘1’ in the A2DControl register.
The A2DType bit in the A2DConfigX registers selects the A2D active configuration (8-bit
resolution or 9-bit) according to the Table 30.
Table 30.
ADC truth table
A2DEnable
A2DType
A2D operation
0
X
Disabled
1
0
ADC working as a 8-bit ADC
1
1
ADC working as a 9-bit ADC
The multiplexer channel to be converted can be chosen by writing the A2DChannel1[4:0] or
A2DChannel2[4:0] bits in the A2DConfigX register; the channel addresses table is reported
in the Table 31.
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AD converter
Table 31.
L6460
Channel addresses
A2DChannelX[4:0] (bin.)
Converted channel
Note
00000
VSupply scaled
See voltage divider specification.
00001
VSupplyInt scaled
See voltage divider specification.
00010
Vref_2_5V
00011
Temp Sensor1
Temperature sensor1
00100
Temp Sensor2
Temperature sensor2
00101
V3v3 scaled
See voltage divider specification.
0011X
Not used
01000
Not used
01001
GPIO[0]
01010
GPIO[1]
01011
GPIO[2]
01100
GPIO[3]
01101
GPIO[4]
01110
GPIO[5]
01111
GPIO[6]
10000
GPIO[7]
10001
GPIO[8] clamp
10010
GPIO[9]
10011
GPIO[10]
10100
GPIO[11]
10101
GPIO[12]
10110
GPIO[13]
10111
GPIO[14]
11000
MuxRefOpAmp1
11001
MuxRefOpAmp2
11010
OutStripStepperPhA
11011
OutStripStepperPhB
11100
Not used
11101
ST reserved
References AUX1 switching reg.
11110
ST reserved
0.8V reference voltage
11111
ST reserved
1.65V reference voltage
See current DAC circuit
The sample time can be changed by modifying the A2DSampleX[2:0] bits in the
A2DConfigX register; depending on which is the A2DType bit, the available sample times
are reported in Table 32 and Table 33.
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L6460
AD converter
Table 32.
ADC sample times when working as a 8-bit ADC
Sample time
A2DSampleX[2:0] (binary)
Table 33.
Typ
Unit
000
16*Tosc
µs
001
32*Tosc
µs
010
64*Tosc
µs
011
128*Tosc
µs
100
256*Tosc
µs
101
512*Tosc
µs
110
1024*Tosc
µs
111
2048*Tosc
µs
ADC sample time when working as a 9-bit ADC
Sample time
A2DSampleX[2:0] (binary)
Typ
Unit
000
32*Tosc
µs
001
64*Tosc
µs
010
128*Tosc
µs
011
256*Tosc
µs
100
512*Tosc
µs
101
1024*Tosc
µs
110
2048*Tosc
µs
111
4096*Tosc
µs
A conversion on channel 1 can be triggered by writing a logic ‘1’ in the A2DTrig1 bit in the
A2DConfigX register and a conversion on channel 2 can be triggered writing a logic ‘1’ in the
A2DTrig2 bit in the same register. While a request on a channel is pending but not yet
completed L6460 will force to logic ‘0’ the corresponding A2DdoneX bit in the A2DResultX
registers and L6460 will not accept other conversion request on that channel.
Continuous conversion on one channel can be accomplished by setting to logic ‘1’ the
A2DcontinuousX bit in the A2DConfigX register. When A2DcontinuousX bit is set, other
conversions can be accomplished on the other channel; these conversions will be inserted
between two conversions of the other channel and the end of the conversion will be signaled
using A2DdoneX bit. Of course when a channel is in continuous mode its sample time and
channel address cannot be changed.
Continuous conversions on both 2 channels can be also accomplished by setting to logic ‘1’
the A2Dcontinuous1 and A2Dcontinuous2 bits; the conversions are made in sequence.
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AD converter
15.1
L6460
Voltage divider specifications
As can be seen in the A2D block diagram, in order to report some voltages in the A2D
working range, they are scaled with a resistor divider before the conversion.
Here below are reported the resistor voltage divider specifications:
Table 34.
Parameter
RSupply_ratio
Voltage divider specification
Description
VSupply divider ratio
RSupplyInt_ratio VSupply Int divider ratio
RV3V3_ratio
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V3v3 divider ratio
Doc ID 17713 Rev 1
Notes
Min
Typ
Max
-
1/15
-
-
1/15
-
-
1/2
-
Unit
L6460
16
Current DAC circuit
Current DAC circuit
L6460 includes a multiple range 6-bit current sink DAC. The LSB value of this DAC can be
selected using the DacRange[1:0] bits in the CurrDacCtrl register.
The output of this circuit is connected to GPIO[8] that is a 5 V tolerant pin. The value of this
pin can be converted using ADC. The pin value can be scaled before being converted by
enabling the internal resistor divider connected to this pin. If the current sunk by resistor
divider is not acceptable the pin voltage can be converted without scaling its value. When
the conversion without scaling resistor is chosen a clamping connection is used to avoid
voltage compatibility of the pin to the ADC system. The clamping circuit will sink a typical
current of half microampere from the pin during the sampling time.
Figure 25. Current DAC block diagram
Va3
Reference Current
Generator
DacRange [1:0]
EnDac
Current Sink
DAC
DacValue[5:0]
DacRange[1:0]
Gpio[8]
RCurrDac
Clamp circuit
Gpio8 Clamp
(to ADC)
EnDac
A2DChannel1: [40] Combinatorial
Address
Recognized
Mask
A2DChannel2: [40] Combinatorial
Address
Recognized
Mask
EnDacScale
Gpio[8] Digital Driver
The circuit is enabled by setting to logic ‘1’ the EnDac bit in the CurrDacCtrl register then the
desired sunk current value is chosen by changing the value of the DacValue[5:0] bits in the
same register being DacValue[0] the least significant bit and DacValue[5] the most
significant bit.
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Current DAC circuit
L6460
The current DAC has three possible current ranges that can be selected using the
DacRange[1:0] bits in the CurrDacCtrl register. The DAC range selection table is shown in
Table 35.
Table 35.
Current DAC truth table
DacRange[1]
DacRange[0]
LSB typical current
ILSB typ
Full scale typical
current IFULL typ
0
0
Disabled
Disabled
0
1
10 µA
0.63 mA
1
0
100 µA
6.3 mA
1
1
1 mA
63 mA
By changing LSB current value, all steps will change following this relation:
Istep(N) = N * ILSB
where N is the value of DacValue[5:0] bits.
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L6460
17
Operational amplifiers
Operational amplifiers
L6460 contains two rail to rail output, high bandwidth internally compensated operational
amplifiers supplied by VGPIO_SPI pin. The operative supply range is 3.3 V ± 4.5%
Each operational amplifier can have all pin accessible or, to save pins, can be internally
configured as a buffer. They can also be used as comparators; to do that the user must
disable internal compensation by writing a logic level “1” in the OpXCompMode bit in the
OpAmpXCtrl register.
in Figure 26 are reported the block diagrams of the two operational amplifiers.
Figure 26. Configurable 3.3 V operational amplifiers
GPIO[11]
Op1Ref[1:0]
Op1EnIntRef
Op1PlusRef
V GPIO_SPI
Op1EnPlusPin
Op1CompMode
To A/D System
GPIO[9]
+
OpAmp 1
-
GPIO[10]
EnOp1
EnOp2
Op1BufConf
Op1EnMinusPin
Op2BufConf
Op2EnMinusPin
+-
GPIO[13]
+-
GPIO[12]
Op2CompMode
Op2EnPlusPin
V GPIO_SPI
Op2PlusRef
Op2EnIntRef
Op2Ref[1:0]
GPIO[14]
Note:
Op1EnPlusRef and Op2EnPlusRef cannot be used to drive external pin so the user must be
sure not to enable the path between one of these voltage references and the external pin.
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Operational amplifiers
L6460
The operational amplifiers are capable to drive a capacitive load in buffer configuration up to
a maximum of 100 pF; for higher capacitance it is necessary to add resistive loads to
increase the OP output current, and/or to add a low resistor (10 Ω) in series to the load
capacitance.
To use the operational amplifiers as comparators the user must disable internal
compensation writing a logic one in the OpXDisComp bit in the OpAmpXCtrl register.
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L6460
Low voltage power switches
Low voltage power switches are analog switches designed to operate from a single +2.4 V
to +3.6 V VGPIO_SPI supply. They are intended to provide and remove power supply to low
voltage devices. When switched on, they connect the VGPIO_SPI pin to their output pin
(GPIO[6] for low voltage power switch 1 or GPIO[7] for low voltage power switch 2) thus
powering the device connected to it. The turning on and off of each switch can be controlled
through serial interface.
L6460 provides 2 low voltage power switches, each of them has current limitation to
minimum 150mA to limit inrush current when charging a capacitive load. When the limit
current has been reached, for more than a Tfilter time, then a flag is activated; this flag is
latched in the central logic and can be cleared by the firmware. Please note that, in case of
capacitive load, the current limit is reached the first time the low power switch is turned on:
therefore the user will find a limit flag that must be cleared.
The 2 low voltage power switches can be externally paralleled to obtain a single super low
voltage power switch. Low voltage pass switches sink current needed for their functionality
from pin VGPIO_SPI, they never inject current on this pin.
Figure 27. Low power switch block diagram
V GPIO_SPI
EnLowVSw[x]
LowVSwIlim[x]
To SPI
Driving
Circuit
18
Low voltage power switches
GPIO[6] (LPS 1)
or
GPIO[7] (LPS 2)
Current
Limit
Sensor
GPIO[6]/GPIO[7]
Driver
S
LowVSwIlimLth[x]
R
ClrLowVrSwLth
Reset State
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General purpose PWM
19
L6460
General purpose PWM
L6460 includes three general purpose PWM generators that can be redirected on GPIO
pins (see Chapter 22). Two of these generators (Aux_PWM_1 and Aux_PWM_2) work with
a fixed period FOSC/512 and have a programmable duty cycle; the other one (GP_PWM)
has a programmable base time clock and a programmable time for both high and low levels.
19.1
General purpose PWM generators 1 and 2 (AuxPwm1 and
AuxPwm2)
The Duty cycle of these PWM generators can be changed by writing the AuxPwmXCtrl bits
(where X can be 1 or 2) in the AuxPwm1Ctrl and AuxPwm2Ctrl registers. Their positive duty
cycle will change according to the equation:
PWM_X_DUTY = AuxPwmXCtrl [ 9:0 ]/512
According to this equation a programmed “0” value will cause a 0% duty cycle (output
always at logic level 0).
19.2
Programmable PWM generator (GpPwm)
GpPWM has a programmable base clock that can be changed by programming the
GpPwmBase[6:0] bits in the GpPwmBase register. The clock will change according to the
equation:
PWM_BASE_PERIOD = ( GpPwmBase [ 6:0 ] + 1 ) × Tosc
The high and low level duration (expressed in base clock periods), can be programmed
writing the GpPwmHigh[7:0] and GpPwmLow[7:0] bits in the GpPwmCtrl register so they will
change according to following equations:
High_level_Time = GpPwmHigh [ 7:0 ] × PWM_BASE_PERIOD
Low_level_Time = GpPwmLow [ 7:0 ] × PWM_BASE_PERIOD
The resulting period of the PWM will be:
Period = ( GpPwmHigh [ 7:0 ] + GpPwmLow [ 7:0 ] ) + PWM_BASE_PERIOD
and the positive duty cycle will result:
High_level_Time
GpPwmHigh [ 7:0 ]
- = -------------------------------------------------------------------------------------------------------DutyCycle = ---------------------------------------------------------------------------------------------High_level_Time + Low_level_Time
GpPwmHigh [ 7:0 ] + GpPwmLow [ 7:0 ]
A programmed value of 0 in GpPwmHigh[7:0] and GpPwmLow[7:0] bits will force the PWM
generator output to be always at logic level “0”.
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Doc ID 17713 Rev 1
L6460
Interrupt controller
L6460 contains one programmable interrupt controller that can be used to advice the
firmware, through the serial interface, when a certain event happens inside the IC. The
output of the interrupt circuit can be also redirected on a GPIO pin therefore the event can
be signaled directly to the external circuits.
Figure 28. Interrupt controller diagram
IntCtrlAutoDisable
EnIntCtrlPulse
Pulse
Generator
To Gpio
EnIntCtrl
EnIntCtrlPulse
Enable signals
Disable Pulse DisableSignals
Generation
logic
IntCtrlPolarity
Monitored signals
DisableMonitor
Decode logic
20
Interrupt controller
The Table 36 contains the events that can be monitored by the interrupt controller.
Table 36.
Interrupt controller event
Event
Event description
Mtr1Fault
Bridge 1 fault (Ilimit event)
Mtr2Fault
Bridge 2 fault (Ilimit event)
Mtr3Fault
Bridge 3 fault (Ilimit event)
Mtr4Fault
Bridge 4 fault (Ilimit event)
nAWAKE
nAWAKE pin low
SwRegCtrl Ilimit
Switching regulator controller Ilimit event.
VMainSW Ilimit
Main switching regulator Ilimit event.
LowPowSw 1
Low voltage power switch 1 Ilimit event.
LowPowSw 2
Low voltage power switch 2 Ilimit event
Warm
Notes
Warming event
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Interrupt controller
L6460
Table 36.
Interrupt controller event (continued)
Event
WDWarn
WD
DigCmp
Event description
Notes
Watch dog warning event
Watch dog event
Digital comparator
ADCDone1
ADC conversion done 1
(1)
ADCDone2
ADC conversion done 2
(1)
Vloop1Ilim
AUX1 Ilimit event.
1. This event is disabled if the related ADC channel is configured in continuous mode.
Any event detection can be enabled and disabled by setting at logic level 1 the relative
enable bit in the interrupt controller configuration register (IntCrtlCfg).
The interrupt controller can be programmed to give a pulse when a monitored event
happens or to continuously maintaining the output active until the interrupt condition is
finished.
When programmed to signal the enabled events by giving pulses, the interrupt controller can
be configured to disable the event that caused the interrupt request until the firmware reenables it writing the relative bit in the control register (IntCrtlCtrl) or to continue to monitor
the event.
The GPIO output of this circuit can be programmed to be active high or active low.
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L6460
21
Digital comparator
Digital comparator
L6460 includes one digital comparator that can be used to signal, through serial interface,
that a channel converted by the ADC is greater, greater-equal, lesser, lesser equal, or equal
than a fixed value set by serial interface or than the value converted by the other ADC
channel.
This circuit can be used to monitor the temperature of the IC advising the firmware when it
reaches a certain value decided by the firmware by setting one ADC channel to do
continuous conversions of the temperature sensor.
The circuit operation can be enabled or disabled changing the EnDigCmp bit in the
configuration register DigCmpCfg. By setting the DigCmpUpdate[1:0] bits in the
configuration register, the comparator can be programmed to update its output in one of the
following ways:
●
DigCmpUpdate[1:0]=00
–
●
DigCmpUpdate[1:0]=01
–
●
Each time a conversion is performed on ADC channel 0.
DigCmpUpdate[1:0]=10
–
●
Continuously (each clock).
Each time a conversion is performed on ADC channel 1.
DigCmpUpdate[1:0]=11
–
ADC state machine driven.
When the last option is selected, the digital comparator will update its output in two different
ways depending on the configuration of the ADC converter. If ADC converter is configured to
do continuous conversions on both channels, the output of the comparator will be updated
when the double conversion is completed. If ADC converter is not configured to do
continuous conversions on both channels, the output of the comparator will be updated each
time a conversion is completed.
The comparator output can be digitally filtered so that the programmed condition has to be
found for three consecutive checks before to be signaled.
The Figure 29 shows the block diagram of digital comparator.
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Digital comparator
L6460
Figure 29. Digital comparator block diagram
DigCmpValue[9:0]
ADC FSM
Update
Signal
A2DDone1
Logic ‘1’
A2DDone0
DigCmpSelCh0[1]
DigCmpUpdate[1:0]
A2DResult0[8:0]
Three check
s
filter
A2DResult1[8:0]
DigCmpSelCh0[0]
CmpOut
Data0[9:0]
DigCmpSelCh1[0]
COMPARATOR
SelCmpType[1:0]
EnDigCmp
Data1 [9:0]
DigCmpSelCh1[1]
In Table 37 is reported the comparison type truth table.
Table 37.
Comparison type truth table
EnDigCmp
SelCmpType[1]
SelCmpType[0]
Comparison type
0
X
X
Disabled
1
0
0
Data0[9:0] ≤1³1÷Data1[9:0]
1
0
1
Data0[9:0] = Data1[9:0]
1
1
0
Data0[9:0] > Data1[9:0]
1
1
1
Data0[9:0] ≤= Data1[9:0]
In Table 38 is reported the Data0/Data1 selection truth table.
Table 38.
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DataX selection truth table
DigCmpSelChX[1]
DigCmpSelChX[0]
DataX[9:0]
0
X
DigCmpValue[9:0]
1
0
A2DResult1[8:0]
1
1
A2DResult1[8:0]
Doc ID 17713 Rev 1
L6460
22
GPIO pins
GPIO pins
Some of the pins of L6460 are indicated as GPIO (General purpose I/O). These pins can be
configured to be used in different ways depending on customer application. All GPIOs can
be used as digital input/output pins with digital value settable/readable using serial interface
or as analog input pins that can be converted using the A2D system. Some of the pins can
be used for special purposes: i.e. two of them can be used to access to the pass switch
function, other two are used as feedback pins for the auxiliary synchronous switching
regulators.
All input Schmitt triggers and output circuitry used for start-up purposes are powered by the
internally generated V3v3, while the digital output buffers are powered by VGPIO_SPI pin. To
ensure independency between V3v3 and VGPIO_SPI the GPIOs output drivers are open-drain
driver or the high side MOS is in back-to-back configuration to avoid the presence of the
body diode between output and supply.
All digital output signals can be inverted before being provided on the relative GPIO pins.
Here below is reported the table with GPIO functions.
Table 39.
GPIO functions description
Function(1)
Pin
Name
Input
Output
Notes
Special
Analog
Digital
Analog
Digital
- SPI IN
- SPI OUT
- Interrupt ctrl.
- AuxPwm1
- AuxPwm2
Start-up
Open drain
configuration
output
pin
Open drain
output
GPIO[0]
- ADC input
GPIO[1]
- ADC input
- Comp1 In- Vaux1 F.B.
- SPI IN
- SPI OUT
- Interrupt ctrl.
- AuxPwm1
- AuxPwm2
GPIO[2]
- ADC input
- Comp2 In- Vaux2 F.B.
- SPI IN
- IN PWM
- SPI OUT
- Interrupt ctrl.
- AuxPwm2
- AuxPwm3
Open drain
output
- SPI IN
- SPI OUT
- AuxPwm2
- AuxGpPwm3
Start-up
Open drain
configuration
output
pin
- SPI IN
- SPI OUT
- Interrupt ctrl.
- AuxPwm1
- AuxPwm3
Start-up
configuration Open drain
output
pin
- SPI IN
- SPI OUT
- Reg. loop 1
- Comp1 out
- AuxPwm3
Full driver BB
Slave Control powered by
V3v3
GPIO[3]
GPIO[4]
GPIO[5]
- ADC input
- ADC input
- ADC input
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GPIO pins
Table 39.
L6460
GPIO functions description (continued)
Function(1)
Pin
Name
Input
GPIO[7]
Notes
Special
Analog
GPIO[6]
Output
- ADC input
- ADC input
Digital
- SPI IN
- SPI IN
- SPI IN(2)
GPIO[8]
- ADC input
GPIO[9]
- SPI IN
- ADC input
- ID 1
- OpAmp1 in+
- IN PWM
Analog
Digital
- Low Pow Sw 1
- SPI OUT
- A2DGpo
- AuxPwm2
- Comp2 out
Full driver
connected to
VGPIO_SPI
- Low Pow Sw 2
- SPI OUT
- AuxPwm1
- AuxPwm3
- Comp1 out
Full driver
connected to
VGPIO_SPI
- CurrDAC
- SPI OUT
- AuxPwm1
- AuxPwm3
- Comp2 out
5 volt input
tolerant
Open drain
output
- SPI OUT
- Interrupt contr.
- AuxPwm1
- Reg. loop 3
Full driver
connected to
VGPIO_SPI
- SPI OUT
- Interrupt ctrl.
- AuxPwm2
- AuxPwm3
Full driver
connected to
VGPIO_SPI
- SPI OUT
- A2DGpo
- AuxPwm1
- AuxPwm2
Full driver
connected to
VGPIO_SPI
- SPI OUT
- Interrupt ctrl
- Comp2 out
- Reg. loop 2
Full driver BB
(can be
powered by
V3v3 with a
metal change)
- ADC input
GPIO[13]
- SPI IN
- OpAmp2 in-
- SPI OUT
- AuxPwm1
- Reg. loop 3
- AuxPwm3
Full driver
connected to
VGPIO_SPI
GPIO[14] - ADC input
- SPI OUT
- Interrupt ctrl.
- AuxPwm2
- AuxPwm3
Full driver
connected to
VGPIO_SPI
- SPI IN
- ADC input
GPIO[10]
- ID 2
- OpAmp1 in- IN PWM
GPIO[11] - ADC input
GPIO[12]
- SPI IN
- IN PWM
- OpAmp1 Out
- ADC input
- SPI IN
- OpAmp2 in+ - STEP_REQ
- SPI IN
- OpAmp2 Out
1. In this table are used the abbreviations of the following In Table 40.
2. GPIO[8] input Schmitt trigger is disabled by default (after a reset) to be able to read the digital value from this pin it needs
to be enabled writing a logic ‘1’ in the EnGpio8DigIn in CurrDacCtrl register.
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Doc ID 17713 Rev 1
L6460
GPIO pins
Table 40.
Abbreviations
Abbreviation
ADC input
Meaning
Input to the ADC system.
SPI IN
Digital state of this pin is readable through SPI.
SPI OUT
Digital state of this pin can be set through SPI.
BB
Back to back high side driver.
Comp1 IN -
This pin can be used as minus input for comparator 1.
Comp2 IN -
This pin can be used as minus input for comparator 2.
Vaux1 FB
This pin can be used as feedback input for AUX1 regulator obtained by
using bridge 3.
A2DGpo
This pin can be used to carry out the A2DGpo value related to the ADC
conversion L6460 is doing.
Reg. Loop 3
This pin can be used as output of the regulation loop used by AUX3
regulator obtained by using bridge 4.
STEP_REQ
This pin can be used to request a stepper sequencer evolution step.
Interrupt Ctrl
This pin can be used to carry out the interrupt controller circuit output.
Vaux2 FB
This pin can be used as feedback pin by AUX2 regulator obtained by using
bridge 3
IN PWM
This pin can be used to provide an external PWM to bridges.
Reg. Loop 1
This pin can be used as output of the regulation loop used by AUX1
regulator.
Comp1 OUT
This pin can be used as output of the comparator 1.
AuxPwm1
Low Volt. Pow. Sw. 1
This pin can be used to carry out the PWM generated by AuxPwm1 circuit.
This pin can be used as output of low voltage power switch 1.
Reg. Loop 2
This pin can be used as output of the regulation loop used by AUX2
regulator.
Comp2 OUT
This pin can be used as output of the comparator 2.
AuxPwm2
Low Volt. Pow. Sw. 2
Reg. Loop 3
This pin can be used to carry out the PWM generated by AuxPwm2 circuit.
This pin can be used as output of low voltage power switch 2.
This pin can be used as output of the regulation loop used by AUX3
regulator.
AuxPwm3
This pin can be used to carry out the PWM generated by AuxPwm3 circuit.
CurrDAC
This pin can be used to carry out the output of the current DAC circuit.
AuxPwm4
This pin can be used to carry out the PWM generated by AuxPwm4 circuit.
OpAmp1 in+
This pin can be used as operational amplifier 1 non-inverting input.
OpAmp1 in-
This pin can be used as operational amplifier 1 inverting input.
OpAmp1 Out
This pin can be used as operational amplifier 1 output.
OpAmp2 in+
This pin can be used as operational amplifier 2 non-inverting input.
OpAmp2 in-
This pin can be used as operational amplifier 2 inverting input.
Doc ID 17713 Rev 1
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GPIO pins
L6460
Table 40.
Abbreviations (continued)
Abbreviation
OpAmp2 Out
Meaning
This pin can be used as operational amplifier 2 output.
ID 1
This pin is used to determine the SPI ID1 bit value.
ID 2
This pin is used to determine the SPI ID2 bit value.
Slave Control
This pin is used as slave control when the IC is configured as master.
Hereafter are reported the detailed specifications for each GPIO.
To enable the functionality of the GPIO as output pin, the relative GpioOutEnable[14:0] bit
must be enabled in GpioOutEnable register.
Each GPIO could be configured by setting the appropriate GpioXMode[2:0] in the GpioCtrlX
register.
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Doc ID 17713 Rev 1
L6460
22.1
GPIO pins
GPIO[0]
The GPIO[0] truth table is (for the abbreviation list please refer to Table 40).
Table 41.
GPIO[0] truth table
GPIO[0] SPI BITS
State at
StartUp
Function
Note
X
Detection of StartUp config
See
Chapter 8
X
X
HiZ (SPI_IN)
0
0
0
SPI OUT
(1)
1
0
0
1
InterruptCtrl
(1)
0
1
0
1
0
AuxPwm1
(1)
0
1
0
1
1
AuxPwm2
(1)
0
1
1
0
0
SPI OUT inverted
(1)
0
1
1
0
1
InterruptCtrl inverted
(1)
0
1
1
1
0
AuxPwm1 inverted
(1)
0
1
1
1
1
AuxPwm2 inverted
(1)
GpioOut
Enable [0]
Mode[2]
Mode[1]
Mode[0]
1
X
X
X
0
0
X
0
1
0
1. In all configurations in which GPIO[0] is enabled as output:
a) the GPIO[0] pin can be always used as an analog input to the ADC system (ADC function) by writing its
address in the A2DChannelX[4:0] in the A2DConfigX register and starting a conversion;
b) the GPIO[0] pin can be always used as a digital input so its value can be always read through SPI
interface (SPI_IN function);
c) the GPIO[0] pin is an open drain output.
Doc ID 17713 Rev 1
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GPIO pins
L6460
Figure 30. GPIO[0] block diagram
V 3v3
To Serial Interface
To ADC
V 3v3
To Control Logic
Start-up pin State
Detect circuit
V 3v3
From Serial
Interface
Logic Decode
EnStartUpDtc
From Power Up
FSM
100/139
V 3v3
GPIO[0] Driver
Doc ID 17713 Rev 1
GPIO[0]
L6460
22.2
GPIO pins
GPIO[1]
The GPIO[1] truth table is (for the abbreviation list please refer to Table 40).
Table 42.
GPIO[1] truth table
AUX1Enable
or
AUX1System
GPIO[1] SPI BITS
Function
Note
X
AUX1 FB
(1)
X
X
HiZ (SPI_IN)
1
X
X
Comp1 IN -
(2)
1
0
0
0
SPI OUT
(2)
0
1
0
0
1
AuxPwm1
(2)
0
1
0
1
0
AuxPwm2
(2)
0
1
0
1
1
InterruptCtrl
(2)
0
1
1
0
0
SPI OUT inverted
(2)
0
1
1
0
1
AuxPwm1 inverted
(2)
0
1
1
1
0
AuxPwm2inverted
(2)
0
1
1
1
1
IntCtrlinverted
(2)
GpioOut
Enable [1]
Mode[2]
Mode[1]
Mode[0]
1
X
X
X
0
0
0
0
0
0
1. AUX1Enable or AUX1System bit =1 represent the case in which AUX1 is used as a system or not system
regulator.
2. In all configurations in which GPIO[1] is enabled as output:
a) the GPIO[1] pin can be always used as an analog input to the ADC system (ADC function) by writing
its address in the A2DChannelX[4:0] in the A2DConfigX register and starting a conversion;
b) the GPIO[1] pin can be always used as a digital input so its value can be always read through SPI
interface (SPI_IN function);
c) the GPIO[1] pin is an open drain output.
Doc ID 17713 Rev 1
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GPIO pins
L6460
Figure 31. GPIO[1] block diagram
V 3v3
To Serial Interface
To ADC
To AUX1 Feedback
comparator
GPIO[1]
V 3v3
From Serial
Interface
V 3v3
Logic Decode
Gpio[1] Driver
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Doc ID 17713 Rev 1
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22.3
GPIO pins
GPIO[2]
The GPIO[2] truth table is (for the abbreviation list please refer to Table 40).
Table 43.
GPIO[2] truth table
AUX2Enable
or
AUX2System
GPIO[1] SPI BITS
Function
Note
X
AUX2 FB
(1)
X
X
HiZ (SPI_IN)
1
X
X
Comp1 IN -
(2)
1
0
0
0
SPI OUT
(2)
0
1
0
0
1
AuxPwm2
(2)
0
1
0
1
0
AuxPwm3
(2)
0
1
0
1
1
InterruptCtrl
(2)
0
1
1
0
0
SPI OUT inverted
(2)
0
1
1
0
1
AuxPwm2 inverted
(2)
0
1
1
1
0
AuxPwm3 inverted
(2)
0
1
1
1
1
IntCtrlinverted
(2)
GpioOut
Enable [1]
Mode[2]
Mode[1]
Mode[0]
1
X
X
X
0
0
0
0
0
0
1. AUX2Enable or AUX2System bit =1 represent the case in which AUX1 is used as a System or Not System
regulator.
2. In all configurations in which GPIO[2] is enabled as output:
a) the GPIO[2] pin can be always used as an analog input to the ADC system (ADC function) by writing
its address in the A2DChannelX[4:0] in the A2DConfigX register and starting a conversion;
b) the GPIO[2] pin can be always used as a digital input so its value can be always read through SPI
interface (SPI_IN function);
c) please note that GPIO[2] output is directly connected to ExtPWM3 input for Bridge 3 or 4 and therefore
particular care must be taken in order to avoid wrong PWM signals when ExtPWM3 is selected for
bridge 3 or 4;
d) the GPIO[2] pin is an open drain output.
Doc ID 17713 Rev 1
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GPIO pins
L6460
Figure 32. GPIO[2] block diagram
To ExtPWM3
V 3v3
To Serial Interface
To ADC
To AUX2 Feedback
comparator
GPIO[2]
V 3v3
From Serial
Interface
V 3v3
Logic Decode
Gpio[2] Driver
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Doc ID 17713 Rev 1
L6460
22.4
GPIO pins
GPIO[3]
The GPIO[3] truth table is (for the abbreviation list please refer to Table 40).
Table 44.
GPIO[3] truth table
GPIO[3] SPI BITS
State at
StartUp
Function
Note
X
Detection of StartUp config
See
Chapter 8
X
X
HiZ (SPI_IN)
0
0
0
SPI OUT
(1)
1
0
0
1
AuxPwm1
(1)
0
1
0
1
0
AuxPwm2
(1)
0
1
0
1
1
AuxPwm2
(1)
0
1
1
0
0
SPI OUT inverted
(1)
0
1
1
0
1
AuxPwm1 inverted
(1)
0
1
1
1
0
AuxPwm2 inverted
(1)
0
1
1
1
1
AuxPwm3 inverted
(1)
GpioOut
Enable [3]
Mode[2]
1
X
X
X
0
0
X
0
1
0
Mode[1] Mode[0]
1. In all configurations in which GPIO[3] is enabled as output:
a) the GPIO[3] pin can be always used as an analog input to the ADC system (ADC function) by writing its
address in the A2DChannelX[4:0] in the A2DConfigX register and starting a conversion;
b) the GPIO[3] pin can be always used as a digital input so its value can be always read through SPI
interface (SPI_IN function);
c) the GPIO[3] pin is an open drain output.
Doc ID 17713 Rev 1
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GPIO pins
L6460
Figure 33. GPIO[3] block diagram
V 3v3
To Serial Interface
To ADC
V 3v3
Start-up pin State
Detect circuit
To Control Logic
GPIO[3]
V 3v3
V 3v3
From Serial
Interface
Logic Decode
EnStartUpDtc
From Power Up
FSM
106/139
Gpio[3] Driver
Doc ID 17713 Rev 1
L6460
22.5
GPIO pins
GPIO[4]
The GPIO[4] truth table is (for the abbreviation list please refer to Table 40).
Table 45.
GPIO[4] truth table
GPIO[4] SPI BITS
State at
StartUp
Function
Note
X
Detection of StartUp config
See
Chapter 8
X
X
HiZ (SPI_IN)
0
0
0
SPI OUT
(1)
1
0
0
1
Interrupt Ctrl
(1)
0
1
0
1
0
AuxPwm1
(1)
0
1
0
1
1
AuxPwm3
(1)
0
1
1
0
0
SPI OUT inverted
(1)
0
1
1
0
1
Interrupt Ctrl
(1)
0
1
1
1
0
AuxPwm1 inverted
(1)
0
1
1
1
1
AuxPwm3 inverted
(1)
GpioOut
Enable [4]
Mode[2]
Mode[1]
Mode[0]
1
X
X
X
0
0
X
0
1
0
1. In all configurations in which GPIO[4] is enabled as output:
a) the GPIO[4] pin can be always used as an analog input to the ADC system (ADC function) by writing its
address in the A2DChannelX[4:0] in the A2DConfigX register and starting a conversion;
b) the GPIO[4] pin can be always used as a digital input so its value can be always read through SPI
interface (SPI_IN function);
c) the GPIO[4] pin is an open drain output.
Doc ID 17713 Rev 1
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GPIO pins
L6460
Figure 34. GPIO[4] block diagram
V 3v3
To Serial Interface
To ADC
V 3v3
Start-up pin State
Detect circuit
To Control Logic
V 3v3
V 3v3
From Serial
Interface
Logic Decode
EnStartUpDtc
From PowerUp
FSM
108/139
Gpio[4] Driver
Doc ID 17713 Rev 1
GPIO[4]
L6460
22.6
GPIO pins
GPIO[5]
The GPIO[5] truth table is (for the abbreviation list please refer to Table 40).
Table 46.
GPIO[5] truth table
AUX1
system
Master(1)
and
Vloop1
external(2)
GPIO[5] SPI BITS
GpioOut
enable[5]
Function
Note
Mode[2] Mode[1] Mode[0]
1
X
X
X
X
X
Slave control
0
1
X
X
X
X
Reg Loop1 OUT
0
0
0
X
X
X
HiZ (SPI_IN)
0
0
1
0
0
0
SPI OUT
(3)
0
0
1
0
0
1
Comp1OUT
(3)
0
0
1
0
1
0
Reg Loop1 OUT
(3)
0
0
1
0
1
1
AuxPwm3
(3)
0
0
1
1
0
0
SPI OUT inverted
(3)
0
0
1
1
0
1
Comp1OUT inverted
(3)
0
0
1
1
1
0
Reg Loop1 OUT
inverted
(3)
0
0
1
1
1
1
AuxPwm3 inverted
(3)
(3)
1. Master bit is at logic level “1” when L6460 is used as a master device (seeChapter 8)
2. This bit is at logic level “1” if AUX1 regulator is a system regulator but its power stage is externally realized
(and therefore the regulation loop is not used to drive bridge 3). In this case Vloop1IsSys bit will be at logic
level “1”, while Vloop1OnMtr3SideA and Vloop1OnMtr3SideB bits will be at logic level “0” in
CoreConfigReg register.
3. In all configurations in which GPIO[5] is enabled as output:
a) the GPIO[5] pin can be always used as an analog input to the ADC system (ADC function) by writing its
address in the A2DChannelX[4:0] in the A2DConfigX register and starting a conversion;
b) the GPIO[5] pin can be always used as a digital input so its value can be always read through SPI
interface (SPI_IN function);
c) the GPIO[5] pin is a rail to rail, back to back output supplied by V3v3.
Doc ID 17713 Rev 1
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GPIO pins
L6460
Figure 35. GPIO[5] block diagram
To internal Logic & SPI
V 3v3
To ADC
V 3V3
V 3v3
From Control
logic
GPIO[5]
Logic Decode
Back to Back
Driver
110/139
Doc ID 17713 Rev 1
L6460
22.7
GPIO pins
GPIO[6]
The GPIO[6] truth table is (for the abbreviation list please refer to Table 40):
Table 47.
GPIO[6] truth table
GPIO[6] SPI BITS
StdByMode
AEnLow
VSw[1]
GpioOut
Mode[2] Mode[1] Mode[0]
enable[6]
Function
Note
1
X
X
X
X
X
Low Volt. Pow. Sw. 1
0
1
X
X
X
X
Low Volt. Pow. Sw. 1
0
0
0
X
X
X
HiZ (SPI_IN)
0
0
1
0
0
0
SPI OUT
(2)
0
0
1
0
0
1
A2DGpo
(2)
0
0
1
0
1
0
AuxPwm2
(2)
0
0
1
0
1
1
Comp2OUT
(2)
0
0
1
1
0
0
A2DGpo inverted
(2)
0
0
1
1
0
1
AuxGpPwm2 inverted
(2)
0
0
1
1
1
1
Comp2OUT inverted
(2)
(1)
1. When EnLowVSw[1]= ‘1’ the GpioOutEnable[6] bit is forced to 0.
2. In all configurations in which GPIO[6] is enabled as output:
a) the GPIO[6] pin can be always used as an analog input to the ADC system (ADC function) by writing its
address in the A2DChannelX[4:0] in the A2DConfigX register and starting a conversion;
b) the GPIO[6] pin can be always used as a digital input so its value can be always read through SPI
interface (SPI_IN function);
c) the GPIO[6] pin is a rail to rail output supplied by VGPIO_SPI.
Doc ID 17713 Rev 1
111/139
GPIO pins
L6460
Figure 36. GPIO[6] block diagram
V GPIO_SPI
Power Switch 1
To internal
Logic & SPI
V 3v3
V 3v3
From Serial
Interface
EnPass1
To ADC
V 3v3
GPIO[6]
Logic Decode
Stand By mode
Gpio[6] Driver
112/139
Doc ID 17713 Rev 1
L6460
22.8
GPIO pins
GPIO[7]
The GPIO[7] truth table is (for the abbreviation list please refer to Table 40).
Table 48.
GPIO[7] truth table
GPIO[7] SPI BITS
EnLowVSw[2]
GpioOut
enable[7]
Function
Note
(1)
Mode[2] Mode[1] Mode[0]
1
X
X
X
X
Low Volt. Pow. Sw. 2
0
0
X
X
X
HiZ (SPI_IN)
0
1
0
0
0
SPI OUT
(2)
0
1
0
0
1
AuxPwm1
(2)
0
1
0
1
0
AuxPwm3
(2)
0
1
0
1
1
Comp1OUT
(2)
0
1
1
0
0
AuxPwm1 inverted
(2)
0
1
1
0
1
AuxPwm3 inverted
(2)
0
1
1
1
1
Comp1OUT inverted
(2)
1. When EnLowVSw[2] = ‘1’ the GpioOutEnable[7] bit is forced to 0.
2. In all configurations in which GPIO[7] is enabled as output:
a) the GPIO[7] pin can be always used as an analog input to the ADC system (ADC function) by writing
its address in the A2DChannelX[4:0] in the A2DConfigX register and starting a conversion;
b) the GPIO[7] pin can be always used as a digital input so its value can be always read through SPI
interface (SPI_IN function);
c) the GPIO[7] pin is a rail to rail output supplied by VGPIO_SPI.
Doc ID 17713 Rev 1
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GPIO pins
L6460
Figure 37. GPIO[7] block diagram
V GPIO_SPI
Power Switch 2
To internal
Logic & SPI
V 3v3
V 3v3
From Serial
Interface
114/139
EnPass2
To ADC
V GPIO_SPI
GPIO[7]
Logic Decode
Doc ID 17713 Rev 1
L6460
22.9
GPIO pins
GPIO[8]
The GPIO[8] truth table is (for the abbreviation list please refer to Table 40).
Table 49.
GPIO[8] truth table
GPIO[8] SPI bits
Function (2)
Note
X
CurrDAC
(3)
X
X
HiZ (SPI_IN)
(4)
0
0
0
SPI OUT
(4)
1
0
0
1
AuxPwm1
(4)
0
1
0
1
0
AuxPwm3
(4)
0
1
0
1
1
Comp2OUT
(4)
0
1
1
0
0
AuxPwm1
inverted
(4)
0
1
1
0
1
AuxPwm3
inverted
(4)
0
1
1
1
1
Comp2OUT inverted
(4)
EnDac
(1)
GpioOut
enable[8]
Mode[2]
Mode[1]
Mode[0]
1
X
X
X
0
0
X
0
1
0
1. The EnDAC bit in the CurrDacCtrl register enables the Current DAC (seeChapter 17)
2. This pin is 5 volt input tolerant.
3. When EnDAC = ‘1’ the GpioOutEnable[8] bit is forced to 0. The current DAC circuit is directly connected to
GPIO[8] pin so as soon as it is enabled it will sink current from pin.
4. The GPIO[8] pin can be always used as a digital input so its value can be always read through SPI
interface (SPI_IN function). To avoid affecting the precision of CurrDAC when this is used to sink very low
currents, it is necessary to enable the digital input functionality of GPIO[8]. Therefore to read their values
through SPI interface (SPI_IN function), it is necessary to enable the EnGpio8DigIn bit in the CurrDacCtrl
register.
Doc ID 17713 Rev 1
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GPIO pins
L6460
Figure 38. GPIO[8] block diagram
V 3v3
To internal Logic & SPI
EnGpio8DigIn
To ADC
V 3v3
V 3v3
From Serial
Interface
Logic Decode
GPIO[8]
Gpio[8] Driver
From Serial
Interface
116/139
Current Sink
Circuit
Doc ID 17713 Rev 1
L6460
22.10
GPIO pins
GPIO[9]
The GPIO[9] truth table is (for the abbreviation list please refer to Table 40).
Table 50.
GPIO[9] truth table
GPIO[9] SPI bits
Function (2)
Note
X
OpAmp1 in+
(3)
X
X
HiZ (SPI_IN)
0
0
0
SPI OUT
(4)
1
0
0
1
Interrupt Ctrl
(4)
0
1
0
1
0
AuxPwm2
(4)
0
1
0
1
1
Reg Loop 3
(4)
0
1
1
0
0
Interrupt Ctrl inverted
(4)
0
1
1
0
1
AuxPwm2 inverted
(4)
0
1
1
1
1
Reg Loop 3 inverted
(4)
Op1EnPlusPin
(1)
GpioOut
enable[9]
Mode[2]
Mode[1]
Mode[0]
1
X
X
X
0
0
X
0
1
0
1. The Op1EnPlusPin bit in the OpAmp1Ctrl register enables the connection of the positive input of Op1 to
GPIO[9] pin.
2. The GPIO[9] pin is used by the system when firmware requires the ID read action (Chapter 25)
3. When Op1EnPlusPin = ‘1’ the GpioOutEnable[9] bit is forced to 0.
4. In all configurations in which GPIO[9] is enabled as output:
a)the GPIO[9] pin can be always used as an analog input to the ADC system (ADC function) by writing its
address in the A2DChannelX[4:0] in the A2DConfigX register and starting a conversion;
b) the GPIO[9] pin can be always used as a digital input so its value can be always read through SPI
interface (SPI_IN function);
c)please note that GPIO[9] output is directly connected to ExtPWM1 input for Bridge 1 or 2 and therefore
particular care must be taken in order to avoid wrong PWM signals when ExtPWM1 is selected for
bridge 1 or 2;
d)the GPIO[9] pin is a rail to rail output supplied by VGPIO_SPI.
Doc ID 17713 Rev 1
117/139
GPIO pins
L6460
Figure 39. GPIO[9] block diagram
To internal Logic & SPI
ID1
V 3v3
Pin State Sample
Circuit
SampleID
To ADC
V GPIO_SPI
V 3v3
From SPI
Logic Decode
Gpio[9] Driver
To OpAmp1 In+
118/139
Doc ID 17713 Rev 1
GPIO[9]
L6460
22.11
GPIO pins
GPIO[10]
The GPIO[10] truth table is (for the abbreviation list please refer to Table 40).
Table 51.
GPIO[10] truth table
GPIO[10] SPI bits
Function (2)
Note
X
OpAmp1 in-
(3)
X
X
HiZ (SPI_IN)
0
0
0
SPI OUT
(4)
1
0
0
1
Interrupt Ctrl
(4)
0
1
0
1
0
AuxPwm2
(4)
0
1
0
1
1
AuxPwm3
(4)
0
1
1
0
0
Interrupt Ctrl inverted
(4)
0
1
1
0
1
AuxPwm2 inverted
(4)
0
1
0
0
0
AuxPwm3 inverted
(4)
Op1EnPlusPin
(1)
GpioOut
enable[10]
Mode[2]
Mode[1]
Mode[0]
1
X
X
X
0
0
X
0
1
0
1. The Op1EnMinusPin bit in the OpAmp1Ctrl register enables the connection of the positive input of Op1 to
GPIO[10] pin.
2. The GPIO[10] pin is used by the system when firmware requires the ID read action (Chapter 25)
3. When Op1EnPlusPin = ‘1’ the GpioOutEnable[10] bit is forced to 0.
4. In all configurations in which GPIO[10] is enabled as output:
a) the GPIO[10] pin can be always used as an analog input to the ADC system (ADC function) by writing
its address in the A2DChannelX[4:0] in the A2DConfigX register and starting a conversion;
b) the GPIO[10] pin can be always used as a digital input so its value can be always read through SPI
interface (SPI_IN function);
c) please note that GPIO[10] output is directly connected to ExtPWM2 input for bridge 1 or 2 and
therefore particular care must be taken in order to avoid wrong PWM signals when ExtPWM2 is
selected for bridge 1 or 2;
d) the GPIO[10] pin is a rail to rail output supplied by VGPIO_SPI.
Doc ID 17713 Rev 1
119/139
GPIO pins
L6460
Figure 40. GPIO[10] block diagram
To internal Logic & SPI
ID2
V 3v3
Pin State Sample
Circuit
SampleID
To ADC
GPIO[10]
V GPIO_SPI
V 3v3
From SPI
Logic Decode
Gpio[10] Driver
To OpAmp1 In-
120/139
Doc ID 17713 Rev 1
L6460
22.12
GPIO pins
GPIO[11]
The GPIO[11] truth table is (for the abbreviation list please refer to Table 40).
Table 52.
GPIO[11] truth table
GPIO[11] SPI bits
EnOpl
(1)
Function
Note
X
OpAmp1 Out
(2)
X
X
HiZ (SPI_IN)
0
0
0
SPI OUT
(3)
1
0
0
1
A2DGpo
(3)
0
1
0
1
0
AuxPwm1
(3)
0
1
0
1
1
AuxPwm2
(3)
0
1
1
0
0
SPI OUT inverted
(3)
0
1
1
0
1
A2DGpo inverted
(3)
0
1
1
1
0
AuxPwm1 inverted
(3)
0
1
1
1
1
AuxPwm2 inverted
(3)
GpioOut
enable[11]
Mode[2]
Mode[1]
Mode[0]
1
X
X
X
0
0
X
0
1
0
1. The EnOp1 bit in the OpAmp1Ctrl register enables the operational amplifier 1.
2. When EnOp1 = ‘1’ the GpioOutEnable[11] bit is forced to 0.
3. In all configurations in which GPIO[11] is enabled as output:
a) the GPIO[11] pin can be always used as an analog input to the ADC system (ADC function) by writing
its address in the A2DChannelX[4:0] in the A2DConfigX register and starting a conversion;
b) the GPIO[11] pin can be always used as a digital input so its value can be always read through SPI
interface (SPI_IN function);
c) please note that GPIO[11] output is directly connected to ExtPWM4 input for bridge 3 or 4 and
therefore particular care must be taken in order to avoid wrong PWM signals when ExtPWM4 is
selected for bridge 3 or 4;
d) the GPIO[11] pin is a rail to rail output supplied by VGPIO_SPI.
Doc ID 17713 Rev 1
121/139
GPIO pins
L6460
Figure 41. GPIO[11] block diagram
To internal Logic & SPI
V 3v3
To ADC
V GPIO_SPI
V 3v3
GPIO[11]
From Central
Logic
Logic Decode
OpAmp 1
122/139
Doc ID 17713 Rev 1
L6460
22.13
GPIO pins
GPIO[12]
The GPIO[12] truth table is (for the abbreviation list please refer to Table 40.
Table 53.
GPIO[12] truth table
GPIO[12] SPI bits
AUX2enable
or
Op2En
AUX2syste
m (1)
PlusPin
1
X
X
X
X
X
RegLoop2
0
1
X
X
X
X
OpAmp2 in+
0
0
0
X
X
X
HiZ (SPI_IN)
0
0
1
0
0
0
SPI OUT
(3)
0
0
1
0
0
1
Interrupt Ctrl
(3)
0
0
1
0
1
0
Comp2OUT
(3)
0
0
1
0
1
1
RegLoop2
(3)
0
0
1
1
0
0
Interrupt Ctrl inverted
(3)
0
0
1
1
0
1
Comp2OUT inverted
(3)
0
0
1
1
1
1
RegLoop2 inverted
(3)
Function
GpioOut
Mode[2] Mode[1] Mode[0]
enable[12]
Note
(2)
1. AUX2Enable or AUX2System bit =1 represent the case in which AUX2 is used as a regulator (system or
not system).
2. When Op2EnPlusPin = ‘1’ the GpioOutEnable[11] bit is forced to 0.
3. In all configurations in which GPIO[12] is enabled as output:
a) the GPIO[12] pin can be always used as an analog input to the ADC system (ADC function) by writing
its address in the A2DChannelX[4:0] in the A2DConfigX register and starting a conversion;
b) the GPIO[12] pin can be always used as a digital input so its value can be always read through SPI
interface (SPI_IN function);
c) please note that GPIO[12] output is directly connected to StepCmd input for stepper driver and
therefore particular care must be taken in order to avoid wrong PWM signals when StepCmd is
selected for stepper driver (STEP_REQUEST function)
d) the GPIO[12] pin is a rail to rail, back to back output supplied by VGPIO_SPI.
Doc ID 17713 Rev 1
123/139
GPIO pins
L6460
Figure 42. GPIO[12] block diagram
To internal Logic & SPI
V 3v3
To ADC
V GPIO_SPI
V 3v3
From SPI
Logic Decode
To OpAmp2 In+
124/139
Back to Back
Driver
Doc ID 17713 Rev 1
GPIO[12]
L6460
22.14
GPIO pins
GPIO[13]
The GPIO[13] truth table is (for the abbreviation list please refer to Table 40).
Table 54.
GPIO[13] truth table
GPIO[13] SPI BITS
Op2En
Function
Note
X
OpAmp2 in-
(2)
X
X
HiZ (SPI_IN)
0
0
0
SPI OUT
(3)
1
0
0
1
AuxPwm1
(3)
0
1
0
1
0
Reg Loop 3
(3)
0
1
0
1
1
AuxPwm3
(3)
0
1
1
0
0
AuxPwm1 inverted
(3)
0
1
1
0
1
Reg Loop 3 inverted
(3)
0
1
1
1
1
AuxPwm3 inverted
(3)
mimusPin(1)
GpioOut
enable[13]
Mode[2]
Mode[1]
Mode[0]
1
X
X
X
0
0
X
0
1
0
1. The Op2EnMinusPin bit in the OpAmp2Ctrl register enables the connection of the positive input of Op1 to
GPIO[13] pin.
2. When Op2EnMinusPin = ‘1’ the GpioOutEnable[13] bit is forced to 0.
3. In all configurations in which GPIO[9] is enabled as output:
a) the GPIO[13] pin can be always used as an analog input to the ADC system (ADC function) by writing
its address in the A2DChannelX[4:0] in the A2DConfigX register and starting a conversion;
b) the GPIO[13] pin can be always used as a digital input so its value can be always read through SPI
interface (SPI_IN function);
c) the GPIO[13] pin is a rail to rail output supplied by VGPIO_SPI.
Doc ID 17713 Rev 1
125/139
GPIO pins
L6460
Figure 43. GPIO[13] block diagram
To internal Logic &SPI
V 3v3
To ADC
V GPIO_SP
V 3v3
From SPI
Logic Decode
Gpio[13] Driver
To OpAmp2 In-
126/139
Doc ID 17713 Rev 1
GPIO[13]
L6460
22.15
GPIO pins
GPIO[14]
The GPIO[14] truth table is (for the abbreviation list please refer to Table 40).
Table 55.
GPIO[14] truth table
GPIO[14] SPI bits
EnOp2
(1)
Function
Note
X
OpAmp2 Out
(2)
X
X
HiZ (SPI_IN)
0
0
0
SPI OUT
(3)
1
0
0
1
Interrupt Ctrl
(3)
0
1
0
1
0
AuxPwm2
(3)
0
1
0
1
1
AuxPwm3
(3)
0
1
1
0
0
SPI OUT inverted
(3)
0
1
1
0
1
Interrupt Ctrl inverted
(3)
0
1
1
1
0
AuxPwm2 inverted
(3)
0
1
1
1
1
AuxPwm3 inverted
(3)
GpioOut
enable[14]
Mode[2]
Mode[1]
Mode[0]
1
X
X
X
0
0
X
0
1
0
1. The EnOp2 bit in the OpAmp2Ctrl register enables the operational amplifier 2.
2. When EnOp2 = ‘1’ the GpioOutEnable[14] bit is forced to 0.
3. In all configurations in which GPIO[14] is enabled as output:
a) the GPIO[14] pin can be always used as an analog input to the ADC system (ADC function) by writing
its address in the A2DChannelX[4:0] in the A2DConfigX register and starting a conversion;
b) the GPIO[14] pin can be always used as a digital input so its value can be always read through SPI
interface (SPI_IN function);
c) the GPIO[14] pin is a rail to rail output supplied by VGPIO_SPI.
Doc ID 17713 Rev 1
127/139
GPIO pins
L6460
Figure 44. GPIO[14] block diagram
To internal Logic & SPI
V 3v3
To ADC
V GPIO_SP
V 3v3
GPIO[14]
From Central
Logic
Logic Decode
Gpio[14] Driver
OpAmp 2
128/139
Doc ID 17713 Rev 1
L6460
23
Serial interface
Serial interface
L6460 can communicate with an external microprocessor by using an integrated slave SPI
(serial protocol interface). Through this interface almost all L6460 functionalities can be
controlled and all the ICs can be seen as a register map made by 128 register of 16-bit
each.
The SPI is a simple industry standard communications interface commonly used in
embedded systems and it has the following four I/O pins:
–
MISO (master input slave output)
–
MOSI (master output slave input)
–
SCLK (serial clock [controlled by the master])
–
nSS (slave select active low [controlled by the master])
The “MISO” (master in, slave out) signal carries synchronous data from the slave to the
master device. The MOSI (master out, slave in) signal carries synchronous data from the
master to the slave device. The SCLK signal is driven by the master, synchronizing all data
transfers. Each SPI slave device has one nSS signal that is an active-low slave input/master
output pin. Slave devices do not respond to transactions unless their nSS input signal is
driven low. Master device interfacing with multiple SPI slave devices has an nSS signal for
each slave device.
L6460 will maintain its MISO pin in high impedance until it does not recognize its address in
serial frame.
23.1
Read transaction
A read transaction (see Figure 45) is always started by the master device that lowers the
nSS pin. The other bits are then sent on the MOSI pin with this order:
1.
7-bit representing the address of the register that must be read (MSB first [A6…A0]);
2.
2-bit that must be “10” for a read transaction;
3.
2-bit representing L6460 IC address;
4.
1-bit reserved for future use that must be set at “0”.
At this point the data stored in the register at the selected address will be shifted out on the
MISO pin.
The read operation is terminated by raising the signal on nSS pin.
Doc ID 17713 Rev 1
129/139
Serial interface
L6460
Figure 45. SPI read transaction
nSS
SCLK
Register
Address field
MOSI
A6
Data Field
A0
High Impedance
MISO
23.2
Control IC
Field address
D15
D0
Write transaction
A write transaction (see Figure 46) is always started by the master lowering the signal on
nSS pin. The other bits are then sent on the MOSI pin with this order:
1.
7-bit representing the address of the register that must be written (MSB first [A6…A0]);
2.
2-bit that must be “01” for a read transaction;
3.
2-bit representing L6460 IC address;
4.
1-bit reserved for future use that must be set at “0”.
The data to be written (MSB first D15…D0) are then read from MOSI pin. The length of data
field can be 16 or 20 bits, but only the first 16-bit are accepted as valid data. Data is latched
on rising edge of the nSS line.
Figure 46. SPI write transaction
nSS
SCLK
Control IC
Field addres
Register
Address field
MOSI
MISO
A6
A0
Data Field
D15
D0
High Impedance
The SPI input and output timing definitions are shown in the Table 5 on page 17
130/139
Doc ID 17713 Rev 1
L6460
Serial interface
Figure 47. SPI input timing diagram
T nss
T sclk
setup
T nss
period
hold
T nss
min
V IH
V IL
nSS
T sclk
T sclk
hig
low
SCLK
V IH
V IL
MOSI
V IH
V IL
T mosi
T mosi
setup
hold
T sclk
rise
T sclk
fall
Figure 48. SPI output timing diagram
T nss
T sclk
setup
period
T nss
hold
T nss
min
V IH
V IL
nSS
T sclk
high
T sclk
low
V IH
V IL
SCLK
MOSI
T sclk
rise
T sclk
fall
MISO
V OH
V OL
T miso
valid
T miso
Doc ID 17713 Rev 1
disable
131/139
Registers list
24
L6460
Registers list
Many of the L6460 functionalities are controlled or can be supervised by accessing to the
relative register through serial interface. All these registers can be seen from the user
(microcontroller) point of view as a register table. Each register is one word wide (16-bit) and
can be read using a 7-bit address
Table 56.
Register address map
Address[6:0]
(binary)
Name
Comment
Address[6:0]
(binary)
Name
000_0000
DevName
Read only
100_0000
AuxPwm1Ctrl
000_0001
CoreConfigReg
100_0001
AuxPwm2Ctrl
000_0010
ICTemp
100_0010
GpPwm3Base
000_0011
ICStatus
100_0011
GpPwm3Ctrl
000_0100
EnTestRegs
100_0100
000_0101
SampleID
100_0101
000_0110
WatchDogCfg
100_0110
IntCtrlCfg
000_0111
WatchDogStatus
100_0111
IntCtrlCtrl
000_1000
SoftResReg
100_1000
DigCmpCfg
000_1001
100_1001
DigCmpValue
000_1010
100_1010
000_1011
100_1011
000_1100
HibernateStatus
100_1100
000_1101
HibernateCmd
100_1101
000_1110
100_1110
000_1111
Mtr1_2PwrCtrl
100_1111
001_0000
MainVSwCfg
101_0000
A2DControl
101_0001
A2DConfig1
101_0010
A2DResult1
101_0011
A2DConfig2
101_0100
A2DResult2
001_0001
001_0010
MainlinCfg
001_0011
001_0100
001_0101
101_0101
001_0110
101_0110
001_0111
101_0111
001_1000
132/139
SwCtrCfg
StdByMode
101_1000
GpioOutEnable
001_1001
101_1001
GpioCtrl1
001_1010
101_1010
GpioCtrl2
001_1011
101_1011
GpioCtrl3
Doc ID 17713 Rev 1
Comment
L6460
Registers list
Table 56.
Register address map (continued)
Address[6:0]
(binary)
Address[6:0]
(binary)
Name
Comment
001_1100
101_1100
GpioPadVal
Read only
001_1101
101_1101
GpioOutVal
001_1110
101_1110
001_1111
101_1111
Name
Comment
010_0000
Mtrs1_2Cfg
110_0000
010_0001
Mtr1Cfg
110_0001
010_0010
Mtr1Ctrl
110_0010
010_0011
Mtr1Limit
110_0011
010_0100
Mtr2Cfg
110_0100
OpAmpCtrl1
010_0101
Mtr2Ctrl
110_0101
OpAmpCtrl2
010_0110
Mtr2Limit
110_0110
010_0111
LowVSwitchCtrl
110_0111
010_1000
Mtrs3_4Cfg
110_1000
010_1001
Mtr3Cfg
110_1001
010_1010
Mtr3Ctrl
110_1010
010_1011
Mtr3ILimit
110_1011
010_1100
Mtr4Cfg
110_1100
010_1101
Mtr4Ctrl
110_1101
010_1110
Mtr4ILimit
110_1110
010_1111
110_1111
011_0000
StpCfg1
111_0000
011_0001
StpCfg2
111_0001
011_0010
StpCtrl
111_0010
011_0011
StpCmd
111_0011
011_0100
StpTest
111_0100
011_0101
Aux1SwCfg
111_0101
011_0110
Aux2SwCfg
111_0110
011_0111
Aux3SwCfg1
111_0111
011_1000
Aux3SwCfg2
111_1000
011_1001
Power Mode
Control
111_1001
011_1010
111_1010
011_1011
111_1011
REV_MFCT
111_1100
RESERVED
011_1100
CurrDacCtrl
Doc ID 17713 Rev 1
133/139
Registers list
L6460
Table 56.
Register address map (continued)
Address[6:0]
(binary)
134/139
Address[6:0]
(binary)
Name
011_1101
111_1101
RESERVED
011_1110
111_1110
RESERVED
011_1111
111_1111
RESERVED
Name
Comment
Doc ID 17713 Rev 1
Comment
nRESET
JP7
1
2
3
2
JP1
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
LED
SCLK
D2
R39
Open
330
LED
1
RESET
AWAKE
R3
R11
R41
1K
R40
560
R10
4.7K
R13
1
2
LED
D1
D5
Gpio5
nSS
MISO
MOSI
J7
VSWMAIN
GND
3.3V 2.5A
4.7K
R2
nSS
100nF
C29
1
Master
4.7K
R1
Q3
BC846B
CON17X2
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
J10
nRESET
MISO
MOSI
SCLK
Slave
Vsupply
nAWAKE
J8
CON5X2
1 2
3 4
5 6
7 8
9 10
J1
VLINMAIN
GND
1.2V 0.5A
nSS
1
2
3
2
4.7K
330
C28
330nF
+
JP9
+
R9
4.7K
4.7K
R6
C1
1uF
C16
680uF 50V
C5
680nF
Close on Master
AWAKE
C27
10uF 10V
R18
1K
R36
2.2K
+3_3VS
Q4
BSP51
+3_3VS
R38
Open
LED
330
1
1
1
V3v 3
Q2
BC846B
1
C4
1uF
Vsupply
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
3
2
3
2
3
2
C6
100nF
nAWAKE
R7
4.7K
SCLK
Gpio8
MISO
MOSI
33uH 3A Coilcraf t DO5010H-333MLD
+3_3VS
L1
C12
C13
100pF
100nF
+
C25
470uF 16V
D3
STPS3L60U
D4
R12
JP4
JP3
JP2
Start up configuration
V3v 3
R17
R16
R15
73
72
71
70
J2
3
Doc ID 17713 Rev 1
1K
1K
1K
DC2_plus
Vsupply
MISO
MOSI
VLINmain_FB
VLINmain_OUT
Gpio8
VSWmain_SW
Vsupply
VSWmain_FB
VREF_FB
IREF_FB
SCLK
Vsupply
N.C
DC4_plus
JP12
R23
2.2
JP11
R22
1
3.9
R24
JP13
3.9
R25
JP14
2.2
R26
JP15
R20
R19
1K
1K
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
1
R27
JP16
+3_3VS
TAB
TAB
TAB
TAB
TAB
DC1_plus
Vsupply
CPL
CPH
Vpump
VSWDRV_gate
VSWDRV_SW
Gpio6
VGPIO_SPI
Gpio7
Vsupply Int
V3v 3
nRESET
Vsupply
DC3_plus
N.C
U1
L6460
JP8
Gpio8
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
2
nSS
Gpio0
Gpio1
Gpio2
DC3_sense
Gpio5
Gpio9
Gpio10
Gpio11
N.C.
DC3_minus
DC3_sense
DC4_sense
DC4_minus
N.C.
Gpio14
Gpio13
Gpio12
nAWAKE
DC4_sense
Gpio12
Gpio13
Gpio14
TAB
TAB
TAB
TAB
Gpio3
Gpio4
DC1_plus
VSWDRV_sns
VSWDRV_FB
Gpio4
Gpio3
DC1_minus
DC1_minus
GND1
GND2
DC2_minus
DC2_minus
Gpio2
Gpio1
Gpio0
nSS
DC2_plus
Gpio11
Gpio10
Gpio9
Gpio5
3
2
3
2
JP6
JP5
1
1
C9
Device ID
C11
V3v 3
1uF 1210
C3
Gpio6
+3_3VS
Gpio7
100nF
C7
1nF
1nF
100nF
100nF
Vsupply
ID2
ID1
100nF
C8
nRESET
1
R14
1K
LED
D6
CON3
1
2
3
GND
2.2K
R37
R5 4.7K
R8
4.7K
+
C21
1nF
1nF
1
2
J6
Gpio13
Gpio14
Gpio6
Gpio7
Gpio11
Gpio12
Gpio1
Gpio2
R21
1K
R43
22K
Phase B
Phase A
Stepper
C15
100pF
1
2
1nF J5
C24
C14
100nF
C22
1nF
C23
RESET
C26
330uF 25V
L2
100nF
C31
+3_3VS
33uH 4.5A Coilcraf t DO5040H-333MLD
Q5
STD12NF06L
R42
0.047 1W
Vsupply
+3_3VS
D7
6CWQ06
DC2_plus
DC2_minus
DC1_plus
DC1_minus
Q1
BC846B
100nF
C10
1
2
J4
C2
1uF
C17
C18
1nF J3
1nF
1
2
C20
C19
3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
2
R44
39K
1
2
J9
VSWDRV
GND
12V 3A
CON10
1
2
3
4
5
6
7
8
9
10
J11
25
Vsupply
GND
L6460
Schematic examples
Schematic examples
Figure 49. Application with 2 DC motors, 1 stepper motor and 3 power supplies
135/139
BATTERY +
GND
12V 1.5A max
D3
BZX284C15
1
2
C32
100pF
C22
22uF 16V
J10
+
1
R14
4.7K 1W
R24
10K
R19
10K
C23
100nF
J8
+Vop
Q4
BSP51
1
R15
1K
R11
560
R45
1K
R48
330
1
Q9
R44 2.2K
BC857B
1
GREEN330
LED
1
R38
4.7K
R37
ES3B
J5
1
2
Q2
BSP51
-
+
0.1 1W
R25
150K 0.1%
R28
150K 0.1%
C5
10pF
R23
10K 0.1%
R20
10K 0.1%
R17
C19
10uF 10V
R7
1K
R5
2.2K
2
3
U2A
LM358
+
+3_3VS
C18
330nF
VSWMAIN
GND
3.3V 3A
D12
Gpio5
D5
1
2
Master
JP5
Q6
BC846B
3
2
Slave
RESET
VLINMAIN
GND
1.2V 0.5A
nRESET
MISO
MOSI
SCLK
nAWAKE
CON10A
1 2
3 4
5 6
7 8
9 10
J7
CON34A
D10
10K 1W
R32
LED
GREEN
D8
+
C21
1uF
+
R31
4.7K
4.7K
R29
C28
100nF
R3
R2
1K
1K
1K
DC2_plus
Vsupply
MISO
MOSI
VLINmain_FB
VLINmain_OUT
Gpio8
VSWmain_SW
Vsupply
VSWmain_FB
VREF_FB
IREF_FB
SCLK
Vsupply
N.C.
DC4_plus
V3v 3
D6
STPS3L60U
Q5
BC846B
1
V3v 3
R1
C14
100nF
R26
4.7K
nAWAKE
Gpio14
Gpio13
Gpio12
JP9
Close on Master
AWAKE
D16
Y ELLOW LED
Charge in progress
C27
470uF 16V
R43
1K
L4
3
2
3
2
3
2
17
18
19
20
21
22
Gpio8
23
24
25
26
27
28
SCLK 29
30
31
32
MISO
MOSI
33uH 2A Coilcraf t DO3316P-333MLD
C20
470uF 63V
C15
680nF
Vsupply
JP3 1
JP2 1
JP1 1
Start up configuration
LED
GREEN
33uH 3A Coilcraf t DO5010H-333MLD
+3_3VS
L1
C6
100pF
C7
100nF
+
C8
470uF 16V
D1
STPS3L60U
Vsupply
330
4.7K
+3_3VS
1
2
AWAKE
R34
330
J2
R35
LED
GREEN
SCLK
R33
Vsupply
GND
MISO
MOSI
nSS
D9
nSS
D17
RED LED
Disconnect the battery
Vsupply
nSS
nRESET
JP4
4
2
3
3
2
2
3
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
1K
R49
R22
R18
+3_3VS
TAB
TAB
TAB
TAB
TAB
DC1_plus
Vsupply
CPL
CPH
Vpump
VSWDRV_gate
VSWDRV_SW
Gpio6
VGPIO_SPI
Gpio7
Vsupply Int
V3v 3
nRESET
Vsupply
DC3_plus
N.C.
L6460
6
5
1K
1K
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
-
+
1
Gpio5
Gpio9
Gpio10
Gpio11
4.7K
R6
LM358
7
U2B
JP7
JP6
+Vop
3
2
3
2
1
C17
V3v 3
Device ID
C16
1uF
Gpio6
+3_3VS
Gpio7
100nF
ID2
ID1
100nF
100nF
D13
LED
GREEN
D11
CON3
1
2
3
JP8
R12
R13
4.7K
4.7K
RESET
R39
680
C9
330uF 25V
L2
+
+
C25
100nF
+
C30
100nF
Gpio2
C31
100pF
L5
33uH 2A Coilcraf t DO3316P-333MLD
C24
470uF 16V
R30
1K
R27
1K
Gpio1
C26
100pF
270
1K
1
2
J11
1
2
J9
LED
GREEN
1
1
2
J6
CON8
1
2
3
4
5
6
7
8
J12
D14
R9
1K
R8
15K
D15
LED
GREEN
R42
680
R21
1K
R16
820
R41
C11
100pF
R40
+3_3VS
C10
100pF
L3
33uH 2A Coilcraf t DO3316P-333MLD
C29
470uF 16V
2.2K
R36
Gpio6
Gpio7
Gpio8
Gpio11
Gpio12
+3_3VS
33uH 4.5A Coilcraf t DO5040H-333MLD
Q1
STD12NF06L
R4
0.047 1W
ResetOn
RED LED
1
R10
1K
+3_3VS
D2
6CWQ06
Vsupply
D4
STPS1L60U
Q3
BC846B
nRESET
DC2_plus
DC2_minus
DC1_plus
DC1_minus
D7
STPS1L60U
1
2
J4
Vsupply
1nF
1nF
C13
C4
C3
1nF J3
1nF
1
2
C2
C1
C12
D21
LED
GREEN
10K 1W
R47
D20
LED
RED
U1
D19
LED
RED
R46
10K 1W
D18
LED
GREEN
8
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
8
4
Doc ID 17713 Rev 1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
3
DC3_sense
Gpio5
Gpio9
Gpio10
Gpio11
N.C.
DC3_minus
DC3_sense
DC4_sense
DC4_minus
N.C.
Gpio14
Gpio13
Gpio12
nAWAKE
DC4_sense
2
DC1_plus
VSWDRV_sns
VSWDRV_FB
Gpio4
Gpio3
DC1_minus
DC1_minus
GND1
GND2
DC2_minus
DC2_minus
Gpio2
Gpio1
Gpio0
nSS
DC2_plus
4
TAB
TAB
TAB
TAB
3
70
71
72
73
2
136/139
Gpio2
Gpio1
Gpio0
nSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
VSWDC3GND
5V 1A
VDC3+
GND
1.8V 1A
Q7
BC846B
VSWDRV
GND
12.8V
3A
3
Gpio4
Gpio3
2
To PractiSpin
J1
Schematic examples
L6460
Figure 50. Application with 2 DC motors, a battery charger and 5 power supplies
L6460
26
Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.
Figure 51. TQFP64 mechanical data an package dimensions
mm
inch
DIM.
MIN.
TYP.
A
MAX.
MIN.
TYP.
1.20
A1
0.05
A2
0.95
b
0.17
MAX.
0.0472
0.15
0.002
1.00
1.05
0.0374 0.0393 0.0413
0.22
0.27
0.0066 0.0086 0.0086
0.006
c
0.09
0.20
0.0035
D
11.80
12.00
12.20
0.464
0.472
0.480
D1
9.80
10.00
10.20
0.386
0.394
0.401
D2
2.00
D3
0.0078
0.787
7.50
0.295
E
11.80
12.00
12.20
0.464
0.472
0.480
E1
9.80
10.00
10.20
0.386
0.394
0.401
E2
2.00
E3
L
ccc
0.295
0.50
0.45
L1
k
0.787
7.50
e
0.60
0.0197
0.75
0.0177 0.0236 0.0295
1.00
0˚
OUTLINE AND
MECHANICAL DATA
3.5˚
0.0393
7˚
0.080
0˚
3.5˚
7˚
TQFP64 (10x10x1.0mm)
Exposed Pad Down
0.0031
7278840 B
Doc ID 17713 Rev 1
137/139
Revision history
27
L6460
Revision history
Table 57.
138/139
Document revision history
Date
Revision
02-Jul-2010
1
Changes
Initial release.
Doc ID 17713 Rev 1
L6460
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Doc ID 17713 Rev 1
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