TI SN74LVC1G08DRLR

SN74LVC1G08
SINGLE 2-INPUT POSITIVE-AND GATE
www.ti.com
SCES217T – APRIL 1999 – REVISED FEBRUARY 2007
FEATURES
•
•
•
•
•
•
•
Available in the Texas Instruments
NanoFree™ Package
Supports 5-V VCC Operation
Inputs Accept Voltages to 5.5 V
Max tpd of 3.6 ns at 3.3 V
Low Power Consumption, 10-µA Max ICC
±24-mA Output Drive at 3.3 V
•
•
DBV PACKAGE
(TOP VIEW)
A
1
B
2
GND
3
Ioff Supports Partial-Power-Down Mode
Operation
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
DRL PACKAGE
(TOP VIEW)
DCK PACKAGE
(TOP VIEW)
A
1
B
2
GND
3
VCC
5
5
4
A
1
B
2
GND
3
VCC
5
VCC
4
Y
Y
Y
4
DRY PACKAGE
(TOP VIEW)
A
1
6
YZP PACKAGE
(BOTTOM VIEW)
VCC
B
2
5
NC
GND
3
4
Y
GND
3 4
B
2
A
1 5
Y
VCC
NC – No internal connection
See mechanical drawings for dimensions.
DESCRIPTION/ORDERING INFORMATION
The SN74LVC1G08 performs the Boolean function or
Y = A • B or Y = A + B
in positive logic.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the
package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoFree is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1999–2007, Texas Instruments Incorporated
SN74LVC1G08
SINGLE 2-INPUT POSITIVE-AND GATE
www.ti.com
SCES217T – APRIL 1999 – REVISED FEBRUARY 2007
ORDERING INFORMATION
–40°C to 85°C
Reel of 3000
SN74LVC1G08YZPR
_ _ _CE_
SON – DRY
Reel of 5000
SN74LVC1G08DRYR
CE _
Reel of 3000
SN74LVC1G08DBVR
Reel of 250
SN74LVC1G08DBVT
Reel of 3000
SN74LVC1G08DCKR
Reel of 250
SN74LVC1G08DCKT
Reel of 4000
SN74LVC1G08DRLR
SOT (SOT-23) – DBV
SOT (SOT-553) – DRL
(2)
C08_
CE_
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
DBV/DCK/DRL/DRY: The actual top-side marking has one additional character that designates the assembly/test site.
YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).
FUNCTION TABLE
INPUTS
A
B
OUTPUT
Y
H
H
H
L
X
L
X
L
L
LOGIC DIAGRAM (POSITIVE LOGIC)
2
TOP-SIDE MARKING (2)
NanoFree™ – WCSP (DSBGA)
0.23-mm Large Bump – YZP
(Pb-free)
SOT (SC-70) – DCK
(1)
ORDERABLE PART
NUMBER
PACKAGE (1)
TA
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SN74LVC1G08
SINGLE 2-INPUT POSITIVE-AND GATE
www.ti.com
SCES217T – APRIL 1999 – REVISED FEBRUARY 2007
Absolute Maximum Ratings
(1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
VCC
Supply voltage range
–0.5
6.5
V
VI
Input voltage range (2)
–0.5
6.5
V
–0.5
6.5
V
–0.5
VCC + 0.5
state (2)
UNIT
VO
Voltage range applied to any output in the high-impedance or power-off
VO
Voltage range applied to any output in the high or low state (2) (3)
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous ouput current
±50
mA
±100
mA
Continuous current through VCC or GND
θJA
Package thermal impedance (4)
DBV package
206
DCK package
252
DRL package
142
DRY package
234
YZP package
Tstg
(1)
(2)
(3)
(4)
Storage temperature range
V
°C/W
132
–65
150
°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
The value of VCC is provided in the recommended operating conditions table.
The package thermal impedance is calculated in accordance with JESD 51-7.
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3
SN74LVC1G08
SINGLE 2-INPUT POSITIVE-AND GATE
www.ti.com
SCES217T – APRIL 1999 – REVISED FEBRUARY 2007
Recommended Operating Conditions (1)
VCC
Supply voltage
Operating
Data retention only
VCC = 1.65 V to 1.95 V
VIH
High-level input voltage
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
MIN
MAX
1.65
5.5
1.5
Low-level input voltage
1.7
V
2
0.7 × VCC
0.35 × VCC
VCC = 2.3 V to 2.7 V
0.7
VCC = 3 V to 3.6 V
0.8
V
0.3 × VCC
VCC = 4.5 V to 5.5 V
VI
Input voltage
0
5.5
V
VO
Output voltage
0
VCC
V
VCC = 1.65 V
–4
VCC = 2.3 V
IOH
High-level output current
–8
–16
VCC = 3 V
–32
VCC = 1.65 V
4
VCC = 2.3 V
IOL
Low-level output current
∆t/∆v Input transition rise or fall rate
8
16
VCC = 3 V
32
VCC = 1.8 V ± 0.15 V, 2.5 V ± 0.2 V
20
VCC = 3.3 V ± 0.3 V
10
(1)
Operating free-air temperature
ns/V
5
–40
85
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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mA
24
VCC = 4.5 V
VCC = 5 V ± 0.5 V
TA
mA
–24
VCC = 4.5 V
4
V
0.65 × VCC
VCC = 1.65 V to 1.95 V
VIL
UNIT
°C
SN74LVC1G08
SINGLE 2-INPUT POSITIVE-AND GATE
www.ti.com
SCES217T – APRIL 1999 – REVISED FEBRUARY 2007
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = –100 µA
VOH
1.65 V to 5.5 V
1.65 V
1.2
IOH = –8 mA
2.3 V
1.9
4.5 V
IOL = 100 µA
1.65 V to 5.5 V
0.1
IOL = 4 mA
1.65 V
0.45
IOL = 8 mA
2.3 V
0.3
IOL = 32 mA
A or B inputs
0.4
VI = 5.5 V or GND
VI or VO = 5.5 V
ICC
VI = 5.5 V or GND,
IO = 0
∆ICC
One input at VCC – 0.6 V,
Other inputs at VCC or GND
Ci
VI = VCC or GND
V
0.55
4.5 V
Ioff
(1)
3.8
3V
IOL = 24 mA
II
2.3
IOH = –32 mA
IOL = 16 mA
UNIT
V
2.4
3V
IOH = –24 mA
MAX
VCC – 0.1
IOH = –4 mA
IOH = –16 mA
VOL
MIN TYP (1)
VCC
0.55
0 to 5.5 V
±5
µA
0
±10
µA
1.65 V to 5.5 V
10
µA
500
µA
3 V to 5.5 V
3.3 V
4
pF
All typical values are at VCC = 3.3 V, TA = 25°C.
Switching Characteristics
over recommended operating free-air temperature range, CL = 15 pF (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
A or B
Y
tpd
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
VCC = 5 V
± 0.5 V
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
1.5
7.2
0.7
4.4
0.8
3.6
0.8
3.4
ns
Switching Characteristics
over recommended operating free-air temperature range, CL = 30 pF or 50 pF (unless otherwise noted) (see Figure 2)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
A or B
Y
tpd
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
VCC = 5 V
± 0.5 V
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
2.4
8
1.1
5.5
1
4.5
1
4
ns
Operating Characteristics
TA = 25°C
PARAMETER
Cpd
Power dissipation capacitance
TEST
CONDITIONS
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
VCC = 5 V
TYP
TYP
TYP
TYP
f = 10 MHz
21
24
26
31
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UNIT
pF
5
SN74LVC1G08
SINGLE 2-INPUT POSITIVE-AND GATE
www.ti.com
SCES217T – APRIL 1999 – REVISED FEBRUARY 2007
PARAMETER MEASUREMENT INFORMATION
VLOAD
S1
RL
From Output
Under Test
Open
TEST
GND
CL
(see Note A)
S1
Open
VLOAD
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
RL
GND
LOAD CIRCUIT
INPUTS
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
VI
tr/tf
VCC
VCC
3V
VCC
£2 ns
£2 ns
£2.5 ns
£2.5 ns
VM
VLOAD
CL
RL
VD
VCC/2
VCC/2
1.5 V
VCC/2
2 × VCC
2 × VCC
6V
2 × VCC
15 pF
15 pF
15 pF
15 pF
1 MW
1 MW
1 MW
1 MW
0.15 V
0.15 V
0.3 V
0.3 V
VI
Timing Input
VM
0V
tW
tsu
VI
Input
VM
VM
th
VI
Data Input
VM
VM
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VI
VM
Input
VM
0V
tPLH
VM
VM
VOL
tPHL
VM
VM
0V
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
tPLZ
VLOAD/2
VM
tPZH
VOH
Output
VM
tPZL
tPHL
VOH
Output
VI
Output
Control
VM
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Waveform 2
S1 at GND
(see Note B)
VOL + VD
VOL
tPHZ
VM
VOH – VD
VOH
»0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, ZO = 50 W.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
6
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SN74LVC1G08
SINGLE 2-INPUT POSITIVE-AND GATE
www.ti.com
SCES217T – APRIL 1999 – REVISED FEBRUARY 2007
PARAMETER MEASUREMENT INFORMATION (continued)
VLOAD
S1
RL
From Output
Under Test
Open
TEST
GND
CL
(see Note A)
S1
Open
VLOAD
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
RL
GND
LOAD CIRCUIT
INPUTS
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
VI
tr/tf
VCC
VCC
3V
VCC
£2 ns
£2 ns
£2.5 ns
£2.5 ns
VM
VLOAD
CL
RL
VD
VCC/2
VCC/2
1.5 V
VCC/2
2 × VCC
2 × VCC
6V
2 × VCC
30 pF
30 pF
50 pF
50 pF
1 kW
500 W
500 W
500 W
0.15 V
0.15 V
0.3 V
0.3 V
VI
Timing Input
VM
0V
tW
tsu
VI
Input
VM
VM
th
VI
Data Input
VM
VM
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VI
VM
Input
VM
0V
tPLH
VOH
Output
VM
VOL
tPHL
VM
VM
0V
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
tPLZ
VLOAD/2
VM
tPZH
VOH
Output
VM
tPZL
tPHL
VM
VI
Output
Control
VM
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Waveform 2
S1 at GND
(see Note B)
VOL + VD
VOL
tPHZ
VM
VOH – VD
VOH
»0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, ZO = 50 W.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 2. Load Circuit and Voltage Waveforms
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7
PACKAGE OPTION ADDENDUM
www.ti.com
22-Oct-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
SN74LVC1G08DBVR
ACTIVE
SOT-23
DBV
5
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC1G08DBVRE4
ACTIVE
SOT-23
DBV
5
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC1G08DBVRG4
ACTIVE
SOT-23
DBV
5
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC1G08DBVT
ACTIVE
SOT-23
DBV
5
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC1G08DBVTE4
ACTIVE
SOT-23
DBV
5
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC1G08DBVTG4
ACTIVE
SOT-23
DBV
5
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC1G08DCKR
ACTIVE
SC70
DCK
5
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC1G08DCKRE4
ACTIVE
SC70
DCK
5
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC1G08DCKRG4
ACTIVE
SC70
DCK
5
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC1G08DCKT
ACTIVE
SC70
DCK
5
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC1G08DCKTE4
ACTIVE
SC70
DCK
5
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC1G08DCKTG4
ACTIVE
SC70
DCK
5
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC1G08DRLR
ACTIVE
SOT
DRL
5
4000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC1G08DRLRG4
ACTIVE
SOT
DRL
5
4000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC1G08DRYR
ACTIVE
SON
DRY
6
5000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC1G08DRYRG4
ACTIVE
SON
DRY
6
5000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC1G08YZPR
ACTIVE
WCSP
YZP
5
3000 Green (RoHS &
no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
22-Oct-2007
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Oct-2007
TAPE AND REEL BOX INFORMATION
Device
Package Pins
Site
Reel
Diameter
(mm)
Reel
Width
(mm)
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
SN74LVC1G08DBVR
DBV
5
SITE 34
180
9
3.23
3.17
1.37
4
8
Q3
SN74LVC1G08DBVR
DBV
5
SITE 45
0
0
3.23
3.17
1.37
4
8
Q3
SN74LVC1G08DBVT
DBV
5
SITE 34
180
9
3.23
3.17
1.37
4
8
Q3
SN74LVC1G08DBVT
DBV
5
SITE 45
330
16
10.6
15.8
4.9
16
24
Q3
SN74LVC1G08DCKR
DCK
5
SITE 34
180
9
2.24
2.34
1.22
4
8
Q3
SN74LVC1G08DCKT
DCK
5
SITE 34
180
9
2.24
2.34
1.22
4
8
Q3
SN74LVC1G08DRLR
DRL
5
SITE 35
180
9
1.78
1.78
0.69
4
8
Q3
SN74LVC1G08DRYR
DRY
6
SITE 48
179
8
1.2
1.65
0.7
4
8
Q1
SN74LVC1G08YZPR
YZP
5
SITE 55
180
8
1.02
1.52
0.66
4
8
Q1
SN74LVC1G08YZPR
YZP
5
SITE 12
180
8
1.02
1.52
0.66
4
8
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Oct-2007
Device
Package
Pins
Site
Length (mm)
Width (mm)
Height (mm)
SN74LVC1G08DBVR
DBV
5
SITE 34
205.0
200.0
33.0
SN74LVC1G08DBVR
DBV
5
SITE 45
0.0
185.0
220.0
SN74LVC1G08DBVT
DBV
5
SITE 34
201.0
192.0
26.0
SN74LVC1G08DBVT
DBV
5
SITE 45
0.0
0.0
0.0
SN74LVC1G08DCKR
DCK
5
SITE 34
205.0
200.0
33.0
SN74LVC1G08DCKT
DCK
5
SITE 34
201.0
192.0
26.0
SN74LVC1G08DRLR
DRL
5
SITE 35
202.0
201.0
28.0
SN74LVC1G08DRYR
DRY
6
SITE 48
220.0
205.0
50.0
SN74LVC1G08YZPR
YZP
5
SITE 55
220.0
220.0
34.0
SN74LVC1G08YZPR
YZP
5
SITE 12
220.0
220.0
0.0
Pack Materials-Page 2
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