SN74LVC1G132 SINGLE 2-INPUT NAND GATE WITH SCHMITT-TRIGGER INPUTS www.ti.com SCES546B – FEBRUARY 2004 – REVISED SEPTEMBER 2006 • FEATURES • • • • • • Available in Texas Instruments NanoStar™ and NanoFree™ Packages Supports 5-V VCC Operation Inputs Accept Voltages to 5.5 V Max tpd of 5.3 ns at 3.3 V Low Power Consumption, 10-µA Max ICC ±24-mA Output Drive at 3.3 V • • DBV PACKAGE (TOP VIEW) A 5 1 B 2 GND 3 4 Ioff Supports Partial-Power-Down Mode Operation Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) DCK PACKAGE (TOP VIEW) VCC A 1 B 2 GND 3 5 4 YEP OR YZP PACKAGE (BOTTOM VIEW) VCC GND 3 4 B 2 A 1 5 Y VCC Y Y See mechanical drawings for dimensions. DESCRIPTION/ORDERING INFORMATION The SN74LVC1G132 contains one 2-input NAND gate with Schmitt-trigger inputs designed for 1.65-V to 5.5-V VCC operation and performs the Boolean function Y = A • B or Y = A + B in positive logic. Because of Schmitt action, this device has different input threshold levels for positive-going (VT+) and negative-going (VT–) signals. This device can be triggered from the slowest of input ramps and still give clean jitter-free output signals. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. NanoStar™ and NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. ORDERING INFORMATION PACKAGE (1) TA ORDERABLE PART NUMBER NanoStar™ – WCSP (DSBGA) 0.23-mm Large Bump – YEP –40°C to 85°C NanoFree™ – WCSP (DSBGA) 0.23-mm Large Bump – YZP (Pb-free) SOT (SOT-23) – DBV SOT (SC-70) – DCK (1) (2) TOP-SIDE MARKING (2) SN74LVC1G132YEPR Reel of 3000 _ _ _D5_ SN74LVC1G132YZPR Reel of 3000 SN74LVC1G132DBVR Reel of 250 SN74LVC1G132DBVT Reel of 3000 SN74LVC1G132DCKR Reel of 250 SN74LVC1G132DCKT C3B_ D5_ Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site. YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free). Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. NanoStar, NanoFree are trademarks of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2004–2006, Texas Instruments Incorporated SN74LVC1G132 SINGLE 2-INPUT NAND GATE WITH SCHMITT-TRIGGER INPUTS www.ti.com SCES546B – FEBRUARY 2004 – REVISED SEPTEMBER 2006 FUNCTION TABLE INPUTS B OUTPUT Y L L H L H H H L H H H L A LOGIC DIAGRAM (POSITIVE LOGIC) A Y B Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) VCC MIN MAX Supply voltage range –0.5 6.5 V range (2) VI Input voltage –0.5 6.5 V VO Voltage range applied to any output in the high-impedance or power-off state (2) –0.5 6.5 V VO Voltage range applied to any output in the high or low state (2) (3) –0.5 VCC + 0.5 V IIK Input clamp current VI < 0 –50 mA IOK Output clamp current VO < 0 –50 mA IO Continuous output current ±50 mA ±100 mA Continuous current through VCC or GND θJA Tstg (1) (2) (3) (4) 2 UNIT Package thermal impedance (4) DBV package 206 DCK package 252 YEP/YZP package 132 Storage temperature range –65 150 °C/W °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. The value of VCC is provided in the recommended operating conditions table. The package thermal impedance is calculated in accordance with JESD 51-7. Submit Documentation Feedback SN74LVC1G132 SINGLE 2-INPUT NAND GATE WITH SCHMITT-TRIGGER INPUTS www.ti.com SCES546B – FEBRUARY 2004 – REVISED SEPTEMBER 2006 Recommended Operating Conditions VCC Supply voltage VI Input voltage VO Output voltage IOH (1) Operating Data retention only High-level output current MIN MAX 1.65 5.5 1.5 5.5 V 0 VCC V VCC = 1.65 V –4 VCC = 2.3 V –8 –16 VCC = 3 V –32 4 VCC = 2.3 V 8 16 VCC = 3 V (1) Operating free-air temperature mA 24 VCC = 4.5 V TA mA –24 VCC = 1.65 V Low-level output current V 0 VCC = 4.5 V IOL UNIT 32 –40 85 °C All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. Submit Documentation Feedback 3 SN74LVC1G132 SINGLE 2-INPUT NAND GATE WITH SCHMITT-TRIGGER INPUTS www.ti.com SCES546B – FEBRUARY 2004 – REVISED SEPTEMBER 2006 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER MIN TYP (1) MAX 1.65 V 0.79 1.16 2.3 V 1.11 1.56 TEST CONDITIONS VCC VT+ Positive-going input threshold voltage 3V 1.5 1.87 4.5 V 2.16 2.74 5.5 V 2.61 3.33 1.65 V 0.39 0.62 2.3 V 0.58 0.87 3V 0.84 1.14 4.5 V 1.41 1.79 5.5 V 1.87 2.29 1.65 V 0.37 0.62 2.3 V 0.48 0.77 VT– Negative-going input threshold voltage ∆VT Hysteresis (VT+ – VT–) IOH = –100 µA VOH 1.04 5.5 V 0.71 1.11 1.2 IOH = –8 mA 2.3 V 1.9 4.5 V IOL = 100 µA 1.65 V to 5.5 V 0.1 IOL = 4 mA 1.65 V 0.45 IOL = 8 mA 2.3 V 0.3 3.8 0.4 3V Ioff VI or VO = 5.5 V ICC VI = VCC or GND, IO = 0 ∆ICC One input at VCC – 0.6 V, Other inputs at VCC or GND Ci VI = VCC or GND (1) All typical values are at VCC = 3.3 V, TA = 25°C. V 0.55 4.5 V VI = 5.5 V or GND V 2.3 IOH = –32 mA IOL = 32 mA V V 2.4 3V IOL = 24 mA V VCC – 0.1 1.65 V IOL = 16 mA II 0.87 0.71 1.65 V to 5.5 V IOH = –24 mA A or B inputs 0.56 IOH = –4 mA IOH = –16 mA VOL 3V 4.5 V UNIT 0.55 1.65 V to 5.5 V ±1 µA 0 ±10 µA 1.65 V to 5.5 V 10 µA 3 V to 5.5 V 500 µA 3.3 V 3.5 pF Switching Characteristics over recommended operating free-air temperature range, CL = 15 pF (unless otherwise noted) (see Figure 1) PARAMETER tpd 4 FROM (INPUT) TO (OUTPUT) A or B Y VCC = 1.8 V ±0.15 V VCC = 2.5 V ±0.2 V VCC = 3.3 V ±0.3 V VCC = 5 V ±0.5 V MIN MAX MIN MAX MIN MAX MIN MAX 4 16 2.5 7 2 5.3 1.5 4.4 Submit Documentation Feedback UNIT ns SN74LVC1G132 SINGLE 2-INPUT NAND GATE WITH SCHMITT-TRIGGER INPUTS www.ti.com SCES546B – FEBRUARY 2004 – REVISED SEPTEMBER 2006 Switching Characteristics over recommended operating free-air temperature range, CL = 30 pF or 50 pF (unless otherwise noted) (see Figure 2) PARAMETER tpd FROM (INPUT) TO (OUTPUT) A or B Y VCC = 1.8 V ±0.15 V VCC = 2.5 V ±0.2 V VCC = 3.3 V ±0.3 V VCC = 5 V ±0.5 V UNIT MIN MAX MIN MAX MIN MAX MIN MAX 4 16 3 7.5 2 6 2 5 ns Operating Characteristics TA = 25°C PARAMETER Cpd Power dissipation capacitance TEST CONDITIONS VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V TYP TYP TYP TYP f = 10 MHz 17 18 18 20 Submit Documentation Feedback UNIT pF 5 SN74LVC1G132 SINGLE 2-INPUT NAND GATE WITH SCHMITT-TRIGGER INPUTS www.ti.com SCES546B – FEBRUARY 2004 – REVISED SEPTEMBER 2006 PARAMETER MEASUREMENT INFORMATION VLOAD S1 RL From Output Under Test Open TEST GND CL (see Note A) S1 Open VLOAD tPLH/tPHL tPLZ/tPZL tPHZ/tPZH RL GND LOAD CIRCUIT INPUTS VCC 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5 V ± 0.5 V VI tr/tf VCC VCC 3V VCC £2 ns £2 ns £2.5 ns £2.5 ns VM VLOAD CL RL VD VCC/2 VCC/2 1.5 V VCC/2 2 × VCC 2 × VCC 6V 2 × VCC 15 pF 15 pF 15 pF 15 pF 1 MW 1 MW 1 MW 1 MW 0.15 V 0.15 V 0.3 V 0.3 V VI Timing Input VM 0V tW tsu VI Input VM VM th VI Data Input VM VM 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VI VM Input VM 0V tPLH VM VM VOL tPHL VM VM 0V Output Waveform 1 S1 at VLOAD (see Note B) tPLH tPLZ VLOAD/2 VM tPZH VOH Output VM tPZL tPHL VOH Output VI Output Control VM VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Waveform 2 S1 at GND (see Note B) VOL + VD VOL tPHZ VM VOH – VD VOH »0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, ZO = 50 W. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms 6 Submit Documentation Feedback SN74LVC1G132 SINGLE 2-INPUT NAND GATE WITH SCHMITT-TRIGGER INPUTS www.ti.com SCES546B – FEBRUARY 2004 – REVISED SEPTEMBER 2006 PARAMETER MEASUREMENT INFORMATION VLOAD S1 RL From Output Under Test Open TEST GND CL (see Note A) S1 Open VLOAD tPLH/tPHL tPLZ/tPZL tPHZ/tPZH RL GND LOAD CIRCUIT INPUTS VCC 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5 V ± 0.5 V VI tr/tf VCC VCC 3V VCC £2 ns £2 ns £2.5 ns £2.5 ns VM VLOAD CL RL VD VCC/2 VCC/2 1.5 V VCC/2 2 × VCC 2 × VCC 6V 2 × VCC 30 pF 30 pF 50 pF 50 pF 1 kW 500 W 500 W 500 W 0.15 V 0.15 V 0.3 V 0.3 V VI Timing Input VM 0V tW tsu VI Input VM VM th VI Data Input VM VM 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VI VM Input VM 0V tPLH VM VM VOL tPHL VM VM 0V Output Waveform 1 S1 at VLOAD (see Note B) tPLH tPLZ VLOAD/2 VM tPZH VOH Output VM tPZL tPHL VOH Output VI Output Control VM VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Waveform 2 S1 at GND (see Note B) VOL + VD VOL tPHZ VM VOH – VD VOH »0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, ZO = 50 W. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 2. Load Circuit and Voltage Waveforms Submit Documentation Feedback 7 PACKAGE OPTION ADDENDUM www.ti.com 17-Jan-2008 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty 74LVC1G132DBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) TBD Lead/Ball Finish CU NIPDAU Level-1-260C-UNLIM 74LVC1G132DBVTE4 ACTIVE SOT-23 DBV 5 74LVC1G132DCKRE4 ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74LVC1G132DCKRG4 ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74LVC1G132DCKTE4 ACTIVE SC70 DCK 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74LVC1G132DCKTG4 ACTIVE SC70 DCK 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC1G132DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC1G132DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC1G132DBVTE4 ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC1G132DBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC1G132DCKR ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC1G132DCKT ACTIVE SC70 DCK 5 250 CU NIPDAU Level-1-260C-UNLIM SN74LVC1G132YZPR ACTIVE WCSP YZP 5 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM Green (RoHS & no Sb/Br) Call TI MSL Peak Temp (3) Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ SN74LVC1G132DBVR SOT-23 3000 180.0 DBV 5 Reel Reel Diameter Width (mm) W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 9.2 3.23 3.17 1.37 4.0 8.0 Q3 SN74LVC1G132DBVT SOT-23 DBV 5 250 180.0 9.2 3.23 3.17 1.37 4.0 8.0 Q3 SN74LVC1G132DCKR SC70 DCK 5 3000 180.0 9.2 2.24 2.34 1.22 4.0 8.0 Q3 SN74LVC1G132DCKT SC70 DCK 5 250 180.0 9.2 2.24 2.34 1.22 4.0 8.0 Q3 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74LVC1G132DBVR SOT-23 DBV 5 3000 202.0 201.0 28.0 SN74LVC1G132DBVT SOT-23 DBV 5 250 202.0 201.0 28.0 SN74LVC1G132DCKR SC70 DCK 5 3000 202.0 201.0 28.0 SN74LVC1G132DCKT SC70 DCK 5 250 202.0 201.0 28.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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