STMICROELECTRONICS STA240

STA240
Sirius SDARS channel, service & source decoder
Data Brief
Features
■
2 Satellite and 1 terrestrial signal demodulators
and decoders
■
Advanced DSP processor to implement PAC
audio decoder
■
Requires a single 17MHz clock reference; all
high-speed clock signals are derived using
on-chip PLL
■
Programmable I2S to support 32K/48K/44.1K
audio sample rate (32K/48K Sample rates use
internal clocks, 44.1K Sample rate uses
external clock)
■
I2C master interface to control tuner and audio
DAC
■
External control through uart interface using
sirius standard protocol (SSP) over RS-232
LBGA288
Description
STA240 is a fully integrated 3rd generation
Baseband signal processor for Sirius Satellite
Digital Radio Service (SDARS). It is implemented
using ST Micro's advanced 0.13µm HCMOS9
technology.
Analog to digital converters
■
Three internal 10 BIT A/D converters for
76.5MHZ if signals conversion
It allows a highly efficient implementation of a
Sirius “SDARS Satellite Digital Audio Radio
Service” receiver when used with its companion
STA210 tuner ASIC.
Low power technology
■
1.2V, 0.13 µm technology
■
3.3V capable I/OS
STA240 is packaged in a low profile BGA (LBGA
19x19)
Table 1.
June 2007
Device summary
Part Number
Package
Packing
STA240
LBGA288
Tray
Rev 1
For further information contact your local STMicroelectronics sales office.
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www.st.com
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Application block diagram
1
STA240
Application block diagram
Figure 1.
Application block diagram
FLASH
1M x 16
STA210N
IF
Tuner FE
I2C
IFAGC
STA240
STA240
Baseband
Baseband
Processor
Processor
SDRAM
8Mbx8 or 16Mx8
2/6
Audio/I 2S
Data
AC00142
STA240
Electrical specifications
2
Electrical specifications
2.1
Absolute maximum ratings
Table 2.
Absolute maximum ratings
Symbol
2.2
Parameter
Value
Unit
VDD
1.2V Power supply voltage
-0.5 to 2
V
VDDIO
3.3V Power supply voltage
-0.5 to 4
V
AD_VDD
1.2V Power supply voltage
-0.5 to 2
V
AD_VDD3
3.3V Power supply voltage
-0.5 to 4
V
APLL_VDD
1.2V Power supply voltage
-0.5 to 2
V
Vi
Voltage on input pin
-0.5 to (VDDIO + 0.5)
V
Vo
Voltage on output pin
-0.5 to (VDDIO + 0.5)
V
Tstg
Storage temperature
-55 to +150
°C
Top
Operative ambient temperature
-40 to +85
°C
Tj
Operative junction temperature
-40 to +125
°C
Thermal data
Table 3.
Symbol
Thermal Data
Parameter
Value
Unit
Rth j-case
Thermal resistance junction to case
10
°C/W
Rth j-amb
Thermal resistance junction to ambient (1)
31
°C/W
1. According to JEDEC specification on a 4 layers board
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Package information
3
STA240
Package information
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect. The category of
second Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label.
ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
Figure 2.
LBGA 288 mechanical data & package dimensions
mm
inch
Ref.
MIN.
TYP.
A
A1
MAX.
MIN.
TYP.
1.700
0.270
MAX.
0.0669
0.0106
A2
1.085
0.0427
A3
0.300
0.0118
A4
0.800
0.450
D
18.800 19.000 19.200 0.7402 0.7480 0.7559
e
E
0.500
0.0315
b
D1
OUTLINE AND
MECHANICAL DATA
0.550 0.0177 0.0197 0.0217
17.000
0.6693
1.000
0.0394
18.800 19.000 19.200 0.7402 0.7480 0.7559
E1
17.000
0.6693
F
1.000
0.0394
ddd
0.200
0.0079
eee
0.250
0.0098
fff
0.100
0.0039
LBGA288 (19x19x1.70)
Low Profile Ball Grid Array
Bottom view
7131786 C
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STA240
4
Revision history
Revision history
Table 4.
Document revision history
Date
Revision
18-Jun-2007
1
Changes
Initial release.
5/6
STA240
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