STMICROELECTRONICS STA5630TR

STA5630
Low power GPS RF front-end
Data brief
Features
■
Integrated LNA
■
Low power consumption (< 25 mW)
■
1.8 V supply voltage
■
GPS and Galileo compliant
■
Minimum external components
■
Serial interface
■
3 bits A/D converter
■
CMOS 65 nm technology
■
2 kV HBM ESD protected
■
Standard QFN-32 package
VFQFPN32
Description
The chip is a fully integrated RF front-end able to
down-convert either the GPS L1 signal from
1575.42 MHz to 4.092 MHz.
The STA5630 embeds high performance LNA
minimizing external component count. The chip
uses state of the art CMOS 65 nm technology.
A 3-bit ADC converts the IF signal to Sign (SIGN)
and Magnitude (MAG0 and MAG1). The
magnitude bits are internally integrated in order to
control the variable gain amplifiers. The VGA gain
can be also set by the SPI interface.
Table 1.
The STA5630 accepts a range of reference clocks
(10 to 52 MHz) and generates a 16.368 MHz
sampling clock (GPS_CLK) for the baseband. The
STA5630 embeds LDO to supply the internal core
of the device facilitating requirements to external
power supply.
High performance low power and cost effective
device, the STA5630 is the ideal solution for
automotive, cellular and consumer battery
powered applications.
Device summary
Order code
Marking
Package
Packing
STA5630
STA5630
VFQFPN32
Tray
STA5630TR
STA5630
VFQFPN32
Tape and reel
July 2009
Doc ID 16055 Rev 1
For further information contact your local STMicroelectronics sales office.
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www.st.com
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Contents
STA5630
Contents
1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
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STA5630
1
Applications
Applications
Three main applications cases are considered and described hereafter.
The first uses a passive antenna and only a single RF SAW in front of the internal LNA. It
targets low cost and medium performance applications. In this case LNA is ON and RFA is
set at minimum gain.
The second uses a passive antenna and two RF SAWs. It maximizes the performances in
presence of severe blockers. In this case LNA is ON and RFA is set at maximum gain.
The third case uses an active antenna. This solution targets applications where the GPS
antenna is far from the RF front-end. In this case the signal can be fed into either LNA or
RFA input depending on the application conditions.
STA5630 is suitable for baseband requiring 16.368/4.092 clock/RF interface and one, two or
three bits samples. It accepts reference clocks (TCXO) in the range of 10-52 MHz and
delivers a TCXO buffered copy to the baseband.
The STA5630 has two default modes selectable by an external pin (MODE):
●
MODE 0: the chip is configured to use 16.368 MHz as reference frequency,
●
MODE 1: the chip is configured to use 26 MHz as reference frequency.
Other modes are programmed through the serial interface
1.1
Block diagram
Figure 1.
Block diagram
LNA_OUT
TP_IF_P
RFA_IN
TP_IF_N
Image
Rejection
Mixer
F_IF = 4.092 MHz
LNA_EN
Complex IF
filter
RFA
SIGN
VGA
AGC
LNA_IN
LNA
Buffer
V18_IN
Selectable BW
GPS BW = 2MHz
GALILEO BW = 4MHz
MAG1
3
bits
MAG0
MAG1
Digital
Integrator
PFD
CP
/2
ADC
GPS_CLK
V12_OUT
LDO
F_LO = 3142.656 MHz
/R
1 ÷ 63
V12_RFOUT
/N
56 ÷ 2047
/48
or
/ 96
SPI_NCS
SPI_CLK
<chip config >
SPI_DI
SPI_DO
TCXO_CLK
Digital
Interface
V18_IO
Default Mode Selector
MODE0: TCXO=16.368 MHz
MODE1: TCXO=26 MHz
CHIP_EN
RF_EN
MODE
Doc ID 16055 Rev 1
TCXO
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Pin description
STA5630
2
Pin description
Table 2.
Pin list description
Pin #
Pin name
Description
Type
1
TP_IF_P
RF/IF receiver chain test positive output
Analog output
2
V12_RFA
RF amplifier (RFA) power supply (1.2V)
Supply pin
3
RFA_IN
RFA input, DC coupled
4
V12_IF
IF section power supply (1.2V)
5
V12_OUT
6
V12_RF_OUT
7
V18_IN
8
Analog input
Supply pin
LDO IF/DIG output. Power supply (1.2V) delivered for
IF/ADC/DIG_TCXO/VCO/VDD_IO VCC
Output
LDO RF output: Power supply (1.2V) delivered for
LNA/RFA/MIXER VCC
Output
LDOs power supply (1.8V)
Supply pin
V12_LNA
Low noise amplifier (LNA) power supply (1.2V)
Supply pin
LNA output
9
LNA_OUT
10
GND
11
LNA_IN
12
GND
13
CHIP_EN
14
Analog output
Ground
Ground
LNA input, DC coupled
Ground
Analog input
Ground
Chip Enable
Digital input
MODE
Power-On Default Configuration Selector
Digital input
15
V18_IO
I/Os power supply (1.8V)
Supply pin
16
GPS_CLK
GPS clock (16.368MHz)
Digital output
17
MAG0
Mag0 data (Last significant bit)
Digital output
18
MAG1
Mag1 data
Digital output
19
SIGN
Sign data (most significant bit)
Digital output
20
SPI_CLK
Serial Parallel Interface Clock
Digital input
21
SPI_NCS
Serial Parallel Interface Chip Select (Active Low - 1.8V
domain)
Digital input
22
SPI_DI
Serial Parallel Interface Data Input
Digital input
23
SPI_DO
Serial Parallel Interface Data Output
Digital output
24
TCXO_CLK
TCXO Buffered Output
Digital output
25
V12_IO
Power supply for I/Os digital section (1.2V)
26
GND_IO
I/Os Ground
27
TCXO_IN
TCXO Input, DC coupled
28
V12_DIG
Digital section and TCXO buffer input power supply (1.2V)
Supply pin
29
V12_VCO
VCO power supply (1.2V)
Supply pin
30
V12_ADC
ADC section power supply (1.2V)
Supply pin
31
V12_MIX
Mixer power supply (1.2V)
Supply pin
32
TP_IF_N
RF/IF receiver chain test negative output
EP
GND
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Supply pin
Ground
Ground
Analog input
Analog output
Ground
Doc ID 16055 Rev 1
STA5630
3
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Figure 2.
VFQFPN32 (5x5x1.0 mm) mechanical data and package dimensions
mm
inch
OUTLINE AND
MECHANICAL DATA
DIM.
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
A
0.800
0.900
1.000
0.031
0.035
0.039
A
0.800
0.900
1.000 0.0315 0.0354 0.0394
A1
0.020
0.050
A3
0.200
0.0008 0.0020
0.0079
b
0.180
0.250
0.300 0.0071 0.0098 0.0118
D
4.850
5.000
5.150 0.1909 0.1969 0.2028
D2
3.500
3.600
3.700 0.1378 0.1417 0.1457
E
4.850
5.000
5.150 0.1909 0.1969 0.2028
E2
3.500
3.600
3.700 0.1378 0.1417 0.1457
e
L
ddd
0.500
0.300
0.400
0.0197
0.500 0.0118 0.0157 0.0197
0.050
0.0020
VFQFPN32 (5x5x1.0mm)
Very Fine Quad Flat Package No lead
7376875 F
Doc ID 16055 Rev 1
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Revision history
4
STA5630
Revision history
Table 3.
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Document revision history
Date
Revision
22-Jul-2009
1
Changes
Initial release.
Doc ID 16055 Rev 1
STA5630
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