STMICROELECTRONICS STLVDS32BDR

STLVDS32B
High speed differential line receivers
Features
■
Meets or exceeds the requirements of ansi
TIA/EIA-644 standard
■
Operates with a single 3.3 V supply
■
Designed for signaling rate up to 400 Mbps
■
Differential input thresholds ±100 mV max
■
Typical propagation delay time of 2.5 ns
■
Power dissipation 60 mW typical per receiver
at 200 MHz
■
Low voltage TTL (LVTTL) logic output levels
■
Pin compatible with the AM26LS32,
SN65LVD32
■
Open circuit fail safe
■
ESD protection:
■
7 kV receiver pins
■
3 kV all pins vs gnd
SOP
input common mode voltage allows 1 V of ground
potential difference between two LVDS nodes.
Description
The STLVDS32 is a differential line receiver that
implements the electrical characteristics of low
voltage differential signaling (LVDS). This
signaling technique lowers the output voltage
levels of 5 V differential standard levels (such as
TIA/EIA-422B) to reduce the power, increase the
switching speeds and allow operations with a
3.3 V supply rail. This differential receiver
provides a valid logical output state with a 3.3 V
supply rail. It also provides a valid logical output
state with a ±100 mV differential input voltage
within the input common mode voltage range. The
Table 1.
TSSOP
The intended application of this device and
signalling technique is both point-to-point and
multidrop data transmission over controlled
impedance media approximately 100 Ω. The
transmission media may be printed circuit board
traces, backplanes or cables. The ultimate rate
and distance of data transfer depend upon the
attenuation characteristics of the media and noise
coupling to the environment.
The STLVDS32 version is characterized for
operation from -55°C to 125°C.
Device summary
Order code
Temperature
range
Package
Packaging
STLVDS32BDR
-55 to 125 °C
SO16 (Tape & reel)
2500 parts per reel
STLVDS32BTR
-55 to 125 °C
TSSOP16 (Tape & reel)
2500 parts per reel
August 2007
Rev. 13
1/17
www.st.com
17
STLVDS32B
Contents
1
Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4
Typical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5
Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
6
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
7
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2/17
STLVDS32B
Pin configuration
1
Pin configuration
Figure 1.
Pin connections and functional diagram
Table 2.
Pin description
Pin n°
Symbol
Name and function
2, 6, 10, 14
1A to 4A
Receiver inputs
1, 7, 9, 15
1B to 4B
Negated receiver inputs
3, 5, 11, 13
1Y to 4Y
Receiver outputs
4
G
Enable
12
G
Enable
8
GND
Ground
16
VCC
Supply voltage
3/17
Pin configuration
STLVDS32B
Figure 2.
Logic diagram and logic symbol
Table 3.
Truth table
Differential inputs
A, B
VID ≥ 100mV
-100mV < VID < 100mV
VID ≤-100mV
X
Enables
Outputs
G
G
Y
H
X
H
X
L
H
H
X
?
X
L
?
H
X
L
X
L
L
L
H
Z
H
X
H
X
L
H
OPEN
L=Low level, H=High Level, X=Don’t care, Z= High Impedance
4/17
STLVDS32B
Maximum ratings
2
Maximum ratings
Table 4.
Absolute maximum ratings
Symbol
VCC
Parameter
Supply voltage (1)
VI
Input voltage
VI
Input voltage (A or B inputs)
ESD
Tstg
Value
Unit
-0.5 to 4.6
V
-0.5 to (VCC + 0.5)
V
-0.5 to 4.6
V
Pins receivers
7
All pins vs gnd
3
Human body model
kV
Storage temperature range
-65 to +150
°C
1. All voltages except differential I/O bus voltage, are with respect to the network ground terminal.
Note:
Absolute Maximum Ratings are those values beyond which damage to the device may
occur. Functional operation under these condition is not implied.
Table 5.
Recommended operating conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
3.3
3.6
V
VCC
Supply voltage
3.0
VIH
HIGH level input voltage (ENABLE)
2.0
VIL
LOW level input voltage (ENABLE)
|VID|
Magnitude of differential input voltage
VIC
Common mode input voltage
TA
Operating temperature range
V
0.8
V
0.1
0.6
V
0.5|VID|
2.4-0.5|VID|
V
VCC - 0.8
-40
85
°C
5/17
Electrical characteristics
STLVDS32B
3
Electrical characteristics
Table 6.
Electrical characteristics
(Over recommended operating conditions unless otherwise noted. All typical values are at
TA = 25°C, and VCC = 3.3 V).
Symbol
Parameter
VITH+
Positive going differential input voltage
threshold
VITH-
Negative going differential input
voltage threshold
VOH
High level output voltage
VOL
Low level output voltage
ICC
Supply current
Test conditions
Min.
IOH = -8 mA
2.4
IOH = -4 mA
2.8
Unit
100
mV
mV
V
IOH = 8 mA
0.4
V
10
18
mA
0.25
0.5
mA
-2
-10
-20
-1.2
-3
Disabled
Input current (A or B inputs)
Max.
-100
Enabled, No Load
II
Typ.
VI = 0 V
VI = 2.4 V
Power off input current (A or B inputs)
VCC = 0, VI = 3.6 V
ICS
Cold spare leakage current
IIH
µA
20
µA
VI = 3.6 V, VDD = 0 V
±20
µA
High level input current (EN, G, G or
inputs)
VIH = 2 V
10
µA
IIL
Low level input current (EN, G, G or
inputs)
VIL = 0.8 V
10
µA
IOZ
High impedance output current
VO = 0 or VCC
±10
µA
II(OFF)
6/17
10
STLVDS32B
Table 7.
Electrical characteristics
Switching characteristics
(Over recommended operating conditions unless otherwise noted. All typical values are at
TA = 25°C, and VCC = 3.3 V).
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
tPLH
Propagation delay time, low to
high output
1.5
2.5
3.3
ns
tPHL
Propagation delay time, high to
low output
1.5
2.5
3.3
ns
tr
Output signal rise time
Output signal fall time
tf
CL = 10 pF, Figure 3.
0.4
ns
0.4
ns
tsk(O)
Channel to channel output skew
(Note: 1)
0.1
0.3
ns
tsk(P)
Pulse skew (|tPHL - tPLH|) (Note 2)
0.2
0.4
ns
tsk(PP)
Part to part skew (Note 3)
1
ns
3
12
ns
5
12
ns
tPZH
Propagation delay time, high
impedance to high level output
tPZL
Propagation delay time, high
impedance to low level output
Figure 4.
tPHZ
Propagation delay time, high level
to high impedance output
5
12
ns
tPLZ
Propagation delay time, low level
to high impedance output
5
12
ns
Note:
1
tsk(O) is the maximum delay time difference between the propagation delay of one channel
and that of the others on the same chip with any event on the inputs.
2
tsk(P) is the magnitude difference in differential propagation delay time between the positive
going edge and the negative going edge of the same channel.
3
tsk(PP) is the differential channel-to-channel skew of any event between devices. This
specification applies to devices at the same VCC, and within 5°C of each other within the
operating temperature range
7/17
Typical characteristics
STLVDS32B
4
Typical characteristics
Figure 3.
Timing test and waveforms
Note:
A: All input pulse are supplied by a generator having the following characteristics:
tr or tf ≤1 ns, pulse repetition rate (PRR) = 50 Mpps, pulse width = 10 ± 0.2 ns.
Note:
B: CL includes instrumentation and fixture capacitance within 6 mm of the D.U.T.
8/17
STLVDS32B
Typical characteristics
Figure 4.
Enable and disable time test circuit and waveform
Note:
A: All input pulse are supplied by a generator having the following characteristics:
tr or tf ≤1 ns, pulse repetition rate (PRR) = 50 Mpps, pulse width = 10 ± 0.2 ns.
Note:
B: CL includes instrumentation and fixture capacitance within 6 mm of the D.U.T.
9/17
Typical performance characteristics
STLVDS32B
5
Typical performance characteristics
Figure 5.
(Unless otherwise specified TJ = 25°C)
Output current vs output voltage
Figure 6.
10/17
Output current vs output voltage
STLVDS32B
6
Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect. The category of
second Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com.
11/17
Package mechanical data
STLVDS32B
SO-16 mechanical data
Dim.
mm.
Min.
Typ.
A
a1
inch.
Max.
Min.
Typ.
1.75
0.1
0.068
0.25
a2
Max.
0.004
0.010
1.64
0.063
b
0.35
0.46
0.013
0.018
b1
0.19
0.25
0.007
0.010
C
0.5
0.019
c1
45° (typ.)
D
9.8
10
0.385
0.393
E
5.8
6.2
0.228
0.244
e
1.27
0.050
e3
8.89
0.350
F
3.8
4.0
0.149
0.157
G
4.6
5.3
0.181
0.208
L
0.5
1.27
0.019
0.050
M
S
0.62
0.024
8° (max.)
0016020D
12/17
STLVDS32B
Package mechanical data
TSSOP16 mechanical data
mm.
inch.
Dim.
Min.
Typ.
A
Max.
Min.
Typ.
Max.
1.2
A1
0.05
A2
0.8
b
0.047
0.15
0.002
0.004
0.006
1.05
0.031
0.039
0.041
0.19
0.30
0.007
0.012
c
0.09
0.20
0.004
0.0079
D
4.9
5
5.1
0.193
0.197
0.201
E
6.2
6.4
6.6
0.244
0.252
0.260
E1
4.3
4.4
4.48
0.169
0.173
0.176
1
e
0.65 BSC
K
0°
L
0.45
A
0.60
0.0256 BSC
8°
0°
0.75
0.018
8°
0.024
0.030
A2
A1
b
e
K
c
L
E
D
E1
PIN 1 IDENTIFICATION
1
0080338D
13/17
Package mechanical data
STLVDS32B
Tape & reel SO-16 mechanical data
mm.
inch.
Dim.
Min.
A
Max.
Min.
330
13.2
Typ.
Max.
12.992
C
12.8
D
20.2
0.795
N
60
2.362
T
14/17
Typ.
0.504
22.4
0.519
0.882
Ao
6.45
6.65
0.254
0.262
Bo
10.3
10.5
0.406
0.414
Ko
2.1
2.3
0.082
0.090
Po
3.9
4.1
0.153
0.161
P
7.9
8.1
0.311
0.319
STLVDS32B
Package mechanical data
Tape & reel TSSOP16 mechanical data
mm.
inch.
Dim.
Min.
A
Typ.
Max.
Min.
330
Max.
12.992
C
12.8
D
20.2
0.795
N
60
2.362
T
13.2
Typ.
0.504
22.4
0.519
0.882
Ao
6.7
6.9
0.264
0.272
Bo
5.3
5.5
0.209
0.217
Ko
1.6
1.8
0.063
0.071
Po
3.9
4.1
0.153
0.161
P
7.9
8.1
0.311
0.319
15/17
Revision history
STLVDS32B
7
Revision history
Table 8.
Revision history
Date
Revision
07-Jul-2004
9
tr and tf description changed in table 6 - pag 7.
05-Dec-2005
10
Temperature Range has been changed in cover page, add ICS on table 5.
28-Mar-2006
11
Order code updated and new template.
20-Mar-2007
12
Title in cover page updated.
28-Aug-2007
13
Added Table 1. in cover page.
16/17
Changes
STLVDS32B
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