74LCX74 Low voltage CMOS dual D-Type Flip Flop with 5V tolerant inputs Features ■ 5V tolerant inputs ■ High speed: – fMAX = 150MHz (Max) at VCC = 3V ■ Power down protection on inputs and outputs ■ Symmetrical output impedance: – |IOH| = IOL = 24mA (Min) at VCC = 3V ■ PCI bus levels guaranteed at 24mA ■ Balanced propagation delays: – tPLH ≅ tPHL SO-14 TSSOP14 Description The 74LCX74 is a low voltage CMOS dual D-type flip flop with preset and clear non inverting fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power and high speed 3.3V applications; it can be interfaced to 5V signal environment for inputs. ■ Operating voltage range: – VCC (Opr) = 2.0V to 3.6V ■ Pin and function compatible with 74 series 74 ■ Latch-up performance exceeds 500mA (JESD 17) ■ ESD performance: – HBM > 2000V (MIL STD 883 method 3015); MM > 200V A signal on the D INPUT is transferred to the Q OUTPUT during the positive going transition of the clock pulse. CLR and PR are independent of the clock and accomplished by a low setting on the appropriate input. It has same speed performance at 3.3V than 5V AC/ACT family, combined with a lower power consumption. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. Order codes July 2006 Part number Package Packaging 74LCX74MTR SO-14 Tape and reel 74LCX74TTR TSSOP14 Tape and reel Rev 8 1/17 www.st.com 17 Contents 74LCX74 Contents 1 Logic symbols and I/O equivalent circuit . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 2 3 Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.3 Truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.1 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 5 Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 7 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2/17 74LCX74 1 1.1 Logic symbols and I/O equivalent circuit Logic symbols and I/O equivalent circuit Figure 1. IEC logic symbols Figure 2. Input and output equivalent circuit Logic diagram Figure 3. Note: Logic diagram This logic diagram has not to be used to estimate propagation delays 3/17 Pin settings 74LCX74 2 Pin settings 2.1 Pin connection Figure 4. 2.2 Pin connection (top through view) Pin description Table 1. Pin description 2.3 Pin N° Symbol 1, 13 1CLR, 2CLR Name and function Asynchronous reset - direct input 2, 12 1D, 2D 3, 11 1CK, 2CK Clock input (LOW to HIGH, Edge Triggered) Data inputs 4, 10 1PR, 2PR Asynchronous set - direct input 5, 9 1Q, 2Q True Flip-Flop outputs 6, 8 1Q, 2Q Complement Flip-Flop outputs 7 GND Ground (0V) 14 VCC Positive supply voltage Truth table Table 2. Truth table Inputs Function CLR PR D CK Q Q L H X X L H CLEAR H L X X H L PRESET L L X X H H H H L L H H H H H L H H X (1) Qn Qn 1. X do not care 4/17 Outputs No change 74LCX74 3 Maximum rating Maximum rating stressing the device above the rating listed in the “absolute maximum ratings” table may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. refer also to the STMicroelectronics sure program and other relevant quality documents. Table 3. Absolute maximum ratings Symbol Value Unit Supply voltage -0.5 to +7.0 V VI DC input voltage -0.5 to +7.0 V VO DC output voltage (VCC = 0V) -0.5 to +7.0 V VO DC output voltage (high or low state) (1) -0.5 to VCC + 0.5 V IIK DC input diode current -50 mA IOK DC output diode current (2) -50 mA IO DC output current ± 50 mA ICC DC supply current per supply pin ± 100 mA IGND DC ground current per supply pin ± 100 mA Tstg Storage temperature -65 to +150 °C 300 °C Value Unit 2.0 to 3.6 V VCC TL Parameter Lead temperature (10 sec) 1. IO absolute maximum rating must be observed 2. VO < GND 3.1 Recommended operating conditions Table 4. Recommended operating conditions Symbol VCC Parameter Supply voltage (1) VI Input voltage 0 to 5.5 V VO Output voltage (VCC = 0V) 0 to 5.5 V VO Output voltage (high or low state) 0 to VCC V IOH, IOL High or low level output current (VCC = 3.0 to 3.6V) ± 24 mA IOH, IOL High or low level output current (VCC = 2.7V) ± 12 mA -40 to 85 °C 0 to 10 ns/V Top dt/dv Operating temperature Input Rise and Fall Time (2) 1. Truth table guaranteed: 1.5V to 3.6V 2. VIN from 0.8V to 2V at VCC = 3.0V 5/17 Electrical characteristics 4 74LCX74 Electrical characteristics Table 5. DC specifications Test condition Symbol VIH Parameter Value -40 to 85°C VCC (V) Min High level input voltage Unit Max 2.0 V 2.7 to 3.6 VIL VOH Low level input voltage 0.8 2.7 to 3.6 IO=-100 µA VCC-0.2 2.7 IO=-12 mA 2.2 IO=-18 mA 2.4 IO=-24 mA 2.2 High level output voltage 3.0 VOL IO=100 µA 0.2 2.7 IO=12 mA 0.4 IO=16 mA 0.4 IO=24 mA 0.55 VI = 0 to 5.5V ±5 µA VI or VO = 5.5V 10 µA VI = VCC or GND 10 VI or VO= 3.6 to 5.5V ± 10 VIH = VCC - 0.6V 500 Low level output voltage Input leakage current 2.7 to 3.6 Ioff Power OFF leakage current ICC Quiescent supply current 2.7 to 3.6 I incr. per Input 2.7 to 3.6 ∆ICC V 2.7 to 3.6 3.0 II V 0 V µA µA Table 6. Dynamic switching characteristics Test condition Symbol VOLP VOLV Parameter Dynamic low level quiet output (1) TA = 25 °C VCC (V) 3.3 Value Min CL = 50pF VIL = 0V, VIH = 3.3V Typ Unit Max 0.8 V -0.8 1. Number of outputs defined as "n". Measured with "n-1" outputs switching from HIGH to LOW or LOW to HIGH. The remaining output is measured in the LOW state. 6/17 74LCX74 Electrical characteristics Table 7. AC electrical characteristics Test condition Symbol Parameter Propagation delay tPLH tPHL time (CK to Q or Q) Propagation delay tPLH tPHL time (PR or CLR to Q or Q) tS Setup time, HIGH or LOW level D to CK th Hold time, HIGH or LOW level D to CK tW CK Pulse width, HIGH or LOW PR or CLR Pulse Width, LOW trec Recovery time PR or CLR to CK fMAX Clock pulse frequency tOSLH tOSHL Output to output skew time (1) (2) CL (pF) VCC (V) RL (Ω) Value ts = tr (ns) 2.7 3.0 to 3.6 50 500 2.5 50 500 2.5 50 500 2.5 50 500 2.5 2.7 3.0 to 3.6 2.7 -40 to 85 °C Min Max 1.5 8.0 1.5 7.0 1.5 8.0 1.5 7.0 Unit ns ns 2.5 3.0 to 3.6 ns 2.5 2.7 1.5 3.0 to 3.6 ns 1.5 2.7 3.0 50 500 2.5 50 500 2.5 2.7 50 500 2.5 3.0 to 3.6 50 500 2.5 3.0 to 3.6 2.7 3.0 to 3.6 ns 3.0 0 ns 0 150 MHz 1.0 ns 1. Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switching in the same direction, either HIGH or LOW (tOSLH = | tPLHm - tPLHn|, tOSHL = | tPHLm - tPHLn|) 2. Parameter guaranteed by design Table 8. Capacitive characteristics Test condition Symbol Parameter CIN Input capacitance CPD Power dissipation capacitance (1) Value TA = 25 °C VCC (V) Min Typ Unit Max 3.3 VIN = 0 to VCC 6 pF 3.3 fIN = 10MHz VIN = 0 or VCC 40 pF 1. CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/2 (per gate) 7/17 Test circuit 5 74LCX74 Test circuit Figure 5. Test circuit CL = 50pF or equivalent (includes jig and probe capacitance) RL = 500Ω or equivalent RT = ZOUT of pulse generator (typically 50Ω) 6 Waveforms Figure 6. 8/17 Propagation delays, setup and hold times (f = 1MHz; 50% duty cycle) 74LCX74 Waveforms Figure 7. Propagation delays (f=1MHz; 50% duty cycle) Figure 8. Recovery times (f=1MHz; 50% duty cycle) 9/17 Waveforms 74LCX74 Figure 9. 10/17 Pulse width (f=1MHz; 50% duty cycle) 74LCX74 7 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com 11/17 Package mechanical data 74LCX74 SO-14 MECHANICAL DATA DIM. mm. MIN. TYP inch MAX. MIN. TYP. MAX. A 1.35 1.75 0.053 0.069 A1 0.1 0.25 0.004 0.010 A2 1.10 1.65 0.043 0.065 B 0.33 0.51 0.013 0.020 C 0.19 0.25 0.007 0.010 D 8.55 8.75 0.337 0.344 E 3.8 4.0 0.150 0.157 e 1.27 0.050 H 5.8 6.2 0.228 0.244 h 0.25 0.50 0.010 0.020 L 0.4 1.27 0.016 0.050 k 0° 8° 0° 8° ddd 0.100 0.004 0016019D 12/17 74LCX74 Package mechanical data TSSOP14 MECHANICAL DATA mm. inch DIM. MIN. TYP A MAX. MIN. TYP. MAX. 1.2 A1 0.05 A2 0.8 b 0.047 0.15 0.002 0.004 0.006 1.05 0.031 0.039 0.041 0.19 0.30 0.007 0.012 c 0.09 0.20 0.004 0.0089 D 4.9 5 5.1 0.193 0.197 0.201 E 6.2 6.4 6.6 0.244 0.252 0.260 E1 4.3 4.4 4.48 0.169 0.173 0.176 1 e 0.65 BSC K 0˚ L 0.45 A 0.60 0.0256 BSC 8˚ 0˚ 0.75 0.018 8˚ 0.024 0.030 A2 A1 b e K c L E D E1 PIN 1 IDENTIFICATION 1 0080337D 13/17 Package mechanical data 74LCX74 Tape & Reel SO-14 MECHANICAL DATA mm. inch DIM. MIN. A MAX. MIN. 330 13.2 TYP. MAX. 12.992 C 12.8 D 20.2 0.795 N 60 2.362 T 14/17 TYP 0.504 22.4 0.519 0.882 Ao 6.4 6.6 0.252 0.260 Bo 9 9.2 0.354 0.362 Ko 2.1 2.3 0.082 0.090 Po 3.9 4.1 0.153 0.161 P 7.9 8.1 0.311 0.319 74LCX74 Package mechanical data Tape & Reel TSSOP14 MECHANICAL DATA mm. inch DIM. MIN. A TYP MAX. MIN. 330 MAX. 12.992 C 12.8 D 20.2 0.795 N 60 2.362 T 13.2 TYP. 0.504 22.4 0.519 0.882 Ao 6.7 6.9 0.264 0.272 Bo 5.3 5.5 0.209 0.217 Ko 1.6 1.8 0.063 0.071 Po 3.9 4.1 0.153 0.161 P 7.9 8.1 0.311 0.319 15/17 Revision history 8 74LCX74 Revision history Table 9. Revision history 16/17 Date Revision Changes 15-Sep-2004 7 Ordering codes revision - pag. 1. 10-Jul-2006 8 New template, temperature ranges updated 74LCX74 Please Read Carefully: Information in this document is provided solely in connection with ST products. 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