STLVDS32 High speed differential line receivers Feature summary ■ Meets or exceeds the requirements of ansi TIA/EIA-644 standard ■ Operates with a single 3.3V supply ■ Designed for signaling rate up to 400mbps ■ Differential input thresholds ±100mV max ■ Typical propagation delay time of 2.5ns ■ Power dissipation 60mW typical per receiver at 200MHz ■ Low voltage TTL (LVTTL) logic output levels ■ Pin compatible with the AM26LS32, SN65LVD32 ■ Open circuit fail safe ■ ESD protection: ■ 7kV receiver pins ■ 3kV all pins vs gnd TSSOP mode voltage allows 1V of ground potential difference between two LVDS nodes. Description The STLVDS32 is a differential line receiver that implements the electrical characteristics of low voltage differential signaling (LVDS). This signaling technique lowers the output voltage levels of 5V differential standard levels (such as TIA/EIA-422B) to reduce the power, increase the switching speeds and allow operations with a 3.3V supply rail. This differential receiver provides a valid logical output state with a 3.3V supply rail. It also provides a valid logical output state with a ±100mV differential input voltage within the input common mode voltage range. The input common The intended application of this device and signalling technique is both point-to-point and multidrop data transmission over controlled impedance media approximately 100Ω. The transmission media may be printed circuit board traces, backplanes or cables. The ultimate rate and distance of data transfer depend upon the attenuation characteristics of the media and noise coupling to the environment. The STLVDS32 version is characterized for operation from -55°C to 125°C. . Order code Part number Temperature Range Package Packaging STLVDS32BTR -55 to 125 °C TSSOP16 (Tape & Reel) 2500 parts per reel March 2007 Rev. 12 1/15 www.st.com 15 STLVDS32 Contents 1 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4 Typical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5 Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2/15 STLVDS32 Pin configuration 1 Pin configuration Figure 1. Pin connections and functional diagram Table 1. Pin description Pin n° Symbol Name and function 2, 6, 10, 14 1A to 4A Receiver Inputs 1, 7, 9, 15 1B to 4B Negated Receiver Inputs 3, 5, 11, 13 1Y to 4Y Receiver Outputs 4 G Enable 12 G Enable 8 GND Ground 16 VCC Supply Voltage 3/15 Pin configuration STLVDS32 Figure 2. Logic diagram and logic symbol Table 2. Truth table Differential inputs A, B VID ≥ 100mV -100mV < VID < 100mV VID ≤-100mV X Enables Outputs G G Y H X H X L H H X ? X L ? H X L X L L L H Z H X H X L H OPEN L=Low level, H=High Level, X=Don’t care, Z= High Impedance 4/15 STLVDS32 Maximum ratings 2 Maximum ratings Table 3. Absolute maximum ratings Symbol VCC Parameter Supply voltage (1) VI Input voltage VI Input voltage (A or B inputs) ESD Tstg Value Unit -0.5 to 4.6 V -0.5 to (VCC + 0.5) V -0.5 to 4.6 V Pins receivers 7 All pins vs gnd 3 Human body model kV Storage temperature range -65 to +150 °C 1. All voltages except differential I/O bus voltage, are with respect to the network ground terminal. Note: Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied. Table 4. Recommended operating conditions Symbol Parameter Min. Typ. Max. Unit 3.3 3.6 V VCC Supply Voltage 3.0 VIH HIGH Level Input Voltage (ENABLE) 2.0 VIL LOW Level Input Voltage (ENABLE) |VID| Magnitude of Differential Input Voltage VIC Common Mode Input Voltage TA Operating Temperature Range V 0.8 V 0.1 0.6 V 0.5|VID| 2.4-0.5|VID| V VCC - 0.8 -40 85 °C 5/15 Electrical characteristics STLVDS32 3 Electrical characteristics Table 5. Electrical characteristics (Over recommended operating conditions unless otherwise noted. All typical values are at TA = 25°C, and VCC = 3.3V). Symbol Parameter VITH+ Positive Going Differential Input Voltage Threshold VITH- Negative Going Differential Input Voltage Threshold VOH High Level Output Voltage VOL Low Level Output Voltage ICC Supply Current Test Min. IOH = -8mA 2.4 IOH = -4mA 2.8 Unit 100 mV mV V IOH = 8mA 0.4 V 10 18 mA 0.25 0.5 mA -2 -10 -20 -1.2 -3 Disabled Input Current (A or B inputs) Max. -100 Enabled, No Load II Typ. VI = 0V VI = 2.4V µA 20 µA VI = 3.6V, VDD = 0V ±20 µA High Level Input Current (EN, G, G or Inputs) VIH = 2V 10 µA IIL Low Level Input Current (EN, G, G or Inputs) VIL = 0.8V 10 µA IOZ High Impedance Output Current VO = 0 or VCC ±10 µA II(OFF) Power off Input Current (A or B inputs) VCC = 0, VI = 3.6V ICS Cold Spare Leakage Current IIH 6/15 10 STLVDS32 Table 6. Symbol Electrical characteristics Switching characteristics (Over recommended operating conditions unless otherwise noted. All typical values are at TA = 25°C, and VCC = 3.3V). Parameter Test Min. Typ. Max. Unit tPLH Propagation Delay Time, Low to High Output 1.5 2.5 3.3 ns tPHL Propagation Delay Time, High to Low Output 1.5 2.5 3.3 ns tr tf Output Signal Rise Time Output Signal Fall Time CL = 10p, Fig. 3 0.4 ns 0.4 ns tsk(O) Channel to Channel Output Skew (Note 1) 0.1 0.3 ns tsk(P) Pulse Skew (|tPHL - tPLH|) (Note 2) 0.2 0.4 ns tsk(PP) Part to Part Skew (Note 3) 1 ns tPZH Propagation Delay Time, High Impedance to High Level Output 3 12 ns tPZL Propagation Delay Time, High Impedance to Low Level Output 5 12 ns tPHZ Propagation Delay Time, High Level to High Impedance Output 5 12 ns tPLZ Propagation Delay Time, Low Level to High Impedance Output 5 12 ns Fig. 4 Note 1: tsk(O) is the maximum delay time difference between the propagation delay of one channel and that of the others on the same chip with any event on the inputs. Note 2: tsk(P) is the magnitude difference in differential propagation delay time between the positive going edge and the negative going edge of the same channel. Note 3: tsk(PP) is the differential channel-to-channel skew of any event between devices. This specification applies to devices at the same VCC, and within 5°C of each other within the operating temperature range 7/15 Typical characteristics STLVDS32 4 Typical characteristics Figure 3. Timing test and waveforms Note: A: All input pulse are supplied by a generator having the following characteristics: tr or tf ≤1ns, pulse repetition rate (PRR) = 50Mpps, pulse width = 10 ± 0.2ns. Note: B: CL includes instrumentation and fixture capacitance within 6mm of the D.U.T. 8/15 STLVDS32 Typical characteristics Figure 4. Enable and disable time test circuit and waveform Note: A: All input pulse are supplied by a generator having the following characteristics: tr or tf ≤ 1ns, pulse repetition rate (PRR) = 50Mpps, pulse width = 10 ± 0.2ns. Note: B: CL includes instrumentation and fixture capacitance within 6mm of the D.U.T. 9/15 Typical performance characteristics STLVDS32 5 Typical performance characteristics Figure 5. (Unless otherwise specified TJ = 25°C) Output current vs output voltage Figure 6. 10/15 Output current vs output voltage STLVDS32 6 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. 11/15 Package mechanical data STLVDS32 TSSOP16 MECHANICAL DATA mm. inch DIM. MIN. TYP A MAX. MIN. TYP. MAX. 1.2 A1 0.05 A2 0.8 b 0.047 0.15 0.002 0.004 0.006 1.05 0.031 0.039 0.041 0.19 0.30 0.007 0.012 c 0.09 0.20 0.004 0.0079 D 4.9 5 5.1 0.193 0.197 0.201 E 6.2 6.4 6.6 0.244 0.252 0.260 E1 4.3 4.4 4.48 0.169 0.173 0.176 1 e 0.65 BSC K 0˚ L 0.45 A 0.60 0.0256 BSC 8˚ 0˚ 0.75 0.018 8˚ 0.024 0.030 A2 A1 b e K c L E D E1 PIN 1 IDENTIFICATION 1 0080338D 12/15 STLVDS32 Package mechanical data Tape & Reel TSSOP16 MECHANICAL DATA mm. inch DIM. MIN. A TYP MAX. MIN. 330 MAX. 12.992 C 12.8 D 20.2 0.795 N 60 2.362 T 13.2 TYP. 0.504 22.4 0.519 0.882 Ao 6.7 6.9 0.264 0.272 Bo 5.3 5.5 0.209 0.217 Ko 1.6 1.8 0.063 0.071 Po 3.9 4.1 0.153 0.161 P 7.9 8.1 0.311 0.319 13/15 Revision history STLVDS32 7 Revision history Table 7. Revision history Date Revision 07-Jul-2004 9 tr and tf description changed in table 6 - pag 7. 05-Dec-2005 10 Temperature Range has been changed in cover page, add ICS on table 5. 28-Mar-2006 11 Order code has been updated and new template. 20-Mar-2007 12 Title in cover page has been updated. 14/15 Changes STLVDS32 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. 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