STMICROELECTRONICS STM32F103R6T6

STM32F103x6
STM32F103x8 STM32F103xB
Performance line, ARM-based 32-bit MCU with Flash, USB, CAN,
seven 16-bit timers, two ADCs and nine communication interfaces
Preliminary Data
Features
■
Core: ARM 32-bit Cortex™-M3 CPU
– 72 MHz, 90 DMIPS with 1.25 DMIPS/MHz
– Single-cycle multiplication and hardware
division
– Nested interrupt controller with 43
maskable interrupt channels
– Interrupt processing (down to 6 CPU
cycles) with tail chaining
■
■
■
■
– 2.0 to 3.6 V application supply and I/Os
– POR, PDR, and programmable voltage
detector (PVD)
– 4-to-16 MHz quartz oscillator
– Internal 8 MHz factory-trimmed RC
– Internal 32 kHz RC
– PLL for CPU clock
– Dedicated 32 kHz oscillator for RTC with
calibration
■
Low power
■
Conversion range: 0 to 3.6 V
Dual-sample and hold capability
Synchronizable with advanced control timer
Temperature sensor
DMA
– 7-channel DMA controller
– Peripherals supported: timers, ADC, SPIs,
I2Cs and USARTs
Up to 7 timers
up to 6 channels for PWM output
Dead time generation and emergency
stop
– 2 x 16-bit watchdog timers (Independent
and Window)
– SysTick timer: a 24-bit downcounter
■
Up to 9 communication interfaces
– Up to 2 x I2C interfaces (SMBus/PMBus)
– Up to 3 USARTs (ISO 7816 interface, LIN,
IrDA capability, modem control)
– Up to 2 SPIs (18 Mbit/s)
– CAN interface (2.0B Active)
– USB 2.0 full speed interface
2 x 12-bit, 1 µs A/D converters (16-channel)
–
–
–
–
Up to 80 fast I/O ports
– Up to three 16-bit timers, each with up to 4
IC/OC/PWM or pulse counter
– 16-bit, 6-channel advanced control timer:
– Sleep, Stop and Standby modes
– VBAT supply for RTC and backup registers
■
Debug mode
– 32/49/80 5 V-tolerant I/Os
– All mappable on 16 external interrupt
vectors
– Atomic read/modify/write operations
Memories
Clock, reset and supply management
BGA100
10 x 10 mm
– Serial wire debug (SWD) & JTAG interfaces
– 32-to-128 Kbytes of Flash memory
– 6-to-20 Kbytes of SRAM
■
LQFP64
10 x 10 mm
LQFP100
14 x 14 mm
LQFP48
7 x 7 mm
Table 1.
Device summary
Reference
Root part number
STM32F103x6 STM32F103C6, STM32F103R6
STM32F103x8
STM32F103C8, STM32F103R8
STM32F103V8
STM32F103xB STM32F103RB STM32F103VB
July 2007
Rev 2
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.
1/67
www.st.com
1
Contents
STM32F103xx
Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1
Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3
Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4
Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1
2/67
Test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1.1
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1.2
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1.3
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1.4
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1.5
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1.6
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.1.7
Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.2
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.3
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.3.1
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.3.2
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 27
5.3.3
Embedded reset and power control block characteristics . . . . . . . . . . . 28
5.3.4
Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.3.5
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.3.6
External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.3.7
Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5.3.8
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5.3.9
Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5.3.10
EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5.3.11
Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 42
5.3.12
I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
5.3.13
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
STM32F103xx
6
TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
5.3.15
Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
5.3.16
CAN (controller area network) interface . . . . . . . . . . . . . . . . . . . . . . . . . 54
5.3.17
12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
5.3.18
Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
7.1
8
5.3.14
Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
6.1
7
Contents
Future family enhancements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
3/67
List of tables
STM32F103xx
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
4/67
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Device features and peripheral counts (STM32F103xx performance line). . . . . . . . . . . . . . 7
Pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 28
Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Maximum current consumption in Run and Sleep modes . . . . . . . . . . . . . . . . . . . . . . . . . 29
Maximum current consumption in Stop and Standby modes . . . . . . . . . . . . . . . . . . . . . . . 30
Typical current consumption in Run and Sleep modes . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Typical current consumption in Stop and Standby modes . . . . . . . . . . . . . . . . . . . . . . . . . 32
High-speed external (HSE) user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
HSE 4-16 MHz oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
SCL frequency (fPCLK1= 36 MHz.,VDD = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
USB DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
USB: Full speed electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
ADC accuracy (fPCLK2 = 14 MHz, fADC = 14 MHz, RAIN <10 kΩ, VDDA = 3.3 V). . . . . . . . . 55
TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
LFBGA100 - low profile fine pitch ball grid array package mechanical data. . . . . . . . . . . . 59
LQFP100 – 100-pin low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . 61
LQFP64 – 64 pin low-profile quad flat package mechanical data. . . . . . . . . . . . . . . . . . . . 62
LQFP48 – 48 pin low-profile quad flat package mechanical data. . . . . . . . . . . . . . . . . . . . 63
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
STM32F103xx
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
STM32F103xx performance line block diagram
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
STM32F103xx performance line LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
STM32F103xx performance line LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
STM32F103xx performance line LQFP48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
STM32F103xx performance line BGA100 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Typical application with a 8-MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Unused I/O pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
I2C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
SPI timing diagram - slave mode and CPHA = 11). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
USB timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . . 57
Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . . 57
LFBGA100 - low profile fine pitch ball grid array package outline . . . . . . . . . . . . . . . . . . . 59
Recommended PCB design rules (0.80/0.75 mm pitch BGA) . . . . . . . . . . . . . . . . . . . . . . 60
LQFP100 – 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . 61
LQFP64 – 64 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
LQFP48 – 48 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
5/67
Introduction
1
STM32F103xx
Introduction
This datasheet provides the STM32F103xx performance line ordering information and
mechanical device characteristics.
For information on programming, erasing and protection of the internal Flash memory
please refer to the STM32F10xxx Flash programming reference manual, pm0042, available
from www.st.com.
For information on the Cortex-M3 core please refer to the Cortex-M3 Technical Reference
Manual.
2
Description
The STM32F103xx performance line family incorporates the high-performance ARM
Cortex-M3 32-bit RISC core operating at a 72 MHz frequency, high-speed embedded
memories (Flash memory up to 128Kbytes and SRAM up to 20 Kbytes), and an extensive
range of enhanced I/Os and peripherals connected to two APB buses. All devices offer two
12-bit ADCs, three general purpose 16-bit timers plus one PWM timer, as well as standard
and advanced communication interfaces: up to two I2Cs and SPIs, three USARTs, an USB
and a CAN.
The STM32F103xx performance line family operates in the −40 to +105 °C temperature
range, from a 2.0 to 3.6 V power supply. A comprehensive set of power-saving mode allows
to design low-power applications.
The complete STM32F103xx performance line family includes devices in 4 different
package types: from 48 pins to 100 pins. Depending on the device chosen, different sets of
peripherals are included, the description below gives an overview of the complete range of
peripherals proposed in this family.
These features make the STM32F103xx performance line microcontroller family suitable for
a wide range of applications:
●
Motor drive and application control
●
Medical and handheld equipment
●
PC peripherals gaming and GPS platforms
●
Industrial applications: PLC, inverters, printers, and scanners
●
Alarm systems, Video intercom, and HVAC
Figure 1 shows the general block diagram of the device family.
6/67
STM32F103xx
Device overview
Table 2.
Device features and peripheral counts (STM32F103xx performance line)
Peripheral
STM32F103Cx
STM32F103Rx
64
32
SRAM - Kbytes
10
20
10
20
20
2
3
2
3
3
Timers
32
General purpose
Advanced Control
1
64
128
STM32F103Vx
Flash - Kbytes
Communication
2.1
Description
1
64
128
1
SPI
1
2
1
2
2
I2C
1
2
1
2
2
USART
2
3
2
3
3
USB
1
1
1
1
1
CAN
1
1
1
1
1
GPIOs
12-bit synchronized ADC
Number of channels
32
2
10 channels
CPU frequency
80
2
16 channels
72 MHz
Operating voltage
2.0 to 3.6 V
Operating temperature
Packages
49
-40 to +85 °C / -40 to +105 °C
LQFP48
LQFP64
LQFP100,
BGA100
7/67
Description
2.2
STM32F103xx
Overview
ARM® CortexTM-M3 core with embedded Flash and SRAM
The ARM Cortex-M3 processor is the latest generation of ARM processors for embedded
systems. It has been developed to provide a low-cost platform that meets the needs of MCU
implementation, with a reduced pin count and low-power consumption, while delivering
outstanding computational performance and an advanced system response to interrupts.
The ARM Cortex-M3 32-bit RISC processor features exceptional code-efficiency, delivering
the high-performance expected from an ARM core in the memory size usually associated
with 8- and 16-bit devices.
The STM32F103xx performance line family having an embedded ARM core, is therefore
compatible with all ARM tools and software.
Figure 1 shows the general block diagram of the device family.
Embedded Flash memory
●
Up to 128 Kbytes of embedded Flash is available for storing programs and data.
Embedded SRAM
Up to 20 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait
states.
Nested vectored interrupt controller (NVIC)
The STM32F103xx performance line embeds a Nested Vectored Interrupt Controller able to
handle up to 43 maskable interrupt channels (not including the 16 interrupt lines of CortexM3) and 16 priority levels.
●
Closely coupled NVIC gives low latency interrupt processing
●
Interrupt entry vector table address passed directly to the core
●
Closely coupled NVIC core interface
●
Allows early processing of interrupts
●
Processing of late arriving higher priority interrupts
●
Support for tail-chaining
●
Processor state automatically saved
●
Interrupt entry restored on interrupt exit with no instruction overhead
This hardware block provides flexible interrupt management features with minimal interrupt
latency.
External interrupt/event controller (EXTI)
The external interrupt/event controller consists of 19 edge detectors lines used to generate
interrupt/event requests. Each line can be independently configured to select the trigger
event (rising edge, falling edge, both) and can be masked independently. A pending register
maintains the status of the interrupt requests. The EXTI can detect external line with pulse
width lower than the Internal APB2 clock period. Up to 80 GPIOs are connected to the 16
external interrupt lines.
8/67
STM32F103xx
Description
Clocks and startup
System clock selection is performed on startup, however the internal RC 8 MHz oscillator is
selected as default CPU clock on reset. An external 4-16 MHz clock can be selected and is
monitored for failure. During such a scenario, it is disabled and software interrupt
management follows. Similarly, full interrupt management of the PLL clock entry is available
when necessary (for example with failure of an indirectly used external oscillator).
Several prescalers allow the configuration of the AHB frequency, the High Speed APB
(APB2) and the low Speed APB (APB1) domains. The maximum frequency of the AHB and
the High Speed APB domains is 72 MHz. The maximum allowed frequency of the Low
Speed APB domain is 36 MHz.
Boot modes
At startup, boot pins are used to select one of three boot options:
●
Boot from User Flash
●
Boot from System Memory
●
Boot from SRAM
The boot loader is located in System Memory. It is used to reprogram the Flash memory by
using the USART.
Power supply schemes
●
VDD = 2.0 to 3.6 V: external power supply for I/Os and the internal regulator.
Provided externally through VDD pins.
●
VSSA, VDDA = 2.0 to 3.6 V: external analog power supplies for ADC, Reset blocks, RCs
and PLL. In VDD range (ADC is limited at 2.4 V).
●
VBAT = 1.8 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup
registers (through power switch) when VDD is not present.
Power supply supervisor
The device has an integrated Power On Reset (POR)/Power Down Reset (PDR) circuitry. It
is always active, and ensures proper operation starting from/down to 2 V. The device
remains in reset mode when VDD is below a specified threshold, VPOR/PDR, without the need
for an external reset circuit.
The device features an embedded programmable voltage detector (PVD) that monitors the
VDD power supply and compares it to the VPVD threshold. An interrupt can be generated
when VDD drops below the VPVD and/or when VDD is higher than the VPVD threshold. The
interrupt service routine can then generate a warning message and/or put the MCU into a
safe state. The PVD is enabled by software.
Refer to Table 9: Embedded reset and power control block characteristics for the values of
VPOR/PDR and VPVD.
9/67
Description
STM32F103xx
Voltage regulator
The regulator has three operation modes: main (MR), low power (LPR) and power down.
●
MR is used in the nominal regulation mode (Run)
●
LPR is used in the Stop modes.
●
Power down is used in Standby Mode: the regulator output is in high impedance: the
kernel circuitry is powered-down, inducing zero consumption (but the contents of the
registers and SRAM are lost)
This regulator is always enabled after reset. It is disabled in Standby Mode, providing high
impedance output.
Low-power modes
The STM32F103xx performance line supports three low-power modes to achieve the best
compromise between low power consumption, short startup time and available wakeup
sources:
●
Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
●
Stop mode
Stop mode allows to achieve the lowest power consumption while retaining the content
of SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI
and the HSE RC oscillators are disabled. The voltage regulator can also be put either in
normal or in low power mode.
The device can be woken up from Stop mode by any of the EXTI line. The EXTI line
source can be one of the 16 external lines, the PVD output, the RTC alarm or the USB
wakeup.
●
Standby mode
The Standby mode allows to achieve the lowest power consumption. The internal
voltage regulator is switched off so that the entire 1.8 V domain is powered off. The
PLL, the HSI and the HSE RC oscillators are also switched off. After entering Standby
mode, SRAM and registers content are lost except for registers in the Backup domain
and Standby circuitry.
The device exits Standby mode when an external reset (NRST pin), a IWDG reset, a
rising edge on the WKUP pin, or an RTC alarm occurs.
Note:
The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop
or Standby mode.
DMA
The flexible 7-channel general-purpose DMA is able to manage memory-to-memory,
peripheral-to-memory and memory-to-peripheral transfers. The DMA controller supports
circular buffer management avoiding the generation of interrupts when the controller
reaches the end of the buffer.
Each channel is connected to dedicated hardware DMA requests, with support for software
trigger on each channel. Configuration is made by software and transfer sizes between
source and destination are independent.
The DMA can be used with the main peripherals: SPI, I2C, USART, general purpose and
advanced control timers TIMx and ADC.
10/67
STM32F103xx
Description
RTC (real-time clock) and backup registers
The RTC and the backup registers are supplied through a switch that takes power either on
VDD supply when present or through the VBAT pin. The backup registers (ten 16-bit
registers) can be used to store data when VDD power is not present.
The real-time clock provides a set of continuously running counters which can be used with
suitable software to provide a clock calendar function, and provides an alarm interrupt and a
periodic interrupt. It is clocked by an external 32.768 kHz oscillator, the internal low power
RC oscillator or the High Speed External clock divided by 128. The internal low power RC
has a typical frequency of 32 kHz. The RTC can be calibrated using an external 512 Hz
output to compensate for any natural quartz deviation. The RTC features a 32-bit
programmable counter for long term measurement using the Compare register to generate
an alarm. A 20-bit prescaler is used for the time base clock and is by default configured to
generate a time base of 1 second from a clock at 32.768 kHz.
Independent watchdog
The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is
clocked from an independent 32 kHz internal RC and as it operates independently from the
main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog
to reset the device when a problem occurs, or as a free running timer for application time out
management. It is hardware or software configurable through the option bytes. The counter
can be frozen in debug mode.
Window watchdog
The window watchdog is based on a 7-bit downcounter that can be set as free running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from the
main clock. It has an early warning interrupt capability and the counter can be frozen in
debug mode.
SysTick timer
This timer is dedicated for OS, but could also be used as a standard down counter. It
features:
●
A 24-bit down counter
●
Autoreload capability
●
Maskable system interrupt generation when the counter reaches 0.
●
Programmable clock source
General purpose timers (TIMx)
There are up to 3 synchronizable standard timers embedded in the STM32F103xx
performance line devices. These timers are based on a 16-bit auto-reload up/down counter,
a 16-bit prescaler and feature 4 independent channels each for input capture/output
compare, PWM or one pulse mode output. This gives up to 12 input captures / output
compares / PWMs on the largest packages. They can work together with the Advanced
Control Timer via the Timer Link feature for synchronization or event chaining.
The counter can be frozen in debug mode.
Any of the standard timers can be used to generate PWM outputs. Each of the timers has
independent DMA request generations.
11/67
Description
STM32F103xx
Advanced control timer (TIM1)
The advanced control timer (TIM1) can be seen as a three-phase PWM multiplexed on 6
channels. It can also be seen as a complete general-purpose timer. The 4 independent
channels can be used for
●
Input Capture
●
Output Compare
●
PWM generation (edge or center-aligned modes)
●
One Pulse Mode output
●
Complementary PWM outputs with programmable inserted dead-times.
If configured as a standard 16-bit timer, it has the same features as the TIMx timer. If
configured as the 16-bit PWM generator, it has full modulation capability (0-100%).
The counter can be frozen in debug mode.
Many features are shared with those of the standard TIM timers which have the same
architecture. The advanced control timer can therefore work together with the TIM timers via
the Timer Link feature for synchronization or event chaining.
I²C bus
Up to two I²C bus interfaces can operate in multi-master and slave modes. They can support
standard and fast modes.
They support dual slave addressing (7-bit only) and both 7/10-bit addressing in master
mode. A hardware CRC generation/verification is embedded.
They can be served by DMA and they support SM Bus 2.0/PM Bus.
Universal synchronous/asynchronous receiver transmitter (USART)
One of the USART interfaces is able to communicate at speeds of up to 4.5 Mbit/s. The
other available interfaces communicate at up to 2.25 Mbit/s. They provide hardware
management of the CTS and RTS signals, IrDA SIR ENDEC support, are ISO 7816
compliant and have LIN Master/Slave capability.
All USART interfaces can be served by the DMA controller.
Serial peripheral interface (SPI)
Up to two SPIs are able to communicate up to 18 Mbits/s in slave and master modes in fullduplex and simplex communication modes. The 3-bit prescaler gives 8 master mode
frequencies and the frame is configurable from 8-bit to 16-bit. The hardware CRC
generation/verification supports basic SD Card/MMC modes.
Both SPIs can be served by the DMA controller.
Controller area network (CAN)
The CAN is compliant with specifications 2.0A and B (active) with a bit rate up to 1 Mbit/s. It
can receive and transmit standard frames with 11-bit identifiers as well as extended frames
with 29-bit identifiers. It has three transmit mailboxes, two receive FIFOs with 3 stages and
14 scalable filter banks.
12/67
STM32F103xx
Description
Universal serial bus (USB)
The STM32F103xx performance line embeds a USB device peripheral compatible with the
USB Full-speed 12 Mbs. The USB interface implements a full speed (12 Mbit/s) function
interface. It has software configurable endpoint setting and suspend/resume support. The
dedicated 48 MHz clock source is generated from the internal main PLL.
GPIOs (general-purpose inputs/outputs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions. All GPIOs are high currentcapable.
The I/Os alternate function configuration can be locked if needed following a specific
sequence in order to avoid spurious writing to the I/Os registers.
I/Os on APB2 with up to 18 MHz toggling speed
ADC (analog to digital converter)
Two 12-bit Analog to Digital Converters are embedded into STM32F103xx performance line
devices and each ADC shares up to 16 external channels, performing conversions in singleshot or scan modes. In scan mode, automatic conversion is performed on a selected group
of analog inputs.
Additional logic functions embedded in the ADC interface allow:
●
Simultaneous sample and hold
●
Interleaved sample and hold
●
Single shunt
The ADC can be served by the DMA controller.
An analog watchdog feature allows very precise monitoring of the converted voltage of one,
some or all selected channels. An interrupt is generated when the converted voltage is
outside the programmed thresholds.
The events generated by the standard timers (TIMx) and the Advanced Control timer (TIM1)
can be internally connected to the ADC start trigger, injection trigger, and DMA trigger
respectively, to allow the application to synchronize A/D conversion and timers.
Temperature sensor
The temperature sensor has to generate a linear voltage with any variation in temperature.
The conversion range is between 2 V < VDDA < 3.6 V. The temperature sensor is internally
connected to the ADC_IN16 input channel which is used to convert the sensor output
voltage into a digital value.
Serial wire JTAG debug port (SWJ-DP)
The ARM SWJ-DP Interface is embedded. and is a combined JTAG and serial wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
The JTAG TMS and TCK pins are shared respectively with SWDIO and SWCLK and a
specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP.
13/67
Description
STM32F103xx
STM32F103xx performance line block diagram
Ibus
CORTEX M3 CPU
Fmax: 72 MHz
NVIC
flash obl
Interface
Dbus
System
AHB:Fmax=48/72 MHz
@VDDA
SUPPLY
SUPERVISION
NRST
VDDA
VSSA
Rst
PVD
Int
AHB2
APB2
PCLK1
PCLK2
HCLK
FCLK
GPIOA
PB[15:0]
GPIOB
PC[15:0]
GPIOC
PD[15:0]
GPIOD
PE[15:0]
GPIOE
4 Channels
3 compl. Channels
Brk input
TIM1
MOSI,MISO,
SCK,NSS as AF
SPI1
@VDD
PLL &
CLOCK
MANAGT
XTAL OSC
4-16 MHz
IWDG
Standby
interface
@VDDA
XTAL 32 kHz
AHB2
APB1
RTC
AWU
Backup
reg
12bit ADC2 IF
OSC32_IN
OSC32_OUT
ANTI_TAMP
Backup interface
TIM2
4 Channels
TIM3
4 Channels
TIM 4
8 Channels
USART2
RX,TX, CTS, RTS,
SmartCard as AF
USART3
RX,TX, CTS, RTS,
SmartCard as AF
2x(8x16bit)SPI2
MOSI,MISO,SCK,NSS
as AF
I2C1
SCL,SDA,SMBAL
as AF
I2C2
SCL,SDA
as AF
bxCAN
USB 2.0 FS
VREF-
VBAT
@VBAT
USART1
12bit ADC1 IF
OSC_IN
OSC_OUT
RC 8 MHz
RC 32 kHz
@VDDA
16AF
VREF+
VDD = 2 to 3.6V
VSS
@VDD
64 bit
EXTI
WAKEUP
PA[15:0]
RX,TX, CTS, RTS,
SmartCard as AF
FLASH 128 KB
APB2 : Fmax=48 / 72 MHz
80AF
POR / PDR
VOLT. REG.
3.3V TO 1.8V
SRAM
20 KB
GP DMA
7 channels
POWER
APB1 : Fmax=24 / 36 MHz
JNTRST
JTDI
JTCK/SWCLK
JTMS/SWDIO
JTDO
as AF
Trace
Controller
pbus
JTAG & SWD
BusMatrix
Figure 1.
USBDP/CANTX
USBDM/CANRX
SRAM 512B
WWDG
Temp sensor
ai14390
1. TA = –40 °C to +105 °C (junction temperature up to 125 °C).
2. AF = alternate function on I/O port pin.
14/67
STM32F103xx
Pin descriptions
STM32F103xx performance line LQFP100 pinout
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
VDD_3
VSS_3
PE1
PE0
PB9
PB8
BOOT0
PB7
PB6
PB5
PB4
PB3
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PC12
PC11
PC10
PA15
PA14
Figure 2.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
LQFP100
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
VDD_2
VSS_2
NC
PA 13
PA 12
PA 11
PA 10
PA 9
PA 8
PC9
PC8
PC7
PC6
PD15
PD14
PD13
PD12
PD11
PD10
PD9
PD8
PB15
PB14
PB13
PB12
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
PE2
PE3
PE4
PE5
PE6
VBAT
PC13-ANTI_TAMP
PC14-OSC32_IN
PC15-OSC32_OUT
VSS_5
VDD_5
OSC_IN
OSC_OUT
NRST
PC0
PC1
PC2
PC3
VSSA
VREFVREF+
VDDA
PA0-WKUP
PA1
PA2
PA3
VSS_4
VDD_4
PA4
PA5
PA6
PA7
PC4
PC5
PB0
PB1
PB2
PE7
PE8
PE9
PE10
PE11
PE12
PE13
PE14
PE15
PB10
PB11
VSS_1
VDD_1
3
Pin descriptions
ai14391
15/67
Pin descriptions
STM32F103xx performance line LQFP64 pinout
VDD_3
VSS_3
PB9
PB8
BOOT0
PB7
PB6
PB5
PB4
PB3
PD2
PC12
PC11
PC10
PA15
PA14
Figure 3.
STM32F103xx
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
1
47
2
46
3
45
4
44
5
43
6
42
7
41
8
LQFP64
40
9
39
10
38
11
37
12
36
13
35
14
34
15
33
16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
VDD_2
VSS_2
PA13
PA12
PA11
PA10
PA9
PA8
PC9
PC8
PC7
PC6
PB15
PB14
PB13
PB12
PA3
VSS_4
VDD_4
PA4
PA5
PA6
PA7
PC4
PC5
PB0
PB1
PB2
PB10
PB11
VSS_1
VDD_1
VBAT
PC13-ANTI_TAMP
PC14-OSC32_IN
PC15-OSC32_OUT
PD0 OSC_IN
PD1 OSC_OUT
NRST
PC0
PC1
PC2
PC3
VSSA
VDDA
PA0-WKUP
PA1
PA2
ai14392
STM32F103xx performance line LQFP48 pinout
VDD_3
VSS_3
PB9
PB8
BOOT0
PB7
PB6
PB5
PB4
PB3
PA15
PA14
Figure 4.
48 47 46 45 44 43 42 41 40 39 38 37
36
1
2
35
3
34
33
4
32
5
31
6
LQFP48
30
7
29
8
28
9
27
10
26
11
25
12
13 14 15 16 17 18 19 20 21 22 23 24
VDD_2
VSS_2
PA13
PA12
PA11
PA10
PA9
PA8
PB15
PB14
PB13
PB12
PA3
PA4
PA5
PA6
PA7
PB0
PB1
PB2
PB10
PB11
VSS_1
VDD_1
VBAT
PC13-ANTI_TAMP
PC14-OSC32_IN
PC15-OSC32_OUT
PD0 OSC_IN
PD1 OSC_OUT
NRST
VSSA
VDDA
PA0-WKUP
PA1
PA2
ai14393
16/67
STM32F103xx
Figure 5.
Pin descriptions
STM32F103xx performance line BGA100 ballout
1
A
2
PC14PC13OSC32_IN ANTI_TAMP
3
4
5
6
7
8
9
10
PE2
PB9
PB7
PB4
PB3
PA15
PA14
APA13
B
PC15OSC32_OUT
VBAT
PE3
PB8
PB6
PD5
PD2
PC11
PC10
PA12
C
OSC_IN
VSS_5
PE4
PE1
PB5
PD6
PD3
PC12
PA9
PA11
D
OSC_OUT
VDD_5
PE5
PE0
BOOT0
PD7
PD4
PD0
PA8
PA10
E
NRST
PCD
PE6
VSS_4
VSS_3
VSS_2
VSS_1
PD1
PC9
PC7
F
PC0
PC1
PC3
VDD_4
VDD_3
VDD_2
VDD_1
NC
PC8
PC6
G
VSSA
PA0-WKUP
PA4
PC4
PB2
PE10
PE14
PB15
PD11
PD15
H
VREF–
PA1
PA5
PC5
PE7
PE11
PE15
PB14
PD10
PD14
J
VREF+
PA2
PA6
PB0
PE8
PE12
PB10
PB13
PD9
PD13
K
VDDA
PA3
PA7
PB1
PE9
PE13
PB11
PB12
PD8
PD12
AI16001
17/67
Pin descriptions
LQFP48
LQFP64
LQFP100
Pin name
Type(1)
I / O Level(2)
Pin definitions
BGA100
Table 3.
STM32F103xx
Main function(3)
(after reset)
A3
-
-
1
PE2/TRACECK
I/O
FT
PE2
TRACECK
B3
-
-
2
PE3/TRACED0
I/O
FT
PE3
TRACED0
C3
-
-
3
PE4/TRACED1
I/O
FT
PE4
TRACED1
D3
-
-
4
PE5/TRACED2
I/O
FT
PE5
TRACED2
E3
-
-
5
PE6/TRACED3
I/O
FT
PE6
TRACED3
B2
1
1
6
VBAT
S
VBAT
A2
2
2
7
PC13-ANTI_TAMP(4)
I/O
PC13
8
PC14-OSC32_IN(4)
I/O
PC14-OSC32_IN
I/O
PC15-OSC32_OUT
Pins
A1
3
3
Default alternate functions
ANTI_TAMP
B1
4
4
9
PC15-OSC32_OUT(4)
C2
-
-
10
VSS_5
S
VSS_5
D2
-
-
11
VDD_5
S
VDD_5
C1
5
5
12
OSC_IN
I
OSC_IN
D1
6
6
13
OSC_OUT
O
OSC_OUT
E1
7
7
14
NRST
I/O
NRST
F1
-
8
15
PC0/ADC_IN10
I/O
PC0
ADC_IN10
F2
-
9
16
PC1/ADC_IN11
I/O
PC1
ADC_IN11
E2
-
10
17
PC2/ADC_IN12
I/O
PC2
ADC_IN12
F3
-
11
18
PC3/ADC_IN13
I/O
PC3
ADC_IN13
G1
8
12
19
VSSA
S
VSSA
H1
-
-
20
VREF-
S
VREF-
J1
-
-
21
VREF+
S
VREF+
K1
9
13
22
VDDA
S
VDDA
23
PA0-WKUP/
USART2_CTS/
ADC_IN0/TIM2_CH1_ETR
G2
10
14
PA0
WKUP/USART2_CTS(6)/AD
C_IN0/
TIM2_CH1_ETR(6)
I/O
PA1
USART2_RTS(6)/
ADC_IN1/
TIM2_CH2(6)
I/O
H2
11
15
24
PA1/USART2_RTS/
ADC_IN1/TIM2_CH2
J2
12
16
25
PA2/USART2_TX/
ADC_IN2/ TIM2_CH3
I/O
PA2
USART2_TX(6)/
ADC_IN2/ TIM2_CH3(6)
K2
13
17
26
PA3/USART2_RX/
ADC_IN3/TIM2_CH4
I/O
PA3
USART2_RX(6)/
ADC_IN3/TIM2_CH4(6)
E4
-
18
27
VSS_4
S
VSS_4
F4
-
19
28
VDD_4
S
VDD_4
18/67
STM32F103xx
Pin definitions (continued)
LQFP64
LQFP100
Default alternate functions
LQFP48
Main function(3)
(after reset)
BGA100
Pin name
Type(1)
Pins
I / O Level(2)
Table 3.
Pin descriptions
G3
14
20
29
PA4/SPI1_NSS/
USART2_CK/ADC_IN4
I/O
PA4
SPI1_NSS(6)/
USART2_CK(6)/ ADC_IN4
H3
15
21
30
PA5/SPI1_SCK/ ADC_IN5
I/O
PA5
SPI1_SCK(6)/ ADC_IN5
J3
16
22
31
PA6/SPI1_MISO/
ADC_IN6/TIM3_CH1
I/O
PA6
SPI1_MISO(6)/
ADC_IN6/TIM3_CH1(6)
K3
17
23
32
PA7/SPI1_MOSI/
ADC_IN7/TIM3_CH2
I/O
PA7
SPI1_MOSI(6)/
ADC_IN7/TIM3_CH2(6)
G4
-
24
33
PC4/ADC_IN14
I/O
PC4
ADC_IN14
H4
-
25
34
PC5/ADC_IN15
I/O
PC5
ADC_IN15
J4
18
26
35
PB0/ADC_IN8/ TIM3_CH3
I/O
PB0
ADC_IN8/TIM3_CH3(6)
K4
19
27
36
PB1/ADC_IN9/ TIM3_CH4
I/O
PB1
ADC_IN9/TIM3_CH4(6)
G5
20
28
37
PB2 / BOOT1
I/O
FT
PB2/BOOT1
H5
-
-
38
PE7
I/O
FT
PE7
J5
-
-
39
PE8
I/O
FT
PE8
K5
-
-
40
PE9
I/O
FT
PE9
G6
-
-
41
PE10
I/O
FT
PE10
H6
-
-
42
PE11
I/O
FT
PE11
J6
-
-
43
PE12
I/O
FT
PE12
K6
-
-
44
PE13
I/O
FT
PE13
G7
-
-
45
PE14
I/O
FT
PE14
H7
-
-
46
PE15
I/O
FT
PE15
J7
21
29
47
PB10/I2C2_SCL/
USART3_TX
I/O
FT
PB10
I2C2_SCL/USART3_TX(5)(6)
K7
22
30
48
PB11/I2C2_SDA /
USART3_RX
I/O
FT
PB11
I2C2_SDA/
USART3_RX(5)(6)
E7
23
31
49
VSS_1
S
VSS_1
F7
24
32
50
VDD_1
S
VDD_1
33
PB12/SPI2_NSS /
51 I2C2_SMBAl/ USART3_CK / I/O
TIM1_BKIN
I/O
I/O
K8
25
J8
26
34
52
PB13/SPI2_SCK /
USART3_CTS /
TIM1_CH1N
H8
27
35
53
PB14/SPI2_MISO /
USART3_RTS /
TIM1_CH2N
PB12
SPI2_NSS(5)
/I2C2_SMBAl(5)/
USART3_CK(5)(6)/
TIM1_BKIN(6)
FT
PB13
SPI2_SCK(5)/
USART3_CTS(5)(6)/
TIM1_CH1N (6)
FT
PB14
SPI2_MISO(5)
/USART3_RTS(5)(6)
TIM1_CH2N (6)
FT
19/67
Pin descriptions
LQFP48
LQFP64
LQFP100
Type(1)
I / O Level(2)
Pin definitions (continued)
BGA100
Table 3.
STM32F103xx
Main function(3)
(after reset)
G8
28
36
54
PB15/SPI2_MOSI
TIM1_CH3N
I/O
FT
PB15
K9
-
-
55
PD8
I/O
FT
PD8
J9
-
-
56
PD9
I/O
FT
PD9
H9
-
-
57
PD10
I/O
FT
PD10
G9
-
-
58
PD11
I/O
FT
PD11
K10
-
-
59
PD12
I/O
FT
PD12
J10
-
-
60
PD13
I/O
FT
PD13
H10
-
-
61
PD14
I/O
FT
PD14
G10
-
-
62
PD15
I/O
FT
PD15
F10
-
37
63
PC6
I/O
FT
PC6
E10
38
64
PC7
I/O
FT
PC7
F9
39
65
PC8
I/O
FT
PC8
Pins
Pin name
Default alternate functions
SPI2_MOSI(5)/
TIM1_CH3N(6)
E9
-
40
66
PC9
I/O
FT
PC9
D9
29
41
67
PA8/USART1_CK/
TIM1_CH1/MCO
I/O
FT
PA8
USART1_CK/
TIM1_CH1(6)/MCO
C9
30
42
68
PA9/USART1_TX/
TIM1_CH2
I/O
FT
PA9
USART1_TX(6)/
TIM1_CH2(6)
D10 31
43
69
PA10/USART1_RX/
TIM1_CH3
I/O
FT
PA10
USART1_RX(6)/
TIM1_CH3(6)
C10 32
44
70
PA11 / USART1_CTS/
CANRX / USBDM/
TIM1_CH4
I/O
FT
PA11
USART1_CTS/
CANRX(6)/
TIM1_CH4(6) / USBDM
B10 33
45
71
PA12 / USART1_RTS/
CANTX / USBDP/
TIM1_ETR
I/O
FT
PA12
USART1_RTS/
CANTX(6) /
TIM1_ETR(6) / USBDP
A10 34
46
72
PA13/JTMS/SWDIO
I/O
FT
JTMS/SWDIO
PA13
F8
-
-
73
E6
35
47
74
VSS_2
S
VSS_2
F6
36
48
75
VDD_2
S
VDD_2
A9
37
49
76
PA14/JTCK/SWCLK
I/O
FT
JTCK/SWCLK
PA14
A8
38
50
77
PA15/JTDI
I/O
FT
JTDI
PA15
B9
-
51
78
PC10
I/O
FT
PC10
B8
-
52
79
PC11
I/O
FT
PC11
C8
-
53
80
PC12
I/O
FT
PC12
20/67
Not connected
STM32F103xx
LQFP48
LQFP64
LQFP100
Type(1)
I / O Level(2)
Pin definitions (continued)
BGA100
Table 3.
Pin descriptions
Main function(3)
(after reset)
D8
5
5
81
PD0
I/O
FT
OSC_IN(7)
E8
6
6
82
PD1
I/O
FT
OSC_OUT(7)
54
83
PD2/TIM3_ETR
I/O
FT
PD2
Pins
B7
Pin name
Default alternate functions
TIM3_ETR
C7
-
-
84
PD3
I/O
FT
PD3
D7
-
-
85
PD4
I/O
FT
PD4
B6
-
-
86
PD5
I/O
FT
PD5
C6
-
-
87
PD6
I/O
FT
PD6
D6
-
-
88
PD7
I/O
FT
PD7
A7
39
55
89
PB3/JTDO/TRACESWO
I/O
FT
JTDO
PB3/TRACESWO
A6
40
56
90
PB4/JNTRST
I/O
FT
JNTRST
PB4
C5
41
57
91
PB5/I2C1_SMBAl
I/O
PB5
I2C1_SMBAl
B5
42
58
92
PB6/I2C1_SCL/ TIM4_CH1
I/O
FT
PB6
I2C1_SCL(6)/
TIM4_CH1(5)(6)
A5
43
59
93
PB7/I2C1_SDA/ TIM4_CH2
I/O
FT
PB7
I2C1_SDA(6)/
TIM4_CH2(5) (6)
D5
44
60
94
BOOT0
I
B4
45
61
95
PB8/TIM4_CH3
I/O
FT
PB8
TIM4_CH3(5) (6)
A4
46
62
96
PB9/TIM4_CH4
I/O
FT
PB9
TIM4_CH4(5) (6)
D4
-
-
97
PE0/TIM4_ETR
I/O
FT
PE0
TIM4_ETR(5)
C4
-
-
98
PE1
I/O
FT
PE1
E5
47
63
99
VSS_3
S
VSS_3
F5
48
64
100
VDD_3
S
VDD_3
BOOT0
1. I = input, O = output, S = supply, HiZ = high impedance.
2. FT= 5 V tolerant.
3. Function availability depends on the chosen device. Refer to Table 2 on page 7.
4. PC13, PC14 and PC15 are supplied through the power switch, and so their use in ouptut mode is limited: they can be used
only in output 2 MHz mode with a maximum load of 30 pF and only one pin can be put in output mode at a time.
5. Available only on devices with a Flash memory density equal or higher than 64 Kbytes.
6. This alternate function can be remapped by software to some other port pins (if available on the used package). For more
details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual,
UM0306, available from the STMicroelectronics website: www.st.com.
7. For the LQFP48 and LQFP64 packages, the pins number 5 and 6 are configured as OSC_IN/OSC_OUT after reset,
however the functionality of PD0 and PD1 can be remapped by software on these pins.
21/67
Memory mapping
4
STM32F103xx
Memory mapping
The memory map is shown in Figure 6.
Figure 6.
Memory map
APB memory space
0xFFFF FFFF
reserved
0xE010 0000
reserved
0x6000 0000
reserved
4 Kbits
reserved
1 Kbit
reserved
3 Kbits
0x4002 3400
0x4002 3000
0xFFFF FFFF
0x4002 2400
0xFFFF F000
Flash Interface
0x4002 2000
0xE010 0000
0xE000 0000
0x4002 1400
0x4002 1000
Cortex-M3 Internal
Peripherals
1 Kbit
3 Kbits
reserved
7
1 Kbit
RCC
3 Kbits
reserved
0x4002 0400
DMA
1 Kbit
reserved
1 Kbit
USART1
1 Kbit
reserved
1 Kbit
0x4002 0000
6
0x4001 3C00
0x4001 3800
0xC000 0000
0x4001 3400
SPI1
1 Kbit
TIM1
1 Kbit
ADC2
1 Kbit
ADC1
1 Kbit
0x4001 3000
0x4001 2C00
5
0x4001 2800
0x4001 2400
0xA000 0000
2 Kbits
reserved
0x4001 1C00
4
1 Kbit
Port D
1 Kbit
Port C
1 Kbit
Port B
1 Kbit
Port A
1 Kbit
EXTI
1 Kbit
AFIO
1 Kbit
0x4001 1800
0x1FFF FFFF
reserved
0x4001 1400
0x1FFF F9FF
0x8000 0000
Port E
OPTION BYTES
0x1FFF F800
0x4001 1000
0x4001 0C00
0x4001 0800
3
SYSTEM MEMORY
0x4001 0400
0x4001 0000
0x1FFF F000
0x6000 0000
reserved
0x4000 7400
35 Kbits
PWR
1 Kbit
BKP
1 Kbit
reserved
1 Kbit
0x4000 7000
2
0x4000 6C00
reserved
0x4000 0000
PERIPHERALS
0x4000 6800
0x4000 6400
0x4000 6000
bxCAN
1 Kbit
shared 512 byte
USB/CAN SRAM
1 Kbit
USB Registers
1 Kbit
I2C2
1 Kbit
I2C1
1 Kbit
0x4000 5C00
1
0x4000 5800
0x2000 0000
0x4000 5400
SRAM
0x0801 FFFF
reserved
2 Kbits
USART3
1 Kbit
USART2
1 Kbit
reserved
2 Kbits
0x4000 4C00
0
FLASH
0x4000 4800
0x4000 4400
0x0000 0000
CODE
0x0800 0000
0x4000 3C00
SPI2
1 Kbit
reserved
1 Kbit
IWDG
1 Kbit
WWDG
1 Kbit
RTC
1 Kbit
0x4000 3800
0x4000 3400
0x4000 3000
Reserved
0x4000 2C00
0x4000 2800
reserved
7 Kbits
0x4000 0C00
TIM4
1 Kbit
TIM3
1 Kbit
TIM2
1 Kbit
0x4000 0800
0x4000 0400
0x4000 0000
ai14394
22/67
STM32F103xx
5
Electrical characteristics
5.1
Test conditions
Electrical characteristics
Unless otherwise specified, all voltages are referred to VSS.
5.1.1
Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at TA=25°C and TA=TAmax (given by the
selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean±3Σ).
5.1.2
Typical values
Unless otherwise specified, typical data are based on TA = 25 °C, VDD = 3.3 V (for the
2 V ≤VDD ≤3.6 V voltage range). They are given only as design guidelines and are not
tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean±2Σ).
5.1.3
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
5.1.4
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 7.
5.1.5
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 8.
23/67
Electrical characteristics
Figure 7.
STM32F103xx
Pin loading conditions
Figure 8.
Pin input voltage
STM32F103xx pin
STM32F103xx pin
C = 50 pF
VIN
ai14141
Power supply scheme
Figure 9.
Power supply scheme
VBAT
3.3 V
Backup circuitry
(OSC32K,RTC,
Wake-up logic
Backup registers)
Po wer swi tch
1.8-3.6 V
OUT
GP I/Os
IN
Level shifter
5.1.6
ai14142
IO
Logic
Kernel logic
(CPU,
Digital
& Memories)
VDD
VDD
1/2/3/4/5
5 × 100 nF
+ 1 × 10 µF
Regulator
VSS
1/2/3/4/5
3.3V
VDD
VDDA
VREF
10 nF
+ 1 µF
10 nF
+ 1 µF
VREF+
VREF-
ADC
Analog:
RCs, PLL,
...
VSSA
ai14125
24/67
STM32F103xx
5.1.7
Electrical characteristics
Current consumption measurement
Figure 10. Current consumption measurement scheme
IDD_VBAT
VBAT
IDD
VDD
VDDA
ai14126
25/67
Electrical characteristics
5.2
STM32F103xx
Absolute maximum ratings
Stresses above the absolute maximum ratings listed in Table 4: Voltage characteristics,
Table 5: Current characteristics, and Table 6: Thermal characteristics may cause permanent
damage to the device. These are stress ratings only and functional operation of the device
at these conditions is not implied. Exposure to maximum rating conditions for extended
periods may affect device reliability.
Table 4.
Voltage characteristics
Symbol
Ratings
Min
Max
–0.3
4.0
Input voltage on five volt tolerant pin(2)
VSS −0.3
+5.5
Input voltage on any other pin(2)
VSS − 0.3
VDD+0.3
Variations between different power pins
50
50
Variations between all the different ground pins
50
50
External 3.3 V supply voltage (including VDDA
and VDD)(1)
VDD–VSS
VIN
|∆VDDx|
Unit
V
mV
|VSSX − VSS|
Electrostatic discharge voltage (human body
model)
VESD(HBM)
see Section 5.3.11:
Absolute maximum ratings
(electrical sensitivity)
1. All 3.3 V power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external 3.3 V
supply.
2. IINJ(PIN) must never be exceeded (see Table 5: Current characteristics). This is implicitly insured if VIN
maximum is respected. If VIN maximum cannot be respected, the injection current must be limited
externally to the IINJ(PIN) value. A positive injection is induced by VIN>VDD while a negative injection is
induced by VIN < VSS.
Table 5.
Current characteristics
Symbol
Ratings
Max.
IVDD
Total current into VDD power lines (source)(1)
150
IVSS
Total current out of VSS ground lines (sink)(1)
150
Output current sunk by any I/O and control pin
25
Output current source by any I/Os and control pin
−25
Injected current on NRST pin
±5
Injected current on HSE OSC_IN and LSE OSC_IN pins
±5
Injected current on any other pin(4)
±5
IIO
IINJ(PIN) (2)(3)
ΣIINJ(PIN)
(2)
Total injected current (sum of all I/O and control
pins)(4)
Unit
mA
± 25
1. All 3.3 V power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external 3.3 V
supply.
2. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum
cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive
injection is induced by VIN > VDD while a negative injection is induced by VIN < VSS.
3. Negative injection disturbs the analog performance of the device. See note in Section 5.3.17: 12-bit ADC
characteristics.
4. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the
positive and negative injected currents (instantaneous values). These results are based on
characterization with ΣIINJ(PIN) maximum current injection on four I/O port pins of the device.
26/67
STM32F103xx
Electrical characteristics
Table 6.
Thermal characteristics
Symbol
Ratings
Value
Unit
TSTG
Storage temperature range
–65 to +150
°C
TJ
Maximum junction temperature (see Thermal characteristics)
5.3
Operating conditions
5.3.1
General operating conditions
Table 7.
5.3.2
General operating conditions
Symbol
Parameter
fHCLK
Conditions
Min
Max
Unit
Internal AHB clock frequency
0
72
fPCLK1
Internal APB1 clock frequency
0
36
fPCLK2
Internal APB2 clock frequency
0
72
VDD
Standard operating voltage
2
3.6
V
VBAT
Backup operating voltage
1.8
3.6
V
TA
Ambient temperature range
−40
105
°C
MHz
Operating conditions at power-up / power-down
The parameters given in Table 8 are derived from tests performed under the ambient
temperature condition summarized in Table 7.
Table 8.
Operating conditions at power-up / power-down
Symbol
Parameter
tVDD
VDD rise/fall time rate
Conditions
Min Typ Max Unit
20
µs/V
20
ms/V
27/67
Electrical characteristics
5.3.3
STM32F103xx
Embedded reset and power control block characteristics
The parameters given in Table 9 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Table 7.
Table 9.
Symbol
VPVD
Embedded reset and power control block characteristics
Parameter
Programmable voltage
detector level selection
VPVDhyst
PVD hysteresis
VPOR/PDR
Power on/power down reset
threshold
VPDRhyst
PDR hysteresis
Conditions
Min Typ Max
PLS[2:0]=000 (rising edge)
2.1
2.18 2.26
V
PLS[2:0]=000 (falling edge)
2
2.08 2.16
V
PLS[2:0]=001 (rising edge)
2.19 2.28 2.37
V
PLS[2:0]=001 (falling edge)
2.09 2.18 2.27
V
PLS[2:0]=010 (rising edge)
2.28 2.38 2.48
V
PLS[2:0]=010 (falling edge)
2.18 2.28 2.38
V
PLS[2:0]=011 (rising edge)
2.38 2.48 2.58
V
PLS[2:0]=011 (falling edge)
2.28 2.38 2.48
V
PLS[2:0]=100 (rising edge)
2.47 2.58 2.69
V
PLS[2:0]=100 (falling edge)
2.37 2.48 2.59
V
PLS[2:0]=101 (rising edge)
2.57 2.68 2.79
V
PLS[2:0]=101 (falling edge)
2.47 2.58 2.69
V
PLS[2:0]=110 (rising edge)
2.66 2.78
2.9
V
PLS[2:0]=110 (falling edge)
2.56 2.68
2.8
V
PLS[2:0]=111 (rising edge)
2.76 2.88
3
V
PLS[2:0]=111 (falling edge)
2.66 2.78
2.9
V
100
Falling edge
1.8
Rising edge
1.84 1.92
mV
1.88 1.96
2.0
40
TRSTTEMPO Reset temporization
5.3.4
Unit
1
2.5
V
V
mV
4.5
mS
Embedded reference voltage
The parameters given in Table 10 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Table 7.
Table 10.
Symbol
VREFINT
28/67
Embedded internal reference voltage
Parameter
Internal reference voltage
Conditions
Min
Typ
Max
Unit
−45°C < TA < +105°C
1.16
1.20
1.26
V
−45°C < TA < +85°C
1.16
1.20
1.24
V
STM32F103xx
5.3.5
Electrical characteristics
Supply current characteristics
The current consumption is measured as described in Figure 10: Current consumption
measurement scheme.
Maximum current consumption
The MCU is placed under the following conditions:
●
All I/O pins are in input mode with a static value at VDD or VSS (no load)
●
All peripherals are disabled except if it is explicitly mentioned
●
The Flash access time is adjusted to fHCLK frequency (0 wait state from 0 to 24 MHz, 1
wait state from 24 to 48 MHz and 2 wait states above)
The parameters given in Table 11 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Table 7.
Table 11.
Maximum current consumption in Run and Sleep modes(1)
Max(3)
Symbol
Parameter
Conditions
External clock with PLL, code running from
Flash, all peripherals enabled (see RCC
register description):
fPCLK1= fHCLK/2, fPCLK2 = fHCLK
Supply
current in
Run mode
IDD
External clock, PLL stopped, code running
from Flash, all peripherals enabled (see RCC
register description):
fPCLK1= fHCLK/2, fPCLK2 = fHCLK
External clock with PLL, code running from
RAM, all peripherals enabled (see RCC
register description):
fPCLK1= fHCLK/2, fPCLK2 = fHCLK
External clock, PLL stopped, code running
from RAM, all peripherals enabled (see RCC
register description):
fPCLK1= fHCLK/2, fPCLK2 = fHCLK
Supply
current in
Sleep mode
External clock with PLL, code running from
RAM or Flash, all peripherals enabled (see
RCC register description):
fPCLK1= fHCLK/2, fPCLK2 = fHCLK
External clock, PLL stopped, code running
from RAM or Flash, all peripherals enabled
(see RCC register description):
fPCLK1= fHCLK/2, fPCLK2 = fHCLK
FHCLK
Typ(2)
72 MHz
TA =
85 °C
TA=
105 °C
36
TBD
TBD
48 MHz
30
TBD
TBD
36 MHz
22
TBD
TBD
24 MHz
21
TBD
TBD
8 MHz
10
TBD
TBD
72 MHz
32
45
47
48 MHz
22
31
33
36 MHz
13
18
20
24 MHz
11
15
17
8 MHz
4.5
TBD
TBD
72 MHz
22
35
37
48 MHz
14
23
25
36 MHz
13
22
24
24 MHz
10
17
19
8 MHz
3.5
TBD
TBD
Unit
mA
mA
1. TBD stands for to be determined.
2. Typical values are measured at TA = 25 °C, and VDD = 3.3 V
3. Data based on characterization results, tested in production at VDmax, fHCLK max. TAmax, and code executed from RAM.
29/67
Electrical characteristics
Table 12.
STM32F103xx
Maximum current consumption in Stop and Standby modes(1)
Typ(2)
Symbol
Parameter
Supply current
in Stop mode
IDD
Supply current
in Standby
mode(5)
IDD_VBAT
Conditions
Max(3)
VDD/ VBAT VDD/VBAT
= 2.4 V
= 3.3 V
TA =
85 °C
TA =
105 °C
TBD
TBD
Regulator in Run mode,
Low-speed and high-speed internal
RC oscillators and high-speed
oscillator OFF (no independent
watchdog)
TBD
24
Regulator in Low Power mode,
Low-speed and high-speed internal
RC oscillators and high-speed
oscillator OFF (no independent
watchdog)
TBD(4)
14(4)
TBD(4) TBD(4)
Low-speed internal RC oscillator and
independent watchdog OFF, lowspeed oscillator and RTC OFF
TBD(4)
2(4)
TBD(4) TBD(4)
1(4)
1.4(4)
TBD(4) TBD(4)
Backup domain
Low-speed oscillator and RTC ON
supply current
Unit
µA
1. TBD stands for to be determined.
2. Typical values are measured at TA = 25 °C, VDD = 3.3 V, unless otherwise specified.
3. Data based on characterization results, tested in production at VDD max, fHCLK max. and TA max (for other temperature.
4. Values expected for next silicon revision.
5. To have the Standby consumption with RTC ON, add IDD_VBAT (Low-speed oscillator and RTC ON) to IDD Standby (when
VDD is present the Backup Domain is powered by VDD supply).
30/67
STM32F103xx
Electrical characteristics
Typical current consumption
The MCU is placed under the following conditions:
●
All I/O pins are in input mode with a static value at VDD or VSS (no load).
●
All peripherals are disabled except if it is explicitly mentioned.
●
The Flash access time is adjusted to fHCLK frequency (0 wait state from 0 to 24 MHz, 1
wait state from 24 to 48 MHZ and 2 wait states above).
●
Ambient temperature and VDD supply voltage conditions summarized in Table 7.
Table 13.
Symbol
Typical current consumption in Run and Sleep modes(1)
Parameter
Conditions
Oscillator running at 8 MHz with PLL, code
running from Flash, all peripheral disabled
(see RCC register description): fPCLK1=
fHCLK/2, fPCLK2=fHCLK
Supply
current in
Run mode
Running on HSI clock, code running from
Flash, all peripheral disabled (see RCC
register description): fPCLK1= fHCLK/2,
fPCLK2=fHCLK. AHB pre-scaler used to
reduce the frequency
Running on HSI clock, code running from
RAM, all peripheral disabled (see RCC
register description): fPCLK1= fHCLK/2,
fPCLK2=fHCLK. AHB pre-scaler used to
reduce the frequency
IDD
fHCLK
Typ(2)
72 MHz
21
48 MHz
18
36 MHz
TBD
24 MHz
13
16 MHz
TBD
8 MHz
7.8
4 MHz
7
2 MHz
6.3
1 MHz
6.2
500 kHz
6.1
125 kHz
5.95
8 MHz
2.3
4 MHz
1.6
2 MHz
1.2
1 MHz
1
500 kHz
0.88
125 kHz
0.82
72 MHz
6
48 MHz
TBD
36 MHz
TBD
24 MHz
TBD
16 MHz
1
8 MHz
TBD
4 MHz
TBD
2 MHz
TBD
1 MHz
TBD
500 kHz
TBD
Unit
mA
mA
mA
mA
Oscillator running at 8MHz with PLL, code
running from Flash, all peripheral disabled
(see RCC register description): fPCLK1=
fHCLK/2, fPCLK2=fHCLK
Supply
current in
Sleep mode
Running on HSI clock, code running from
Flash, all peripheral disabled (see RCC
register description): fPCLK1= fHCLK/2,
fPCLK2=fHCLK. AHB pre-scaler used to
reduce the frequency
mA
1. TBD stands for to be determined.
2. Typical values are measures at TA = 25 °C, VDD = 3.3 V.
31/67
Electrical characteristics
Table 14.
Symbol
STM32F103xx
Typical current consumption in Stop and Standby modes(1)
Conditions
VDD
Typ(2)
Regulator in Run mode,
Low-speed and high-speed internal RC
oscillators OFF
High-speed oscillator OFF (no
independent watchdog)
3.3 V
24
2.4 V
TBD
Regulator in Low Power mode,
Low-speed and high-speed internal RC
oscillators OFF,
High-speed oscillator OFF (no
independent watchdog)
3.3 V
14(3)
2.4 V
TBD(3)
Low-speed internal RC oscillator and
independent watchdog OFF
3.3 V
2(3)
2.4 V
TBD(3)
Low-speed internal RC oscillator and
independent watchdog ON
3.3 V
3.1(3)
2.4 V
TBD(3)
Low-speed internal RC oscillator ON,
independent watchdog OFF
3.3 V
2.9(3)
2.4 V
TBD(3)
3.3 V
1.4(3)
2.4 V
1(3)
3.3 V
0.5(3)
2.4 V
TBD(3)
Parameter
Supply current in
Stop mode
IDD
Supply current in
Standby mode(4)
Low-speed oscillator and RTC ON
IDD_VBAT
Backup domain
supply current
Low-speed oscillator OFF, RTC ON
Unit
1. TBD stands for to be determined.
2. Typical values are measures at TA = 25 °C, VDD = 3.3 V.
3. Values expected for next silicon revision.
4. To obtain Standby consumption with RTC ON, add IDD_VBAT (Low-speed oscillator and RTC ON) to IDD
Standby.
32/67
µA
µA
µA
STM32F103xx
5.3.6
Electrical characteristics
External clock source characteristics
High-speed external user clock
The characteristics given in Table 15 result from tests performed using an high-speed
external clock source, and under ambient temperature and supply voltage conditions
summarized in Table 7.
Table 15.
High-speed external (HSE) user clock characteristics
Symbol
Parameter
Conditions
Min
fHSE_ext
User external clock source
frequency(1)
VHSEH
OSC_IN input pin high level
voltage
VHSEL
OSC_IN input pin low level
voltage
VSS
tw(HSE)
tw(HSE)
OSC_IN high or low time(1)
16
Typ
Max
Unit
8
25
MHz
VDD
0.7VDD
V
tr(HSE)
tf(HSE)
IL
0.3VDD
ns
OSC_IN rise or fall
time(1)
OSC_IN Input leakage
current
5
VSS ≤VIN ≤VDD
±1
µA
1. Value based on design simulation and/or technology characteristics. It is not tested in production.
Low-speed external user clock
The characteristics given in Table 16 result from tests performed using an low-speed
external clock source, and under ambient temperature and supply voltage conditions
summarized in Table 7.
Table 16.
Symbol
Low-speed external user clock characteristics
Parameter
Conditions
Min
Typ
Max
Unit
32.768
1000
kHz
fLSE_ext
User External clock source
frequency(1)
VLSEH
OSC32_IN input pin high level
voltage
0.7VDD
VDD
VLSEL
OSC32_IN input pin low level
voltage
VSS
0.3VDD
tw(LSE)
tw(LSE)
OSC32_IN high or low time(1)
450
tr(LSE)
tf(LSE)
OSC32_IN rise or fall time(1)
V
IL
ns
OSC32_IN Input leakage
current
5
VSS ≤VIN ≤VDD
±1
µA
1. Value based on design simulation and/or technology characteristics. It is not tested in production.
33/67
Electrical characteristics
STM32F103xx
Figure 11. High-speed external clock source AC timing diagram
VHSEH
90%
VHSEL
10%
tr(HSE)
tf(HSE)
tW(HSE)
tW(HSE)
t
THSE
EXTER NAL
CLOCK SOURC E
fHSE_ext
OSC _IN
IL
STM32F103xx
ai14143
Figure 12. Low-speed external clock source AC timing diagram
VLSEH
90%
VLSEL
10%
tr(LSE)
tf(LSE)
tW(LSE)
OSC32_IN
IL
tW(LSE)
t
TLSE
EXTER NAL
CLOCK SOURC E
fLSE_ext
STM32F103xx
ai14144b
34/67
STM32F103xx
Electrical characteristics
High-speed external clock
The high-speed external (HSE) clock can be supplied with a 4 to 16 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on characterization
results obtained with typical external components specified in Table 17. In the application,
the resonator and the load capacitors have to be placed as close as possible to the oscillator
pins in order to minimize output distortion and startup stabilization time. Refer to the crystal
resonator manufacturer for more details on the resonator characteristics (frequency,
package, accuracy).
Table 17.
Symbol
fOSC_IN
RF
CL1
CL2(2)
HSE 4-16 MHz oscillator characteristics(1)
Parameter
Conditions
Oscillator frequency
Min
Typ
Max
Unit
4
8
16
MHz
Feedback resistor
Recommended load capacitance
versus equivalent serial
resistance of the crystal (RS)(3)
i2
HSE driving current
gm
Oscillator Transconductance
RS = 30 Ω
200
kΩ
30
pF
VDD= 3.3 V
VIN=VSS with 30 pF
load
Startup
tSU(HSE)(4) startup time
1
25
mA
mA/V
VSS is stabilized
2
ms
1. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
2. For CL1 and CL2 it is recommended to use high-quality ceramic capacitors in the 5 pF to 25pF range (typ.),
designed for high-frequency applications, and selected to match the requirements of the crystal or
resonator. CL1 and CL2, are usually the same size. The crystal manufacturer typically specifies a load
capacitance which is the series combination of CL1 and CL2. PCB and MCU pin capacitance must be
included when sizing CL1 and CL2 (10 pF can be used as a rough estimate of the combined pin and board
capacitance).
3. The relatively low value of the RF resistor offers a good protection against issues resulting from use in a
humid environment, due to the induced leakage and the bias condition change. However, it is
recommended to take this point into account if the MCU is used in tough humidity conditions.
4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz
oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly
with the crystal manufacturer
Figure 13. Typical application with a 8-MHz crystal
Resonator with
integrated capacitors
CL1
fHSE
OSC_IN
8 MH z
resonator
CL2
REXT(1)
RF
OSC_OU T
Bias
controlled
gain
STM32F103xx
ai14145
1. REXT value depends on the crystal characteristics. Typical value is in the range of 5 to 6RS.
35/67
Electrical characteristics
STM32F103xx
Low-speed external clock
The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on characterization
results obtained with typical external components specified in Table 18. In the application,
the resonator and the load capacitors have to be placed as close as possible to the oscillator
pins in order to minimize output distortion and startup stabilization time. Refer to the crystal
resonator manufacturer for more details on the resonator characteristics (frequency,
package, accuracy).
Table 18.
LSE oscillator characteristics (fLSE = 32.768 kHz)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
RF
Feedback resistor
CL1
CL2
Recommended load capacitance
versus equivalent serial
resistance of the crystal (RS)(1)
RS = 30 kΩ
15
pF
I2
LSE driving current
VDD = 3.3 V
VIN = VSS
1.4
µA
gm
Oscillator Transconductance
tSU(LSE)(2)
5
5
startup time
VSS is stabilized
MΩ
µA/V
3
s
1. The oscillator selection can be optimized in terms of supply current using an high quality resonator with
small RS value for example MSIV-TIN32.768kHz. Refer to crystal manufacturer for more details
2.
tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768
kHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary
significantly with the crystal manufacturer
Figure 14. Typical application with a 32.768 kHz crystal
Resonator with
integrated capacitors
CL1
fLSE
OSC32_IN
32.768 kH z
resonator
CL2
RF
OSC32_OU T
Bias
controlled
gain
STM32F103xx
ai14146
36/67
STM32F103xx
5.3.7
Electrical characteristics
Internal clock source characteristics
The parameters given in Table 19 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Table 7.
High-speed internal (HSI) RC oscillator
Table 19.
Symbol
fHSI
HSI oscillator characteristics(1)(2)
Parameter
Conditions
Min
Frequency
ACCHSI Accuracy of HSI oscillator
tsu(HSI)
HSI oscillator start up time
IDD(HSI)
HSI oscillator power
consumption
Typ
Max(3)
8
Unit
MHz
TA = –40 to 105 °C
TBD
±3
TBD
%
at TA = 25°C
TBD
±1
TBD
%
2
µs
80
100
µA
Typ
Max(2)
Unit
60
kHz
85
µs
1.2
µA
1
1. VDD = 3.3 V, TA = −40 to 105 °C unless otherwise specified.
2. TBD stands for to be determined.
3. Values based on device characterization, not tested in production.
LSI Low Speed Internal RC Oscillator
Table 20.
Symbol
fLSI
LSI oscillator characteristics (1)
Parameter
Conditions
Frequency
tsu(LSI)
LSI oscillator start up time
IDD(LSI)
LSI oscillator power
consumption
Min
30
0.65
1. VDD = 3 V, TA = −40 to 105 °C unless otherwise specified.
2. Value based on device characterization, not tested in production.
37/67
Electrical characteristics
STM32F103xx
Wakeup time from low power mode
The wakeup times given in Table 21 is measured on a wakeup phase with a 8-MHz HSI RC
oscillator. The clock source used to wake up the device depends from the current operating
mode:
●
Stop or Standby mode: the clock source is the RC oscillator
●
Sleep mode: the clock source is the clock that was set before entering Sleep mode.
All timings are derived from tests performed under ambient temperature and VDD supply
voltage conditions summarized in Table 7.
Table 21.
Symbol
Low-power mode wakeup timings(1)
Parameter
Conditions
tWUSLEEP(2) Wakeup from Sleep mode
tWUSTOP(2)
Wakeup on HSI RC clock
Typ
Max
Unit
0.75
TBD
µs
Wakeup from Stop mode
(regulator in run mode)
HSI RC wakeup time = 2 µs
4
TBD
Wakeup from Stop mode
(regulator in low power mode)
HSI RC wakeup time = 2 µs,
Regulator wakeup from LP
mode time = 5 µs
7
TBD
HSI RC wakeup time = 2 µs,
Regulator wakeup from power
down time = 38 µs
40
TBD
tWUSTDBY(3) Wakeup from Standby mode
µs
µs
1. TBD stands for to be determined.
2. The wakeup time from Sleep and Stop mode are measured from the wakeup event to the point in which the
user application code reads the first instruction.
3. The wakeup time from Standby mode is measured from the wakeup event to the point in which the device
exits from reset.
5.3.8
PLL characteristics
The parameters given in Table 22 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Table 7.
Table 22.
PLL characteristics(1)
Value
Symbol
Parameter
Test Conditions
Min
PLL input clock
fPLL_IN
fPLL_OUT
Max(2)
8.0
Unit
MHz
PLL input clock duty cycle
40
60
%
PLL multiplier output clock
16
72
MHz
32
144
MHz
200
µs
TBD
%
fVCO
VCO frequency range
tLOCK
PLL lock time
tJITTER
Cycle to cycle jitter (+/-3Σ
peak to peak)
When PLL operates
(locked)
VDD is stable
1. TBD stands for to be determined.
2. Data based on device characterization, not tested in production.
38/67
Typ
TBD
STM32F103xx
5.3.9
Electrical characteristics
Memory characteristics
Flash memory
The characteristics are given at TA = −40 to 105 °C unless otherwise specified.
Table 23.
Flash memory characteristics
Max(1)
Unit
20
40
µs
TA = −40 to +105 °C
20
40
ms
TA = −40 to +105 °C
20
40
ms
Read mode
fHCLK = 72 MHz with
2 wait states,
VDD = 3.3 V
20
mA
Write / Erase modes
fHCLK = 72 MHz,
VDD = 3.3 V
5
mA
Power-down mode /
HALT,
VDD = 3.0 to 3.6 V
50
µA
Symbol
Parameter
Conditions
Min
tprog
Word programming time
TA = −40 to +105 °C
tERASE
Page (1kB) erase time
tME
Mass erase time
IDD
Supply current
Typ
1. Values based on characterization and not tested in production.
Table 24.
Flash memory endurance and data retention
Value
Symbol
Parameter
NEND
Endurance
tRET
Data retention
Conditions
TA = 85 °C
Unit
Min(1)
Typ
1
10
30
Max
kcycles
Years
1. Values based on characterization not tested in production.
39/67
Electrical characteristics
5.3.10
STM32F103xx
EMC characteristics
Susceptibility tests are performed on a sample basis during device characterization.
Functional EMS (electromagnetic susceptibility)
While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the
device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
●
Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 1000-4-2 standard.
●
FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and
VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is
compliant with the IEC 1000-4-4 standard.
A device reset allows normal operations to be resumed.
The test results are given in Table 25. They are based on the EMS levels and classes
defined in application note AN1709.
Table 25.
EMS characteristics(1)
Symbol
Parameter
Conditions
Level/
Class
VFESD
VDD = 3.3 V, TA = +25 °C,
Voltage limits to be applied on any I/O pin to
fHCLK=48 MHz
induce a functional disturbance
conforms to IEC 1000-4-2
TBD
VEFTB
Fast transient voltage burst limits to be
VDD = 3.3 V, TA = +25 °C,
applied through 100pF on VDD and VSS pins fHCLK = 48 MHz
to induce a functional disturbance
conforms to IEC 1000-4-4
4A
1. TBD stands for to be determined.
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
40/67
●
Corrupted program counter
●
Unexpected reset
●
Critical Data corruption (control registers...)
STM32F103xx
Electrical characteristics
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1
second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).
Electromagnetic Interference (EMI)
The electromagnetic field emitted by the device are monitored while a simple application is
executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with SAE J
1752/3 standard which specifies the test board and the pin loading.
Table 26.
Symbol
SEMI
EMI characteristics
Parameter
Peak level
Conditions
Monitored
Frequency Band
0.1 to 30 MHz
VDD = 3.3 V, TA = 2 5 °C,
30 to 130 MHz
LQFP100 package
compliant with SAE J
130 MHz to 1GHz
1752/3
SAE EMI Level
Max vs. [fHSE/fHCLK]
Unit
8/48 MHz 8/72 MHz
12
12
22
19
23
29
4
4
dBµV
-
41/67
Electrical characteristics
5.3.11
STM32F103xx
Absolute maximum ratings (electrical sensitivity)
Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size is
either 3 parts (cumulative mode) or 3 parts × (n + 1) supply pins (non-cumulative mode).
The human body model (HBM) can be simulated. The tests are compliant with JESD22A114A standard.
For more details, refer to the application note AN1181.
Table 27.
ESD absolute maximum ratings(1)
Symbol
Ratings
Conditions
VESD(HBM)
Electrostatic discharge voltage
(human body model)
VESD(CDM)
Electrostatic discharge voltage
(charge device model)
Maximum value(2)
Unit
2000
TA = +25 °C
V
TBD
1. TBD stands for to be determined.
2. Values based on characterization results, not tested in production.
Static latch-up
Two complementary static tests are required on six parts to assess the latch-up
performance:
●
A supply overvoltage is applied to each power supply pin
●
A current injection is applied to each input, output and configurable I/O pin
These tests are compliant with EIA/JESD 78A IC latch-up standard.
Table 28.
Symbol
LU
42/67
Electrical sensitivities
Parameter
Static latch-up class
Conditions
TA = +105 °C
Class
II level A
STM32F103xx
5.3.12
Electrical characteristics
I/O port pin characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in Table 29 are derived from tests
performed under ambient temperature and VDD supply voltage conditions summarized in
Table 7.
All unused pins must be held at a fixed voltage, by using the I/O output mode, an external
pull-up or pull-down resistor (see Figure 15).
Table 29.
Symbol
VIL
VIH
I/O static characteristics(1)
Parameter
Conditions
Input low level voltage(2)
TTL ports
voltage(2)
VIL
Input low level
VIH
Input high level voltage(2)
Ilkg
Typ
Max
–0.5
0.8
2
VDD+0.5
2
5.5V
–0.5
0.35 VDD
0.65 VDD
VDD+0.5
Unit
V
IO TC input high level
voltage(2)
IO FT high level voltage(2)
Vhys
Min
CMOS ports
V
IO TC Schmitt trigger voltage
hysteresis(3)
200
mV
IO TC Schmitt trigger voltage
hysteresis(3)
5% VDD(4)
mV
Input leakage current
(5)
VSS ≤VIN ≤VDD
Standard I/Os
±1
VIN= 5 V
5 V tolerant I/Os
3
µA
RPU
Weak pull-up equivalent
resistor(6)
VIN = VSS
30
40
50
kΩ
RPD
Weak pull-down equivalent
resistor(6)
VIN = VDD
30
40
50
kΩ
CIO
I/O pin capacitance
5
pF
1. VDD = 3.3 V, TA = −40 to 105 °C unless otherwise specified.
2. Values based on characterization results, and not tested in production.
3. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.
4. With a minimum of 100 mV.
5. Leakage could be higher than max. if negative current is injected on adjacent pins.
6. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable
PMOS/NMOS. This MOS/NMOS contribution to the series resistance is minimum (~10% order).
43/67
Electrical characteristics
STM32F103xx
Figure 15. Unused I/O pin connection
VDD
1 0 kΩ
STM32F103xx
UNU SED I/O PORT
STM32F103xx
UNU SED I/O PORT
1 0 kΩ
ai14147b
Output driving current
The GPIOs (general purpose input/outputs) can sink or source up to +/-8 mA, and sink
+20 mA (with a relaxed VOL).
In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 5.2:
44/67
●
The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run
consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating
IVDD (see Table 5).
●
The sum of the currents sunk by all the I/Os on VSS plus the maximum Run
consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating
IVSS (see Table 5).
STM32F103xx
Electrical characteristics
Output voltage levels
Unless otherwise specified, the parameters given in Table 30 are derived from tests
performed under ambient temperature and VDD supply voltage conditions summarized in
Table 7.
Table 30.
Symbol
Output voltage characteristics
Parameter
VOL(1)
Output low level voltage for an I/O pin
when 8 pins are sunk at same time
VOH(2)
Output high level voltage for an I/O pin
when 4 pins are sourced at same time
VOL (1)
Output low level voltage for an I/O pin
when 8 pins are sunk at same time
VOH (2)
Output high level voltage for an I/O pin
when 4 pins are sourced at same time
VOL(1)
Output low level voltage for an I/O pin
when 8 pins are sunk at same time
VOH(2)
Output high level voltage for an I/O pin
when 4 pins are sourced at same time
VOL (1)
Output low level voltage for an I/O pin
when 8 pins are sunk at same time
VOH (2)
Output high level voltage for an I/O pin
when 4 pins are sourced at same time
Conditions
TTL port
IIO = +8 mA
2.7 V < VDD < 3.6 V
CMOS port
IIO =+ 8mA
2.7 V < VDD < 3.6 V
IIO = +20 mA
2.7 V < VDD < 3.6 V
IIO = +6 mA
2 V < VDD < 2.7 V
Min
Max
Unit
0.4
V
VDD–0.4
0.4
V
2.4
1.3
V
VDD–1.3
0.4
V
VDD–0.4
1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 5
and the sum of IIO (I/O ports and control pins) must not exceed IVSS.
2. The IIO current sourced by the device must always respect the absolute maximum rating specified in
Table 5 and the sum of IIO (I/O ports and control pins) must not exceed IVDD.
45/67
Electrical characteristics
STM32F103xx
Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Figure 16 and
Table 31, respectively.
Unless otherwise specified, the parameters given in Table 31 are derived from tests
performed under ambient temperature and VDD supply voltage conditions summarized in
Table 7.
Table 31.
I/O
mode(1)
I/O AC characteristics(1)
Symbol
Parameter
fmax(IO)out Maximum frequency(2)
10
tf(IO)out
Output high to low level fall
time(3)
tr(IO)out
Output low to high level
rise time(3)
fmax(IO)out Maximum frequency(2)
01
tf(IO)out
Output high to low level fall
time(3)
tr(IO)out
Output low to high level
rise time(3)
Fmax(IO)out Maximum
11
tf(IO)out
tr(IO)out
-
tEXTIpw
frequency(2)
Conditions
Min Max Unit
CL = 50 pF, VDD = 2 V to 3.6 V
2
125
CL = 50 pF, VDD = 2 V to 3.6 V
ns
125
CL = 50 pF, VDD = 2 V to 3.6 V
10
CL = 50 pF, VDD = 2 V to 3.6 V
ns
25
CL = 30 pF, VDD = 2.7 V to 3.6 V
50
MHz
CL = 50 pF, VDD = 2.7 V to 3.6 V
30
MHz
CL = 50 pF, VDD = 2 V to 2.7 V
20
MHz
12
CL = 30 pF, VDD = 2.7 V to 3.6 V
5
CL = 50 pF, VDD = 2.7 V to 3.6 V
8
CL = 50 pF, VDD = 2 V to 2.7 V
12
Pulse width of external
signals detected by the
EXTI controller
5
8
ns
10
1. Refer to the Reference user manual UM0306 for a description of GPIO Port configuration register.
2. The maximum frequency is defined in Figure 16.
3. Values based on design simulation and validated on silicon, not tested in production.
46/67
MHz
25
CL = 30 pF, VDD = 2.7 V to 3.6 V
Output high to low level fall
CL = 50 pF, VDD = 2.7 V to 3.6 V
time(3)
CL = 50 pF, VDD = 2 V to 2.7 V
Output low to high level
rise time(3)
MHz
ns
STM32F103xx
Electrical characteristics
Figure 16. I/O AC characteristics definition
90%
10%
50%
50%
90%
10%
EXT ERNAL
OUTPUT
ON 50pF
tr(I O)out
tr(I O)out
T
Maximum frequency is achieved if (tr + tf) £ 2/3)T and if the duty cycle is (45-55%)
when loaded by 50pF
ai14131
5.3.13
NRST pin characteristics
The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, RPU (see Table 29).
Unless otherwise specified, the parameters given in Table 32 are derived from tests
performed under ambient temperature and VDD supply voltage conditions summarized in
Table 7.
Table 32.
Symbol
NRST pin characteristics(1)
Parameter
Conditions
Min
Typ
Max
VIL(NRST)
NRST Input low level voltage
–0.5
0.8
VIH(NRST)
NRST Input high level voltage
2
VDD+0.5
Vhys(NRST)
NRST Schmitt trigger voltage
hysteresis
RPU
Unit
V
Weak pull-up equivalent resistor(2)
200
VIN = VSS
30
(3)
VF(NRST)
NRST Input filtered pulse
VNF(NRST)
NRST Input not filtered pulse(3)
300
40
50
kΩ
100
ns
µs
1. TBD stands for to be determined.
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution
to the series resistance must be minimum (~10% order).
3. Values guaranteed by design, not tested in production.
47/67
Electrical characteristics
STM32F103xx
Figure 17. Recommended NRST pin protection
VDD
External
reset circuit
NRST
RPU
Internal Reset
FILTER
0.1 µF
STM32F101xx
ai14132b
2. The reset network protects the device against parasitic resets.
3. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 32. Otherwise the reset will not be taken into account by the device.
5.3.14
TIM timer characteristics
Unless otherwise specified, the parameters given in Table 33 are derived from tests
performed under ambient temperature, fPCLKx frequency and VDD supply voltage conditions
summarized in Table 7.
Refer to Section 5.3.12: I/O port pin characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).
Table 33.
Symbol
tres(TIM)
fEXT
ResTIM
tCOUNTER
TIMx(1) characteristics
Parameter
Conditions
Min
Max
1
tTIMxCLK
13.9
ns
Timer resolution time
fTIMxCLK = 72 MHz
Timer external clock
frequency on CH1 to CH4 f
TIMxCLK = 72 MHz
0
fTIMxCLK/2
MHz
0
36
MHz
16
bit
65536
tTIMxCLK
910
µs
65536 × 65536
tTIMxCLK
59.6
s
Timer resolution
16-bit counter clock period
1
when internal clock is
fTIMxCLK = 72 MHz 0.0139
selected
tMAX_COUNT Maximum possible count
fTIMxCLK = 72 MHz
1. TIMx is used as a general term to refer to the TIM1, TIM2, TIM3 and TIM4 timers.
48/67
Unit
STM32F103xx
5.3.15
Electrical characteristics
Communications interfaces
I2C interface characteristics
Unless otherwise specified, the parameters given in Table 34 are derived from tests
performed under ambient temperature, fPCLK1 frequency and VDD supply voltage conditions
summarized in Table 7.
The STM32F103xx performance line I2C interface meets the requirements of the standard
I2C communication protocol with the following restrictions: the I/O pins SDA and SCL are
mapped to are not “true” open-drain. When configured as open-drain, the PMOS connected
between the I/O pin and VDD is disabled, but is still present. In addition, there is a protection
diode between the I/O pin and VDD. As a consequence, when multiple master devices are
connected to the I2C bus, it is not possible to power off the STM32F103xx while another I2C
master node remains powered on. Otherwise, the STM32F103xx would be powered by the
protection diode.
The I2C characteristics are described in Table 34. Refer also to Section 5.3.12: I/O port pin
characteristics for more details on the input/output alternate function characteristics (SDA
and SCL).
Table 34.
I2C characteristics
Standard mode I2C(1)
Symbol
Fast mode I2C(1)(2)
Parameter
Unit
Min
Max
Min
Max
tw(SCLL)
SCL clock low time
4.7
1.3
tw(SCLH)
SCL clock high time
4.0
0.6
tsu(SDA)
SDA setup time
250
100
th(SDA)
SDA data hold time
0(3)
0(4)
900(3)
tr(SDA)
tr(SCL)
SDA and SCL rise time
1000
20 + 0.1Cb
300
tf(SDA)
tf(SCL)
SDA and SCL fall time
300
20 + 0.1Cb
300
th(STA)
Start condition hold time
4.0
0.6
tsu(STA)
Repeated Start condition
setup time
4.7
0.6
tsu(STO)
Stop condition setup time
4.0
0.6
µs
tw(STO:STA)
Stop to Start condition time
(bus free)
4.7
1.3
µs
Cb
Capacitive load for each bus
line
µs
ns
µs
400
400
pF
1. Values based on standard I2C protocol requirement, not tested in production.
2. fPCLK1 must be higher than 2 MHz to achieve the maximum standard mode I2C frequency. It must be
higher than 4 MHz to achieve the maximum fast mode I2C frequency.
3. The maximum hold time of the Start condition has only to be met if the interface does not stretch the low
period of SCL signal.
4. The device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the
undefined region of the falling edge of SCL.
49/67
Electrical characteristics
STM32F103xx
Figure 18. I2C bus AC waveforms and measurement circuit
VDD
VDD
4 .7 kΩ
4 .7 kΩ
100Ω
STM32F103xx
SDA
I2C bus
100Ω
SCL
S TART REPEATED
S TART
S TART
tsu(STA)
SDA
tf(SDA)
tr(SDA)
tw(SCKL)
th(STA)
SCL
tw(SCKH)
tsu(SDA)
tr(SCK)
th(SDA)
tsu(STA:STO)
S TOP
tsu(STO)
tf(SCK)
ai14149b
1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.
Table 35.
SCL frequency (fPCLK1= 36 MHz.,VDD = 3.3 V)(1)(2)(3)
I2C_CCR value
fSCL (kHz)
RP = 4.7 kΩ
400
TBD
300
TBD
200
TBD
100
TBD
50
TBD
20
TBD
1. TBD = to be determined.
2. RP = External pull-up resistance, fSCL = I2C speed,
3. For speeds around 200 kHz, the tolerance on the achieved speed is of ±5%. For other speed ranges, the
tolerance on the achieved speed ±2%. These variations depend on the accuracy of the external
components used to design the application.
50/67
STM32F103xx
Electrical characteristics
SPI interface characteristics
Unless otherwise specified, the parameters given in Table 36 are derived from tests
performed under ambient temperature, fPCLKx frequency and VDD supply voltage conditions
summarized in Table 7.
Refer to Section 5.3.12: I/O port pin characteristics for more details on the input/output
alternate function characteristics (NSS, SCK, MOSI, MISO).
Table 36.
Symbol
fSCK
1/tc(SCK)
tr(SCK)
tf(SCK)
SPI characteristics(1)
Parameter
Conditions
Min
Max
Master mode
TBD
TBD
Slave mode
0
TBD
SPI clock frequency
SPI clock rise and fall
time
MHz
Capacitive load: C=50 pF
TBD
tsu(NSS)(2)
NSS setup time
Slave mode
0
th(NSS)(2)
NSS hold time
Slave mode
0
Master mode, fPCLK= TBD,
presc = TBD
TBD
Master mode
TBD
Slave mode
TBD
Master mode
TBD
Slave mode
TBD
Master mode, fPCLK= TBD
TBD(3)
Slave mode, fPCLK= TBD
TBD(3)
Slave mode
TBD
TBD
Slave mode, fPCLK= TBD
TBD
TBD
Slave mode
TBD
TBD
(2)
SCK high and low
tw(SCKH)
tw(SCKL)(2) time
tsu(MI) (2)
tsu(SI)(2)
th(MI) (2)
th(SI)(2)
Data input setup time
Data input hold time
ta(SO)(2)(4)
Data output access
time
tdis(SO)(2)(5)
Data output disable
time
tv(SO) (2)(1) Data output valid time
tv(MO)
(2)(1)
Data output valid time
th(SO)(2)
th(MO)(2)
Unit
Data output hold time
ns
Slave mode (after enable edge)
TBD
fPCLK= TBD
TBD
Master mode (after enable
edge)
TBD
fPCLK= TBD
TBD
Slave mode (after enable edge)
TBD
Master mode (after enable
edge)
TBD
TBD
1. TBD = to be determined.
2. Values based on design simulation and/or characterization results, and not tested in production.
3. Depends on fPCLK. For example, if fPCLK= 8MHz, then tPCLK = 1/fPLCLK =125 ns and tv(MO) = 255 ns.
4. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate
the data.
5. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put
the data in Hi-Z
51/67
Electrical characteristics
STM32F103xx
Figure 19. SPI timing diagram - slave mode and CPHA = 0
NSS input
SCK Input
tSU(NSS)
CPHA= 0
CPOL=0
tc(SCK)
th(NSS)
tw(SCKH)
tw(SCKL)
CPHA= 0
CPOL=1
tv(SO)
ta(SO)
MISO
OUT P UT
tr(SCK)
tf(SCK)
th(SO)
MS B O UT
BI T6 OUT
tdis(SO)
LSB OUT
tsu(SI)
MOSI
I NPUT
M SB IN
LSB IN
B I T1 IN
th(SI)
ai14134
1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.
Figure 20. SPI timing diagram - slave mode and CPHA = 11)
NSS input
SCK Input
tSU(NSS)
CPHA=1
CPOL=0
CPHA=1
CPOL=1
tc(SCK)
tw(SCKH)
tw(SCKL)
tv(SO)
ta(SO)
MISO
OUT P UT
MS B O UT
tsu(SI)
MOSI
I NPUT
th(NSS)
th(SO)
BI T6 OUT
tr(SCK)
tf(SCK)
tdis(SO)
LSB OUT
th(SI)
M SB IN
B I T1 IN
LSB IN
ai14135
52/67
STM32F103xx
Electrical characteristics
Figure 21. SPI timing diagram - master mode
High
NSS input
SCK Input
CPHA= 0
CPOL=0
SCK Input
tc(SCK)
CPHA=1
CPOL=0
CPHA= 0
CPOL=1
CPHA=1
CPOL=1
tw(SCKH)
tw(SCKL)
tsu(MI)
MISO
INP UT
tr(SCK)
tf(SCK)
MS BIN
BI T6 IN
LSB IN
th(MI)
MOSI
OUTUT
M SB OUT
B I T1 OUT
tv(MO)
LSB OUT
th(MO)
ai14136
1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.
USB characteristics
The USB interface is USB-IF certified (Full Speed).
Table 37.
USB DC electrical characteristics
Symbol
Parameter
Conditions
Min.(1)
Max.(1)
Unit
Input levels
VDI
Differential input sensitivity
I(USBDP, USBDM)
0.2
VCM
Differential common mode
range
Includes VDI range
0.8
2.5
VSE
Single ended receiver
threshold
1.3
2.0
V
Output levels
VOL
VOH
Static output level low
Static output level high
RL of 1.5 kΩ to 3.6 V(2)
RL of 15 kΩ to
VSS(2)
0.3
V
2.8
3.6
1. All the voltages are measured from the local ground potential.
2. RL is the load connected on the USB drivers
53/67
Electrical characteristics
STM32F103xx
Figure 22. USB timings: definition of data signal rise and fall time
Crossover
points
Differen tial
Data L ines
VCRS
VS S
Table 38.
tr
tf
ai14137
USB: Full speed electrical characteristics
Symbol
Parameter
Conditions
Min
Max
Unit
tr
Rise time(1)
CL = 50 pF
4
20
ns
tf
Fall Time(1)
CL = 50 pF
4
20
ns
trfm
Rise/ fall time matching
tr/tf
90
110
%
VCRS
Output signal crossover voltage
1.3
2.0
V
Driver characteristics
1. Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB
Specification - Chapter 7 (version 2.0).
5.3.16
CAN (controller area network) interface
Refer to I/O port characteristics for more details on the input/output alternate function characteristics (CANTX and CANRX).
5.3.17
12-bit ADC characteristics
Unless otherwise specified, the parameters given in Table 39 are derived from tests
performed under ambient temperature, fPCLK2 frequency and VDDA supply voltage
conditions summarized in Table 7.
Note:
It is recommended to perform a calibration after each power-up.
Table 39.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
2.4V
3.6V
V
VDDA
ADC power supply
VREF+
Positive reference voltage
2.0
VDDA
V
ADC clock frequency
0.6
14
MHz
0.05
1
MHz
823
kHz
17
1/fADC
VDDA
V
fADC
fS
fTRIG
VAIN
54/67
ADC characteristics(1)
Sampling rate
TBD
External trigger frequency
Conversion voltage
range(2)
fADC = 14 MHz
VSSA
STM32F103xx
Electrical characteristics
Table 39.
ADC characteristics(1) (continued)
Symbol
RAIN
CAIN
Ilkg
Parameter
Conditions
Min
Typ
Max
Unit
External input impedance
kΩ
TBD(2)(3)
External capacitor on analog
input
pF
Negative input leakage current VIN < VSS, | IIN | < 400 µA
on analog pins
on adjacent analog pin
5
6
µA
RADC
Sampling switch resistance
1
kΩ
CADC
Internal sample and hold
capacitor
5
pF
tCAL
Calibration time
5.9
µs
83
1/fADC
fADC = 14MHz
0.214
tlat
Injection conversion latency
tS
Sampling time
tSTAB
Power-up time
tCONV
Total conversion time (including
sampling time)
fADC = 14 MHz
fADC = 14 MHz
3
0.107
0
0
1
fADC = 14 MHz
µs
1/fADC
17.1
µs
1
µs
18
µs
14 (1.5 for sampling
+12.5 for successive
approximation)
1/fADC
1. TBD = to be determined.
2. Depending on the input signal variation (fAIN), CAIN can be increased for stabilization time and reduced to
allow the use of a larger serial resistor (RAIN). It is valid for all fADC frequencies ≤14 MHz.
3. During the sample time the input capacitance CAIN (5 max) can be charged/discharged by the external
source. The internal resistance of the analog source must allow the capacitance to reach its final voltage
level within tS. After the end of the sample time tS, changes of the analog input voltage have no effect on
the conversion result. Values for the sample clock tS depend on programming.
Table 40.
ADC accuracy (fPCLK2 = 14 MHz, fADC = 14 MHz, RAIN <10 kΩ, VDDA =
3.3 V)(1)
Symbol
|ET|
|EO|
Parameter
Total unadjusted error(2)
Offset
error(2)
Error(2)
|EG|
Gain
|ED|
Differential linearity error(2)
|EL|
Integral linearity
error(2)
Conditions
Typ
Max
3
TBD
1
TBD
2
TBD
3
TBD
2
TBD
Unit
LSB
1. TBD = to be determined.
2. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any of the standard (nonrobust) analog input pins should be avoided as this significantly reduces the accuracy of the conversion
being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to
standard analog pins which may potentially inject negative current.
Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 5.3.12 does not
affect the ADC accuracy.
55/67
Electrical characteristics
STM32F103xx
Figure 23. ADC accuracy characteristics
EG
1023
1022
1021
1LSB
IDEAL
V
–V
DDA
SSA
= -----------------------------------------
1024
(2)
ET
(1)
6
4
ET=Total Unadjusted Error: maximum deviation
between the actual and the ideal transfer curves.
EO=Offset Error: deviation between the first actual
transition and the first ideal one.
EG=Gain Error: deviation between the last ideal
transition and the last actual one.
ED=Differential Linearity Error: maximum deviation
between actual steps and the ideal one.
EL=Integral Linearity Error: maximum deviation
between any actual transition and the end point
correlation line.
(3)
7
5
(1) Example of an actual transfer curve
(2) The ideal transfer curve
(3) End point correlation line
EO
EL
3
ED
2
1 LSBIDEAL
1
0
1
VSSA
2
3
4
5
6
7
1021 1022 1023 1024
VDDA
ai14395
Figure 24. Typical connection diagram using the ADC
VDD
STM32F103xx
VT
0.6V
RAIN
VAIN
RADC
AINx
CAIN(1)
VT
0.6V
IL±1mA
12-bit A/D
conversion
CADC
ai14150
1. Refer to Table 39 for the values of RADC and CADC.
2. CPARASITIC must be added to CAIN. It represents the capacitance of the PCB (dependent on soldering and
PCB layout quality) plus the pad capacitance (3 pF). A high CPARASITIC value will downgrade conversion
accuracy. To remedy this, fADC should be reduced.
56/67
STM32F103xx
Electrical characteristics
General PCB design guidelines
Power supply decoupling should be performed as shown in Figure 25 or Figure 26,
depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be
ceramic (good quality). They should be placed them as close as possible to the chip.
Figure 25. Power supply and reference decoupling (VREF+ not connected to VDDA)
STM32F103xx
VREF+
(see note 1)
1 µF // 10 nF
VDDA
1 µF // 10 nF
VSSA /VREF+
(see note 1)
ai14388
1. VREF+ and VREF– inputs are available only on 100-pin packages.
Figure 26. Power supply and reference decoupling (VREF+ connected to VDDA)
STM32F103xx
VREF+/VDDA
(See note 1)
1 µF // 10 nF
VREF–/VSSA
(See note 1)
ai14389
1. VREF+ and VREF– inputs are available only on 100-pin packages.
57/67
Electrical characteristics
5.3.18
Temperature sensor characteristics
Table 41.
TS characteristics
Symbol
Parameter
TL
VSENSE linearity with temperature
±1.5
°C
Average slope
4.478
mV/°C
1.4
V
Avg_Slope
V25
tSTART
58/67
STM32F103xx
Conditions
Min
Voltage at 25 °C
Startup time
4
Typ
Max
10
Unit
µs
STM32F103xx
6
Package characteristics
Package characteristics
Figure 27. LFBGA100 - low profile fine pitch ball grid array package outline
C
Seating plane
ddd C
A2 A4 A3
A1
A
D
B
D1
F
e
A
K
J
H
G
F
E
D
C
B
A
F
E1
E
e
1 2 3 4 5 6 7 8 9 10
A1 corner index area
(see note 5)
∅b (100
balls)
∅eee
M C A B
∅ fff M C
Bottom view
Table 42.
ai14396
LFBGA100 - low profile fine pitch ball grid array package mechanical data
mm
inches
Dim.
Min
Typ
A
A1
Max
Min
Typ
1.700
Max
0.067
0.270
0.011
A2
1.085
0.043
A3
0.30
0.012
A4
0.80
0.031
b
0.45
0.50
0.55
0.018
0.020
0.022
D
9.85
10.00
10.15
0.388
0.394
0.40
D1
E
7.20
9.85
10.00
0.283
10.15
0.388
0.394
E1
7.20
0.283
e
0.80
0.031
F
1.40
0.055
0.40
ddd
0.12
0.005
eee
0.15
0.006
fff
0.08
0.003
N (number of balls)
100
59/67
Package characteristics
STM32F103xx
Figure 28. Recommended PCB design rules (0.80/0.75 mm pitch BGA)
Dpad
0.37 mm
0.52 mm typ. (depends on solder
Dsm
mask registration tolerance
Solder paste 0.37 mm aperture diameter
– Non solder mask defined pads are recommended
– 4 to 6 mils screen print
Dpad
Dsm
60/67
STM32F103xx
Package characteristics
Figure 29. LQFP100 – 100-pin low-profile quad flat package outline
A
D
D1
A2
A1
b
e
E1
E
c
L1
L
h
ai14397
Table 43.
LQFP100 – 100-pin low-profile quad flat package mechanical data
mm
inches
Dim.
Min
Typ
A
Max
Min
Typ
1.60
A1
0.05
A2
1.35
b
0.17
C
0.09
Max
0.063
0.15
0.002
0.006
1.40
1.45
0.053
0.055
0.057
0.22
0.27
0.007
0.009
0.011
0.20
0.004
0.008
D
16.00
0.630
D1
14.00
0.551
E
16.00
0.630
E1
14.00
0.551
e
0.50
0.020
θ
0°
3.5°
7°
0°
3.5°
7°
L
0.45
0.60
0.75
0.018
0.024
0.030
L1
1.00
0.039
Number of pins
N
100
61/67
Package characteristics
STM32F103xx
Figure 30. LQFP64 – 64 pin low-profile quad flat package outline
D
A
D1
A2
A1
b
E1
E
e
c
L1
L
ai14398
Table 44.
LQFP64 – 64 pin low-profile quad flat package mechanical data
mm
inches
Dim.
Min
Typ
A
Max
Min
1.60
A1
0.05
A2
1.35
b
0.17
c
0.09
Max
0.063
0.15
0.002
0.006
1.40
1.45
0.053
0.055
0.057
0.22
0.27
0.007
0.009
0.011
0.20
0.004
0.008
D
12.00
0.472
D1
10.00
0.394
E
12.00
0.472
E1
10.00
0.394
e
0.50
0.020
θ
0°
3.5°
7°
0°
3.5°
7°
L
0.45
0.60
0.75
0.018
0.024
0.030
L1
1.00
0.039
Number of pins
N
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Typ
64
STM32F103xx
Package characteristics
Figure 31. LQFP48 – 48 pin low-profile quad flat package outline
D
A
D1
A2
A1
b
E1
e
E
c
L1
L
ai14399
Table 45.
LQFP48 – 48 pin low-profile quad flat package mechanical data
inches(1)
mm
Dim.
Min
Typ
A
Max
Min
Typ
1.60
A1
0.05
A2
1.35
b
0.17
C
0.09
Max
0.063
0.15
0.002
0.006
1.40
1.45
0.053
0.055
0.057
0.22
0.27
0.007
0.009
0.011
0.20
0.004
0.008
D
9.00
0.354
D1
7.00
0.276
E
9.00
0.354
E1
7.00
0.276
e
0.50
0.020
θ
0°
3.5°
7°
0°
3.5°
7°
L
0.45
0.60
0.75
0.018
0.024
0.030
L1
1.00
0.039
Number of pins
N
48
1. Values in inches are converted from mm and rounded to 3 decimal digits.
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Package characteristics
6.1
STM32F103xx
Thermal characteristics
The average chip-junction temperature, TJ, in degrees Celsius, may be calculated using the
following equation:
TJ = TA + (PD x ΘJA)
(1)
Where:
●
TA is the Ambient Temperature in ° C,
●
ΘJA is the Package Junction-to-Ambient Thermal Resistance, in ° C/W,
●
PD is the sum of PINT and PI/O (PD = PINT + PI/O),
●
PINT is the product of IDD and VDD, expressed in Watts. This is the Chip Internal Power.
PI/O represents the Power Dissipation on Input and Output Pins;
Most of the time for the application PI/O < PINT and can be neglected. On the other hand, PI/O
may be significant if the device is configured to drive continuously external modules and/or
memories.
An approximate relationship between PD and TJ (if PI/O is neglected) is given by:
PD = K / (TJ + 273 °C)
(2)
Therefore (solving equations 1 and 2):
K = PD x (TA + 273°C) + ΘJA x PD2
(3)
where:
K is a constant for the particular part, which may be determined from equation (3) by
measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ
may be obtained by solving equations (1) and (2) iteratively for any value of TA.
Table 46.
Symbol
ΘJA
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Thermal characteristics
Parameter
Value
Thermal resistance junction-ambient
LFBGA100 - 10 x 10 mm / 0.5 mm pitch
41
Thermal resistance junction-ambient
LQFP100 - 14 x 14 mm / 0.5 mm pitch
46
Thermal Resistance Junction-Ambient
LQFP64 - 10 x 10 mm / 0.5 mm pitch
45
Thermal resistance junction-ambient
LQFP48 - 7 x 7 mm / 0.5 mm pitch
55
Unit
°C/W
STM32F103xx
7
Order codes
Order codes
Table 47.
Order codes
Flash program
memory
SRAM
memory
Kbytes
Kbytes
STM32F103C6T6
32
10
STM32F103C8T6
64
20
STM32F103R6T6
32
10
STM32F103R8T6
64
20
STM32F103RBT6
128
20
STM32F103V8T6
64
20
STM32F103VBT6
128
20
STM32F103V8H6
64
20
STM32F103VBH6
128
20
Part number
Package
LQFP48
LQFP64
LQFP100
LFBGA100
7.1
Future family enhancements
Further developments of the STM32F103xx performance line will see an expansion of the
current options. Larger packages will soon be available with up to 512KB Flash, 64KB
SRAM and with extended features such as EMI support, SDIO, I2S, DAC and additional
timers and USARTS.
65/67
Revision history
8
Revision history
Table 48.
Document revision history
Date
Revision
01-jun-2007
1
Initial release.
2
Flash memory size modified in Note 5, Note 4, Note 6, Note 7 and
BGA100 pins added to Table 3: Pin definitions. Figure 5: STM32F103xx
performance line BGA100 ballout added.
THSE changed to TLSE in Figure 12: Low-speed external clock source AC
timing diagram. VBAT ranged modified in Power supply schemes.
tSU(LSE) changed to tSU(HSE) in Table 17: HSE 4-16 MHz oscillator
characteristics. IDD(HSI) max value added to Table 19: HSI oscillator
characteristics.
Sample size modified and machine model removed in Electrostatic
discharge (ESD).
Number of parts modified and standard reference updated in Static
latch-up. 25 °C and 85 °C conditions removed and class name modified
in Table 28: Electrical sensitivities. RPU and RPD min and max values
added to Table 29: I/O static characteristics. RPU min and max values
added to Table 32: NRST pin characteristics.
Figure 18: I2C bus AC waveforms and measurement circuit and
Figure 17: Recommended NRST pin protection corrected.
Notes removed below Table 7, Table 32, Table 37.
IDD typical values changed in Table 11: Maximum current consumption in
Run and Sleep modes. Table 33: TIMx characteristics modified.
tSTAB, VREF+ value, tlat and fTRIG added to Table 39: ADC characteristics.
In Table 24: Flash memory endurance and data retention, typical
endurance and data retention for TA = 85 °C added, data retention for TA
= 25 °C removed.
VBG changed to VREFINT in Table 10: Embedded internal reference
voltage. Document title changed. Controller area network (CAN) section
modified.
Figure 9: Power supply scheme modified.
Features on page 1 list optimized. Small text changes.
20-Jul-2007
66/67
STM32F103xx
Changes
STM32F103xx
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