STMICROELECTRONICS STM32F100RCT6BTR

STM32F100xC STM32F100xD
STM32F100xE
High-density value line, advanced ARM-based 32-bit MCU with
256 to 512 KB Flash, 16 timers, ADC, DAC & 11 comm interfaces
Datasheet −production data
Features
■
Core: ARM 32-bit Cortex™-M3 CPU
– 24 MHz maximum frequency, 1.25 DMIPS
/MHz (Dhrystone 2.1) performance
– Single-cycle multiplication and hardware
division
■
Memories
– 256 to 512 Kbytes of Flash memory
– 24 to 32 Kbytes of SRAM
– Flexible static memory controller with 4
Chip Selects. Supports SRAM, PSRAM
and NOR memories
– LCD parallel interface, 8080/6800 modes
■
Clock, reset and supply management
– 2.0 to 3.6 V application supply and I/Os
– POR, PDR and programmable voltage
detector (PVD)
– 4-to-24 MHz crystal oscillator
– Internal 8 MHz factory-trimmed RC
– Internal 40 kHz RC
– PLL for CPU clock
– 32 kHz oscillator for RTC with calibration
■
Low power
– Sleep, Stop and Standby modes
– VBAT supply for RTC and backup registers
■
Serial wire debug (SWD) and JTAG I/F
■
DMA
– 12-channel DMA controller
– Peripherals supported: timers, ADC, SPIs,
I2Cs, USARTs and DACs
■
1 × 12-bit, 1.2 µs A/D converter (up to 16 ch.)
– Conversion range: 0 to 3.6 V
– Temperature sensor
■
2 × 12-bit D/A converters
■
Up to 112 fast I/O ports
– 51/80/112 I/Os, all mappable on 16
external interrupt vectors and almost all
5 V-tolerant
September 2012
This is information on a product in full production.
LQFP144
20 × 20 mm
LQFP100
14 × 14 mm
LQFP64
10 × 10 mm
■
Up to 16 timers
– Up to seven 16-bit timers, each with up to 4
IC/OC/PWM or pulse counter
– One 16-bit, 6-channel advanced-control
timer: up to 6 channels for PWM output,
dead time generation and emergency stop
– One 16-bit timer, with 2 IC/OC, 1
OCN/PWM, dead-time generation and
emergency stop
– Two 16-bit timers, each with
IC/OC/OCN/PWM, dead-time generation
and emergency stop
– Two watchdog timers
– SysTick timer: 24-bit downcounter
– Two 16-bit basic timers to drive the DAC
■
Up to 11 communications interfaces
– Up to two I2C interfaces (SMBus/PMBus)
– Up to 3 USARTs (ISO 7816 interface, LIN,
IrDA capability, modem control)
– Up to 2 UARTs
– Up to 3 SPIs (12 Mbit/s)
– Consumer electronics control (CEC) I/F
■
CRC calculation unit, 96-bit unique ID
Table 1.
Device summary
Reference
Part number
STM32F100xC
STM32F100RC, STM32F100VC,
STM32F100ZC
STM32F100xD
STM32F100RD, STM32F100VD,
STM32F100ZD
STM32F100xE
STM32F100RE, STM32F100VE,
STM32F100ZE
Doc ID 15081 Rev 7
1/98
www.st.com
1
Contents
STM32F100xC, STM32F100xD, STM32F100xE
Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3
2/98
2.1
Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.2.1
ARM® Cortex™-M3 core with embedded Flash and SRAM . . . . . . . . . 13
2.2.2
Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.2.3
CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . 13
2.2.4
Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.2.5
FSMC (flexible static memory controller) . . . . . . . . . . . . . . . . . . . . . . . . 13
2.2.6
LCD parallel interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.2.7
Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 14
2.2.8
External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . 14
2.2.9
Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.2.10
Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.2.11
Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.2.12
Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.2.13
Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.2.14
Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.2.15
DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.2.16
RTC (real-time clock) and backup registers . . . . . . . . . . . . . . . . . . . . . . 16
2.2.17
Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.2.18
I²C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.2.19
Universal synchronous/asynchronous receiver transmitter (USART) . . 19
2.2.20
Universal asynchronous receiver transmitter (UART) . . . . . . . . . . . . . . 19
2.2.21
Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.2.22
GPIOs (general-purpose inputs/outputs) . . . . . . . . . . . . . . . . . . . . . . . . 20
2.2.23
Remap capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.2.24
ADC (analog-to-digital converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.2.25
DAC (digital-to-analog converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.2.26
Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.2.27
Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 21
Pinouts and pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Doc ID 15081 Rev 7
STM32F100xC, STM32F100xD, STM32F100xE
Contents
4
Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.1
6
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.1.1
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.1.2
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.1.3
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.1.4
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.1.5
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.1.6
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.1.7
Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.2
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.3
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5.3.1
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5.3.2
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 38
5.3.3
Embedded reset and power control block characteristics . . . . . . . . . . . 39
5.3.4
Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5.3.5
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5.3.6
External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
5.3.7
Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
5.3.8
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
5.3.9
Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
5.3.10
FSMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
5.3.11
EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
5.3.12
Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 67
5.3.13
I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
5.3.14
I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
5.3.15
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
5.3.16
TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
5.3.17
Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
5.3.18
12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
5.3.19
DAC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
5.3.20
Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
6.1
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
6.2
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Doc ID 15081 Rev 7
3/98
Contents
STM32F100xC, STM32F100xD, STM32F100xE
6.2.1
Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
6.2.2
Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . . . 93
7
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
8
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
4/98
Doc ID 15081 Rev 7
STM32F100xC, STM32F100xD, STM32F100xE
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
STM32F100xx features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
High-density STM32F100xx pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
FSMC pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 39
Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Maximum current consumption in Run mode, code with data processing
running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Maximum current consumption in Run mode, code with data processing
running from RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
STM32F100xxB maximum current consumption in Sleep mode, code
running from Flash or RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Typical and maximum current consumptions in Stop and Standby modes . . . . . . . . . . . . 43
Typical current consumption in Run mode, code with data processing
running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Typical current consumption in Sleep mode, code running from Flash or RAM . . . . . . . . . 45
Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
HSE 4-24 MHz oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . . 56
Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . 57
Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . 64
Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Doc ID 15081 Rev 7
5/98
List of tables
Table 45.
Table 46.
Table 47.
Table 48.
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
6/98
STM32F100xC, STM32F100xD, STM32F100xE
I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
SCL frequency (fPCLK1= 24 MHz, VDD = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
RAIN max for fADC = 12 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
ADC accuracy - limited test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
LQFP144, 20 x 20 mm, 144-pin thin quad flat package mechanical data . . . . . . . . . . . . . 89
LQPF100 – 14 x 14 mm, 100-pin low-profile quad flat package mechanical data . . . . . . . 90
LQFP64 – 10 x 10 mm, 64 pin low-profile quad flat package mechanical data . . . . . . . . . 91
Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Doc ID 15081 Rev 7
STM32F100xC, STM32F100xD, STM32F100xE
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
Figure 42.
Figure 43.
Figure 44.
STM32F100xx value line block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
STM32F100xx value line LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
STM32F100xx value line LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
STM32F100xx value line in LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . . 55
Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . . 57
Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . . 58
Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . . 59
Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . 64
Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Standard I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Standard I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
5 V tolerant I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
5 V tolerant I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
I2C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . . 84
Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . . 84
12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
LQFP144, 20 x 20 mm, 144-pin thin quad flat
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
LQFP100 – 14 x 14 mm, 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 90
Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
LQFP64 – 10 x 10 mm, 64 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . 91
Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
LQFP100 PD max vs. TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Doc ID 15081 Rev 7
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Introduction
1
STM32F100xC, STM32F100xD, STM32F100xE
Introduction
This datasheet provides the ordering information and mechanical device characteristics of
the STM32F100xC, STM32F100xD and STM32F100xE value line microcontrollers. In the
rest of the document, the STM32F100xC, STM32F100xD and STM32F100xE are referred
to as high-density value line devices.
This STM32F100xC, STM32F100xD and STM32F100xE datasheet should be read in
conjunction with the STM32F100xx high-density ARM-based 32-bit MCUs reference manual
(RM0059). For information on programming, erasing and protection of the internal Flash
memory please refer to the STM32F100xx high-density value line Flash programming
manual (PM0072). The reference and Flash programming manuals are both available from
the STMicroelectronics website www.st.com.
For information on the Cortex™-M3 core please refer to the Cortex™-M3 Technical
Reference Manual, available from the www.arm.com website at the following address:
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0337e/.
8/98
Doc ID 15081 Rev 7
STM32F100xC, STM32F100xD, STM32F100xE
2
Description
Description
The STM32F100xx value line family incorporates the high-performance ARM Cortex™-M3
32-bit RISC core operating at a 24 MHz frequency, high-speed embedded memories (Flash
memory up to 512 Kbytes and SRAM up to 32 Kbytes), a flexible static memory control
(FSMC) interface (for devices offered in packages of 100 pins and more) and an extensive
range of enhanced peripherals and I/Os connected to two APB buses. All devices offer
standard communication interfaces (up to two I2Cs, three SPIs, one HDMI CEC, up to three
USARTs and 2 UARTS), one 12-bit ADC, two 12-bit DACs, up to 9 general-purpose 16-bit
timers and an advanced-control PWM timer.
The STM32F100xx high-density value line family operates in the –40 to +85 °C and –40 to
+105 °C temperature ranges, from a 2.0 to 3.6 V power supply. A comprehensive set of
power-saving mode allows the design of low-power applications.
The STM32F100xx value line family includes devices in three different packages ranging
from 64 pins to 144 pins. Depending on the device chosen, different sets of peripherals are
included, the description below gives an overview of the complete range of peripherals
proposed in this family.
These features make the STM32F100xx value line microcontroller family suitable for a wide
range of applications such as motor drives, application control, medical and handheld
equipment, PC and gaming peripherals, GPS platforms, industrial applications, PLCs,
inverters, printers, scanners, alarm systems, video intercoms, and HVACs.
Doc ID 15081 Rev 7
9/98
Description
STM32F100xC, STM32F100xD, STM32F100xE
2.1
Device overview
Table 2.
STM32F100xx features and peripheral counts
Peripheral
STM32F100Rx
STM32F100Vx
STM32F100Zx
Flash - Kbytes
256
384
512
256
384
512
256
384
512
SRAM - Kbytes
24
32
32
24
32
32
24
32
32
FSMC
No
Yes
(1)
Yes
Advanced-control
1
1
1
General-purpose
10
10
10
SPI
3
3
3
2
2
2
3
3
3
2
2
2
1
1
1
1
16 channels
1
16 channels
1
16 channels
GPIOs
51
80
112
12-bit DAC
Number of channels
2
2
2
2
2
2
Timers
2
I C
Communication
USART
interfaces
UART
CEC
12-bit synchronized ADC
number of channels
CPU frequency
24 MHz
Operating voltage
Operating temperatures
Packages
2.0 to 3.6 V
Ambient operating temperature: –40 to +85 °C /–40 to +105 °C
Junction temperature: –40 to +125 °C
LQFP64
LQFP100
LQFP144
1. For the LQFP100 package, only FSMC Bank1 is available. Bank1 can only support a multiplexed NOR/PSRAM memory.
10/98
Doc ID 15081 Rev 7
STM32F100xC, STM32F100xD, STM32F100xE
STM32F100xx value line block diagram
NJTRST
JTDI
JTCK/SWCLK
JTMS/SWDIO
JTDO
as AF
JTAG & SW
Ibus
Cortex-M3 CPU
Fmax : 24 MHz
NVIC
GP DMA
Power
VDD18
Voltage reg.
3.3 V to 1.8 V
Flash 512 KB
32 bit
SRAM
32 KB
POR
Reset
Supply
supervision
Int
POR / PDR
@VDDA
RC HS
@VDDA
12 channels
80 AF
EXT.I T
WKUP
PA[15:0]
GPIO port A
PB[15:0]
GPIO port B
@VDD
XTAL OSC
4-24 MHz
PLL
Reset &
clock
control
VSS
NRST
VDDA
VSSA
PVD
RC LS
FSMC
VDD= 2.0 V to 3.6 V
@VDD33
Dbus
System
A[25:0]
D[15:0]
CLK
NOE
NWE
NE[3:0]
NBL[1:0]
NWAIT
NADV
as AF
Trace
controller
pbus
Flash obl
interface
as AF
AHB : F max = 24 MHz
TRACECLK
TRACED[0:3]
Bus matrix
Figure 1.
Description
OSC_IN
OSC_OUT
IWDG
PCLK1
PCLK2
HCLK
FCLK
Standby
interface
VBA T = 1.8
. V to 3.6 V
@VBAT
XTAL 32 kHz
RTC
AWU
Backup
register
OSC32_IN
OSC32_OUT
TAM PER-RTC
(ALARM OUT)
Backup interface
GPIO port D
PE[15:0]
GPIO port E
PF[15:0]
GPIO port F
PG[15:0]
GPIO port G
2 channels, 1 compl. channel
and BKIN as AF
TIM15
1 channel, 1 compl. channel
and BKIN as AF
TIM16
1 channel, 1 compl. channel
and BKIN as AF
TIM17
4 channels, 3 compl. channels,
ETR and BKIN as AF
TIM1
MOSI, MISO, SCK, NSS
as AF
SPI1
RX, TX, CTS, RTS, CK
as AF
16 ADC channels
(ADC_INx)
V
AHB2
APB 2
AHB2
APB1
APB1: Fmax = 24 MHz
PD[15:0]
GPIO port C
APB2: Fmax = 24 MHz
PC[15:0]
TIM2
4 channels
as AF
TIM3
4 channels
as AF
TIM4
4 channels
as AF
TIM5
4 channels
TIM12
2 channels
as AF
TIM13
1 channel
as AF
TIM14
1 channel
as AF
USART2
RX,TX, CTS, RTS,
CK as AF
USART3
RX,TX, CTS, RTS,
CK as AF
UART4
RX,TX, CTS, RTS,
CK as AF
UART5
RX,TX, CTS, R
CK as AF
USART1
Temp sensor
WWDG
12-bit ADC1 IF
SPI2
MOSI, MISO,
SCK, NSS as AF
SPI3
MOSI, MISO,
SCK, NSS as AF
REF+
V
REF–
TIM6
HDMI CEC
@VDDA
TIM7
HDMI CEC as AF
I2C1
SCL, SDA, SMBA as AF
I2C2
SCL, SDA, SMBA as AF
12-bit DAC1
DAC1_OUT as AF
12-bit DAC2
DAC2 _OUT as AF
IF
@VDDA
ai17515b
1. AF = alternate function on I/O port pin.
2. TA = –40 °C to +85 °C (junction temperature up to 105 °C) or TA = –40 °C to +105 °C (junction temperature up to 125 °C).
Doc ID 15081 Rev 7
11/98
Description
STM32F100xC, STM32F100xD, STM32F100xE
Figure 2.
Clock tree
)/,7)&/.
WR)ODVKSURJUDPPLQJLQWHUIDFH
0+]
+6,5&
+6,
3HULSKHUDOFORFN
)60&/.
(QDEOH
+&/.
WR$+%EXVFRUH
PHPRU\DQG'0$
0+]PD[
3//65&
6:
3//08/
+6,
[
[[[
3//
6<6&/.
$+%
3UHVFDOHU
0+]
PD[
3//&/.
+6(
0+]
$3%
3UHVFDOHU
+6(26&
26&B287
3HULSKHUDO&ORFN
(QDEOH
/6(26&
N+]
WR57&
/6(
3&/.
WR$3%
SHULSKHUDOV
WR7,0
7,0[&/.
57&&/.
$'&
3UHVFDOHU
3&/.
0+]PD[
3HULSKHUDO&ORFN
(QDEOH
7,0WLPHUV
,I$3%SUHVFDOHU [
HOVH[
26&B,1
0+]PD[
3HULSKHUDO&ORFN
(QDEOH
35(',9
26&B,1
WR&RUWH[6\VWHPWLPHU
)&/.&RUWH[
IUHHUXQQLQJFORFN
7,0
,I$3%SUHVFDOHU [
HOVH[
&66
26&B287
&ORFN
(QDEOH
$3%
3UHVFDOHU
WR)60&
SHULSKHUDOVWR$3%
WR7,07,0
7,0DQG7,0
7,0[&/.
3HULSKHUDO&ORFN
(QDEOH
WR$'&
$'&&/.0+]PD[
57&6(/>@
/6,5&
N+]
0&2
WRLQGHSHQGHQWZDWFKGRJ,:'*
/6,
,:'*&/.
0DLQ
FORF NRXW SXW
3//&/.
+6,
/HJHQG
+6( +LJKVSHHGH[WHUQDOFORFNVLJQDO
+6, +LJKVSHHGLQWHUQDOFORFNVLJQDO
+6(
/6, /RZVSHHGLQWHUQDOFORFNVLJQDO
6<6&/.
/6( /RZVSHHGH[WHUQDOFORFNVLJQDO
0&2
DL
1. To obtain an ADC conversion time of 1.2 µs, APB2 must be at 24 MHz.
12/98
Doc ID 15081 Rev 7
STM32F100xC, STM32F100xD, STM32F100xE
2.2
Overview
2.2.1
ARM® Cortex™-M3 core with embedded Flash and SRAM
Description
The ARM Cortex™-M3 processor is the latest generation of ARM processors for embedded
systems. It has been developed to provide a low-cost platform that meets the needs of MCU
implementation, with a reduced pin count and low-power consumption, while delivering
outstanding computational performance and an advanced system response to interrupts.
The ARM Cortex™-M3 32-bit RISC processor features exceptional code-efficiency,
delivering the high-performance expected from an ARM core in the memory size usually
associated with 8- and 16-bit devices.
The STM32F100xx value line family having an embedded ARM core, is therefore
compatible with all ARM tools and software.
2.2.2
Embedded Flash memory
Up to 512 Kbytes of embedded Flash memory is available for storing programs and data.
2.2.3
CRC (cyclic redundancy check) calculation unit
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit
data word and a fixed generator polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location.
2.2.4
Embedded SRAM
Up to 32 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait
states.
2.2.5
FSMC (flexible static memory controller)
The FSMC is embedded in the high-density value line family. It has four Chip Select outputs
supporting the following modes: SRAM, PSRAM, and NOR.
Functionality overview:
2.2.6
●
The three FSMC interrupt lines are ORed in order to be connected to the NVIC
●
No read FIFO
●
Code execution from external memory
●
No boot capability
●
The targeted frequency is HCLK/2, so external access is at 12 MHz when HCLK is at
24 MHz
LCD parallel interface
The FSMC can be configured to interface seamlessly with most graphic LCD controllers. It
supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to
Doc ID 15081 Rev 7
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Description
STM32F100xC, STM32F100xD, STM32F100xE
specific LCD interfaces. This LCD parallel interface capability makes it easy to build costeffective graphic applications using LCD modules with embedded controllers or highperformance solutions using external controllers with dedicated acceleration.
2.2.7
Nested vectored interrupt controller (NVIC)
The STM32F100xx value line embeds a nested vectored interrupt controller able to handle
up to 60 maskable interrupt channels (not including the 16 interrupt lines of Cortex™-M3)
and 16 priority levels.
●
Closely coupled NVIC gives low latency interrupt processing
●
Interrupt entry vector table address passed directly to the core
●
Closely coupled NVIC core interface
●
Allows early processing of interrupts
●
Processing of late arriving higher priority interrupts
●
Support for tail-chaining
●
Processor state automatically saved
●
Interrupt entry restored on interrupt exit with no instruction overhead
This hardware block provides flexible interrupt management features with minimal interrupt
latency.
2.2.8
External interrupt/event controller (EXTI)
The external interrupt/event controller consists of 18 edge detector lines used to generate
interrupt/event requests. Each line can be independently configured to select the trigger
event (rising edge, falling edge, both) and can be masked independently. A pending register
maintains the status of the interrupt requests. The EXTI can detect an external line with a
pulse width shorter than the Internal APB2 clock period. Up to 112 GPIOs can be connected
to the 16 external interrupt lines.
2.2.9
Clocks and startup
System clock selection is performed on startup, however the internal RC 8 MHz oscillator is
selected as default CPU clock on reset. An external 4-24 MHz clock can be selected, in
which case it is monitored for failure. If failure is detected, the system automatically switches
back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full
interrupt management of the PLL clock entry is available when necessary (for example on
failure of an indirectly used external crystal, resonator or oscillator).
Several prescalers allow the configuration of the AHB frequency, the high-speed APB
(APB2) and the low-speed APB (APB1) domains. The maximum frequency of the AHB and
the APB domains is 24 MHz.
2.2.10
Boot modes
At startup, boot pins are used to select one of three boot options:
14/98
●
Boot from user Flash
●
Boot from system memory
●
Boot from embedded SRAM
Doc ID 15081 Rev 7
STM32F100xC, STM32F100xD, STM32F100xE
Description
The boot loader is located in System Memory. It is used to reprogram the Flash memory by
using USART1. For further details please refer to AN2606.
2.2.11
2.2.12
Power supply schemes
●
VDD = 2.0 to 3.6 V: External power supply for I/Os and the internal regulator.
Provided externally through VDD pins.
●
VSSA, VDDA = 2.0 to 3.6 V: External analog power supplies for ADC, DAC, Reset blocks,
RCs and PLL (minimum voltage to be applied to VDDA is 2.4 V when the ADC or DAC is
used).
VDDA and VSSA must be connected to VDD and VSS, respectively.
●
VBAT = 1.8 to 3.6 V: Power supply for RTC, external clock 32 kHz oscillator and backup
registers (through power switch) when VDD is not present.
Power supply supervisor
The device has an integrated power on reset (POR)/power down reset (PDR) circuitry. It is
always active, and ensures proper operation starting from/down to 2 V. The device remains
in reset mode when VDD is below a specified threshold, VPOR/PDR, without the need for an
external reset circuit.
The device features an embedded programmable voltage detector (PVD) that monitors the
VDD/VDDA power supply and compares it to the VPVD threshold. An interrupt can be
generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is higher
than the VPVD threshold. The interrupt service routine can then generate a warning
message and/or put the MCU into a safe state. The PVD is enabled by software.
2.2.13
Voltage regulator
The regulator has three operation modes: main (MR), low power (LPR) and power down.
●
MR is used in the nominal regulation mode (Run)
●
LPR is used in the Stop mode
●
Power down is used in Standby mode: the regulator output is in high impedance: the
kernel circuitry is powered down, inducing zero consumption (but the contents of the
registers and SRAM are lost)
This regulator is always enabled after reset. It is disabled in Standby mode, providing high
impedance output.
2.2.14
Low-power modes
The STM32F100xx value line supports three low-power modes to achieve the best
compromise between low power consumption, short startup time and available wakeup
sources:
●
Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
●
Stop mode
Stop mode achieves the lowest power consumption while retaining the content of
SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC
and the HSE crystal oscillators are disabled. The voltage regulator can also be put
Doc ID 15081 Rev 7
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Description
STM32F100xC, STM32F100xD, STM32F100xE
either in normal or in low power mode.
The device can be woken up from Stop mode by any of the EXTI line. The EXTI line
source can be one of the 16 external lines, the PVD output or the RTC alarm.
●
Standby mode
The Standby mode is used to achieve the lowest power consumption. The internal
voltage regulator is switched off so that the entire 1.8 V domain is powered off. The
PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering
Standby mode, SRAM and register contents are lost except for registers in the Backup
domain and Standby circuitry.
The device exits Standby mode when an external reset (NRST pin), a IWDG reset, a
rising edge on the WKUP pin, or an RTC alarm occurs.
Note:
The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop
or Standby mode.
2.2.15
DMA
The flexible 12-channel general-purpose DMA is able to manage memory-to-memory,
peripheral-to-memory and memory-to-peripheral transfers. The two DMA controllers
support circular buffer management avoiding the generation of interrupts when the controller
reaches the end of the buffer.
Each channel is connected to dedicated hardware DMA requests, with support for software
trigger on each channel. Configuration is made by software and transfer sizes between
source and destination are independent.
The DMA can be used with the main peripherals: SPI, DAC, I2C, USART, all timers and
ADC.
2.2.16
RTC (real-time clock) and backup registers
The RTC and the backup registers are supplied through a switch that takes power either on
VDD supply when present or through the VBAT pin. The backup registers are ten 16-bit
registers used to store 20 bytes of user application data when VDD power is not present.
The real-time clock provides a set of continuously running counters which can be used with
suitable software to provide a clock calendar function, and provides an alarm interrupt and a
periodic interrupt. It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the
internal low power RC oscillator or the high-speed external clock divided by 128. The
internal low power RC has a typical frequency of 40 kHz. The RTC can be calibrated using
an external 512 Hz output to compensate for any natural crystal deviation. The RTC
features a 32-bit programmable counter for long term measurement using the Compare
register to generate an alarm. A 20-bit prescaler is used for the time base clock and is by
default configured to generate a time base of 1 second from a clock at 32.768 kHz.
2.2.17
Timers and watchdogs
The STM32F100xx devices include an advanced-control timer, nine general-purpose timers,
two basic timers and two watchdog timers.
Table 3 compares the features of the advanced-control, general-purpose and basic timers.
16/98
Doc ID 15081 Rev 7
STM32F100xC, STM32F100xD, STM32F100xE
Table 3.
Description
Timer feature comparison
Timer
Counter
resolution
Counter
type
Prescaler
factor
DMA request Capture/compare Complementary
generation
channels
outputs
TIM1
16-bit
Up,
down,
up/down
16 bits
Yes
4
Yes
TIM2,
TIM3,
TIM4,
TIM5
16-bit
Up,
down,
up/down
Any integer
between 1
and 65536
Yes
4
No
TIM12
16-bit
Up
Any integer
between 1
and 65536
No
2
No
TIM13,
TIM14
16-bit
Up
Any integer
between 1
and 65536
No
1
No
TIM15
16-bit
Up
Any integer
between 1
and 65536
Yes
2
Yes
TIM16,
TIM17
16-bit
Up
Any integer
between 1
and 65536
Yes
1
Yes
TIM6,
TIM7
16-bit
Up
Any integer
between 1
and 65536
Yes
0
No
Advanced-control timer (TIM1)
The advanced-control timer (TIM1) can be seen as a three-phase PWM multiplexed on 6
channels. It has complementary PWM outputs with programmable inserted dead times. It
can also be seen as a complete general-purpose timer. The 4 independent channels can be
used for:
●
Input capture
●
Output compare
●
PWM generation (edge or center-aligned modes)
●
One-pulse mode output
If configured as a standard 16-bit timer, it has the same features as the TIMx timer. If
configured as the 16-bit PWM generator, it has full modulation capability (0-100%).
The counter can be frozen in debug mode.
Many features are shared with those of the standard TIM timers which have the same
architecture. The advanced control timer can therefore work together with the TIM timers via
the Timer Link feature for synchronization or event chaining.
General-purpose timers (TIM2..5, TIM12..17)
There are ten synchronizable general-purpose timers embedded in the STM32F100xx
devices (see Table 3 for differences). Each general-purpose timer can be used to generate
PWM outputs, or as simple time base.
Doc ID 15081 Rev 7
17/98
Description
STM32F100xC, STM32F100xD, STM32F100xE
TIM2, TIM3, TIM4, TIM5
STM32F100xx devices feature four synchronizable 4-channel general-purpose timers.
These timers are based on a 16-bit auto-reload up/downcounter and a 16-bit prescaler.
They feature 4 independent channels each for input capture/output compare, PWM or onepulse mode output. This gives up to 12 input captures/output compares/PWMs on the
largest packages.
The TIM2, TIM3, TIM4, TIM5 general-purpose timers can work together or with the TIM1
advanced-control timer via the Timer Link feature for synchronization or event chaining.
TIM2, TIM3, TIM4, TIM5 all have independent DMA request generation.
These timers are capable of handling quadrature (incremental) encoder signals and the
digital outputs from 1 to 3 hall-effect sensors.
Their counters can be frozen in debug mode.
TIM12, TIM13 and TIM14
These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler.
TIM12 has two independent channels, whereas TIM13 and TIM14 feature one single
channel for input capture/output compare, PWM or one-pulse mode output.
Their counters can be frozen in debug mode.
TIM15, TIM16 and TIM17
These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler.
TIM15 has two independent channels, whereas TIM16 and TIM17 feature one single
channel for input capture/output compare, PWM or one-pulse mode output.
The TIM15, TIM16 and TIM17 timers can work together, and TIM15 can also operate with
TIM1 via the Timer Link feature for synchronization or event chaining.
TIM15 can be synchronized with TIM16 and TIM17.
TIM15, TIM16, and TIM17 have a complementary output with dead-time generation and
independent DMA request generation
Their counters can be frozen in debug mode.
Basic timers TIM6 and TIM7
These timers are mainly used for DAC trigger generation. They can also be used as a
generic 16-bit time base.
Independent watchdog
The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is
clocked from an independent 40 kHz internal RC and as it operates independently from the
main clock, it can operate in Stop and Standby modes. It can be used as a watchdog to
reset the device when a problem occurs, or as a free running timer for application timeout
management. It is hardware or software configurable through the option bytes. The counter
can be frozen in debug mode.
18/98
Doc ID 15081 Rev 7
STM32F100xC, STM32F100xD, STM32F100xE
Description
Window watchdog
The window watchdog is based on a 7-bit downcounter that can be set as free running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from the
main clock. It has an early warning interrupt capability and the counter can be frozen in
debug mode.
SysTick timer
This timer is dedicated for OS, but could also be used as a standard down counter. It
features:
2.2.18
●
A 24-bit down counter
●
Autoreload capability
●
Maskable system interrupt generation when the counter reaches 0.
●
Programmable clock source
I²C bus
The I²C bus interface can operate in multimaster and slave modes. It can support standard
and fast modes.
It supports dual slave addressing (7-bit only) and both 7/10-bit addressing in master mode.
A hardware CRC generation/verification is embedded.
The interface can be served by DMA and it supports SM Bus 2.0/PM Bus.
2.2.19
Universal synchronous/asynchronous receiver transmitter (USART)
The STM32F100xx value line embeds three universal synchronous/asynchronous receiver
transmitters (USART1, USART2 and USART3).
The available USART interfaces communicate at up to 3 Mbit/s. They provide hardware
management of the CTS and RTS signals, they support IrDA SIR ENDEC, the
multiprocessor communication mode, the single-wire half-duplex communication mode and
have LIN Master/Slave capability.
The USART interfaces can be served by the DMA controller.
2.2.20
Universal asynchronous receiver transmitter (UART)
The STM32F100xx value line embeds 2 universal asynchronous receiver transmitters
(UART4, and UART5).
The available UART interfaces support IrDA SIR ENDEC, the multiprocessor communication
mode, the single-wire half-duplex communication mode and have LIN Master/Slave
capability.
The UART interfaces can be served by the DMA controller.
2.2.21
Serial peripheral interface (SPI)
Up to three SPIs are able to communicate up to 12 Mbit/s in slave and master modes in fullduplex and simplex communication modes. The 3-bit prescaler gives 8 master mode
frequencies and the frame is configurable to 8 bits or 16 bits.
The SPIs can be served by the DMA controller.
Doc ID 15081 Rev 7
19/98
Description
STM32F100xC, STM32F100xD, STM32F100xE
HDMI (high-definition multimedia interface) consumer
electronics control (CEC)
The STM32F100xx value line embeds a HDMI-CEC controller that provides hardware
support of consumer electronics control (CEC) (Appendix supplement 1 to the HDMI
standard).
This protocol provides high-level control functions between all audiovisual products in an
environment. It is specified to operate at low speeds with minimum processing and memory
overhead.
2.2.22
GPIOs (general-purpose inputs/outputs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current
capable.
The I/Os alternate function configuration can be locked if needed following a specific
sequence in order to avoid spurious writing to the I/Os registers.
2.2.23
Remap capability
This feature allows the use of a maximum number of peripherals in a given application.
Indeed, alternate functions are available not only on the default pins but also on other
specific pins onto which they are remappable. This has the advantage of making board
design and port usage much more flexible.
For details refer to Table 4: High-density STM32F100xx pin definitions; it shows the list of
remappable alternate functions and the pins onto which they can be remapped. See the
STM32F100xx reference manual for software considerations.
2.2.24
ADC (analog-to-digital converter)
The 12-bit analog to digital converter has up to 16 external channels and performs
conversions in single-shot or scan modes. In scan mode, automatic conversion is performed
on a selected group of analog inputs.
The ADC can be served by the DMA controller.
An analog watchdog feature allows very precise monitoring of the converted voltage of one,
some or all selected channels. An interrupt is generated when the converted voltage is
outside the programmed thresholds.
2.2.25
DAC (digital-to-analog converter)
The two 12-bit buffered DAC channels can be used to convert two digital signals into two
analog voltage signal outputs. The chosen design structure is composed of integrated
resistor strings and an amplifier in noninverting configuration.
20/98
Doc ID 15081 Rev 7
STM32F100xC, STM32F100xD, STM32F100xE
Description
This dual digital Interface supports the following features:
●
two DAC converters: one for each output channel
●
up to 10-bit output
●
left or right data alignment in 12-bit mode
●
synchronized update capability
●
noise-wave generation
●
triangular-wave generation
●
dual DAC channels’ independent or simultaneous conversions
●
DMA capability for each channel
●
external triggers for conversion
●
input voltage reference VREF+
Eight DAC trigger inputs are used in the STM32F100xx. The DAC channels are triggered
through the timer update outputs that are also connected to different DMA channels.
2.2.26
Temperature sensor
The temperature sensor has to generate a voltage that varies linearly with temperature. The
conversion range is between 2 V < VDDA < 3.6 V. The temperature sensor is internally
connected to the ADC1_IN16 input channel which is used to convert the sensor output
voltage into a digital value.
2.2.27
Serial wire JTAG debug port (SWJ-DP)
The ARM SWJ-DP Interface is embedded, and is a combined JTAG and serial wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
The JTAG TMS and TCK pins are shared respectively with SWDIO and SWCLK and a
specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP.
Doc ID 15081 Rev 7
21/98
Pinouts and pin descriptions
STM32F100xC, STM32F100xD, STM32F100xE
Pinouts and pin descriptions
Figure 3.
STM32F100xx value line LQFP144 pinout
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
VDD_3
VSS_3
PE1
PE0
PB9
PB8
BOOT0
PB7
PB6
PB5
PB4
PB3
PG15
VDD_11
VSS_11
PG14
PG13
PG12
PG11
PG10
PG9
PD7
PD6
VDD_10
VSS_10
PD5
PD4
PD3
PD2
PD1
PD0
PC12
PC11
PC10
PA15
PA14
3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
LQFP144
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
VDD_2
VSS_2
NC
PA13
PA12
PA11
PA10
PA9
PA8
PC9
PC8
PC7
PC6
VDD_9
VSS_9
PG8
PG7
PG6
PG5
PG4
PG3
PG2
PD15
PD14
VDD_8
VSS_8
PD13
PD12
PD11
PD10
PD9
PD8
PB15
PB14
PB13
PB12
VSS_6
VDD_6
PF13
PF14
PF15
PG0
PG1
PE7
PE8
PE9
VSS_7
VDD_7
PE10
PE11
PE12
PE13
PE14
PE15
PB10
PB11
VSS_1
VDD_1
PA3
VSS_4
VDD_4
PA4
PA5
PA6
PA7
PC4
PC5
PB0
PB1
PB2
PF11
PF12
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
PE2
PE3
PE4
PE5
PE6
VBAT
PC13-TAMPER-RTC
PC14-OSC32_IN
PC15-OSC32_OUT
PF0
PF1
PF2
PF3
PF4
PF5
VSS_5
VDD_5
PF6
PF7
PF8
PF9
PF10
OSC_IN
OSC_OUT
NRST
PC0
PC1
PC2
PC3
VSSA
VREFVREF+
VDDA
PA0-WKUP
PA1
PA2
ai14667
22/98
Doc ID 15081 Rev 7
STM32F100xC, STM32F100xD, STM32F100xE
STM32F100xx value line LQFP100 pinout
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
VDD_3
VSS_3
PE1
PE0
PB9
PB8
BOOT0
PB7
PB6
PB5
PB4
PB3
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PC12
PC11
PC10
PA15
PA14
Figure 4.
Pinouts and pin descriptions
LQFP100
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
VDD_2
VSS_2
NC
PA 13
PA 12
PA 11
PA 10
PA 9
PA 8
PC9
PC8
PC7
PC6
PD15
PD14
PD13
PD12
PD11
PD10
PD9
PD8
PB15
PB14
PB13
PB12
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
PA3
VSS_4
VDD_4
PA4
PA5
PA6
PA7
PC4
PC5
PB0
PB1
PB2
PE7
PE8
PE9
PE10
PE11
PE12
PE13
PE14
PE15
PB10
PB11
VSS_1
VDD_1
PE2
PE3
PE4
PE5
PE6
VBAT
PC13-TAMPER-RTC
PC14-OSC32_IN
PC15-OSC32_OUT
VSS_5
VDD_5
OSC_IN
OSC_OUT
NRST
PC0
PC1
PC2
PC3
VSSA
VREFVREF+
VDDA
PA0-WKUP
PA1
PA2
ai14391
Doc ID 15081 Rev 7
23/98
Pinouts and pin descriptions
STM32F100xx value line in LQFP64 pinout
VDD_3
VSS_3
PB9
PB8
BOOT0
PB7
PB6
PB5
PB4
PB3
PD2
PC12
PC11
PC10
PA15
PA14
Figure 5.
STM32F100xC, STM32F100xD, STM32F100xE
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
1
47
2
46
3
45
4
44
5
43
6
42
7
41
8
LQFP64
40
9
39
10
38
11
37
12
36
13
35
14
34
15
33
16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
VDD_2
VSS_2
PA13
PA12
PA11
PA10
PA9
PA8
PC9
PC8
PC7
PC6
PB15
PB14
PB13
PB12
PA3
VSS_4
VDD_4
PA4
PA5
PA6
PA7
PC4
PC5
PB0
PB1
PB2
PB10
PB11
VSS_1
VDD_1
VBAT
PC13-TAMPER-RTC
PC14-OSC32_IN
PC15-OSC32_OUT
PD0 OSC_IN
PD1 OSC_OUT
NRST
PC0
PC1
PC2
PC3
VSSA
VDDA
PA0-WKUP
PA1
PA2
ai14392
High-density STM32F100xx pin definitions
LQFP100
LQFP64
Pin name
Type(1)
I / O Level(2)
Main
function(3)
(after reset)
1
1
-
PE2
I/O
FT
PE2
TRACECK/ FSMC_A23
2
2
-
PE3
I/O
FT
PE3
TRACED0/FSMC_A19
3
3
-
PE4
I/O
FT
PE4
TRACED1/FSMC_A20
4
4
-
PE5
I/O
FT
PE5
TRACED2/FSMC_A21
5
5
-
PE6
I/O
FT
PE6
TRACED3/FSMC_A22
6
6
1
VBAT
S
7
7
2
8
8
3
9
9
4
10
-
-
PF0
11
-
-
12
-
13
14
Pins
24/98
Alternate functions(4)
LQFP144
Table 4.
PC13-TAMPERI/O
RTC(5)
Default
VBAT
PC13(6)
TAMPER-RTC
I/O
PC14(6)
OSC32_IN
PC15I/O
OSC32_OUT(5)
PC15(6)
OSC32_OUT
I/O FT
PF0
FSMC_A0
PF1
I/O FT
PF1
FSMC_A1
-
PF2
I/O FT
PF2
FSMC_A2
-
-
PF3
I/O FT
PF3
FSMC_A3
-
-
PF4
I/O FT
PF4
FSMC_A4
PC14OSC32_IN(5)
Doc ID 15081 Rev 7
Remap
STM32F100xC, STM32F100xD, STM32F100xE
High-density STM32F100xx pin definitions (continued)
LQFP100
LQFP64
Pin name
15
-
-
PF5
Type(1)
LQFP144
Pins
I / O Level(2)
Table 4.
Pinouts and pin descriptions
I/O FT
Alternate functions(4)
Main
function(3)
(after reset)
Default
PF5
FSMC_A5
Remap
16 10
-
VSS_5
S
VSS_5
17 11
-
VDD_5
S
VDD_5
18
-
-
PF6
I/O
PF6
19
-
-
PF7
I/O
PF7
20
-
-
PF8
I/O
PF8
21
-
-
PF9
I/O
PF9
22
-
-
PF10
I/O
PF10
23 12
5
OSC_IN
I
OSC_IN
PD0(7)
24 13
6
OSC_OUT
O
OSC_OUT
PD1(7)
25 14
7
NRST
I/O
NRST
26 15
8
PC0
I/O
PC0
ADC_IN10
27 16
9
PC1
I/O
PC1
ADC_IN11
28 17 10
PC2
I/O
PC2
ADC_IN12
29 18 11
PC3
I/O
PC3
ADC_IN13
30 19 12
VSSA
S
VSSA
31 20
-
VREF-
S
VREF-
32 21
-
VREF+
S
VREF+
VDDA
S
VDDA
33 22 13
34 23 14
35 24 15
36 25 16
PA0-WKUP
PA1
PA2
I/O
I/O
I/O
PA0
WKUP/USART2_CTS(8)
ADC_IN0
TIM2_CH1_ETR
TIM5_CH1
PA1
USART2_RTS(8)
ADC_IN1/
TIM5_CH2/TIM2_CH2(8)
PA2
USART2_TX(8)/TIM5_CH3
ADC_IN2/ TIM15_CH1
TIM2_CH3 (8)
USART2_RX(8)/TIM5_CH4
ADC_IN3/TIM2_CH4(8) /
TIM15_CH2
37 26 17
PA3
I/O
PA3
38 27 18
VSS_4
S
VSS_4
39 28 19
VDD_4
S
VDD_4
Doc ID 15081 Rev 7
25/98
Pinouts and pin descriptions
High-density STM32F100xx pin definitions (continued)
Alternate functions(4)
Main
function(3)
(after reset)
Default
Remap
40 29 20
PA4
I/O
PA4
SPI1_NSS(8)/
USART2_CK(8)
DAC_OUT1/ADC_IN4
41 30 21
PA5
I/O
PA5
SPI1_SCK(8)
DAC_OUT2/ADC_IN5
PA6
SPI1_MISO(8)/
ADC_IN6 /
TIM3_CH1(8)
TIM1_BKIN /
TIM16_CH1
TIM1_CH1N/
TIM17_CH1
42 31 22
26/98
Pin name
Type(1)
LQFP64
LQFP100
LQFP144
Pins
I / O Level(2)
Table 4.
STM32F100xC, STM32F100xD, STM32F100xE
PA6
I/O
43 32 23
PA7
I/O
PA7
SPI1_MOSI(8)/
ADC_IN7 /
TIM3_CH2(8)
44 33 24
PC4
I/O
PC4
ADC_IN14 / TIM12_CH1
45 34 25
PC5
I/O
PC5
ADC_IN15 / TIM12_CH2
46 35 26
PB0
I/O
PB0
47 36 27
PB1
I/O
PB1
48 37 28
PB2
I/O FT PB2/BOOT1
49
-
-
PF11
I/O FT
PF11
50
-
-
PF12
I/O FT
PF12
51
-
-
VSS_6
S
VSS_6
52
-
-
VDD_6
S
VDD_6
53
-
-
PF13
I/O FT
PF13
FSMC_A7
54
-
-
PF14
I/O FT
PF14
FSMC_A8
55
-
-
PF15
I/O FT
PF15
FSMC_A9
56
-
-
PG0
I/O FT
PG0
FSMC_A10
57
-
-
PG1
I/O FT
PG1
FSMC_A11
58 38
-
PE7
I/O FT
PE7
FSMC_D4
TIM1_ETR
59 39
-
PE8
I/O FT
PE8
FSMC_D5
TIM1_CH1N
60 40
-
PE9
I/O FT
PE9
FSMC_D6
TIM1_CH1
61
-
-
VSS_7
S
VSS_7
62
-
-
VDD_7
S
VDD_7
63 41
-
PE10
I/O FT
PE10
FSMC_D7
TIM1_CH2N
64 42
-
PE11
I/O FT
PE11
FSMC_D8
TIM1_CH2
65 43
-
PE12
I/O FT
PE12
FSMC_D9
TIM1_CH3N
66 44
-
PE13
I/O FT
PE13
FSMC_D10
TIM1_CH3
Doc ID 15081 Rev 7
ADC_IN8/TIM3_CH3
TIM1_CH2N /
TIM13_CH1
ADC_IN9/TIM3_CH4(8)
TIM1_CH3N /
TIM14_CH1
FSMC_A6
STM32F100xC, STM32F100xD, STM32F100xE
High-density STM32F100xx pin definitions (continued)
Type(1)
Alternate functions(4)
Main
function(3)
(after reset)
Default
Remap
LQFP64
LQFP100
LQFP144
Pins
I / O Level(2)
Table 4.
Pinouts and pin descriptions
Pin name
67 45
-
PE14
I/O FT
PE14
FSMC_D11
TIM1_CH4
68 46
-
PE15
I/O FT
PE15
FSMC_D12
TIM1_BKIN
69 47 29
PB10
I/O FT
PB10
I2C2_SCL/USART3_TX(8)
TIM2_CH3 /
HDMI_CEC
70 48 30
PB11
I/O FT
PB11
I2C2_SDA/USART3_RX(8)
TIM2_CH4
71 49 31
VSS_1
S
VSS_1
72 50 32
VDD_1
S
VDD_1
TIM12_CH1
73 51 33
PB12
I/O FT
PB12
SPI2_NSS/
I2C2_SMBA/
USART3_CK(8)/
TIM1_BKIN(8)
74 52 34
PB13
I/O FT
PB13
SPI2_SCK/
USART3_CTS(8)/
TIM1_CH1N
TIM12_CH2
75 53 35
PB14
I/O FT
PB14
SPI2_MISO/TIM1_CH2N
USART3_RTS(8)/
TIM15_CH1
76 54 36
PB15
I/O FT
PB15
SPI2_MOSI/
TIM1_CH3N(8)/
TIM15_CH1N
TIM15_CH2
77 55
-
PD8
I/O FT
PD8
FSMC_D13
USART3_TX
78 56
-
PD9
I/O FT
PD9
FSMC_D14
USART3_RX
79 57
-
PD10
I/O FT
PD10
FSMC_D15
USART3_CK
80 58
-
PD11
I/O FT
PD11
FSMC_A16
USART3_CTS
81 59
-
PD12
I/O FT
PD12
FSMC_A17
TIM4_CH1 /
USART3_RTS
82 60
-
PD13
I/O FT
PD13
FSMC_A18
TIM4_CH2
83
-
-
VSS_8
S
VSS_8
84
-
-
VDD_8
S
VDD_8
85 61
-
PD14
I/O FT
PD14
FSMC_D0
TIM4_CH3
86 62
-
PD15
I/O FT
PD15
FSMC_D1
TIM4_CH4
87
-
-
PG2
I/O FT
PG2
FSMC_A12
88
-
-
PG3
I/O FT
PG3
FSMC_A13
89
-
-
PG4
I/O FT
PG4
FSMC_A14
90
-
-
PG5
I/O FT
PG5
FSMC_A15
91
-
-
PG6
I/O FT
PG6
92
-
-
PG7
I/O FT
PG7
Doc ID 15081 Rev 7
27/98
Pinouts and pin descriptions
High-density STM32F100xx pin definitions (continued)
Alternate functions(4)
LQFP144
LQFP100
LQFP64
Main
function(3)
(after reset)
Pin name
93
-
-
PG8
94
-
-
VSS_9
S
VSS_9
95
-
-
VDD_9
S
VDD_9
I/O FT
Default
Remap
PG8
96 63 37
PC6
I/O FT
PC6
TIM3_CH1
97 64 38
PC7
I/O FT
PC7
TIM3_CH2
98 65 39
PC8
I/O FT
PC8
TIM13_CH1
TIM3_CH3
99 66 40
PC9
I/O FT
PC9
TIM14_CH1
TIM3_CH4
100 67 41
PA8
I/O FT
PA8
USART1_CK/
TIM1_CH1(8)/MCO
PA9
USART1_TX(8)/
TIM1_CH2(8) /
TIM15_BKIN
101 68 42
PA9
I/O FT
102 69 43
PA10
I/O FT
PA10
USART1_RX(8)/
TIM1_CH3(8) /
TIM17_BKIN
103 70 44
PA11
I/O FT
PA11
USART1_CTS /
TIM1_CH4(8)
104 71 45
PA12
I/O FT
PA12
USART1_RTS /
TIM1_ETR(8)
105 72 46
PA13
I/O FT
JTMSSWDIO
106 73
28/98
Type(1)
Pins
I / O Level(2)
Table 4.
STM32F100xC, STM32F100xD, STM32F100xE
-
Not connected
107 74 47
VSS_2
S
VSS_2
108 75 48
VDD_2
S
VDD_2
109 76 49
PA14
I/O FT
JTCKSWCLK
110 77 50
PA15
I/O FT
JTDI
SPI3_NSS
TIM2_CH1_ETR /
SPI1_NSS
111 78 51
PC10
I/O FT
PC10
UART4_TX
USART3_TX
112 79 52
PC11
I/O FT
PC11
UART4_RX
USART3_RX
113 80 53
PC12
I/O FT
PC12
UART5_TX
USART3_CK
114 81
-
PD0
I/O FT
PD0
FSMC_D2(9)
115 82
-
PD1
I/O FT
PD1
FSMC_D3(9)
116 83 54
PD2
I/O FT
PD2
TIM3_ETR/UART5_RX
117 84
-
PD3
I/O FT
PD3
FSMC_CLK
USART2_CTS
118 85
-
PD4
I/O FT
PD4
FSMC_NOE
USART2_RTS
Doc ID 15081 Rev 7
STM32F100xC, STM32F100xD, STM32F100xE
High-density STM32F100xx pin definitions (continued)
Type(1)
Alternate functions(4)
Main
function(3)
(after reset)
Default
Remap
PD5
FSMC_NWE
USART2_TX
LQFP64
LQFP100
LQFP144
Pins
I / O Level(2)
Table 4.
Pinouts and pin descriptions
Pin name
119 86
-
PD5
120 -
-
VSS_10
S
VSS_10
121 -
-
VDD_10
S
VDD_10
122 87
-
PD6
I/O FT
PD6
FSMC_NWAIT
USART2_RX
123 88
-
PD7
I/O FT
PD7
FSMC_NE1
USART2_CK
124 -
-
PG9
I/O FT
PG9
FSMC_NE2
125 -
-
PG10
I/O FT
PG10
FSMC_NE3
126 -
-
PG11
I/O FT
PG11
127 -
-
PG12
I/O FT
PG12
FSMC_NE4
128 -
-
PG13
I/O FT
PG13
FSMC_A24
129 -
-
PG14
I/O FT
PG14
FSMC_A25
130 -
-
VSS_11
S
VSS_11
131 -
-
VDD_11
S
VDD_11
132 -
-
PG15
I/O FT
PG15
133 89 55
PB3/
I/O FT
JTDO
SPI3_SCK
PB3/TRACESWO
TIM2_CH2 /
SPI1_SCK
134 90 56
PB4
I/O FT
NJTRST
SPI3_MISO
TIM3_CH1
SPI1_MISO
135 91 57
PB5
I/O
PB5
I2C1_SMBA/ SPI3_MOSI
TIM16_BKIN
TIM3_CH2 /
SPI1_MOSI
136 92 58
PB6
I/O FT
PB6
I2C1_SCL(8)/ TIM4_CH1(8)
/ TIM16_CH1N
USART1_TX
PB7
I2C1_SDA(8) /
FSMC_NADV /
TIM4_CH2(8) /
TIM17_CH1N
USART1_RX
I/O FT
137 93 59
PB7
I/O FT
138 94 60
BOOT0
139 95 61
PB8
I/O FT
PB8
TIM4_CH3(8)/TIM16_CH1 /
HDMI_CEC
I2C1_SCL
140 96 62
PB9
I/O FT
PB9
TIM4_CH4(8)/ TIM17_CH1
I2C1_SDA
141 97
-
PE0
I/O FT
PE0
TIM4_ETR / FSMC_NBL0
142 98
-
PE1
I/O FT
PE1
FSMC_NBL1
I
BOOT0
143 99 63
VSS_3
S
VSS_3
144 100 64
VDD_3
S
VDD_3
1. I = input, O = output, S = supply.
Doc ID 15081 Rev 7
29/98
Pinouts and pin descriptions
STM32F100xC, STM32F100xD, STM32F100xE
2. FT = 5 V tolerant.
3. Function availability depends on the chosen device.
4. If several peripherals share the same I/O pin, to avoid conflict between these alternate functions only one
peripheral should be enabled at a time through the peripheral clock enable bit (in the corresponding RCC
peripheral clock enable register).
5. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited
amount of current (3 mA), the use of GPIOs PC13 to PC15 in output mode is limited: the speed should not
exceed 2 MHz with a maximum load of 30 pF and these IOs must not be used as a current source (e.g. to
drive an LED).
6. Main function after the first backup domain power-up. Later on, it depends on the contents of the Backup
registers even after reset (because these registers are not reset by the main reset). For details on how to
manage these IOs, refer to the Battery backup domain and BKP register description sections in the
STM32F100xx reference manual, available from the STMicroelectronics website: www.st.com.
7. For the LQFP64 package, the pins number 5 and 6 are configured as OSC_IN/OSC_OUT after reset,
however the functionality of PD0 and PD1 can be remapped by software on these pins. For the LQFP100
and LQFP144 packages, PD0 and PD1 are available by default, so there is no need for remapping. For
more details, refer to Alternate function I/O and debug configuration section in the STM32F100xx
reference manual.
8. This alternate function can be remapped by software to some other port pins (if available on the used
package). For more details, refer to the Alternate function I/O and debug configuration section in the
STM32F100xx reference manual, available from the STMicroelectronics website: www.st.com.
9. For devices delivered in LQFP64 packages, the FSMC function is not available.
Table 5.
FSMC pin definition
FSMC
LQFP100(1)
Pins
30/98
NOR/PSRAM/SRAM
NOR/PSRAM Mux
PE2
A23
A23
Yes
PE3
A19
A19
Yes
PE4
A20
A20
Yes
PE5
A21
A21
Yes
PE6
A22
A22
Yes
PF0
A0
-
PF1
A1
-
PF2
A2
-
PF3
A3
-
PF4
A4
-
PF5
A5
-
PF6
-
PF7
-
PF8
-
PF9
-
PF10
-
PF11
-
PF12
A6
-
PF13
A7
-
Doc ID 15081 Rev 7
STM32F100xC, STM32F100xD, STM32F100xE
Table 5.
Pinouts and pin descriptions
FSMC pin definition (continued)
FSMC
LQFP100(1)
Pins
NOR/PSRAM/SRAM
NOR/PSRAM Mux
PF14
A8
-
PF15
A9
-
PG0
A10
-
PG1
A11
-
PE7
D4
DA4
Yes
PE8
D5
DA5
Yes
PE9
D6
DA6
Yes
PE10
D7
DA7
Yes
PE11
D8
DA8
Yes
PE12
D9
DA9
Yes
PE13
D10
DA10
Yes
PE14
D11
DA11
Yes
PE15
D12
DA12
Yes
PD8
D13
DA13
Yes
PD9
D14
DA14
Yes
PD10
D15
DA15
Yes
PD11
A16
A16
Yes
PD12
A17
A17
Yes
PD13
A18
A18
Yes
PD14
D0
DA0
Yes
PD15
D1
DA1
Yes
PG2
A12
-
PG3
A13
-
PG4
A14
-
PG5
A15
-
PG6
-
PG7
-
PD0
D2
DA2
Yes
PD1
D3
DA3
Yes
PD3
CLK
CLK
Yes
PD4
NOE
NOE
Yes
PD5
NWE
NWE
Yes
PD6
NWAIT
NWAIT
Yes
Doc ID 15081 Rev 7
31/98
Memory mapping
STM32F100xC, STM32F100xD, STM32F100xE
Table 5.
FSMC pin definition (continued)
FSMC
LQFP100(1)
Pins
NOR/PSRAM/SRAM
NOR/PSRAM Mux
PD7
NE1
NE1
Yes
PG9
NE2
NE2
-
PG10
NE3
NE3
-
PG11
-
PG12
NE4
NE4
-
PG13
A24
A24
-
PG14
A25
A25
-
PB7
NADV
NADV
Yes
PE0
NBL0
NBL0
Yes
PE1
NBL1
NBL1
Yes
1. Ports F and G are not available in devices delivered in 100-pin packages.
4
Memory mapping
The memory map is shown in Figure 6.
32/98
Doc ID 15081 Rev 7
STM32F100xC, STM32F100xD, STM32F100xE
Figure 6.
Memory map
APB memory space
0xFFFF FFFF
0x4002 3400
0x4002 3000
0x4002 2400
0xFFFF FFFF
7
0xE010 0000
Flash interface
0x4002 1400
reserved
0x4002 1000
RCC
0x4002 0400
DMA2
0x4001 4C00
0x4001 4800
0x4001 4400
6
CRC
reserved
0x4002 2000
0x4002 0000
Cortex-M3 internal
peripherals
0xE000 0000
reserved
0x4001 4000
DMA1
reserved
TIM17
TIM16
TIM15
reserved
0x4001 3C00
0xC000 0000
0x4001 3800
0x4001 3400
0x4001 3000
5
0x4001 2C00
0xA000 0000
FSMC regs
0x4001 2800
0x4001 2400
0x4001 2000
4
0x1FFF FFFF
reserved
0x1FFF F80F
0x8000 0000
Option Bytes
0x1FFF F800
3
0x7000 0000
0x6000 0000
System memory
FSMC
external
memory
0x1FFF F000
0x4000 0000
Peripherals
0x4001 1000
Port C
0x4001 0C00
Port B
0x4001 0800
Port A
0x4001 0400
EXTI
0x4001 0000
AFIO
0x4000 7C00
reserved
0x4000 7000
0x4000 5800
SRAM
Flash memory
0x0000 0000
Reserved
Aliased to Flash or
system memory
depending on
0x0000 0000
BOOT pins
BKP
I2C2
reserved
I2C1
0x4000 5000
0x4000 4400
0x4000 3C00
0x0800 0000
PWR
UART5
UART4
0x4000 4800
0
CEC
DAC
0x4000 5400
0x4000 4C00
0x0801 FFFF
Port G
Port F
Port E
0x4000 5C00
0x2000 0000
ADC1
Port D
0x4000 6C00
1
TIM1
reserved
0x4001 1400
0x4000 7400
reserved
SPI1
0x4001 1C00
0x4001 1800
0x4000 7800
2
USART1
reserved
0x4000 3800
0x4000 3400
USART3
USART2
SPI3
SPI2
reserved
0x4000 3000
IWDG
0x4000 2C00
WWDG
0x4000 2800
0x4000 2000
0x4000 1C00
0x4000 1800
0x4000 1400
0x4000 1000
RTC
TIM14
TIM13
TIM12
TIM7
TIM6
0x4000 0C00
TIM5
0x4000 0800
TIM4
0x4000 0400
TIM3
0x4000 0000
TIM2
ai18400
Doc ID 15081 Rev 7
33/98
Electrical characteristics
STM32F100xC, STM32F100xD, STM32F100xE
5
Electrical characteristics
5.1
Parameter conditions
Unless otherwise specified, all voltages are referenced to VSS.
5.1.1
Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean±3Σ).
5.1.2
Typical values
Unless otherwise specified, typical data are based on TA = 25 °C, VDD = 3.3 V (for the
2 V ≤VDD ≤3.6 V voltage range). They are given only as design guidelines and are not
tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean±2Σ).
5.1.3
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
5.1.4
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 7.
5.1.5
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 8.
34/98
Doc ID 15081 Rev 7
STM32F100xC, STM32F100xD, STM32F100xE
Figure 7.
Pin loading conditions
Electrical characteristics
Figure 8.
Pin input voltage
STM32F10xxx pin
STM32F10xxx pin
C = 50 pF
VIN
ai14124b
ai14123b
5.1.6
Power supply scheme
Figure 9.
Power supply scheme
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Caution:
In Figure 9, the 4.7 µF capacitor must be connected to VDD3.
Doc ID 15081 Rev 7
35/98
Electrical characteristics
5.1.7
STM32F100xC, STM32F100xD, STM32F100xE
Current consumption measurement
Figure 10. Current consumption measurement scheme
IDD_VBAT
VBAT
IDD
VDD
VDDA
ai14126
5.2
Absolute maximum ratings
Stresses above the absolute maximum ratings listed in Table 6: Voltage characteristics,
Table 7: Current characteristics, and Table 8: Thermal characteristics may cause permanent
damage to the device. These are stress ratings only and functional operation of the device
at these conditions is not implied. Exposure to maximum rating conditions for extended
periods may affect device reliability.
Table 6.
Symbol
VDD −VSS
VIN(2)
|ΔVDDx|
|VSSX − VSS|
VESD(HBM)
Voltage characteristics
Ratings
Min
Max
–0.3
4.0
Input voltage on five volt tolerant pin
VSS −0.3
VDD +4.0
Input voltage on any other pin
VSS − 0.3
4.0
External main supply voltage (including
VDDA and VDD)(1)
Variations between different VDD power pins
50
Variations between all the different ground
pins
50
Electrostatic discharge voltage (human body
model)
Unit
V
mV
see Section 5.3.12: Absolute
maximum ratings (electrical
sensitivity)
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power
supply, in the permitted range.
2. VIN maximum must always be respected. Refer to Table 7: Current characteristics for the maximum
allowed injected current values.
36/98
Doc ID 15081 Rev 7
STM32F100xC, STM32F100xD, STM32F100xE
Table 7.
Electrical characteristics
Current characteristics
Symbol
Ratings
Max.
Total current into VDD/VDDA power lines (source)(1)
IVDD
Total current out of VSS ground lines (sink)
IVSS
IIO
150
(1)
150
Output current sunk by any I/O and control pin
25
Output current source by any I/Os and control pin
−25
(3)
Injected current on five volt tolerant pins
IINJ(PIN)(2)
Injected current on any other pin
ΣIINJ(PIN)
Unit
mA
-5 / +0
(4)
±5
Total injected current (sum of all I/O and control pins)
(5)
± 25
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power
supply, in the permitted range.
2. Negative injection disturbs the analog performance of the device. See Note: on page 82.
3. Positive injection is not possible on these I/Os. A negative injection is induced by VIN<VSS. IINJ(PIN) must
never be exceeded. Refer to Table 6: Voltage characteristics for the maximum allowed input voltage
values.
4.
A positive injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. IINJ(PIN) must
never be exceeded. Refer to Table 6: Voltage characteristics for the maximum allowed input voltage
values.
5. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the
positive and negative injected currents (instantaneous values).
Table 8.
Thermal characteristics
Symbol
TSTG
TJ
Ratings
Storage temperature range
Maximum junction temperature
5.3
Operating conditions
5.3.1
General operating conditions
Table 9.
Value
Unit
–65 to +150
°C
150
°C
General operating conditions
Symbol
Parameter
fHCLK
Min
Max
Internal AHB clock frequency
0
24
fPCLK1
Internal APB1 clock frequency
0
24
fPCLK2
Internal APB2 clock frequency
0
24
Standard operating voltage
2
3.6
2
3.6
2.4
3.6
1.8
3.6
VDD
VDDA
(1)
VBAT
Analog operating voltage
(ADC not used)
Analog operating voltage
(ADC used)
Conditions
Must be the same potential
as VDD
Backup operating voltage
Doc ID 15081 Rev 7
Unit
MHz
V
V
V
37/98
Electrical characteristics
Table 9.
Symbol
PD
STM32F100xC, STM32F100xD, STM32F100xE
General operating conditions (continued)
Parameter
Power dissipation at TA =
85 °C for suffix 6 or TA =
105 °C for suffix 7(2)
Conditions
Min
Max
LQFP144
666
LQFP100
434
LQFP64
444
Ambient temperature for 6
suffix version
Maximum power dissipation
–40
85
Low power dissipation
–40
105
Ambient temperature for 7
suffix version
Maximum power dissipation
–40
105
Low power dissipation
–40
125
6 suffix version
–40
105
7 suffix version
–40
125
(3)
Unit
mW
°C
TA
TJ
(3)
°C
Junction temperature range
°C
1. When the ADC is used, refer to Table 51: ADC characteristics.
2. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax (see Section 6.2:
Thermal characteristics on page 92).
3. In low power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax (see
Section 6.2: Thermal characteristics on page 92).
Note:
It is recommended to power VDD and VDDA from the same source. A maximum difference of
300 mV between VDD and VDDA can be tolerated during power-up and operation
5.3.2
Operating conditions at power-up / power-down
Subject to general operating conditions for TA.
Table 10.
Symbol
tVDD
38/98
Operating conditions at power-up / power-down
Parameter
Min
Max
VDD rise time rate
0
∞
VDD fall time rate
20
∞
Doc ID 15081 Rev 7
Unit
µs/V
STM32F100xC, STM32F100xD, STM32F100xE
5.3.3
Electrical characteristics
Embedded reset and power control block characteristics
The parameters given in Table 11 are derived from tests performed under the ambient
temperature and VDD supply voltage conditions summarized in Table 9.
.
Table 11.
Embedded reset and power control block characteristics
Symbol
Parameter
Conditions
Programmable voltage
detector level selection
VPVD
VPVDhyst(2)
PVD hysteresis
VPOR/PDR
Power on/power down
reset threshold
VPDRhyst
(2)
tRSTTEMPO(2)
Min
Typ
Max
Unit
PLS[2:0]=000 (rising edge)
2.1
2.18
2.26
V
PLS[2:0]=000 (falling edge)
2
2.08
2.16
V
PLS[2:0]=001 (rising edge)
2.19
2.28
2.37
V
PLS[2:0]=001 (falling edge)
2.09
2.18
2.27
V
PLS[2:0]=010 (rising edge)
2.28
2.38
2.48
V
PLS[2:0]=010 (falling edge)
2.18
2.28
2.38
V
PLS[2:0]=011 (rising edge)
2.38
2.48
2.58
V
PLS[2:0]=011 (falling edge)
2.28
2.38
2.48
V
PLS[2:0]=100 (rising edge)
2.47
2.58
2.69
V
PLS[2:0]=100 (falling edge)
2.37
2.48
2.59
V
PLS[2:0]=101 (rising edge)
2.57
2.68
2.79
V
PLS[2:0]=101 (falling edge)
2.47
2.58
2.69
V
PLS[2:0]=110 (rising edge)
2.66
2.78
2.9
V
PLS[2:0]=110 (falling edge)
2.56
2.68
2.8
V
PLS[2:0]=111 (rising edge)
2.76
2.88
3
V
PLS[2:0]=111 (falling edge)
2.66
2.78
2.9
V
100
mV
Falling edge
1.8(1)
1.88
1.96
V
Rising edge
1.84
1.92
2.0
V
PDR hysteresis
40
Reset temporization
1.5
2.5
mV
4.5
ms
1. The product behavior is guaranteed by design down to the minimum VPOR/PDR value.
2. Guaranteed by design, not tested in production.
Doc ID 15081 Rev 7
39/98
Electrical characteristics
5.3.4
STM32F100xC, STM32F100xD, STM32F100xE
Embedded reference voltage
The parameters given in Table 12 are derived from tests performed under the ambient
temperature and VDD supply voltage conditions summarized in Table 9.
Table 12.
Symbol
VREFINT
Embedded internal reference voltage
Parameter
Internal reference voltage
Conditions
Min
Typ
Max
Unit
–40 °C < TA < +105 °C
1.16
1.20
1.26
V
–40 °C < TA < +85 °C
1.16
1.20
1.24
V
5.1
17.1(2)
µs
10
mV
100
ppm/°C
ADC sampling time when
TS_vrefint(1) reading the internal
reference voltage
Internal reference voltage
VRERINT(2) spread over the temperature
range
TCoeff(2)
VDD = 3 V ±10 mV
Temperature coefficient
1. Shortest sampling time can be determined in the application by multiple iterations.
2. Guaranteed by design, not tested in production.
5.3.5
Supply current characteristics
The current consumption is a function of several parameters and factors such as the
operating voltage, ambient temperature, I/O pin loading, device software configuration,
operating frequencies, I/O pin switching rate, program location in memory and executed
binary code.
The current consumption is measured as described in Figure 10: Current consumption
measurement scheme.
All Run-mode current consumption measurements given in this section are performed with a
reduced code that gives a consumption equivalent to Dhrystone 2.1 code.
Maximum current consumption
The MCU is placed under the following conditions:
●
All I/O pins are in input mode with a static value at VDD or VSS (no load)
●
All peripherals are disabled except if it is explicitly mentioned
●
Prefetch in on (reminder: this bit must be set before clock setting and bus prescaling)
●
When the peripherals are enabled fPCLK1 = fHCLK/2, fPCLK2 = fHCLK
The parameters given in Table 13 are derived from tests performed under the ambient
temperature and VDD supply voltage conditions summarized in Table 9.
40/98
Doc ID 15081 Rev 7
STM32F100xC, STM32F100xD, STM32F100xE
Table 13.
Electrical characteristics
Maximum current consumption in Run mode, code with data processing
running from Flash
Max(1)
Symbol
Parameter
Conditions
External clock (2), all
peripherals enabled
External clock(2), all
peripherals disabled
IDD
Supply
current in
Run mode
fHCLK
Unit
TA = 85 °C
TA = 105 °C
24 MHz
19.7
20
16 MHz
14.6
14.7
8 MHz
8.2
8.6
24 MHz
11.3
11.6
16 MHz
8.7
8.9
8 MHz
5.6
6
24 MHz
19
19
16 MHz
13.1
13.2
8 MHz
10.1
10.1
24 MHz
9.4
9.6
16 MHz
6.7
7
8 MHz
5.4
5.6
mA
HSI clock(2), all peripherals
enabled
HSI clock(2), all peripherals
disabled
1. Based on characterization, not tested in production.
2. External clock or HSI frequency is 8 MHz and PLL is on when fHCLK > 8 MHz.
Table 14.
Maximum current consumption in Run mode, code with data processing
running from RAM
Max(1)
Symbol
Parameter
Conditions
External clock (2), all
peripherals enabled
External clock(2) all
peripherals disabled
IDD
Supply current
in Run mode
fHCLK
Unit
TA = 85 °C
TA = 105 °C
24 MHz
18.5
19
16 MHz
13.1
13.5
8 MHz
7.3
7.6
24 MHz
8.4
8.5
16 MHz
7.3
7.7
8 MHz
4.8
5.2
24 MHz
17.2
17.2
16 MHz
11.7
11.8
8 MHz
8.9
9
24 MHz
8.1
8.3
16 MHz
5.6
5.8
8 MHz
4.3
4.5
mA
HSI clock(2), all
peripherals enabled
HSI clock(2), all
peripherals disabled
1. Based on characterization, tested in production at VDD max, fHCLK max.
2. External clock or HSI frequency is 8 MHz and PLL is on when fHCLK > 8 MHz.
Doc ID 15081 Rev 7
41/98
Electrical characteristics
Table 15.
STM32F100xC, STM32F100xD, STM32F100xE
STM32F100xxB maximum current consumption in Sleep mode, code
running from Flash or RAM
Max(1)
Symbol
Parameter
Conditions
External clock(2) all
peripherals enabled
External clock(2), all
peripherals disabled
IDD
Supply current
in Sleep mode
fHCLK
Unit
TA = 85 °C
TA = 105 °C
24 MHz
14.1
14.3
16 MHz
9.7
10.3
8 MHz
5.9
6.2
24 MHz
4.2
4.6
16 MHz
3.7
4.1
8 MHz
2.9
3.4
24 MHz
12.5
12.7
16 MHz
8.2
8.5
8 MHz
6.4
6.6
24 MHz
2.3
2.5
16 MHz
1.7
2
8 MHz
1.4
1.7
mA
HSI clock(2), all
peripherals enabled
HSI clock(2), all
peripherals disabled
1. Based on characterization, tested in production at VDD max and fHCLK max with peripherals enabled.
2. External clock or HSI frequency is 8 MHz and PLL is on when fHCLK > 8 MHz.
42/98
Doc ID 15081 Rev 7
STM32F100xC, STM32F100xD, STM32F100xE
Table 16.
Electrical characteristics
Typical and maximum current consumptions in Stop and Standby modes
Typ(1)
Symbol
Parameter
Conditions
VDD/VBAT VDD/ VBAT VDD/VBAT TA =
TA =
= 2.0 V
= 2.4 V
= 3.3 V 85 °C 105 °C
Regulator in Run mode,
Low-speed and high-speed
internal RC oscillators and highspeed oscillator OFF (no
Supply current independent watchdog)
in Stop mode Regulator in Low-Power mode,
Low-speed and high-speed
internal RC oscillators and highspeed oscillator OFF (no
independent watchdog)
IDD
Low-speed internal RC oscillator
and independent watchdog ON
31
320
670
24
305
650
Unit
µA
3.2
Low-speed internal RC oscillator
Supply current
ON, independent watchdog OFF
in Standby
mode
Low-speed internal RC oscillator
and independent watchdog OFF,
low-speed oscillator and RTC
OFF
Backup
Low-speed oscillator and RTC
IDD_VBAT domain supply
ON
current
Max
3.1
1.0
1.2
2.2
3.9
5.7
1.4
2
2.3
1. Typical values are measured at TA = 25 °C.
Typical current consumption
The MCU is placed under the following conditions:
●
All I/O pins are in input mode with a static value at VDD or VSS (no load)
●
All peripherals are disabled except if it is explicitly mentioned
●
When the peripherals are enabled fPCLK1 = fHCLK/4, fPCLK2 = fHCLK/2, fADCCLK =
fPCLK2/4
The parameters given in Table 17 are derived from tests performed under the ambient
temperature and VDD supply voltage conditions summarized in Table 9.
Doc ID 15081 Rev 7
43/98
Electrical characteristics
Table 17.
STM32F100xC, STM32F100xD, STM32F100xE
Typical current consumption in Run mode, code with data processing
running from Flash
Typical values(1)
Symbol Parameter
Conditions
Running on high-speed
external clock with an
8 MHz crystal(3)
IDD
Supply
current in
Run mode
fHCLK
All peripherals All peripherals
enabled(2)
disabled
24 MHz
14.1
9.5
16 MHz
10
6.85
8 MHz
5.8
4.05
4 MHz
3.6
2.65
2 MHz
2.3
1.85
1 MHz
1.7
1.46
500 kHz
1.4
1.3
125 kHz
1.15
1.1
24 MHz
13.4
8.7
16 MHz
9.3
6.2
8 MHz
5.2
3.45
4 MHz
2.95
2.1
2 MHz
1.7
1.3
1 MHz
1.1
0.9
500 kHz
0.8
0.7
125 kHz
0.6
0.55
Unit
mA
Running on high-speed
internal RC (HSI)
1. Typical values are measures at TA = 25 °C, VDD = 3.3 V.
2. Add an additional power consumption of 0.8 mA for the ADC and of 0.5 mA for the DAC analog part. In
applications, this consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register).
3. An 8 MHz crystal is used as the external clock source. The AHB prescaler is used to reduce the frequency
when fHCLK < 8 MHz, the PLL is used when fHCLK > 8 MHz.
44/98
Doc ID 15081 Rev 7
STM32F100xC, STM32F100xD, STM32F100xE
Table 18.
Electrical characteristics
Typical current consumption in Sleep mode, code running from Flash or
RAM
Typical values(1)
Symbol Parameter
Conditions
Running on high-speed
external clock with an
8 MHz crystal(3)
IDD
Supply
current in
Sleep
mode
fHCLK
All peripherals All peripherals
enabled(2)
disabled
24 MHz
8.7
2.75
16 MHz
6.1
2.1
8 MHz
3.3
1.3
4 MHz
2.25
1.2
2 MHz
1.65
1.15
1 MHz
1.35
1.1
500 kHz
1.2
1.07
125 kHz
1.1
1.05
24 MHz
8
2.15
16 MHz
5.5
1.5
8 MHz
2.7
0.75
4 MHz
1.65
0.6
2 MHz
1.1
0.55
1 MHz
0.8
0.5
500 kHz
0.65
0.49
125 kHz
0.53
0.47
Unit
mA
Running on high-speed
internal RC (HSI)
1. Typical values are measures at TA = 25 °C, VDD = 3.3 V.
2. Add an additional power consumption of 0.8 mA for the ADC and of 0.5 mA for the DAC analog part. In
applications, this consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register).
3. An 8 MHz crystal is used as the external clock source. The AHB prescaler is used to reduce the frequency
when fHCLK > 8 MHz, the PLL is used when fHCLK > 8 MHz.
Doc ID 15081 Rev 7
45/98
Electrical characteristics
STM32F100xC, STM32F100xD, STM32F100xE
On-chip peripheral current consumption
The current consumption of the on-chip peripherals is given in Table 19. The MCU is placed
under the following conditions:
●
all I/O pins are in input mode with a static value at VDD or VSS (no load)
●
all peripherals are disabled unless otherwise mentioned
●
the given value is calculated by measuring the current consumption
●
–
with all peripherals clocked off
–
with only one peripheral clocked on
ambient operating temperature and VDD supply voltage conditions summarized in
Table 6.
Table 19.
Peripheral current consumption
Peripheral
Typical consumption at 25 °C(1)
TIM2
0.48
TIM3
0.49
TIM4
0.48
TIM5
0.48
TIM6
0.2
TIM7
0.2
TIM12
0.32
TIM13
0.25
TIM14
0.25
1.06(2)
DAC
APB1
46/98
Unit
mA
WWDG
0.15
SPI2
0.2
SPI3
0.19
USART2
0.36
USART3
0.36
UART4
0.35
UART5
0.36
I2C1
0.34
I2C2
0.34
HDMI CEC
0.2
Doc ID 15081 Rev 7
STM32F100xC, STM32F100xD, STM32F100xE
Table 19.
Electrical characteristics
Peripheral current consumption (continued)
Peripheral
Typical consumption at 25 °C(1)
GPIO A
0.26
GPIO B
0.26
GPIO C
0.26
GPIO D
0.26
GPIO E
0.26
GPIO F
0.24
GPIO G
0.25
(3)
1.28
APB2
ADC1
Unit
mA
SPI1
0.2
USART1
0.37
TIM1
0.63
TIM15
0.43
TIM16
0.34
TIM17
0.34
1. fHCLK = fAPB1 = fAPB2 = 24 MHz, default prescaler value for each peripheral.
2. Specific conditions for DAC: EN1 bit in DAC_CR register set to 1.
3. Specific conditions for ADC: fHCLK = 24 MHz, fAPB1 = fAPB2 = fHCLK, fADCCLK = fAPB2/2, ADON bit in the
ADC_CR2 register is set to 1.
5.3.6
External clock source characteristics
High-speed external user clock generated from an external source
The characteristics given in Table 20 result from tests performed using an high-speed
external clock source, and under the ambient temperature and supply voltage conditions
summarized in Table 9.
Table 20.
Symbol
High-speed external user clock characteristics
Parameter
Conditions
Min
Typ
Max
Unit
8
24
MHz
fHSE_ext
User external clock source
frequency(1)
1
VHSEH
OSC_IN input pin high level
voltage(1)
0.7VDD
VDD
VHSEL
OSC_IN input pin low level
voltage(1)
VSS
0.3VDD
tw(HSE)
tw(HSE)
OSC_IN high or low time(1)
5
tr(HSE)
tf(HSE)
OSC_IN rise or fall time(1)
V
Cin(HSE)
ns
OSC_IN input capacitance(1)
Doc ID 15081 Rev 7
20
5
pF
47/98
Electrical characteristics
Table 20.
STM32F100xC, STM32F100xD, STM32F100xE
High-speed external user clock characteristics
Symbol
Parameter
Conditions
Min
(1)
DuCy(HSE) Duty cycle
IL
Typ
45
OSC_IN Input leakage current
VSS ≤VIN ≤VDD
Max
Unit
55
%
±1
µA
1. Guaranteed by design, not tested in production.
Low-speed external user clock generated from an external source
The characteristics given in Table 21 result from tests performed using an low-speed
external clock source, and under the ambient temperature and supply voltage conditions
summarized in Table 9.
Table 21.
Symbol
Low-speed external user clock characteristics
Parameter
Conditions
Min
fLSE_ext
User external clock source
frequency(1)
VLSEH
OSC32_IN input pin high level
voltage(1)
VLSEL
OSC32_IN input pin low level
voltage(1)
VSS
tw(LSE)
tw(LSE)
OSC32_IN high or low time(1)
450
Typ
Max
Unit
32.768
1000
kHz
0.7VDD
VDD
V
tr(LSE)
tf(LSE)
Cin(LSE)
ns
OSC32_IN rise or fall
time(1)
50
OSC32_IN input capacitance(1)
5
DuCy(LSE) Duty cycle(1)
IL
30
OSC32_IN Input leakage current
VSS ≤VIN ≤VDD
1. Guaranteed by design, not tested in production.
48/98
0.3VDD
Doc ID 15081 Rev 7
pF
70
%
±1
µA
STM32F100xC, STM32F100xD, STM32F100xE
Electrical characteristics
Figure 11. High-speed external clock source AC timing diagram
VHSEH
90%
VHSEL
10%
tr(HSE)
tf(HSE)
tW(HSE)
tW(HSE)
t
THSE
External
clock source
fHSE_ext
OSC _IN
IL
STM32F10xxx
ai14127b
Figure 12. Low-speed external clock source AC timing diagram
VLSEH
90%
VLSEL
10%
tr(LSE)
tf(LSE)
tW(LSE)
OSC32_IN
IL
tW(LSE)
t
TLSE
External
clock source
fLSE_ext
STM32F10xxx
ai14140c
High-speed external clock generated from a crystal/ceramic resonator
The high-speed external (HSE) clock can be supplied with a 4 to 24 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on characterization
results obtained with typical external components specified in Table 22. In the application,
the resonator and the load capacitors have to be placed as close as possible to the oscillator
pins in order to minimize output distortion and startup stabilization time. Refer to the crystal
resonator manufacturer for more details on the resonator characteristics (frequency,
package, accuracy).
Doc ID 15081 Rev 7
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Electrical characteristics
Table 22.
STM32F100xC, STM32F100xD, STM32F100xE
HSE 4-24 MHz oscillator characteristics(1)(2)
Symbol
fOSC_IN
RF
Parameter
Conditions
Oscillator frequency
RS = 30 Ω
i2
HSE driving current
VDD = 3.3 V
VIN = VSS with 30 pF
load
gm
Oscillator transconductance
Startup
Startup time
VDD is stabilized
tSU(HSE)
(5)
Typ
Max
Unit
4
8
24
MHz
Feedback resistor
Recommended load capacitance
versus equivalent serial
resistance of the crystal (RS)(4)
CL1
CL2(3)
Min
200
kΩ
30
pF
1
25
mA
mA/V
2
ms
1. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
2. Based on characterization, not tested in production.
3. It is recommended to use high-quality external ceramic capacitors in the 5 pF to 25 pF range (typ.),
designed for high-frequency applications, and selected to match the requirements of the crystal or
resonator. CL1 and CL2, are usually the same size. The crystal manufacturer typically specifies a load
capacitance which is the series combination of CL1 and CL2. PCB and MCU pin capacitance must be
included (10 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing
CL1 and CL2.
4. The relatively low value of the RF resistor offers a good protection against issues resulting from use in a
humid environment, due to the induced leakage and the bias condition change. However, it is
recommended to take this point into account if the MCU is used in tough humidity conditions.
5. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz
oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly
with the crystal manufacturer
Figure 13. Typical application with an 8 MHz crystal
Resonator with
integrated capacitors
CL1
fHSE
OSC_IN
8 MH z
resonator
CL2
REXT(1)
RF
OSC_OU T
Bias
controlled
gain
STM32F10xxx
ai14128b
1. REXT value depends on the crystal characteristics.
Low-speed external clock generated from a crystal/ceramic resonator
The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on characterization
results obtained with typical external components specified in Table 23. In the application,
the resonator and the load capacitors have to be placed as close as possible to the oscillator
pins in order to minimize output distortion and startup stabilization time. Refer to the crystal
resonator manufacturer for more details on the resonator characteristics (frequency,
package, accuracy).
50/98
Doc ID 15081 Rev 7
STM32F100xC, STM32F100xD, STM32F100xE
Electrical characteristics
Note:
For CL1 and CL2 it is recommended to use high-quality ceramic capacitors in the 5 pF to
15 pF range selected to match the requirements of the crystal or resonator. CL1 and CL2, are
usually the same size. The crystal manufacturer typically specifies a load capacitance which
is the series combination of CL1 and CL2.
Load capacitance CL has the following formula: CL = CL1 x CL2 / (CL1 + CL2) + Cstray where
Cstray is the pin capacitance and board or trace PCB-related capacitance. Typically, it is
between 2 pF and 7 pF.
Caution:
To avoid exceeding the maximum value of CL1 and CL2 (15 pF) it is strongly recommended
to use a resonator with a load capacitance CL ≤ 7 pF. Never use a resonator with a load
capacitance of 12.5 pF.
Example: if you choose a resonator with a load capacitance of CL = 6 pF, and Cstray = 2 pF,
then CL1 = CL2 = 8 pF.
Table 23.
LSE oscillator characteristics (fLSE = 32.768 kHz)(1)
Symbol
RF
Parameter
Conditions
Min
Feedback resistor
Typ
Max
5
Unit
MΩ
Recommended load capacitance
versus equivalent serial
resistance of the crystal (RS)(3)
RS = 30 KΩ
15
pF
I2
LSE driving current
VDD = 3.3 V
VIN = VSS
1.4
µA
gm
Oscillator transconductance
CL1
CL2(2)
tSU(LSE)(4)
5
VDD is
stabilized
Startup time
µA/V
TA = 50 °C
1.5
TA = 25 °C
2.5
TA = 10 °C
4
TA = 0 °C
6
TA = -10 °C
10
TA = -20 °C
17
TA = -30 °C
32
TA = -40 °C
60
s
1. Based on characterization, not tested in production.
2. Refer to the note and caution paragraphs above the table.
3. The oscillator selection can be optimized in terms of supply current using an high quality resonator with small RS value for
example MSIV-TIN32.768 kHz. Refer to crystal manufacturer for more details
4.
tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is
reached. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer
Doc ID 15081 Rev 7
51/98
Electrical characteristics
STM32F100xC, STM32F100xD, STM32F100xE
Figure 14. Typical application with a 32.768 kHz crystal
Resonator with
integrated capacitors
CL1
fLSE
OSC32_IN
32.768 KH z
resonator
RF
Bias
controlled
gain
STM32F10xxx
OSC32_OU T
CL2
ai14129b
5.3.7
Internal clock source characteristics
The parameters given in Table 24 are derived from tests performed under the ambient
temperature and VDD supply voltage conditions summarized in Table 9.
High-speed internal (HSI) RC oscillator
Table 24.
HSI oscillator characteristics(1)
Symbol
fHSI
Parameter
Conditions
Frequency
Accuracy of HSI oscillator
TA = –10 to 85
TA = 0 to 70
°C(2)
°C(2)
TA = 25 °C
tsu(HSI)(3) HSI oscillator startup time
IDD(HSI)(3)
Typ
Max
8
TA = –40 to 105 °C(2)
ACCHSI
Min
Unit
MHz
-2.4
2.5
%
-2.2
1.3
%
-1.9
1.3
%
-1
1
%
1
2
µs
100
µA
HSI oscillator power consumption
80
1. VDD = 3.3 V, TA = –40 to 105 °C °C unless otherwise specified.
2. Based on characterization, not tested in production.
3. Guaranteed by design. Not tested in production
Low-speed internal (LSI) RC oscillator
Table 25.
LSI oscillator characteristics (1)
Symbol
fLSI
Parameter
Frequency
tsu(LSI)(2)
LSI oscillator startup time
IDD(LSI)(2)
LSI oscillator power consumption
1. VDD = 3 V, TA = –40 to 105 °C °C unless otherwise specified.
2. Guaranteed by design, not tested in production.
52/98
Doc ID 15081 Rev 7
Min
Typ
Max
Unit
30
40
60
kHz
85
µs
1.2
µA
0.65
STM32F100xC, STM32F100xD, STM32F100xE
Electrical characteristics
Wakeup time from low-power mode
The wakeup times given in Table 26 are measured on a wakeup phase with an 8-MHz HSI
RC oscillator. The clock source used to wake up the device depends from the current
operating mode:
●
Stop or Standby mode: the clock source is the RC oscillator
●
Sleep mode: the clock source is the clock that was set before entering Sleep mode.
All timings are derived from tests performed under the ambient temperature and VDD supply
voltage conditions summarized in Table 9.
Table 26.
Low-power mode wakeup timings
Symbol
Parameter
tWUSLEEP(1)
tWUSTOP(1)
tWUSTDBY(1)
Typ
Unit
Wakeup from Sleep mode
1.8
µs
Wakeup from Stop mode (regulator in run mode)
3.6
Wakeup from Stop mode (regulator in low-power mode)
5.4
Wakeup from Standby mode
50
µs
µs
1. The wakeup times are measured from the wakeup event to the point at which the user application code
reads the first instruction.
5.3.8
PLL characteristics
The parameters given in Table 27 are derived from tests performed under the ambient
temperature and VDD supply voltage conditions summarized in Table 9.
Table 27.
PLL characteristics
Value
Symbol
Parameter
Unit
Min(1)
Typ
Max(1)
PLL input clock(2)
1
8.0
24
MHz
PLL input clock duty cycle
40
60
%
fPLL_OUT
PLL multiplier output clock
16
24
MHz
tLOCK
PLL lock time
200
µs
Jitter
Cycle-to-cycle jitter
300
ps
fPLL_IN
1. Based on device characterization, not tested in production.
2. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with
the range defined by fPLL_OUT.
Doc ID 15081 Rev 7
53/98
Electrical characteristics
5.3.9
STM32F100xC, STM32F100xD, STM32F100xE
Memory characteristics
Flash memory
The characteristics are given at TA = –40 to 105 °C unless otherwise specified.
Table 28.
Flash memory characteristics
Symbol
Parameter
Conditions
Min(1)
Typ
Max(1)
Unit
tprog
16-bit programming time
TA = –40 to +105 °C
40
52.5
70
µs
tERASE
Page (2 KB) erase time
TA = –40 to +105 °C
20
40
ms
Mass erase time
TA = –40 to +105 °C
20
40
ms
Read mode
fHCLK = 24 MHz, VDD = 3.3 V
20
mA
Write / Erase modes
fHCLK = 24 MHz, VDD = 3.3 V
5
mA
Power-down mode / Halt,
VDD = 3.0 to 3.6 V
50
µA
3.6
V
tME
IDD
Vprog
Supply current
Programming voltage
2
1. Guaranteed by design, not tested in production.
Table 29.
Flash memory endurance and data retention
Value
Symbol
NEND
tRET
Parameter
Endurance
Conditions
Min(1)
TA = –40 to +85 °C (6 suffix versions)
TA = –40 to +105 °C (7 suffix versions)
10
1 kcycle(2) at TA = 85 °C
30
Data retention 1
kcycle(2)
at TA = 105 °C
10 kcycles(2) at TA = 55 °C
10
Unit
Typ
Max
kcycles
Years
20
1. Based on characterization not tested in production.
2. Cycling performed over the whole temperature range.
5.3.10
FSMC characteristics
Asynchronous waveforms and timings
Figure 15 through Figure 18 represent asynchronous waveforms and Table 30 through
Table 33 provide the corresponding timings. The results shown in these tables are obtained
with the following FSMC configuration:
54/98
●
AddressSetupTime = 0
●
AddressHoldTime = 1
●
DataSetupTime = 1
Doc ID 15081 Rev 7
STM32F100xC, STM32F100xD, STM32F100xE
Electrical characteristics
Figure 15. Asynchronous non-multiplexed SRAM/PSRAM/NOR
read waveforms
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Doc ID 15081 Rev 7
55/98
Electrical characteristics
Table 30.
STM32F100xC, STM32F100xD, STM32F100xE
Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings(1) (2)
Symbol
Parameter
Max
Unit
tw(NE)
FSMC_NE low time
5THCLK – 1.5
5THCLK + 2
ns
tv(NOE_NE)
FSMC_NEx low to FSMC_NOE low
0.5
1.5
ns
tw(NOE)
FSMC_NOE low time
5THCLK – 1.5
5THCLK + 1.5
ns
th(NE_NOE)
FSMC_NOE high to FSMC_NE high hold time –1.5
tv(A_NE)
FSMC_NEx low to FSMC_A valid
th(A_NOE)
Address hold time after FSMC_NOE high
tv(BL_NE)
FSMC_NEx low to FSMC_BL valid
th(BL_NOE)
FSMC_BL hold time after FSMC_NOE high
0
ns
tsu(Data_NE)
Data to FSMC_NEx high setup time
2THCLK + 25
ns
2THCLK + 25
ns
tsu(Data_NOE) Data to FSMC_NOEx high setup time
ns
0
0.1
ns
ns
0
ns
th(Data_NOE)
Data hold time after FSMC_NOE high
0
ns
th(Data_NE)
Data hold time after FSMC_NEx high
0
ns
tv(NADV_NE)
FSMC_NEx low to FSMC_NADV low
5
ns
tw(NADV)
FSMC_NADV low time
THCLK + 1.5
ns
1. CL = 15 pF.
2. Preliminary values.
56/98
Min
Doc ID 15081 Rev 7
STM32F100xC, STM32F100xD, STM32F100xE
Electrical characteristics
Figure 16. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms
tw(NE)
FSMC_NEx
FSMC_NOE
tv(NWE_NE)
tw(NWE)
t h(NE_NWE)
FSMC_NWE
tv(A_NE)
FSMC_A[25:0]
th(A_NWE)
Address
tv(BL_NE)
FSMC_NBL[1:0]
th(BL_NWE)
NBL
tv(Data_NE)
th(Data_NWE)
Data
FSMC_D[15:0]
t v(NADV_NE)
tw(NADV)
FSMC_NADV(1)
ai14990
1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used.
Table 31.
Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings(1)(2)
Symbol
Parameter
Min
Max
Unit
tw(NE)
FSMC_NE low time
3THCLK – 1
3THCLK + 2
ns
tv(NWE_NE)
FSMC_NEx low to FSMC_NWE low
THCLK – 0.5
THCLK + 1.5
ns
tw(NWE)
FSMC_NWE low time
THCLK – 0.5
THCLK + 1.5
ns
th(NE_NWE)
FSMC_NWE high to FSMC_NE high hold time
THCLK
tv(A_NE)
FSMC_NEx low to FSMC_A valid
th(A_NWE)
Address hold time after FSMC_NWE high
tv(BL_NE)
FSMC_NEx low to FSMC_BL valid
th(BL_NWE)
FSMC_BL hold time after FSMC_NWE high
tv(Data_NE)
FSMC_NEx low to Data valid
th(Data_NWE)
Data hold time after FSMC_NWE high
tv(NADV_NE)
FSMC_NEx low to FSMC_NADV low
5.5
ns
tw(NADV)
FSMC_NADV low time
THCLK + 1.5
ns
ns
7.5
THCLK
ns
ns
1.5
THCLK – 0.5
ns
ns
THCLK + 7
THCLK
ns
ns
1. CL = 15 pF.
2. Preliminary values.
Doc ID 15081 Rev 7
57/98
Electrical characteristics
STM32F100xC, STM32F100xD, STM32F100xE
Figure 17. Asynchronous multiplexed PSRAM/NOR read waveforms
tw(NE)
FSMC_NE
tv(NOE_NE)
t h(NE_NOE)
FSMC_NOE
t w(NOE)
FSMC_NWE
tv(A_NE)
FSMC_A[25:16]
t h(A_NOE)
Address
tv(BL_NE)
th(BL_NOE)
FSMC_NBL[1:0]
NBL
th(Data_NE)
tsu(Data_NE)
t v(A_NE)
tsu(Data_NOE)
Address
FSMC_AD[15:0]
t v(NADV_NE)
th(Data_NOE)
Data
th(AD_NADV)
tw(NADV)
FSMC_NADV
ai14892b
Table 32.
Asynchronous multiplexed PSRAM/NOR read timings(1)(2)
Symbol
Parameter
Max
7THCLK + 2
Unit
tw(NE)
FSMC_NE low time
7THCLK – 2
tv(NOE_NE)
FSMC_NEx low to FSMC_NOE low
3THCLK – 0.5 3THCLK + 1.5
ns
tw(NOE)
FSMC_NOE low time
4THCLK – 1
ns
th(NE_NOE)
FSMC_NOE high to FSMC_NE high hold time
–1
tv(A_NE)
FSMC_NEx low to FSMC_A valid
tv(NADV_NE)
FSMC_NEx low to FSMC_NADV low
tw(NADV)
4THCLK + 2
ns
ns
0
ns
3
5
ns
FSMC_NADV low time
THCLK –1.5
THCLK + 1.5
ns
th(AD_NADV)
FSMC_AD (address) valid hold time after
FSMC_NADV high
THCLK
ns
th(A_NOE)
Address hold time after FSMC_NOE high
THCLK
ns
th(BL_NOE)
FSMC_BL hold time after FSMC_NOE high
0
ns
tv(BL_NE)
FSMC_NEx low to FSMC_BL valid
tsu(Data_NE)
Data to FSMC_NEx high setup time
2THCLK + 24
ns
tsu(Data_NOE) Data to FSMC_NOE high setup time
2THCLK + 25
ns
th(Data_NE)
Data hold time after FSMC_NEx high
0
ns
th(Data_NOE)
Data hold time after FSMC_NOE high
0
ns
1. CL = 15 pF.
2. Preliminary values.
58/98
Min
Doc ID 15081 Rev 7
0
ns
STM32F100xC, STM32F100xD, STM32F100xE
Electrical characteristics
Figure 18. Asynchronous multiplexed PSRAM/NOR write waveforms
tw(NE)
FSMC_NEx
FSMC_NOE
tv(NWE_NE)
tw(NWE)
t h(NE_NWE)
FSMC_NWE
tv(A_NE)
FSMC_A[25:16]
th(A_NWE)
Address
tv(BL_NE)
th(BL_NWE)
FSMC_NBL[1:0]
NBL
t v(A_NE)
t v(Data_NADV)
Address
FSMC_AD[15:0]
t v(NADV_NE)
th(Data_NWE)
Data
th(AD_NADV)
tw(NADV)
FSMC_NADV
ai14891B
Table 33.
Asynchronous multiplexed PSRAM/NOR write timings(1)(2)
Symbol
Parameter
Min
Max
Unit
tw(NE)
FSMC_NE low time
5THCLK – 1
5THCLK + 2
ns
tv(NWE_NE)
FSMC_NEx low to FSMC_NWE low
2THCLK
2THCLK + 1
ns
tw(NWE)
FSMC_NWE low time
2THCLK – 1
2THCLK + 2
ns
th(NE_NWE)
FSMC_NWE high to FSMC_NE high hold time
THCLK – 1
tv(A_NE)
FSMC_NEx low to FSMC_A valid
tv(NADV_NE)
FSMC_NEx low to FSMC_NADV low
tw(NADV)
ns
7
ns
3
5
ns
FSMC_NADV low time
THCLK – 1
THCLK + 1
ns
th(AD_NADV)
FSMC_AD (address) valid hold time after
FSMC_NADV high
THCLK – 3
ns
th(A_NWE)
Address hold time after FSMC_NWE high
4THCLK
ns
tv(BL_NE)
FSMC_NEx low to FSMC_BL valid
th(BL_NWE)
FSMC_BL hold time after FSMC_NWE high
1.6
THCLK – 1.5
tv(Data_NADV) FSMC_NADV high to Data valid
th(Data_NWE)
Data hold time after FSMC_NWE high
ns
THCLK + 1.5
THCLK – 5
ns
ns
ns
1. CL = 15 pF.
2. Preliminary values.
Doc ID 15081 Rev 7
59/98
Electrical characteristics
STM32F100xC, STM32F100xD, STM32F100xE
Synchronous waveforms and timings
Figure 19 through Figure 22 represent synchronous waveforms and Table 35 through
Table 37 provide the corresponding timings. The results shown in these tables are obtained
with the following FSMC configuration:
●
BurstAccessMode = FSMC_BurstAccessMode_Enable;
●
MemoryType = FSMC_MemoryType_CRAM;
●
WriteBurst = FSMC_WriteBurst_Enable;
●
CLKDivision = 1; (0 is not supported, see the STM32F10xxx reference manual)
●
DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM
Figure 19. Synchronous multiplexed NOR/PSRAM read timings
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60/98
Doc ID 15081 Rev 7
STM32F100xC, STM32F100xD, STM32F100xE
Table 34.
Electrical characteristics
Synchronous multiplexed NOR/PSRAM read timings(1)(2)
Symbol
Parameter
Min
Max
Unit
tw(CLK)
FSMC_CLK period
td(CLKL-NExL)
FSMC_CLK low to FSMC_NEx low (x = 0...2)
td(CLKL-NExH)
FSMC_CLK low to FSMC_NEx high (x = 0...2)
td(CLKL-NADVL)
FSMC_CLK low to FSMC_NADV low
td(CLKL-NADVH)
FSMC_CLK low to FSMC_NADV high
td(CLKL-AV)
FSMC_CLK low to FSMC_Ax valid (x = 16...25)
td(CLKL-AIV)
FSMC_CLK low to FSMC_Ax invalid (x = 16...25)
td(CLKH-NOEL)
FSMC_CLK high to FSMC_NOE low
td(CLKL-NOEH)
FSMC_CLK low to FSMC_NOE high
td(CLKL-ADV)
FSMC_CLK low to FSMC_AD[15:0] valid
td(CLKL-ADIV)
FSMC_CLK low to FSMC_AD[15:0] invalid
0
ns
tsu(ADV-CLKH)
FSMC_A/D[15:0] valid data before FSMC_CLK
high
6
ns
th(CLKH-ADV)
FSMC_A/D[15:0] valid data after FSMC_CLK high 0
ns
tsu(NWAITV-CLKH) FSMC_NWAIT valid before FSMC_CLK high
th(CLKH-NWAITV)
FSMC_NWAIT valid after FSMC_CLK high
27.7
ns
1.5
2
ns
ns
4
5
ns
ns
0
2
ns
ns
1
0.5
ns
ns
12
ns
8
ns
2
ns
1. CL = 15 pF.
2. Preliminary values.
Doc ID 15081 Rev 7
61/98
Electrical characteristics
STM32F100xC, STM32F100xD, STM32F100xE
Figure 20. Synchronous multiplexed PSRAM write timings
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62/98
Doc ID 15081 Rev 7
STM32F100xC, STM32F100xD, STM32F100xE
Table 35.
Electrical characteristics
Synchronous multiplexed PSRAM write timings(1)(2)
Symbol
Parameter
Min
Max
Unit
tw(CLK)
FSMC_CLK period
td(CLKL-NExL)
FSMC_CLK low to FSMC_Nex low (x = 0...2)
td(CLKL-NExH)
FSMC_CLK low to FSMC_NEx high (x = 0...2)
td(CLKL-NADVL)
FSMC_CLK low to FSMC_NADV low
td(CLKL-NADVH)
FSMC_CLK low to FSMC_NADV high
td(CLKL-AV)
FSMC_CLK low to FSMC_Ax valid (x = 16...25)
td(CLKL-AIV)
FSMC_CLK low to FSMC_Ax invalid (x = 16...25)
td(CLKL-NWEL)
FSMC_CLK low to FSMC_NWE low
td(CLKL-NWEH)
FSMC_CLK low to FSMC_NWE high
td(CLKL-ADV)
FSMC_CLK low to FSMC_AD[15:0] valid
td(CLKL-ADIV)
FSMC_CLK low to FSMC_AD[15:0] invalid
td(CLKL-Data)
FSMC_A/D[15:0] valid after FSMC_CLK low
tsu(NWAITV-CLKH)
FSMC_NWAIT valid before FSMC_CLK high
7
ns
th(CLKH-NWAITV)
FSMC_NWAIT valid after FSMC_CLK high
2
ns
td(CLKL-NBLH)
FSMC_CLK low to FSMC_NBL high
1
ns
27.7
ns
2
2
ns
ns
4
5
ns
ns
0
2
ns
ns
1
1
ns
ns
12
3
ns
ns
6
ns
1. CL = 15 pF.
2. Preliminary values
Doc ID 15081 Rev 7
63/98
Electrical characteristics
STM32F100xC, STM32F100xD, STM32F100xE
Figure 21. Synchronous non-multiplexed NOR/PSRAM read timings
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Table 36.
Synchronous non-multiplexed NOR/PSRAM read timings(1)(2)
Symbol
Parameter
Max
FSMC_CLK period
td(CLKL-NExL)
FSMC_CLK low to FSMC_NEx low (x = 0...2)
td(CLKL-NExH)
FSMC_CLK low to FSMC_NEx high (x = 0...2)
td(CLKL-NADVL)
FSMC_CLK low to FSMC_NADV low
td(CLKL-NADVH)
FSMC_CLK low to FSMC_NADV high
td(CLKL-AV)
FSMC_CLK low to FSMC_Ax valid (x = 0...25)
td(CLKL-AIV)
FSMC_CLK low to FSMC_Ax invalid (x = 0...25)
td(CLKH-NOEL)
FSMC_CLK high to FSMC_NOE low
td(CLKL-NOEH)
FSMC_CLK low to FSMC_NOE high
1.5
ns
tsu(DV-CLKH)
FSMC_D[15:0] valid data before FSMC_CLK high 6.5
ns
th(CLKH-DV)
FSMC_D[15:0] valid data after FSMC_CLK high
7
ns
tsu(NWAITV-CLKH) FSMC_NWAIT valid before FSMC_SMCLK high
7
ns
th(CLKH-NWAITV)
2
ns
FSMC_NWAIT valid after FSMC_CLK high
2. Preliminary values.
Doc ID 15081 Rev 7
27.7
Unit
tw(CLK)
1. CL = 15 pF.
64/98
Min
ns
1.5
2
ns
ns
4
5
ns
ns
0
4
ns
ns
1.5
ns
STM32F100xC, STM32F100xD, STM32F100xE
Electrical characteristics
Figure 22. Synchronous non-multiplexed PSRAM write timings
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Table 37.
Synchronous non-multiplexed PSRAM write timings(1)(2)
Symbol
Parameter
Min
Max
27.7
Unit
tw(CLK)
FSMC_CLK period
ns
td(CLKL-NExL)
FSMC_CLK low to FSMC_NEx low (x = 0...2)
td(CLKL-NExH)
FSMC_CLK low to FSMC_NEx high (x = 0...2)
td(CLKL-NADVL)
FSMC_CLK low to FSMC_NADV low
td(CLKL-NADVH)
FSMC_CLK low to FSMC_NADV high
td(CLKL-AV)
FSMC_CLK low to FSMC_Ax valid (x = 16...25)
td(CLKL-AIV)
FSMC_CLK low to FSMC_Ax invalid (x = 16...25)
td(CLKL-NWEL)
FSMC_CLK low to FSMC_NWE low
td(CLKL-NWEH)
FSMC_CLK low to FSMC_NWE high
td(CLKL-Data)
FSMC_D[15:0] valid data after FSMC_CLK low
tsu(NWAITV-CLKH)
FSMC_NWAIT valid before FSMC_CLK high
7
ns
th(CLKH-NWAITV)
FSMC_NWAIT valid after FSMC_CLK high
2
ns
td(CLKL-NBLH)
FSMC_CLK low to FSMC_NBL high
1
ns
2
2
ns
ns
4
5
ns
ns
0
2
ns
ns
1
1
ns
ns
6
ns
1. CL = 15 pF.
2. Preliminary values.
Doc ID 15081 Rev 7
65/98
Electrical characteristics
5.3.11
STM32F100xC, STM32F100xD, STM32F100xE
EMC characteristics
Susceptibility tests are performed on a sample basis during device characterization.
Functional EMS (Electromagnetic susceptibility)
While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the
device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
●
Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
●
FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and
VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is
compliant with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed.
The test results are given in Table 38. They are based on the EMS levels and classes
defined in application note AN1709.
Table 38.
EMS characteristics
Symbol
Parameter
Conditions
Level/Class
VFESD
Voltage limits to be applied on any I/O pin to
induce a functional disturbance
VDD = 3.3 V, TA = +25 °C,
fHCLK = 24 MHz, LQFP144
package, conforms to
IEC 61000-4-2
2B
VEFTB
VDD = 3.3 V, TA = +25 °C,
Fast transient voltage burst limits to be
fHCLK = 24 MHz, LQFP144
applied through 100 pF on VDD and VSS pins
package, conforms to
to induce a functional disturbance
IEC 61000-4-4
4A
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and pre
qualification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
●
Corrupted program counter
●
Unexpected reset
●
Critical Data corruption (control registers...)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1
second. To complete these trials, ESD stress can be applied directly on the device, over the
range of specification values. When unexpected behavior is detected, the software can be
hardened to prevent unrecoverable errors occurring (see application note AN1015).
66/98
Doc ID 15081 Rev 7
STM32F100xC, STM32F100xD, STM32F100xE
Electrical characteristics
Electromagnetic Interference (EMI)
The electromagnetic field emitted by the device is monitored while a simple application is
executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with
IEC 61967-2 standard which specifies the test board and the pin loading.
Table 39.
EMI characteristics
Symbol Parameter
SEMI
5.3.12
Peak level
Monitored
frequency band
Conditions
VDD = 3.6 V, TA = 25°C,
LQFP144 package
compliant with SAE
J1752/3
Max vs. [fHSE/fHCLK]
Unit
8/24 MHz
0.1 MHz to 30 MHz
16
30 MHz to 130 MHz
25
130 MHz to 1GHz
25
SAE EMI Level
4
dBµV
-
Absolute maximum ratings (electrical sensitivity)
Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test
conforms to the JESD22-A114/C101 standard.
Table 40.
ESD absolute maximum ratings
Symbol
Ratings
Conditions
Class
Maximum
Unit
value(1)
VESD(HBM)
Electrostatic discharge
voltage (human body model)
TA = +25 °C
conforming to JESD22-A114
2
2000
VESD(CDM)
Electrostatic discharge
TA = +25 °C
voltage (charge device model) conforming to JESD22-C101
II
500
V
1. Based on characterization results, not tested in production.
Static latch-up
Two complementary static tests are required on six parts to assess the latch-up
performance:
●
A supply overvoltage is applied to each power supply pin
●
A current injection is applied to each input, output and configurable I/O pin
These tests are compliant with EIA/JESD78 IC latch-up standard.
Table 41.
Symbol
LU
Electrical sensitivities
Parameter
Static latch-up class
Conditions
TA = +105 °C conforming to JESD78
Doc ID 15081 Rev 7
Class
II level A
67/98
Electrical characteristics
5.3.13
STM32F100xC, STM32F100xD, STM32F100xE
I/O current injection characteristics
As a general rule, current injection to the I/O pins, due to external voltage below VSS or
above VDD (for standard, 3 V-capable I/O pins) should be avoided during normal product
operation. However, in order to give an indication of the robustness of the microcontroller in
cases when abnormal injection accidentally happens, susceptibility tests are performed on a
sample basis during device characterization.
Functional susceptibilty to I/O current injection
While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into the
I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out of range parameter: ADC error above a certain limit (>5
LSB TUE), out of spec current injection on adjacent pins or other functional failure (for
example reset, oscillator frequency deviation).
The test results are given in Table 42
Table 42.
I/O current injection susceptibility
Functional susceptibility
Symbol
IINJ
68/98
Description
Negative
injection
Positive
injection
Injected current on OSC_IN32,
OSC_OUT32, PA4, PA5, PC13
-0
+0
Injected current on all FT pins
-5
+0
Injected current on any other pin
-5
+5
Doc ID 15081 Rev 7
Unit
mA
STM32F100xC, STM32F100xD, STM32F100xE
5.3.14
Electrical characteristics
I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in Table 43 are derived from tests
performed under the conditions summarized in Table 9. All I/Os are CMOS and TTL
compliant.
Table 43.
Symbol
VIL
VIH
Vhys
Ilkg
I/O static characteristics
Parameter
Conditions
Min
Typ
Max
Standard I/O input
low level voltage
–0.3
0.28*(VDD–2 V)+0.8 V
I/O FT(1) input low
level voltage
–0.3
0.32*(VDD–2 V)+0.75 V
Standard I/O input
high level voltage
0.41*(VDD–2 V) +1.3 V
VDD+0.3
I/O FT(1) input high
level voltage
Unit
V
VDD > 2 V
5.5
0.42*(VDD–2)+1 V
VDD ≤2 V
5.2
Standard I/O Schmitt
trigger voltage
hysteresis(2)
200
mV
I/O FT Schmitt trigger
voltage hysteresis(2)
5% VDD(3)
mV
Input leakage
current(4)
VSS ≤VIN ≤VDD
Standard I/Os
±1
µA
VIN = 5 V
I/O FT
3
RPU
Weak pull-up
equivalent resistor(5)
VIN = VSS
30
40
50
kΩ
RPD
Weak pull-down
equivalent resistor(5)
VIN = VDD
30
40
50
kΩ
CIO
I/O pin capacitance
5
pF
1. FT = 5V tolerant. To sustain a voltage higher than VDD+0.3 the internal pull-up/pull-down resistors must be disabled.
2. Hysteresis voltage between Schmitt trigger switching levels. Guaranteed by design, not tested in production.
3. With a minimum of 100 mV.
4. Leakage could be higher than max. if negative current is injected on adjacent pins.
5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
PMOS/NMOS contribution to the series resistance is minimum (~10% order).
All I/Os are CMOS and TTL compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters. The
coverage of these requirements is shown in Figure 23 and Figure 24 for standard I/Os, and
in Figure 25 and Figure 26 for 5 V tolerant I/Os.
Doc ID 15081 Rev 7
69/98
Electrical characteristics
STM32F100xC, STM32F100xD, STM32F100xE
Figure 23. Standard I/O input characteristics - CMOS port
9,+9,/9
PHQW9 ,+
TXLUH
QGDUGUH
WD
&026V
7,+PLQ
7,/PD[
9 9 ,+ ''
9 ''
LUHPHQW9 ,/
UGUHTX
&026VWDQGD
9 ''
9
9,/ ''
,QSXWUDQJH
QRWJXDUDQWHHG
9''9
DLE
Figure 24. Standard I/O input characteristics - TTL port
9,+9,/9
7,+PLQ
77/UHTXLUHPHQWV 9,+ 9
9 9 ,+ ''
,QSXWUDQJH
QRWJXDUDQWHHG
7,/PD[
9 ,/
9 ''
77/UHTXLUHPHQWV 9,/ 9
9''9
DL
70/98
Doc ID 15081 Rev 7
STM32F100xC, STM32F100xD, STM32F100xE
Electrical characteristics
Figure 25. 5 V tolerant I/O input characteristics - CMOS port
9,+9,/9
WV9 ,+
XLUHPHQ
UHT
WDQGDUG
&026V
,QSXWUDQJH
QRWJXDUDQWHHG
9 ,/ 9 ''
W9 ,/ 9 ''
UHTXLUPHQ
26VWDQGDUG
&0
9 ,+ 9 ''
9 ''
9''9
9''
DLE
Figure 26. 5 V tolerant I/O input characteristics - TTL port
9,+9,/9
77/UHTXLUHPHQW9 ,+ 9
9 9 ,+ ''
7,+PLQ
7,/PD[
,QSXWUDQJH
QRWJXDUDQWHHG
9 ,/ 9 ''
77/UHTXLUHPHQWV9 ,/ 9
9''9
DL
Output driving current
The GPIOs (general purpose input/outputs) can sink or source up to +/-8 mA, and sink or
source up to +/- 20 mA (with a relaxed VOL/VOH) except PC13, PC14 and PC15 it can sink
or source up to +/-3mA. When using the GPIOs PC13 to PC15 in output mode, the speed
should not exceed 2 MHz with a maximum load of 30 pF.
In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 5.2:
●
The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run
consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating
IVDD (see Table 7).
●
The sum of the currents sunk by all the I/Os on VSS plus the maximum Run
consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating
IVSS (see Table 7).
Doc ID 15081 Rev 7
71/98
Electrical characteristics
STM32F100xC, STM32F100xD, STM32F100xE
Output voltage levels
Unless otherwise specified, the parameters given in Table 44 are derived from tests
performed under the ambient temperature and VDD supply voltage conditions summarized
in Table 9. All I/Os are CMOS and TTL compliant.
Table 44.
Output voltage characteristics
Symbol
Parameter
VOL(1)
VOH
(3)
VOL(1)
VOH
(3)
VOL(1)
VOH
(3)
VOL(1)
VOH
(3)
Output Low level voltage for an I/O pin
when 8 pins are sunk at the same time
Output High level voltage for an I/O pin
when 8 pins are sourced at the same time
Output low level voltage for an I/O pin
when 8 pins are sunk at the same time
Output high level voltage for an I/O pin
when 8 pins are sourced at the same time
Output low level voltage for an I/O pin
when 8 pins are sunk at the same time
Output high level voltage for an I/O pin
when 8 pins are sourced at the same time
Output low level voltage for an I/O pin
when 8 pins are sunk at the same time
Output high level voltage for an I/O pin
when 8 pins are sourced at the same time
Conditions
CMOS port(2),
IIO = +8 mA,
2.7 V < VDD < 3.6 V
TTL port(2)
IIO = +8 mA
2.7 V < VDD < 3.6 V
IIO = +20 mA(4)
2.7 V < VDD < 3.6 V
IIO = +6 mA(4)
2 V < VDD < 2.7 V
Min
Max
Unit
0.4
V
VDD–0.4
0.4
V
2.4
1.3
V
VDD–1.3
0.4
V
VDD–0.4
1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 7
and the sum of IIO (I/O ports and control pins) must not exceed IVSS.
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
3. The IIO current sourced by the device must always respect the absolute maximum rating specified in
Table 7 and the sum of IIO (I/O ports and control pins) must not exceed IVDD.
4. Based on characterization data, not tested in production.
72/98
Doc ID 15081 Rev 7
STM32F100xC, STM32F100xD, STM32F100xE
Electrical characteristics
Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Figure 27 and
Table 45, respectively.
Unless otherwise specified, the parameters given in Table 45 are derived from tests
performed under the ambient temperature and VDD supply voltage conditions summarized
in Table 9.
Table 45.
MODEx
[1:0] bit
value(1)
I/O AC characteristics(1)
Symbol
Parameter
fmax(IO)out Maximum frequency(2)
10
tf(IO)out
Output high to low level fall
time
tr(IO)out
Output low to high level rise
time
fmax(IO)out Maximum frequency(2)
01
tf(IO)out
Output high to low level fall
time
tr(IO)out
Output low to high level rise
time
fmax(IO)out Maximum frequency(2)
tf(IO)out
Output high to low level fall
time
11
tr(IO)out
-
tEXTIpw
Output low to high level rise
time
Conditions
CL = 50 pF, VDD = 2 V to 3.6 V
Max
Unit
2(3)
MHz
125(3)
CL = 50 pF, VDD = 2 V to 3.6 V
ns
(3)
125
CL= 50 pF, VDD = 2 V to 3.6 V
10(3)
MHz
25(3)
CL= 50 pF, VDD = 2 V to 3.6 V
ns
25(3)
CL = 50 pF, VDD = 2 V to 3.6 V
24
CL = 30 pF, VDD = 2.7 V to 3.6 V
5(3)
CL = 50 pF, VDD = 2.7 V to 3.6 V
8(3)
CL = 50 pF, VDD = 2 V to 2.7 V
12(3)
CL = 30 pF, VDD = 2.7 V to 3.6 V
5(3)
CL = 50 pF, VDD = 2.7 V to 3.6 V
8(3)
CL = 50 pF, VDD = 2 V to 2.7 V
12(3)
Pulse width of external
signals detected by the
EXTI controller
10(3)
MHz
ns
ns
1. The I/O speed is configured using the MODEx[1:0] bits. Refer to the STM32F100xx reference manual for a
description of GPIO Port configuration register.
2. The maximum frequency is defined in Figure 27.
3. Guaranteed by design, not tested in production.
Doc ID 15081 Rev 7
73/98
Electrical characteristics
STM32F100xC, STM32F100xD, STM32F100xE
Figure 27. I/O AC characteristics definition
90%
10%
50%
50%
90%
10%
tr(I O)out
EXT ERNAL
OUTPUT
ON 50pF
tr(I O)out
T
Maximum frequency is achieved if (tr + tf) 2/3)T and if the duty cycle is (45-55%)
when loaded by 50pF
ai14131
5.3.15
NRST pin characteristics
The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, RPU (see Table 43).
Unless otherwise specified, the parameters given in Table 46 are derived from tests
performed under the ambient temperature and VDD supply voltage conditions summarized
in Table 9.
Table 46.
NRST pin characteristics
Symbol
Parameter
VIL(NRST)(1)
VIH(NRST)
(1)
Conditions
Min
–0.5
0.8
NRST Input high level voltage
2
VDD+0.5
Unit
V
Weak pull-up equivalent resistor(2)
RPU
Max
NRST Input low level voltage
NRST Schmitt trigger voltage
hysteresis
Vhys(NRST)
Typ
VF(NRST)(1)
NRST Input filtered pulse
VNF(NRST)(1)
NRST Input not filtered pulse
200
VIN = VSS
30
40
mV
50
kΩ
100
ns
300
ns
1. Guaranteed by design, not tested in production.
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to
the series resistance must be minimum (~10% order).
Figure 28. Recommended NRST pin protection
9''
([WHUQDO
UHVHWFLUFXLW
1567
538
,QWHUQDOUHVHW
)LOWHU
—)
670)[
DLG
1. The reset network protects the device against parasitic resets.
2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 46. Otherwise the reset will not be taken into account by the device.
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Doc ID 15081 Rev 7
STM32F100xC, STM32F100xD, STM32F100xE
5.3.16
Electrical characteristics
TIMx characteristics
The parameters given in Table 47 are guaranteed by design.
Refer to Section 5.3.13: I/O current injection characteristics for details on the input/output
alternate function characteristics (output compare, input capture, external clock, PWM
output).
Table 47.
Symbol
TIMx characteristics
Parameter
tres(TIM)
Timer resolution time
fEXT
Timer external clock
frequency on CHx(2)
ResTIM
tCOUNTER
Conditions(1)
fTIMxCLK = 24 MHz
fTIMxCLK = 24 MHz
Min
tTIMxCLK
41.7
ns
0
fTIMxCLK/2
MHz
0
12
MHz
16
bit
65536
tTIMxCLK
2730
µs
tMAX_COUNT Maximum possible count
65536 × 65536
tTIMxCLK
178
s
1
fTIMxCLK = 24 MHz
fTIMxCLK = 24 MHz
Unit
1
Timer resolution
16-bit counter clock period
when the internal clock is
selected
Max
1. TIMx is used as a general term to refer to the TIM1, TIM2, TIM3, TIM4, TIM5, TIM15, TIM16 and TIM17
timers.
2. CHx is used as a general term to refer to CH1 to CH4 for TIM1, TIM2, TIM3, TIM4 and TIM5, to the CH1 to
CH2 for TIM15, and to CH1 for TIM16 and TIM17.
5.3.17
Communications interfaces
I2C interface characteristics
Unless otherwise specified, the parameters given in Table 48 are preliminary values derived
from tests performed under the ambient temperature, fPCLK1 frequency and VDD supply
voltage conditions summarized in Table 9.
The STM32F100xx value line I2C interface meets the requirements of the standard I2C
communication protocol with the following restrictions: the I/O pins SDA and SCL are
mapped to are not “true” open-drain. When configured as open-drain, the PMOS connected
between the I/O pin and VDD is disabled, but is still present.
The I2C characteristics are described in Table 48. Refer also to Section 5.3.13: I/O current
injection characteristics for more details on the input/output alternate function characteristics
(SDA and SCL).
Doc ID 15081 Rev 7
75/98
Electrical characteristics
Table 48.
STM32F100xC, STM32F100xD, STM32F100xE
I2C characteristics
Standard mode I2C(1) Fast mode I2C(1)(2)
Symbol
Parameter
Unit
Min
Max
Min
Max
tw(SCLL)
SCL clock low time
4.7
1.3
tw(SCLH)
SCL clock high time
4.0
0.6
tsu(SDA)
SDA setup time
250
100
th(SDA)
SDA data hold time
0
0
tr(SDA)
tr(SCL)
SDA and SCL rise time
1000
300
tf(SDA)
tf(SCL)
SDA and SCL fall time
300
300
th(STA)
Start condition hold time
4.0
0.6
tsu(STA)
Repeated Start condition setup
time
4.7
0.6
tsu(STO)
Stop condition setup time
4.0
0.6
µs
tw(STO:STA)
Stop to Start condition time (bus
free)
4.7
1.3
µs
Cb
Capacitive load for each bus line
µs
900(3)
µs
400
400
1. Guaranteed by design, not tested in production.
2. fPCLK1 must be at least 2 MHz to achieve standard mode I2C frequencies. It must be at least 4 MHz to
achieve fast mode I2C frequencies. It must be a multiple of 10 MHz to reach the 400 kHz maximum I2C
fast mode clock.
3. The maximum Data hold time has only to be met if the interface does not stretch the low period of SCL
signal.
76/98
ns
Doc ID 15081 Rev 7
pF
STM32F100xC, STM32F100xD, STM32F100xE
Electrical characteristics
Figure 29. I2C bus AC waveforms and measurement circuit
9''
N!
9''
N!
!
!
,ð&EXV
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6'$
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6WDUW
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6&/
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6WRS
WK6'$
WVX672
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DLG
1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.
Table 49.
SCL frequency (fPCLK1= 24 MHz, VDD = 3.3 V)(1)(2)
I2C_CCR value
fSCL (kHz)(3)
RP = 4.7 kΩ
400
0x8011
300
0x8016
200
0x8021
100
0x0064
50
0x00C8
20
0x01F4
1. RP = External pull-up resistance, fSCL = I2C speed,
2. For speeds around 400 kHz, the tolerance on the achieved speed is of ±2%. For other speed ranges, the
tolerance on the achieved speed ±1%. These variations depend on the accuracy of the external
components used to design the application.
3. Guaranteed by design, not tested in production.
Doc ID 15081 Rev 7
77/98
Electrical characteristics
STM32F100xC, STM32F100xD, STM32F100xE
SPI interface characteristics
Unless otherwise specified, the parameters given in Table 50 are preliminary values derived
from tests performed under the ambient temperature, fPCLKx frequency and VDD supply
voltage conditions summarized in Table 9.
Refer to Section 5.3.13: I/O current injection characteristics for more details on the
input/output alternate function characteristics (NSS, SCK, MOSI, MISO).
Table 50.
SPI characteristics
Symbol
fSCK
1/tc(SCK)
Parameter
Conditions
Min
12
Slave mode
12
8
ns
70
%
MHz
SPI clock rise and fall
time
Capacitive load: C = 30 pF
DuCy(SCK)
SPI slave input clock
duty cycle
Slave mode
30
tsu(NSS)(1)
NSS setup time
Slave mode
4tPCLK
th(NSS)(1)
NSS hold time
Slave mode
2tPCLK
SCK high and low time
Master mode, fPCLK = 24 MHz,
presc = 4
50
Master mode
5
Slave mode
5
Master mode
5
Slave mode
4
tsu(MI) (1)
tsu(SI)(1)
th(MI)
ta(SO)
(1)(2)
60
Data input setup time
(1)
th(SI)(1)
Data input hold time
Data output access time Slave mode, fPCLK = 24 MHz
tdis(SO)(1)(3) Data output disable time Slave mode
ns
0
3tPCLK
2
10
(1)
Data output valid time
Slave mode (after enable edge)
25
tv(MO)(1)
Data output valid time
Master mode (after enable
edge)
5
tv(SO)
th(SO)(1)
th(MO)(1)
Unit
Master mode
SPI clock frequency
tr(SCK)
tf(SCK)
tw(SCKH)(1)
tw(SCKL)(1)
Max
Data output hold time
Slave mode (after enable edge)
15
Master mode (after enable
edge)
2
1. Preliminary values.
2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate
the data.
3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put
the data in Hi-Z
78/98
Doc ID 15081 Rev 7
STM32F100xC, STM32F100xD, STM32F100xE
Electrical characteristics
Figure 30. SPI timing diagram - slave mode and CPHA = 0
NSS input
tc(SCK)
th(NSS)
SCK Input
tSU(NSS)
CPHA= 0
CPOL=0
tw(SCKH)
tw(SCKL)
CPHA= 0
CPOL=1
tv(SO)
ta(SO)
MISO
OUT P UT
tr(SCK)
tf(SCK)
th(SO)
MS B O UT
BI T6 OUT
tdis(SO)
LSB OUT
tsu(SI)
MOSI
I NPUT
B I T1 IN
M SB IN
LSB IN
th(SI)
ai14134c
Figure 31. SPI timing diagram - slave mode and CPHA = 1
NSS input
SCK Input
tSU(NSS)
CPHA=1
CPOL=0
CPHA=1
CPOL=1
tc(SCK)
tw(SCKH)
tw(SCKL)
tv(SO)
ta(SO)
MISO
OUT P UT
MS B O UT
tsu(SI)
MOSI
I NPUT
th(NSS)
th(SO)
BI T6 OUT
tr(SCK)
tf(SCK)
tdis(SO)
LSB OUT
th(SI)
B I T1 IN
M SB IN
LSB IN
ai14135
1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.
Doc ID 15081 Rev 7
79/98
Electrical characteristics
STM32F100xC, STM32F100xD, STM32F100xE
Figure 32. SPI timing diagram - master mode
High
NSS input
SCK output
SCK output
tc(SCK)
CPHA= 0
CPOL=0
CPHA= 0
CPOL=1
CPHA=1
CPOL=0
CPHA=1
CPOL=1
tsu(MI)
MISO
INP UT
tw(SCKH)
tw(SCKL)
tr(SCK)
tf(SCK)
MS BIN
BI T6 IN
LSB IN
th(MI)
MOSI
OUTUT
M SB OUT
B I T1 OUT
tv(MO)
LSB OUT
th(MO)
ai14136
1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.
HDMI consumer electronics control (CEC)
Refer to Section 5.3.13: I/O current injection characteristics for more details on the
input/output alternate function characteristics.
5.3.18
12-bit ADC characteristics
Unless otherwise specified, the parameters given in Table 51 are preliminary values derived
from tests performed under the ambient temperature, fPCLK2 frequency and VDDA supply
voltage conditions summarized in Table 9.
Note:
80/98
It is recommended to perform a calibration after each power-up.
Doc ID 15081 Rev 7
STM32F100xC, STM32F100xD, STM32F100xE
Table 51.
ADC characteristics
Symbol
Parameter
Conditions
Electrical characteristics
Min
Typ
Max
Unit
VDDA
Power supply
2.4
3.6
V
VREF+
Positive reference voltage
2.4
VDDA
V
IVREF
Current on the VREF input
pin
220(1)
µA
fADC
ADC clock frequency
0.6
12
MHz
fS(2)
Sampling rate
0.05
1
MHz
823
kHz
17
1/fADC
VREF+
V
50
kΩ
160(1)
fADC = 12 MHz
fTRIG(2)
External trigger frequency
VAIN(3)
Conversion voltage range
RAIN(2)
External input impedance
RADC(2)
Sampling switch resistance
1
kΩ
CADC(2)
Internal sample and hold
capacitor
8
pF
tCAL(2)
Calibration time
0 (VSSA tied to
ground)
See Equation 1 and
Table 52 for details
fADC = 12 MHz
tlat(2)
Injection trigger conversion
latency
fADC = 12 MHz
tlatr(2)
Regular trigger conversion
latency
fADC = 12 MHz
tS(2)
Sampling time
fADC = 12 MHz
tSTAB(2)
Power-up time
tCONV(2)
Total conversion time
(including sampling time)
5.9
µs
83
1/fADC
0.214
(4)
3
1/fADC
0.143
µs
2(4)
1/fADC
0.125
17.1
µs
1.5
239.5
1/fADC
1
µs
21
µs
0
fADC = 12 MHz
µs
1.17
0
14 to 252 (tS for sampling +12.5 for
successive approximation)
1/fADC
1. Preliminary values.
2. Guaranteed by design, not tested in production.
3. VREF+ is internally connected to VDDA
4. For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 51.
Equation 1: RAIN max formula:
TS
- – R ADC
R AIN < --------------------------------------------------------------N+2
f ADC × C ADC × ln ( 2
)
The above formula (Equation 1) is used to determine the maximum external impedance allowed for an
error below 1/4 of LSB. Here N = 12 (from 12-bit resolution).
Doc ID 15081 Rev 7
81/98
Electrical characteristics
Table 52.
STM32F100xC, STM32F100xD, STM32F100xE
RAIN max for fADC = 12 MHz(1)
Ts (cycles)
tS (µs)
RAIN max (kΩ)
1.5
0.125
0.4
7.5
0.625
5.9
13.5
1.125
11.4
28.5
2.375
25.2
41.5
3.45
37.2
55.5
4.625
50
71.5
5.96
NA
239.5
20
NA
1. Guaranteed by design, not tested in production.
Table 53.
Symbol
ADC accuracy - limited test conditions(1)(2)
Parameter
ET
Total unadjusted error
EO
Offset error
EG
Gain error
ED
Differential linearity error
EL
Integral linearity error
Test conditions
Typ
Max
fPCLK2 = 24 MHz,
fADC = 12 MHz, RAIN < 10 kΩ,
VDDA = 3 V to 3.6 V
VREF+ = VDDA
TA = 25 °C
Measurements made after
ADC calibration
±1.5
±2.5
±1
±2
±0.5
±1.5
±1.5
±2
±1.5
±2
Test conditions
Typ
Max
fPCLK2 = 24 MHz,
fADC = 12 MHz, RAIN < 10 kΩ,
VDDA = 2.4 V to 3.6 V
TA = Full operating range
Measurements made after
ADC calibration
±2
±5
±1.5
±2.5
±1.5
±3
±1.5
±2.5
±1.5
±4.5
Unit
LSB
1. ADC DC accuracy values are measured after internal calibration.
2. Preliminary values.
Table 54.
Symbol
ADC accuracy(1) (2) (3)
Parameter
ET
Total unadjusted error
EO
Offset error
EG
Gain error
ED
Differential linearity error
EL
Integral linearity error
Unit
LSB
1. ADC DC accuracy values are measured after internal calibration.
2. Better performance could be achieved in restricted VDD, frequency, VREF and temperature ranges.
3. Preliminary values.
Note:
82/98
ADC accuracy vs. negative injection current: Injecting a negative current on any analog
input pins should be avoided as this significantly reduces the accuracy of the conversion
being performed on another analog input. It is recommended to add a Schottky diode (pin to
ground) to analog pins which may potentially inject negative currents.
Doc ID 15081 Rev 7
STM32F100xC, STM32F100xD, STM32F100xE
Note:
Electrical characteristics
Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in
Section 5.3.13 does not affect the ADC accuracy.
Figure 33. ADC accuracy characteristics
V
V
[1LSBIDEAL = REF+ (or DDA depending on package)]
4096
4096
EG
(1) Example of an actual transfer curve
(2) The ideal transfer curve
(3) End point correlation line
4095
4094
4093
(2)
ET
7
(1)
6
5
4
ET=Total Unadjusted Error: maximum deviation
between the actual and the ideal transfer curves.
EO=Offset Error: deviation between the first actual
transition and the first ideal one.
EG=Gain Error: deviation between the last ideal
transition and the last actual one.
ED=Differential Linearity Error: maximum deviation
between actual steps and the ideal one.
EL=Integral Linearity Error: maximum deviation
between any actual transition and the end point
correlation line.
(3)
EO
EL
3
ED
2
1 LSBIDEAL
1
0
1
VSSA
2
3
4
5
6
7
4093 4094 4095 4096
VDDA
ai14395b
Figure 34. Typical connection diagram using the ADC
STM32F10xxx
VDD
RAIN(1)
Sample and hold ADC
converter
VT
0.6 V
RADC(1)
AINx
VT
0.6 V
VAIN
Cparasitic
IL±1 µA
12-bit
converter
CADC(1)
ai14139d
1. Refer to Table 51 for the values of RAIN, RADC and CADC.
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy
this, fADC should be reduced.
General PCB design guidelines
Power supply decoupling should be performed as shown in Figure 35 or Figure 36,
depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be
ceramic (good quality). They should be placed them as close as possible to the chip.
Doc ID 15081 Rev 7
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Electrical characteristics
STM32F100xC, STM32F100xD, STM32F100xE
Figure 35. Power supply and reference decoupling (VREF+ not connected to VDDA)
STM32F10xxx
V REF+
1 µF // 10 nF
V DDA
1 µF // 10 nF
V SSA/V REF-
ai14380b
1. VREF+ is available on 100-pin packages and on TFBGA64 packages. VREF- is available on 100-pin
packages only.
Figure 36. Power supply and reference decoupling (VREF+ connected to VDDA)
STM32F10xxx
VREF+/VDDA
1 µF // 10 nF
VREF–/VSSA
ai14381b
1. VREF+ and VREF- inputs are available only on 100-pin packages.
84/98
Doc ID 15081 Rev 7
STM32F100xC, STM32F100xD, STM32F100xE
Electrical characteristics
5.3.19
DAC electrical specifications
Table 55.
DAC characteristics
Symbol
Parameter
Min
Typ
Max(1)
Unit
VDDA
Analog supply voltage
2.4
3.6
V
VREF+
Reference supply voltage
2.4
3.6
V
Ground
0
0
V
Resistive load with buffer ON
5
VSSA
RLOAD
(1)
Comments
VREF+ must always be below
VDDA
kΩ
RO(1)
Impedance output with buffer OFF
15
kΩ
When the buffer is OFF, the
Minimum resistive load
between DAC_OUT and VSS to
have a 1% accuracy is 1.5 MΩ
CLOAD(1)
Capacitive load
50
pF
Maximum capacitive load at
DAC_OUT pin (when the buffer
is ON).
DAC_OUT
min(1)
Lower DAC_OUT voltage with buffer
ON
DAC_OUT
max(1)
Higher DAC_OUT voltage with buffer
ON
DAC_OUT
min(1)
Lower DAC_OUT voltage with buffer
OFF
DAC_OUT
max(1)
Higher DAC_OUT voltage with buffer
OFF
IDDVREF+
DAC DC current consumption in
quiescent mode (Standby mode)
IDDA
DNL(1)
INL(1)
0.2
V
VDDA –
V
0.2
0.5
mV
VREF+
V
– 1LSB
It gives the maximum output
excursion of the DAC.
220
µA
With no load, worst code
(0xF1C) at VREF+ = 3.6 V in
terms of DC consumption on
the inputs
380
µA
With no load, middle code
(0x800) on the inputs
480
µA
With no load, worst code
(0xF1C) at VREF+ = 3.6 V in
terms of DC consumption on
the inputs
±0.5
LSB
Given for the DAC in 10-bit
configuration
±2
LSB
Given for the DAC in 12-bit
configuration
±1
LSB
Given for the DAC in 10-bit
configuration
±4
LSB
Given for the DAC in 12-bit
configuration
DAC DC current consumption in
quiescent mode (2)
Differential non linearity Difference
between two consecutive code-1LSB)
Integral non linearity (difference
between measured value at Code i
and the value at Code i on a line
drawn between Code 0 and last Code
1023)
It gives the maximum output
excursion of the DAC.
It corresponds to 12-bit input
code (0x0E0) to (0xF1C) at
VREF+ = 3.6 V and (0x155) and
(0xEAB) at VREF+ = 2.4 V
Doc ID 15081 Rev 7
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Electrical characteristics
Table 55.
DAC characteristics (continued)
Symbol
Offset(1)
Gain
error(1)
STM32F100xC, STM32F100xD, STM32F100xE
Parameter
Min
Offset error
(difference between measured value
at Code (0x800) and the ideal value =
VREF+/2)
Gain error
Settling time (full scale: for a 10-bit
input code transition between the
tSETTLING(1) lowest and the highest input codes
when DAC_OUT reaches final value
±1LSB
Max(1)
Unit
±10
mV
Given for the DAC in 12-bit
configuration
±3
LSB
Given for the DAC in 10-bit at
VREF+ = 3.6 V
±12
LSB
Given for the DAC in 12-bit at
VREF+ = 3.6 V
±0.5
%
Given for the DAC in 12-bit
configuration
4
µs
CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ
1
MS/s CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ
Typ
3
Comments
Update
rate(1)
Max frequency for a correct
DAC_OUT change when small
variation in the input code (from code i
to i+1LSB)
tWAKEUP(1)
Wakeup time from off state (Setting
the ENx bit in the DAC Control
register)
6.5
10
µs
CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ
input code between lowest and
highest possible ones.
PSRR+ (1)
Power supply rejection ratio (to VDDA)
(static DC measurement
–67
–40
dB
No RLOAD, CLOAD = 50 pF
1. Preliminary values.
2. Quiescent mode refer to the state of the DAC keeping steady value on the output, so no dynamic consumption is involved.
Figure 37. 12-bit buffered /non-buffered DAC
Buffered/Non-buffered DAC
Buffer(1)
R LOAD
12-bit
digital to
analog
converter
DACx_OUT
C LOAD
ai17157
1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly
without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the
DAC_CR register.
86/98
Doc ID 15081 Rev 7
STM32F100xC, STM32F100xD, STM32F100xE
5.3.20
Temperature sensor characteristics
Table 56.
TS characteristics
Symbol
TL(1)
Parameter
Electrical characteristics
Min
VSENSE linearity with temperature
(1)
Typ
Max
Unit
±1
±2
°C
Average slope
4.0
4.3
4.6
mV/°C
V25(1)
Voltage at 25°C
1.32
1.41
1.50
V
tSTART(2)
Startup time
10
µs
TS_temp(3)(2)
ADC sampling time when reading the temperature
17.1
µs
Avg_Slope
4
1. Guaranteed by characterization, not tested in production.
2. Guaranteed by design, not tested in production.
3. Shortest sampling time can be determined in the application by multiple iterations.
Doc ID 15081 Rev 7
87/98
Package characteristics
STM32F100xC, STM32F100xD, STM32F100xE
6
Package characteristics
6.1
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
88/98
Doc ID 15081 Rev 7
STM32F100xC, STM32F100xD, STM32F100xE
Package characteristics
Figure 38. LQFP144, 20 x 20 mm, 144-pin thin quad flat
package outline
Figure 39. Recommended
footprint
Seating plane
C
A
A2 A1
c
b
ccc
0.25 mm
gage plane
C
D
108
109
k
1.35
73
72
0.35
D1
A1
D3
108
73
L
0.5
L1
17.85
72
109
19.9
E1
144
E
E3
22.6
37
1
36
19.9
22.6
ai14
144
Pin 1
identification
37
36
1
e
ME_1A
1. Drawing is not to scale.
2. Dimensions are in millimeters.
Table 57.
LQFP144, 20 x 20 mm, 144-pin thin quad flat package mechanical data
inches(1)
millimeters
Symbol
Min
Typ
A
Max
Min
Typ
1.60
A1
0.05
A2
1.35
b
0.17
c
0.09
D
21.80
D1
19.80
D3
Max
0.063
0.15
0.002
1.40
1.45
0.0531
0.0551
0.0571
0.22
0.27
0.0067
0.0087
0.0106
0.20
0.0035
22.00
22.20
0.8583
0.8661
0.874
20.00
20.20
0.7795
0.7874
0.7953
17.50
0.0059
0.0079
0.689
E
21.80
22.00
22.20
0.8583
0.8661
0.874
E1
19.80
20.00
20.20
0.7795
0.7874
0.7953
E3
17.50
0.689
e
0.50
0.0197
L
0.45
L1
k
ccc
0.60
0.75
0.0177
1.00
0°
3.5°
0.0236
0.0295
0.0394
7°
0.08
0°
3.5°
7°
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Doc ID 15081 Rev 7
89/98
Package characteristics
STM32F100xC, STM32F100xD, STM32F100xE
Figure 40. LQFP100 – 14 x 14 mm, 100-pin low-profile Figure 41. Recommended footprint
quad flat package outline
0.25 mm
0.10 inch
GAGE PLANE
75
k
51
D
76
L
D1
50
0.5
L1
D3
51
75
C
0.3
76
50
16.7
14.3
b
E3 E1 E
100
26
1.2
100
1
26
Pin 1
1
identification
25
12.3
C
ccc
25
16.7
e
A1
ai14906b
A2
A
SEATING PLANE
C
1L_ME
1. Drawing is not to scale.
2. Dimensions are in millimeters.
Table 58.
LQPF100 – 14 x 14 mm, 100-pin low-profile quad flat package mechanical data
inches(1)
millimeters
Symbol
Min
Typ
A
Max
Typ
1.60
A1
0.05
A2
1.35
b
0.17
c
0.09
D
15.80
D1
13.80
D3
Max
0.063
0.15
0.002
1.40
1.45
0.0531
0.0551
0.0571
0.22
0.27
0.0067
0.0087
0.0106
0.20
0.0035
16.00
16.20
0.622
0.6299
0.6378
14.00
14.20
0.5433
0.5512
0.5591
12.00
0.0059
0.0079
0.4724
E
15.80
16.00
16.20
0.622
0.6299
0.6378
E1
13.80
14.00
14.20
0.5433
0.5512
0.5591
E3
12.00
0.4724
e
0.50
0.0197
L
0.45
L1
k
ccc
0.60
0.75
0.0177
1.00
0°
3.5°
0.0236
0.0295
0.0394
7°
0.08
0°
3.5°
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
90/98
Min
Doc ID 15081 Rev 7
7°
STM32F100xC, STM32F100xD, STM32F100xE
Package characteristics
Figure 42. LQFP64 – 10 x 10 mm, 64 pin low-profile quad Figure 43. Recommended
flat package outline
footprint
A
A2
48
A1
33
0.3
49
E
32
0.5
b
E1
12.7
10.3
10.3
e
64
17
1.2
1
16
7.8
D1
c
12.7
L1
D
ai14909
L
ai14398b
1. Drawing is not to scale.
2. Dimensions are in millimeters.
Table 59.
LQFP64 – 10 x 10 mm, 64 pin low-profile quad flat package mechanical data
inches(1)
millimeters
Symbol
Min
Typ
A
Max
Min
Typ
1.60
A1
0.05
A2
1.35
b
0.17
c
0.09
Max
0.0630
0.15
0.0020
0.0059
1.40
1.45
0.0531
0.0551
0.0571
0.22
0.27
0.0067
0.0087
0.0106
0.20
0.0035
0.0079
D
12.00
0.4724
D1
10.00
0.3937
E
12.00
0.4724
E1
10.00
0.3937
e
0.50
0.0197
θ
0°
3.5°
7°
0°
3.5°
7°
L
0.45
0.60
0.75
0.0177
0.0236
0.0295
L1
1.00
0.0394
Number of pins
N
64
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Doc ID 15081 Rev 7
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Package characteristics
6.2
STM32F100xC, STM32F100xD, STM32F100xE
Thermal characteristics
The maximum chip junction temperature (TJmax) must never exceed the values given in
Table 9: General operating conditions on page 37.
The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated
using the following equation:
TJ max = TA max + (PD max x ΘJA)
Where:
●
TA max is the maximum ambient temperature in ° C,
●
ΘJA is the package junction-to-ambient thermal resistance, in ° C/W,
●
PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax),
●
PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip
internal power.
PI/O max represents the maximum power dissipation on output pins where:
PI/O max = Σ (VOL × IOL) + Σ((VDD – VOH) × IOH),
taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the
application.
Table 60.
Package thermal characteristics
Symbol
ΘJA
6.2.1
Parameter
Value
Thermal resistance junction-ambient
LQFP 144 - 20 × 20 mm / 0.5 mm pitch
35
Thermal resistance junction-ambient
LQFP 100 - 14 × 14 mm / 0.5 mm pitch
40
Thermal resistance junction-ambient
LQFP 64 - 10 × 10 mm / 0.5 mm pitch
49
Unit
°C/W
Reference document
JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural
Convection (Still Air). Available from www.jedec.org.
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Doc ID 15081 Rev 7
STM32F100xC, STM32F100xD, STM32F100xE
6.2.2
Package characteristics
Selecting the product temperature range
When ordering the microcontroller, the temperature range is specified in the ordering
information scheme shown in Table 61: Ordering information scheme.
Each temperature range suffix corresponds to a specific guaranteed ambient temperature at
maximum dissipation and, to a specific maximum junction temperature.
As applications do not commonly use the STM32F100xx at maximum dissipation, it is useful
to calculate the exact power consumption and junction temperature to determine which
temperature range will be best suited to the application.
The following examples show how to calculate the temperature range needed for a given
application.
Example: high-performance application
Assuming the following application conditions:
Maximum ambient temperature TAmax = 82 °C (measured according to JESD51-2),
IDDmax = 50 mA, VDD = 3.5 V, maximum 20 I/Os used at the same time in output at low
level with IOL = 8 mA, VOL= 0.4 V and maximum 8 I/Os used at the same time in output
mode at low level with IOL = 20 mA, VOL= 1.3 V
PINTmax = 50 mA × 3.5 V= 175 mW
PIOmax = 20 × 8 mA × 0.4 V + 8 × 20 mA × 1.3 V = 272 mW
This gives: PINTmax = 175 mW and PIOmax = 272 mW
PDmax = 175 + 272 = 447 mW
Thus: PDmax = 447 mW
Using the values obtained in Table 60 TJmax is calculated as follows:
–
For LQFP64, 49 °C/W
TJmax = 82 °C + (49 °C/W × 447 mW) = 82 °C + 20.1 °C = 102.1 °C
This is within the range of the suffix 6 version parts (–40 < TJ < 105 °C).
In this case, parts must be ordered at least with the temperature range suffix 6 (see
Table 61: Ordering information scheme).
Example 2: High-temperature application
Using the same rules, it is possible to address applications that run at high ambient
temperatures with a low dissipation, as long as junction temperature TJ remains within the
specified range.
Assuming the following application conditions:
Maximum ambient temperature TAmax = 115 °C (measured according to JESD51-2),
IDDmax = 20 mA, VDD = 3.5 V, maximum 20 I/Os used at the same time in output at low
level with IOL = 8 mA, VOL= 0.4 V
PINTmax = 20 mA × 3.5 V= 70 mW
PIOmax = 20 × 8 mA × 0.4 V = 64 mW
This gives: PINTmax = 70 mW and PIOmax = 64 mW:
PDmax = 70 + 64 = 134 mW
Thus: PDmax = 134 mW
Doc ID 15081 Rev 7
93/98
Package characteristics
STM32F100xC, STM32F100xD, STM32F100xE
Using the values obtained in Table 60 TJmax is calculated as follows:
–
For LQFP100, 40 °C/W
TJmax = 115 °C + (40 °C/W × 134 mW) = 115 °C + 5.4 °C = 120.4 °C
This is within the range of the suffix 7 version parts (–40 < TJ < 125 °C).
In this case, parts must be ordered at least with the temperature range suffix 7 (see
Table 61: Ordering information scheme).
Figure 44. LQFP100 PD max vs. TA
700
PD (mW)
600
500
Suffix 6
400
Suffix 7
300
200
100
0
65
75
85
95
105
115
TA (°C)
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Doc ID 15081 Rev 7
125
135
STM32F100xC, STM32F100xD, STM32F100xE
7
Ordering information scheme
Ordering information scheme
Table 61.
Ordering information scheme
Example:
STM32 F 100 V
C
T
6
B xxx
Device family
STM32 = ARM-based 32-bit microcontroller
Product type
F = General-purpose
Device subfamily
100 = value line
Pin count
R = 64 pins
V = 100 pins
Z = 144 pins
Flash memory size
C = 256 Kbytes of Flash memory
D = 384 Kbytes of Flash memory
E = 512 Kbytes of Flash memory
Package
T = LQFP
Temperature range
6 = Industrial temperature range, –40 to 85 °C
7 = Industrial temperature range, –40 to 105 °C
Internal code
B
Options
xxx = programmed parts
TR = tape and real
For a list of available options (speed, package, etc.) or for further information on any aspect
of this device, please contact your nearest ST sales office.
Doc ID 15081 Rev 7
95/98
Revision history
8
STM32F100xC, STM32F100xD, STM32F100xE
Revision history
Table 62.
Document revision history
Date
Revision
09-Oct-2008
1
Initial release.
31-Mar-2009
2
I/O information clarified on page 1.
Table 5: High-density STM32F100xx pin definitions modified.
Figure 5: Memory map on page 26 modified.
Note modified in Table 13: Maximum current consumption in Run
mode, code with data processing running from Flash and Table 15:
Maximum current consumption in Sleep mode, code running from
Flash or RAM.
Table 20: High-speed external user clock characteristics and Table
21: Low-speed user external clock characteristics modified. ACCHSI
max values modified in Table 24: HSI oscillator characteristics.
Note modified in Table 13: Maximum current consumption in Run
mode, code with data processing running from Flash and Table 15:
Maximum current consumption in Sleep mode, code running from
Flash or RAM.
Figure 10, Figure 11 and Figure 12 show typical curves (titles
changed).
Small text changes.
01-Sep-2010
3
Major revision of whole document.
Added LQFP144 package and additional peripherals (SPI3, UART4,
UART, TIM5, 12, 14, 13, FSMC).
18-Oct-2010
4
Updated Power consumption data in Table 13 to Table 16
Updated Section 5.3.11: EMC characteristics on page 66
5
Added Section 2.2.6: LCD parallel interface on page 13
In Table 4 on page 24 moved TIM15_BKIN and TIM17_BKIN from
remap to default column. Updated description of PA3, PA5 and PF6
to PF10.
Updated footnotes below Table 6: Voltage characteristics on page 36
and Table 7: Current characteristics on page 37
Added VBAT values in Table 16: Typical and maximum current
consumptions in Stop and Standby modes on page 43
Updated tw min in Table 20: High-speed external user clock
characteristics on page 47
Updated startup time in Table 23: LSE oscillator characteristics
(fLSE = 32.768 kHz) on page 51
Added HSI clock accuracy values in Table 24: HSI oscillator
characteristics on page 52
Updated FSMC Synchronous waveforms and timings on page 60
Updated Table 43: I/O static characteristics on page 69
Added Section 5.3.13: I/O current injection characteristics on
page 68
Corrected TTL and CMOS designations in Table 44: Output voltage
characteristics on page 72
11-Apr-2011
96/98
Changes
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STM32F100xC, STM32F100xD, STM32F100xE
Table 62.
Revision history
Document revision history (continued)
Date
08-Jun-2012
17-Sep-2012
Revision
Changes
6
Updated Table 7: Current characteristics on page 37
Corrected “CLKL-NOEL” in Section 5.3.10: FSMC characteristics on
page 54
Updated Table 48: I2C characteristics on page 76
Corrected note “non-robust “ in Section 5.3.18: 12-bit ADC
characteristics on page 80
Updated Figure 1: STM32F100xx value line block diagram on
page 11
Updated Section 5.3.14: I/O port characteristics on page 69
Updated Section 2.2.22: GPIOs (general-purpose inputs/outputs) on
page 20
Updated Table 4: High-density STM32F100xx pin definitions on
page 24
Updated Section 5.3.1: General operating conditions on page 37
Updated PD0 and PD1 in Table 4: High-density STM32F100xx pin
definitions on page 24
7
Updated PD max specifications in Table 9: General operating
conditions
Added footnote to IDDA parameter description in Table 55: DAC
characteristics
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STM32F100xC, STM32F100xD, STM32F100xE
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