SN54LV139A, SN74LV139A DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS SCLS396G – APRIL 1998 – REVISED JULY 2003 SN54LV139A . . . J OR W PACKAGE SN74LV139A . . . D, DB, DGV, NS, OR PW PACKAGE (TOP VIEW) 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 SN54LV139A . . . FK PACKAGE (TOP VIEW) VCC 2G 2A 2B 2Y0 2Y1 2Y2 2Y3 1A 1B 1Y0 1Y1 1Y2 1Y3 1 16 1A 1G NC VCC 2G SN74LV139A . . . RGY PACKAGE (TOP VIEW) 2 15 3 14 4 13 5 12 6 11 10 7 8 9 1B 1Y0 NC 1Y1 1Y2 2G 2A 2B 2Y0 2Y1 2Y2 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 2A 2B NC 2Y0 2Y1 1Y3 GND NC 2Y3 2Y2 1 D VCC 1G 1A 1B 1Y0 1Y1 1Y2 1Y3 GND D 2Y3 D Ioff Supports Partial-Power-Down Mode Operation Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) 1G D D 2-V to 5.5-V VCC Operation Max tpd of 7.5 ns at 5 V Support Mixed-Mode Voltage Operation on All Ports Designed Specifically for High-Speed Memory Decoders and Data-Transmission Systems Incorporate Two Enable Inputs to Simplify Cascading and/or Data Reception GND D D D NC – No internal connection description/ordering information The ’LV139A devices are dual 2-line to 4-line decoders/demultiplexers designed for 2-V to 5.5-V VCC operation. ORDERING INFORMATION QFN – RGY SN74LV139ARGYR Tube of 40 SN74LV139AD Reel of 2500 SN74LV139ADR SOP – NS Reel of 2000 SN74LV139ANSR 74LV139A SSOP – DB Reel of 2000 SN74LV139ADBR LV139A Tube of 90 SN74LV139APW Reel of 2000 SN74LV139APWR TSSOP – PW –55°C to 125°C TOP-SIDE MARKING Reel of 1000 SOIC – D –40°C to 85°C ORDERABLE PART NUMBER PACKAGE† TA LV139A LV139A LV139A Reel of 250 SN74LV139APWT TVSOP – DGV Reel of 2000 SN74LV139ADGVR LV139A CDIP – J Tube of 25 SNJ54LV139AJ SNJ54LV139AJ CFP – W Tube of 150 SNJ54LV139AW SNJ54LV139AW LCCC – FK Tube of 55 SNJ54LV139AFK SNJ54LV139AFK † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2003, Texas Instruments Incorporated UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54LV139A, SN74LV139A DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS SCLS396G – APRIL 1998 – REVISED JULY 2003 description/ordering information(continued) These devices are designed for high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these decoders can minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay time of these decoders and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible. The ’LV139A devices comprise two individual 2-line to 4-line decoders in a single package. The active-low enable (G) input can be used as a data line in demultiplexing applications. These decoders/demultiplexers feature fully buffered inputs, each of which represents only one normalized load to its driving circuit. These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. FUNCTION TABLE INPUTS OUTPUTS SELECT G 2 B A Y0 Y1 Y2 H X X H H H H L L L L H H H L L H H L H H L H L H H L H L H H H H H L POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Y3 SN54LV139A, SN74LV139A DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS SCLS396G – APRIL 1998 – REVISED JULY 2003 logic diagram (positive logic) 4 1G 1 1Y0 5 1Y1 6 1Y2 2 1A 7 1B 1Y3 3 12 2Y0 15 11 2G 2Y1 10 2Y2 2A 14 9 13 2Y3 2B Pin numbers shown are for the D, DB, DGV, J, NS, PW, RGY, and W packages. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Package thermal impedance, θJA (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W (see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82°C/W (see Note 3): DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W (see Note 3): NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W (see Note 3): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W (see Note 4): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. This value is limited to 5.5 V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51-7. 4. The package thermal impedance is calculated in accordance with JESD 51-5. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54LV139A, SN74LV139A DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS SCLS396G – APRIL 1998 – REVISED JULY 2003 recommended operating conditions (see Note 5) SN54LV139A VCC VIH MAX 2 5.5 Supply voltage VCC = 2 V VCC = 2.3 V to 2.7 V High level input voltage High-level VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V 1.5 VCC × 0.7 Input voltage 0 Output voltage 0 V 0.5 VCC × 0.3 VCC × 0.3 VCC × 0.3 5.5 0 VCC –50 VCC = 2 V VCC = 2.3 V to 2.7 V VCC × 0.3 5.5 0 VCC –50 –2 VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V V V V µA –2 –6 –6 –12 –12 VCC = 2 V VCC = 2.3 V to 2.7 V 50 50 2 2 VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V 6 6 12 12 200 200 100 100 20 20 VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V Input transition rise or fall rate UNIT V 0.5 VCC × 0.3 VCC × 0.3 VI VO ∆t/∆v 5.5 VCC × 0.7 VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V Low level output current Low-level 2 VCC × 0.7 VCC × 0.7 Low level input voltage Low-level IOL MAX 1.5 VCC = 2 V VCC = 2.3 V to 2.7 V High level output current High-level MIN VCC × 0.7 VCC × 0.7 VIL IOH SN74LV139A MIN mA µA mA ns/V TA Operating free-air temperature –55 125 –40 85 °C NOTE 5: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VOH VOL TEST CONDITIONS IOH = –50 µA IOH = –2 mA 2.3 V IOL = 50 µA IOL = 2 mA IOL = 6 mA IOL = 12 mA VI = 5.5 V or GND VI = VCC or GND, Ioff Ci VI or VO = 0 to 5.5 V VI = VCC or GND MIN 2 V to 5.5 V IOH = –6 mA IOH = –12 mA II ICC SN54LV139A VCC IO = 0 TYP VCC–0.1 2 3V 2.48 4.5 V 3.8 MIN TYP MAX VCC–0.1 2 UNIT V 2.48 3.8 2 V to 5.5 V 0.1 0.1 2.3 V 0.4 0.4 3V 0.44 0.44 4.5 V V 0.55 0.55 0 to 5.5 V ±1 ±1 µA 5.5 V 20 20 µA 0 5 5 µA 3.3 V 1.9 PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 4 SN74LV139A MAX POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1.9 pF SN54LV139A, SN74LV139A DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS SCLS396G – APRIL 1998 – REVISED JULY 2003 switching characteristics over recommended operating VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1) PARAMETER tpd d tpd d FROM (INPUT) TO (OUTPUT) A or B Y G Y A or B Y G Y LOAD CAPACITANCE MIN free-air TA = 25°C TYP MAX CL = 15 pF CL = 50 pF temperature SN54LV139A SN74LV139A MIN MAX MIN MAX 7.7* 17.6* 1* 21* 1 21 7.4* 15.8* 1* 19* 1 19 10.2 22.5 1 26.5 1 26.5 9.9 20.2 1 24 1 24 range, UNIT ns ns * On products compliant to MIL-PRF-38535, this parameter is not production tested. switching characteristics over recommended operating VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) PARAMETER tpd d tpd d FROM (INPUT) TO (OUTPUT) A or B Y G Y A or B Y G Y LOAD CAPACITANCE MIN free-air TA = 25°C TYP MAX CL = 15 pF CL = 50 pF temperature SN54LV139A SN74LV139A MIN MAX MIN MAX 5.3* 11* 1* 13* 1 13 5.1* 9.2* 1* 11* 1 11 7.3 14.5 1 16.5 1 16.5 7 12.7 1 14.5 1 14.5 range, UNIT ns ns * On products compliant to MIL-PRF-38535, this parameter is not production tested. switching characteristics over recommended operating VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER tpd d tpd d FROM (INPUT) TO (OUTPUT) A or B Y G Y A or B Y G Y LOAD CAPACITANCE MIN free-air TA = 25°C TYP MAX CL = 15 pF CL = 50 pF temperature SN54LV139A SN74LV139A MIN MAX MIN MAX 3.7* 7.2* 1* 8.5* 1 8.5 3.5* 6.3* 1* 7.5* 1 7.5 5.2 9.2 1 10.5 1 10.5 4.9 8.3 1 9.5 1 9.5 VCC 3.3 V TYP 5V 18.2 range, UNIT ns ns * On products compliant to MIL-PRF-38535, this parameter is not production tested. operating characteristics, TA = 25°C PARAMETER Cpd d Power dissipation capacitance TEST CONDITIONS pF CL = 50 pF, f = 10 MHz 17.3 UNIT pF PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN54LV139A, SN74LV139A DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS SCLS396G – APRIL 1998 – REVISED JULY 2003 PARAMETER MEASUREMENT INFORMATION From Output Under Test RL = 1 kΩ From Output Under Test Test Point S1 VCC Open TEST GND CL (see Note A) CL (see Note A) S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain Open VCC GND VCC LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS VCC 50% VCC Timing Input 0V tw tsu VCC 50% VCC 50% VCC Input th VCC 50% VCC Data Input 50% VCC 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC 50% VCC Input 50% VCC tPLH In-Phase Output tPHL 50% VCC tPHL Out-of-Phase Output 0V VOH 50% VCC VOL 50% VCC 50% VCC 50% VCC 0V tPLZ tPZL ≈VCC Output Waveform 1 S1 at VCC (see Note B) tPLH VOH 50% VCC VOL VC C Output Control 50% VCC tPHZ tPZH Output Waveform 2 S1 at GND (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS VOL + 0.3 V VOL 50% VCC VOH – 0.3 V VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns. D. The outputs are measured one at a time with one input transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPHL and tPLH are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,40 0,23 0,13 24 13 0,07 M 0,16 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 0°–8° 1 0,75 0,50 12 A Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,08 14 16 20 24 38 48 56 A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 DIM 4073251/E 08/00 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. Falls within JEDEC: 24/48 Pins – MO-153 14/16/20/56 Pins – MO-194 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 MECHANICAL DATA MSOI002B – JANUARY 1995 – REVISED SEPTEMBER 2001 D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 8 PINS SHOWN 0.020 (0,51) 0.014 (0,35) 0.050 (1,27) 8 0.010 (0,25) 5 0.008 (0,20) NOM 0.244 (6,20) 0.228 (5,80) 0.157 (4,00) 0.150 (3,81) Gage Plane 1 4 0.010 (0,25) 0°– 8° A 0.044 (1,12) 0.016 (0,40) Seating Plane 0.010 (0,25) 0.004 (0,10) 0.069 (1,75) MAX PINS ** 0.004 (0,10) 8 14 16 A MAX 0.197 (5,00) 0.344 (8,75) 0.394 (10,00) A MIN 0.189 (4,80) 0.337 (8,55) 0.386 (9,80) DIM 4040047/E 09/01 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). Falls within JEDEC MS-012 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-150 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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