T6963CFG TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC T6963CFG DOT MATRIX LCD CONTROLLER LSI The T6963CFG is an LCD controller designed to be used with LCD control driver LSIs and data display memories. The device has an 8−bit parallel data bus and control lines for reading or writing through an MPU interface. It can be directly connected to a TMPZ−80. It has a 128−word character generator ROM which can control an external display RAM of up to 64 Kbytes. Allocation of text, graphics and external character generator RAM can be made easily and the display window can be moved freely within the allocated memory range. The device supports a very broad range of LCD formats by allowing selection of different combinations via a set of programmable inputs. It can be used in text, graphic and combination text−and−graphic modes, and includes various attribute functions. The T6963CFG is lead (Pb)-free (Sn-Ag) product. Weight: 1.2 g (typ.) Features z Display format (pin−selectable) Columns : 32, 40, 64, 80 Lines : 2, 4, 6, 8, 10, 12, 14, 16, 20, 24, 28, 32 The combination of number of columns and number of lines must not cause the frequency to exceed 5.5 MHz. (See Fig. 2) z Character font (pin−selectable) Horizontal dots : 5, 6, 7, 8 Vertical dots : 8 (fixed) It is necessary to set a character font in Graphic mode just as in Text mode. The oscillation frequency does not change with the font selection. z Display duty : 1 / 16 to 1 / 128 z A 128−word character generator ROM (code 0101) T6963CFG−0101 is built in as standard. z External display memory : 64 KB Max The addresses in display memory of the text area, graphic area and external character generator area are determined by software. z Read or Write operations from the CPU do not disturb the display. z A crystal oscillator circuit is built in. The oscillation frequency is adjusted according to the display size. If using an external clock, use the XI pin as the clock input. (XO open.) External capacitors Crystal oscillation : 20 to 30 pF Ceramic oscillation : 30 to 100 pF Built−in feedback resistor : 900 kΩ (typ.) z Toshiba LCD driver LSIs (other than these with a built−in RAM) can be connected to the device. z External display RAM must be static RAM. The T6963CFG cannot refresh D−RAM. z The attribute functions can only be used in Text mode. They cannot be used in Graphic or Combination Character mode. 1 2007-05-15 T6963CFG Block Diagram 2 2007-05-15 T6963CFG Pin Assignment Pin Functions Pin Name I/O Functions Pins for selection of LCD size MDS MD0 MD1 Input DUAL H H H H H H H H L L L L L L L L MDS L L L L H H H H L L L L H H H H MD1 H H L L H H L L H H L L H H L L MD0 H L H L H L H L H L H L H L H L LINES 2 4 6 8 10 12 14 16 4 8 12 16 20 24 28 32 V−DOTS 16 32 48 64 80 96 112 128 32 64 96 128 160 192 224 256 1 SCREEN MD2 MD3 FS0 FS1 Input Input Pins for selection of number of columns Pins for selection of font 2 SCREENS MD2 H L H L MD3 H H L L Columns 32 40 64 80 FS0 H L H L FS1 H H L L Font 5×8 6×8 7×8 8×8 D0 to D7 I/O Data I / O pins between CPU and T6963CFG (D7 is MSB) WR Input Data Write. Write data into T6963CFG when WR = L. RD Input Data Read. Read data fromT6963CFG when RD = L. CE Input Chip Enable for T6963CFG. CE must be L when CPU communicates with T6963CFG. 3 2007-05-15 T6963CFG Pin Name I/O Functions C/D Input HALT Input H ······ Normal, L ······ Stops the oscillation of the clock RESET Input H ······ Normal (T6963CFG has internal pull−up resistor) L ······ Initialize T6963CFG. Text and graphic have addresses and text and graphic area settings are retained. DSPON Output DUAL Input WR = L ······ C / D = H: Command Write C / D = L: Data Write RD = L ······ C / D = H: Status Read C / D = L: Data Read Control pin for external DC / DC. DSPON is L when HALT is L or RESET is L. (When DSPON goes H, the column drivers are cleared.) H ······ Single−Scan L ······ Dual−Scan DUAL H H L L SDSEL H L H L H ······ Sending data by odd / even separation L ······ Sending data by simple serial method SDSEL Input ce0 Upper screen HOD, ED ED HOD, ED ED Lower screen ― ― LOD, ED ED at DUAL = H Chip enable pin for display memory in the address range 0000H to 07FFH ce0 (LOD) Output ce1 (LSCP) Output ce Output d0 to d7 I/O ad0 to ad15 Output Address outputs for display memory (ad15 = L: for upper area of LCD, ad15 = H: for lower area of LCD) R/W Output Read / Write signal for display memory ED Output LOD at DUAL = L ce1 Serial data output for odd columns in lower area of LCD at DUAL = H Chip enable pin for display memory in the address range 0800H to 0FFFH LSCP at DUAL = L Shift clock pulse output for column drivers in lower area of LCD Chip enable pin for display memory of any address Data I / O pins for display memory SDSEL = H: Data output for even columns in both upper and lower areas of LCD SDSEL = L: Data output for columns in both upper and lower areas of LCD HOD Output Data output for odd columns in upper area of LCD CDATA Output Synchronous signal for row driver HSCP Output Shift clock pulse for column driver of upper area of LCD LP Output Latch pulse for column driver. Shift clock pulse for row driver FR Output Frame signal XI Input XO Output Crystal oscillator output CH1, CH2 Output Check signal T1 , T2 Input VDD ― Power supply (5.0 V) VSS ― Power supply (0 V) Crystal oscillator input Test input. Usually open 4 2007-05-15 T6963CFG Functional Definition ● After power on, it is necessary to reset. RESET is kept L between 5 clocks up (oscillation clock). ● When HALT = L, the oscillation stops. The power supply for the LCD must now be turned off, to protect the LCD from DC bias. ● The HALT function includes the RESET function. ● The column / line counter and display register are cleared by RESET. (Other registers are not cleared.) Disable the display using the clear−display register. ● The status must be checked before data or commands are sent. The MSB = 0 status check must be done in particular. There is a possibility of erroneous operation due to a hard interrupt. ● STA0 and STA1 must be checked at the same time. When a command is executed, data transmission errors may occur. ● The T6963CFG can only handle one byte per machine cycle (16 clocks). It is impossible to send more than two data in a machine cycle. ● When using a command with operand data, it important to send the data first, and then execute the command. ● The character codes used by the T6963CFG are different from ASCII codes. 5 2007-05-15 T6963CFG ● State after RESET / HALT (Fig. 1) H : L : F : K0 : VEND : Note 1: Note 2: Terminal Halt Reset D0 to D7 F F d0 to d7 F F r/w H H ce H (Note 1) H (Note 1) ad0 to ad15 H (Note 2) H (Note 2) ce0 , ce1 H (Note 1) H (Note 1) ED, HOD Final data Final data HSCP L L LP L L CDATA H H FR H H CH1 L K0 CH2 L VEND DSPON L L XO H OSC clock Level H Level L Floating (high impedance) Test signal Test signal In Attribute mode, H or L according to state of graphic pointer In Attribute mode, data of graphic pointer 6 2007-05-15 T6963CFG ● The relationship between number of row / column and oscillation clock (Fig. 2) The frequency of the crystal oscillator is adjusted by the following formula. fOSC : Frequency of oscillation fSCP : Frequency of shift clock (fSCP = fOSC / 2) fR : Frequency of Frame M : Number of characters on one line (number of dots on one line 8 M) For all font sizes (e.g. 7 × 8, 6 × 8, 5× 8) the oscillation frequency remains constant. N : Number of rows (duty = 1 / 8N) 8M f SCP × 8N = 1 fR fOSC = fR × 64 × 2 × M × N (fR = 60 Hz) Unit: [MHz] M N 2 4 6 8 10 12 14 16 32 40 64 80 0.492 0.614 0.983 1.229 0.983 1.229 1.966 2.458 0.983 1.229 1.966 2.458 1.966 2.458 3.932 4.915 1.475 1.843 2.949 3.686 2.949 3.686 5.898 7.372 1.966 2.458 3.932 4.915 3.932 4.915 7.864 9.830 2.458 3.072 4.915 6.144 4.915 6.144 9.830 12.288 2.949 3.686 5.898 7.373 5.898 7.373 11.776 14.746 3.440 4.300 6.881 8.602 6.881 8.601 13.763 17.203 3.932 4.915 7.864 9.830 7.864 9.830 15.729 19.660 Note 1: Upper ··· Single−Scan, lower ···· Dual−Scan at fR = 60 Hz Duty 1 / 16 1 / 32 1 / 48 1 / 64 1 / 80 1 / 96 1 / 112 1 / 128 Upper Lower Note 2: M and N to mach 5.5 MHz or less indicate the conditions to apply T6963CFG. 7 2007-05-15 T6963CFG ● RAM Interface The external RAM is used to store display data (text, graphic and external CG data). With single−scan, text data, graphic data and external CG data can be freely allocated to the memory area (64 KB max). With dual−scan, LCD I is allocated to 0000H to 7FFFH (32 KB max), LCD II is allocated to 8000H to FFFFH (32 KB max). Text data, graphic data and external CG data can be freely allocated in LCD I. In LCDII, the same addresses must be allocated as in LCD I, except ad15. ad15 determines selection of LCD I or LCD II. It can be use the address decoded signals ce0 (0000 to 07FFH), ce1 (0800 to 0FFFH) within 4 KB. ce0 and ce1 allow decoding of addresses in the ranges (0000 to 07FFH) and (0800 to 0FFFH) respectively within a 4−KB memory space. (Example) (1) Single−Scan (2) Dual−Scan 8 2007-05-15 T6963CFG ● Flowchart of communications with MPU (1) Status Read A status check must be performed before data is read or written. Status check The Status of T6963CFG can be read from the data lines. RD L WR H CE L C/D H D0 to D7 Status word The T6963CFG status word format is as follows: MSB STA7 D7 LSB STA6 D6 STA5 D5 STA4 D4 STA3 D3 STA2 D2 STA1 D1 STA0 D0 STA0 Check command execution capability 0: Disable 1: Enable STA1 Check data read / write capability 0: Disable 1: Enable STA2 Check Auto mode data read capability 0: Disable 1: Enable STA3 Check Auto mode data write capability 0: Disable 1: Enable STA4 Not used STA5 Check controller operation capability 0: Disable 1: Enable STA6 Error flag. Used for Screen Peek and Screen copy commands. 0: No error 1: Error STA7 Check the blink condition 0: Display off 1: Normal display Note 1: It is necessary to check STA0 and STA1 at the same time. There is a possibility of erroneous operation due to a hardware interrupt. Note 2: For most modes STA0 / STA1 are used as a status check. Note 3: STA2 and STA3 are valid in Auto mode; STA0 and STA1 are invalid. 9 2007-05-15 T6963CFG Status checking flow a) b) Note 4: When using the MSB = 0 command, a Status Read must be performed. If a status check is not carried out, the T6963CFG cannot operate normally, even after a delay time. The hardware interrupt occurs during the address calculation period (at the end of each line). If a MSB = 0 command is sent to the T6963CFG during this period, the T6963CFG enters Wait status. If a status check is not carried out in this state before the next command is sent, there is the possibility that the command or data will not be received. (2) Setting data When using the T6963CFG, first set the data, then set the command. Procedure for sending a command a) The case of 1 data b) The case of 2 data Note: When sending more than two data, the last datum (or last two data) is valid. 10 2007-05-15 T6963CFG Command Definitions Command Code D1 D2 Function REGISTERS SETTING 00100001 00100010 00100100 X address Data Low address Y address 00H High address Set Cursor Pointer Set Offset Register Set Address Pointer SET CONTROL WORD 01000000 01000001 01000010 01000011 Low address Columns Low address Columns High address 00H High address 00H Set Text Home Address Set Text Area Set Graphic Home Address Set Graphic Area MODE SET 1000X000 1000X001 1000X011 1000X100 10000XXX 10001XXX ― ― ― ― ― ― ― ― ― ― ― ― OR mode EXOR mode AND mode Text Attribute mode Internal CG ROM mode External CG RAM mode DISPLAY MODE 10010000 1001XX10 1001XX11 100101XX 100110XX 100111XX ― ― ― ― ― ― ― ― ― ― ― ― Display off Cursor on, blink off Cursor on, blink on Text on, graphic off Text off, graphic on Text on, graphic on CURSOR PATTERN SELECT 10100000 10100001 10100010 10100011 10100100 10100101 10100110 10100111 ― ― ― ― ― ― ― ― ― ― ― ― ― ― ― ― 1−line cursor 2−line cursor 3−line cursor 4−line cursor 5−line cursor 6−line cursor 7−line cursor 8−line cursor DATA AUTO READ / WRITE 10110000 10110001 10110010 ― ― ― ― ― ― Set Data Auto Write Set Data Auto Read Auto Reset DATA READ / WRITE 11000000 11000001 11000010 11000011 11000100 11000101 Data ― Data ― Data ― ― ― ― ― ― ― Data Write and Increment ADP Data Read and Increment ADP Data Write and Decrement ADP Data Read and Decrement ADP Data Write and Nonvariable ADP Data Read and Nonvariable ADP SCREEN PEEK 11100000 ― ― SCREEN COPY 11101000 Screen Peek Screen Copy X: invalid 11 2007-05-15 T6963CFG Command BIT SET / RESET Code D1 D2 11110XXX 11111XXX 1111X000 1111X001 1111X010 1111X011 1111X100 1111X101 1111X110 1111X111 ― ― ― ― ― ― ― ― ― ― ― ― ― ― ― ― ― ― ― ― Function Bit Reset Bit Set Bit 0 (LSB) Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 (MSB) X: invalid ● Setting registers Code Hex. 00100001 21H 00100010 00100100 Function D1 D2 SET CURSOR POINTER X ADRS Y ADRS 22H SET OFFSET REGISTER DATA 00H 24H SET ADDRESS POINTER LOW ADRS HIGH ADRS (1) Set Cursor Pointer The position of the cursor is specified by X ADRS and Y ADRS. The cursor position can only be moved by this command. Data read / write from the MPU never changes the cursor pointer. X ADRS and Y ADRS are specified as follows. X ADRS 00H to 4FH (lower 7 bits are valid) Y ADRS 00H to 1FH (lower 5 bits are valid) b) Dual− Scan X ADRS 00H to 4FH a) Single− Scan X ADRS 00 to 4FH Y ADRS 00H to 0FH Upper screen Y ADRS 00H to 0FH Y ADRS 10H to 1FH Lower screen (2) Set Offset Register The offset register is used to determine the external character generator RAM area. The T6963CFG has a 16−bit address bus as follows: MSB ad15 LSB ad14 ad13 ad12 Offset Register Data ad11 ad10 ad9 ad8 ad7 ad6 Character Code 12 ad5 ad4 ad3 ad2 ad1 ad0 Line Scan 2007-05-15 T6963CFG T6963CFG assign External character generator, when character code set 80H to FFH in using internal character generator. Character code 00H to 80H assign External character generator, when External generator mode. The senior five bits define the start address in external memory of the CG RAM area. The next eight bits represent the character code of the character. In internal CG ROM mode, character codes 00H to 7FH represent the predefined “internal” CG ROM characters, and codes 80H to FFH represent the user’ s own “external” characters. In external CG RAM mode, all 256 codes from 00H to FFH can be used to represent the user' s own characters. The three least significant bits indicate one of the eight rows of eight dots that define the character’ s shape. The relationship between display RAM address and offset register Offset register data 00000 00001 00010 CG RAM hex. address (start to end) 0000 to 07FFH 0800 to 0FFFH 1000 to 17FFH 11100 11101 11110 11111 E000 to E7FFH E800 to EFFFH F000 to F7FFH F800 to FFFFH (Example 1) Offset register Character code Character generator RAM start address 02H 80H 0001 1 0100 4 0000 0 0000 0 H (Example 2) The relationship between display RAM data and display characters γ and ζ are displayed by character generator RAM. 13 2007-05-15 T6963CFG (3) Set Address Pointer The Set Address Pointer command is used to indicate the start address for writing to (or reading from) external RAM. The Flowchart for Set Address Pointer command ● Set Control Word Code Hex. Function 01000000 40H Set Text Home Address 01000001 41H Set Text Area 01000010 42H Set Graphic Home Address 01000011 43H Set Graphic Area D1 D2 Low address High address Columns 00H Low address High address Columns 00H The home address and column size are defined by this command. 14 2007-05-15 T6963CFG (1) Set Text Home Address The starting address in the external display RAM for text display is defined by this command. The text home address indicates the leftmost and uppermost position. The relationship between external display RAM address and display position TH TH + CL TH +TA TH + TA + CL (TH + TA) + TA TH + 2TA + CL (TH + 2TA) +TA TH + 3TA + CL TH + (n − 1) TA TH + (n − 1) TA + CL TH: Text home address TA: Text area number (columns) CL: Columns are fixed by hardware (pin−programmable). (Example) Text home address : 0000H Text area : 0020H MD2 = H, MD3 = H : 32 columns DUAL = H, MDS = L, MD0 = L, MD1 = H: 4 lines 0000H 0001H 001EH 001FH 0020H 0021H 003EH 002FH 0040H 0041H 005EH 005FH 0060H 0061H 007EH 007FH (2) Set Graphic Home Address The starting address of the external display RAM used for graphic display is defined by this command. The graphic home address indicates the leftmost and uppermost position. The relationship between external display RAM address and display position GH GH + CL GH + GA GH + GA + CL (GH + GA) + GA GH + 2GA + CL (GH + 2GA) + GA GH + 3GA + CL GH + (n − 1) GA GH + (n − 1) GA + CL GH: Graphic home address GA: Graphic area number (columns) CL: Columns are fixed by hardware (pin−programmable). 15 2007-05-15 T6963CFG (Example) Graphic home address : 0000H Graphic area : 0020H MD2 = H, MD3 = H : 32 columns DUAL = H, MDS = L, MD0 = H, MD1 = H : 2 lines 0000H 0001H 001EH 001FH 0020H 0021H 003EH 003FH 0040H 0041H 005EH 005FH 0060H 0061H 007EH 007FH 0080H 0081H 009EH 009FH 00A0H 00A1H 00BEH 00BFH 00C0H 00C1H 00DEH 00DFH 00E0H 00E1H 00FEH 00FFH 0100H 0101H 011EH 011FH 0120H 0121H 013EH 013FH 0140H 0141H 015EH 015FH 0160H 0161H 017EH 017FH 0180H 0181H 019EH 019FH 01A0H 01A1H 01BEH 01BFH 01C0H 01C1H 01DEH 01DFH 01E0H 01E1H 01FEH 01FFH (3) Set Text Area The display columns are defined by the hardware setting. This command can be used to adjust the columns of the display. (Example) LCD size Text home address Text area MD2 = H, MD3 = H DUAL = H, MDS = L, MD0 = L, MD1 = H : 20 columns, 4 lines : 0000H : 0014H : 32 columns : 4 lines 0000 0001 ········· 0013 0014 ········· 001F 0014 0015 ········· 0027 0028 ········· 0033 0028 0029 ········· 003B 003C ········· 0047 003C 003D ········· 004F 0050 ········· 005B LCD 16 2007-05-15 T6963CFG (4) Set Graphic Area The display columns are defined by the hardware setting. This command can be used to adjust the columns of the graphic display. (Example) LCD size : 20 columns, 2 lines Graphic home address : 0000H Graphic area : 0014H MD2 = H, MD3 = H : 32 columns DUAL = H, MDS = L, MD0 = H, MD1 = H : 2 lines 0000 0001 ········· 0013 0014 ········· 001F 0014 0015 ········· 0027 0028 ········· 0033 0028 0029 ········· 003B 003C ········· 0047 003C 003D ········· 004F 0050 ········· 005B 0050 0051 ········· 0063 0064 ········· 006F 0064 0065 ········· 0077 0078 ········· 0083 0078 0079 ········· 008B 008C ········· 0097 008C 008D ········· 009F 00A0 ········· 00AB 00A0 00A1 ········· 00B3 00B4 ········· 00BF 00B4 00B5 ········· 00C7 00C8 ········· 00D3 00C8 00C9 ········· 00DB 00DC ········· 00E7 00DC 00DD ········· 00EF 00F0 ········· 00FD 00F0 00F1 ········· 0103 0104 ········· 011F 0104 0105 ········· 0127 0128 ········· 0123 0128 0129 ········· 013B 013C ········· 0147 013C 013D ········· 014F 0150 ········· 015B LCD If the graphic area setting is set to match the desired number of columns on the LCD, the addressing scheme will be automatically modified so that the start address of each line equals the end address of the previous line + 1. 17 2007-05-15 T6963CFG ● Mode set Code Function Operand 1000X000 OR Mode ― 1000X001 EXOR Mode ― 1000X011 AND Mode ― 1000X100 TEXT ATTRIBUTE Mode ― 10000XXX Internal Character Generator Mode ― 10001XXX External Character Generator Mode ― X: invalid The display mode is defined by this command. The display mode does not change until the next command is sent. The logical OR, EXOR, AND of text or graphic display can be displayed. In Internal Character Generator mode, character codes 00H to 7FH are assigned to the built−in character generator ROM. The character codes 80H to FFH are automatically assigned to the external character generator RAM. (Example) Note: Attribute functions can only be applied to text display, since the attribute data is placed in the graphic RAM area. 18 2007-05-15 T6963CFG Attribute function The attribute operations are Reverse display, Character blink and Inhibit. The attribute data is written into the graphic area which was defined by the Set Control Word command. Only text display is possible in Attribute Function mode; graphic display is automatically disabled. However, the Display Mode command must be used to turn both Text and Graphic on in order for the Attribute function to be available. The attribute data for each character in the text area is written to the same address in the graphic area. The Attribute function is defined as follows. Attribute RAM 1byte X X X X d3 d3 d2 d1 d0 0 0 0 0 Normal display 0 1 0 1 Reverse display 0 0 1 1 Inhibit display 1 0 0 0 Blink of normal display 1 1 0 1 Blink of reverse display 1 0 1 1 Blink of inhibit display d2 d1 d0 Function X: invalid ● Display mode Code 1 Function Operand 10010000 Display off ― 1001XX10 Cursor on, blink off ― 1001XX11 Cursor on, blink on ― 100101XX Text on, graphic off ― 100110XX Text off, graphic on ― 100111XX Text on, graphic on ― 0 0 1 D3 D2 D1 X: invalid D0 Cursor blink Cursor display Text display Graphic display on: 1, off: 0 on: 1, off: 0 on: 1, off: 0 on: 1, off: 0 Note: It is necessary to turn on “Text display” and “Graphic display” in the following cases. a) Combination of text / graphic display b) Attribute function 19 2007-05-15 T6963CFG ● Cursor pattern select Code Function Operand 10100000 1−line cursor ― 10100001 2−line cursor ― 10100010 3−line cursor ― 10100011 4−line cursor ― 10100100 5−line cursor ― 10100101 6−line cursor ― 10100110 7−line cursor ― 10100111 8−line cursor ― When cursor display is ON, this command selects the cursor pattern in the range 1 line to 8 lines. The cursor address is defined by the Cursor Pointer Set command. ● Data Auto Read / Write Code Hex. Function Operand 10110000 B0H Set Data Auto Write ― 10110001 B1H Set Data Auto Read ― 10110010 B2H Auto Reset ― This command is convenient for sending a full screen of data from the external display RAM. After setting Auto mode, a Data Write (or Read) command is need not be sent between each datum. A Data Auto Write (or Read) command must be sent after a Set Address Pointer command. After this command, the address pointer is automatically incremented by 1 after each datum. In Auto mode, the T6963CFG cannot accept any other commands. The Auto Reset command must be sent to the T6963CFG after all data has been sent, to clear Auto mode. 20 2007-05-15 T6963CFG Note: A Status check for Auto mode (STA2, STA3 should be checked between sending of each datum. Auto Reset should be performed after checking STA3 = 1 (STA2 = 1). Refer to the following flowchart. a) Auto Read mode b) Auto Write mode 21 2007-05-15 T6963CFG ● Data Read / Write Code Hex. Function Operand 11000000 C0H Data Write and Increment ADP Data 11000001 C1H Data Read and Increment ADP ― 11000010 C2H Data Write and Decrement ADP Data 11000011 C3H Data Read and Decrement ADP ― 11000100 C4H Data Write and Nonvariable ADP Data 11000101 C5H Data Read and Nonvariable ADP ― This command is used for writing data from the MPU to external display RAM, and reading data from external display RAM to the MPU. Data Write / Data Read should be executed after setting address using Set Address Pointer command. The address pointer can be automatically incremented or decremented using this command. Note: This command is necessary for each 1−byte datum. Refer to the following flowchart. 22 2007-05-15 T6963CFG ● Screen Peek Code Hex. 11100000 E0H Function Screen Peek Operand ― This command is used to transfer 1 byte of displayed data to the data stack; this byte can then be read from the MPU by data access. The logical combination of text and graphic display data on the LCD screen can be read by this command. The status (STA6) should be checked just after the Screen Peek command. If the address determined by the Set Address Pointer command is not in the graphic area, this command is ignored and a status flag (STA6) is set. Refer to the following flowchart. Note: This command is available when hardware column number and software column number are the same. Hardware column number is related to MD2 and MD3 setting. Software column number is related to Set Text Area and Set Graphic Area command. 23 2007-05-15 T6963CFG ● Screen Copy Code Hex. 11101000 E8H Function Screen Copy Operand ― This command copies a single raster line of data to the graphic area. The start point must be set using the Set Address Pointer command. Note 1: If the attribute function is being used, this command is not available. (With Attribute data is graphic area data.) Note 2: With Dual−Scan, this command cannot be used (because the T6963CFG cannot separate the upper screen data and lower screen data). Refer to the following flowchart. Note: This command is available when hardware column number and software column number are the same. Hardware column number is related to MD2 and MD3 setting. Software column number is related to Set Text Area and Set Graphic Area command. 24 2007-05-15 T6963CFG ● Bit Set / Reset Code Function Operand 11110XXX Bit Reset ― 11111XXX Bit Set ― 1111X000 Bit 0 (LSB) ― 1111X001 Bit 1 ― 1111X010 Bit 2 ― 1111X011 Bit 3 ― 1111X100 Bit 4 ― 1111X101 Bit 5 ― 1111X110 Bit 6 ― 1111X111 Bit 7 (MSB) ― X: invalid This command use to set or reset a bit of the byte specified by the address pointer. Only one bit can be set / reset at a time. Refer to the following flowchart. 25 2007-05-15 MSB 26 7 6 5 4 3 2 1 0 LSB 0 1 2 3 4 5 6 7 8 9 A B The relation between character codes and character pattern (CG ROM TYPE 0101) Character Code Map C D E F T6963CFG 2007-05-15 The relation between character codes and character pattern (CG ROM TYPE 0201) T6963CFG 27 2007-05-15 T6963CFG Absolute Maximum Ratings (Ta = 25°C) Item Symbol Rating Unit Supply Voltage VDD (Note) −0.3 to 7.0 V Input Voltage VIN (Note) −0.3 to VDD + 0.3 V Operating Temperature Topr −20 to 70 °C Storage Temperature Tstg −55 to 125 °C Note: Referenced to VSS = 0 V. Electrical Characteristics DC Characteristics Test Conditions (Unless Otherwise Noted, VSS = 0 V, VDD = 5.0 V ± 10%, Ta = −20 to 75°C) Item Operating Voltage H Level Symbol Test Circuit Test Condition Min Typ. Max Unit Pin Name VDD ― ― 4.5 5.0 5.5 V VDD ― VDD − 2.2 ― VDD V Input pins VIH ― Input Output Voltage L Level VIL ― 0 ― 0.8 V Input pins H Level VOH ― VDD − 0.3 ― VDD V Output pins ― 0 ― 0.3 V Output pins ― L Level VOL H Level ROH ― VOUT = VDD − 0.5 V ― ― 400 Ω Output pins L Level ROL ― VOUT = 0.5 V ― ― 400 Ω Output pins Input Pull−up Resistance RPU ― ― 50 100 200 kΩ (Note 1) Operating Frequency fOSC ― ― 0.4 ― 5.5 MHz Current Consumption (Operating) IDD (1) ― VDD = 5.0 V fOSC = 3.0 MHz ― 3.3 6 mA VDD Current Consumption (Halt) IDD (2) ― VDD = 5.0 V ― ― 3 µA VDD Output Resistance (Note 2) Note 1: Applied T1, T2 , RESET Note 2: MDS = L, MD0 = L, MD1 = L, MD2 = H, MD3 = H, FS0 = L, FS1 = L, SDSEL = L, DUAL = H, D7 to D0 = LHLHLHLH 28 2007-05-15 T6963CFG AC Characteristics ● Switching Characteristics (1) 0.9×VDD 0.1×VDD 0.9×VDD 0.9×VDD 0.1×VDD 0.1×VDD 0.1×VDD 0.1×VDD 0.9×VDD 0.9×VDD 0.1×VDD 0.9×VDD 0.1×VDD 0.9×VDD 0.1×VDD 0.9×VDD 0.1×VDD Test Conditions (Unless Otherwise Noted, VDD = 5.0 V ± 10%, VSS = 0 V, Ta = −20 to 70°C) Item Operating Frequency SCP Pulse Width Symbol fSCP Test Conditions Ta = −10~70°C Min Max Unit ― 2.75 MHz tCWH, tCWL ― 150 ― ns SCP Rise / Fall Time tr, tf ― ― 30 ns LP Set−up Time tLSU ― 150 290 ns LP Hold Time tLHD ― 5 40 ns Data Set−up Time tDSU ― 170 ― ns Data Hold Time tDHD ― 80 ― ns FR Delay Time td ― 0 90 ns CDATA Set−up Time tCSU ― 450 850 ns CDATA Hold Time tCHD ― 450 950 ns 29 2007-05-15 T6963CFG ● Switching Characteristics (2) Bus Timing 0.9×VDD 0.9×VDD C/D 0.1×VDD 0.1×VDD tCDS CE tCDH 0.1×VDD 0.1×VDD tAS tAH tRD, tWR 0.9×VDD RD , WR 0.1×VDD 0.1×VDD tDS D0 to D7 (WRITE) tDH 0.9×VDD 0.9×VDD 0.1×VDD 0.1×VDD D0 to D7 (READ) 0.9×VDD 0.9×VDD 0.1×VDD 0.1×VDD tACC Hi-Z tOH Test Conditions (Unless Otherwise Noted, VDD = 5.0 V ± 10%, VSS = 0 V, Ta = −20 to 75°C) Item Symbol Test Conditions Min Max Unit C / D Set−up Time tCDS ― 100 ― ns C / D Hold Time tCDH ― 10 ― ns tRD, tWR ― 80 ― ns Address Set−up Time tAS ― 0 ― ns Address Hold Time tAH ― 0 ― ns RD , WR Pulse Width Data Set−up Time tDS ― 80 ― ns Data Hold Time tDH (Note) 40 ― ns Access Time tACC (Note) ― 150 ns Output Hold Time tOH (Note) 10 50 ns Note: With the load circuit connected LOAD CIRCUIT Test pin CL CL =50pF（including wiring and probe capacitance） 30 2007-05-15 T6963CFG ● Switching Characteristics (3) (1) External RAM Read mode 0.9×VDD 0.9×VDD 0.1×VDD 0.1×VDD 0.1×VDD 0.9×VDD 0.9×VDD 0.1×VDD 0.1×VDD 0.9×VDD 0.1×VDD 0.9×VDD 0.1×VDD 0.1×VDD (2) External RAM Write mode 0.9×VDD 0.9×VDD 0.9×VDD 0.1×VDD 0.1×VDD 0.9×VDD 0.9×VDD 0.1×VDD 0.1×VDD 0.9×VDD 0.1×VDD 0.9×VDD 0.1×VDD 0.9×VDD 0.9×VDD Hi-Z 0.1×VDD 0.1×VDD 31 2007-05-15 T6963CFG Test Conditions (Unless Otherwise Noted, VDD = 5.0 V ± 10%, VSS = 0 V, Ta = −20 to 70°C) Item Symbol Test Conditions Min Max Unit Address Delay Time td1 ― ― 250 ns ce Fall Delay Time (Read) td2 ― ― 180 ns ce Rise Delay Time (Read) td3 ― ― 180 ns Data Set−up Time tDS ― 0 ― ns Data Hold Time tDH ― 30 ― ns ce Fall Delay Time (Write) td4 ― ― 200 ns ce Rise Delay Time (Write) td5 ― ― 200 ns r / w Fall Delay Time td6 ― ― 180 ns r / w Rise Delay Time td7 ― ― 180 ns Data Stable Time td8 (Note) ― 450 ns Data Hold Time td9 ― ― 200 ns Note: With the load circuit connected LOAD CIRCUIT Test pin CL CL =50pF（including wiring and probe capacitance） 32 2007-05-15 T6963CFG T6963CFG Example of Application Circuit The T6963CFG can be directly connected to a TMPZ84C00A (Z80 Note 1: CMOS). The T6963CFG can be used with a TMPZ84C00A as shown in the following application circuit. ● MPU memory address mapping Data is transferred to the T6963CFG using a memory request signal. Address DATA (I / O) XXXXH Command / Status XXXX + 1H Note 1: Z80 is a trademark of Zilog Inc. 33 2007-05-15 T6963CFG ● MPU I / O addressing Data is transferred to the T6963CFG using an I / O request signal. I / O Address DATA XXH Command / Status XX + 1H 34 2007-05-15 T6963CFG ● When using PPI LSI (TMP82C55) The T6963CFG can be connected to a PPI LSI. The port A connects to the data bus. The port C connects to the control bus. (C / D, CE , WR , RD ) 35 2007-05-15 T6963CFG Application Circuit (1) 36 2007-05-15 T6963CFG Application Circuit (2) 37 2007-05-15 T6963CFG Sample Program 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : ; ; ; ; ; ; ; ; TXHOME TXAREA GRHOME GRAREA OFFSET ADPSET AWRON AWROFF CMDP DP STACK ; T6963CFG SAMPLE PROGRAM V0.01 SOURCE PROGRAM for TMPZ84C00P 1991 − 2 −15 Display Size: 20 Column × 8 Lines Character Font: 8 Dots Mode EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU 40H 41H 42H 43H 22H 24H 0B0H 0B2H 01H 00H 9FFFH ORG 0000H LD SP, STACK ; ; ; ; ; ; ; ; ; ; ; SET TXT HM ADD SET TXT AREA SET GR HM ADD SET GR AREA SET OFFSET ADD SET ADD PTR SET AUTO WRITE MODE RESET AUTO WRITE MODE CMD PORT DATA PORT STACK POINTER BASE ADDRESS START: ; ; ; SET TEXT HOME ADDRESS LD CALL LD CALL ; ; ; HL, 0000H DT2 A, TXHOME CMD ; TEXT HOME ADDRESS 0000H SET GRAPHIC HOME ADDRESS LD CALL LD CALL HL, 0200H DT2 A, GRHOME CMD ; GRAPHIC HOME ADDRESS 0200H ; 38 2007-05-15 T6963CFG 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : ; ; SET TEXT AREA LD CALL LD CALL ; ; ; ; ; ; ; ; GRAPHIC AREA 20 Columns A,80H CMD SET OFFSET REGISTER (00010 10000000 000 = 1400H CG RAM START ADDRESS) CHARACTER CODE 80H LD HL, 0002H CALL DT2 LD A, OFFSET CALL CMD DISPLAY MODE (TEXT ON, GRAPHICS OFF, CURSOR OFF) LD CALL ; ; ; HL, 0014H DT2 A, GRAREA CMD MODE SET (OR MODE, Internal Character Generator MODE) LD CALL ; ; ; ; TEXT AREA 20 Columns SET GRAPHIC AREA LD CALL LD CALL ; ; ; HL, 0014H DT2 A, TXAREA CMD A, 94H CMD WRITE TEXT BLANK CODE LD CALL LD CALL HL, 0000H DT2 A, ADPSET CMD ; SET Address Pointer 0000H ; (TEXT HOME ADDRESS) LD A, AWRON ; SET DATA AUTO WRITE 39 2007-05-15 T6963CFG 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : CALL CMD ; LD BC, 00A0H ; 20 Columns × 8Lines (160 = A0H) LD CALL A, 00H ADT ; WRITE DATA 00H ; (WRITE BLANK CODE) DEC LD OR JR BC A, B C NZ, TXCR LD CALL A, AWROFF CMD TXCR: ; ; ; ; AUTO RESET WRITE EXTERNAL CHARACTER GENERATOR DATA LD LD CALL LD CALL DE, EXTCG HL, 1400H DT2 A, ADPSET CMD ; CG data address in Program ; CG RAM Start Address (1400H) LD CALL A, AWRON CMD ; SET DATA AUTO WRITE LD B, 40H ; 8 Character × 8 byte (64 = 40H) LD CALL INC INC DJNZ A, (DE) ADT HL DE EXCG ; WRITE DATA TO EXTERNAL RAM ; LD CALL A, AWROFF CMD ; AUTO RESET ; EXCG: ; ; ; WRITE TEXT DISPLAY DATA (INTERNAL CG) 40 2007-05-15 T6963CFG 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : LD CALL LD CALL HL, 002BH DT2 A, ADPSET CMD ; Address Pointer 3 Line, 4 Column LD CALL A, AWRON CMD ; SET DATA AUTO WRITE LD LD B, 0DH DE, TXPRT ; 13 Character LD CALL INC DJNZ A, (DE) ADT DE TXLP1 ; WRITE DATA LD CALL A, AWROFF CMD ; AUTO RESET TXLP1: ; ; ; WRITE TEXT DISPLAY DATA (EXTERNAL CG upper part) LD CALL LD CALL HL, 0057H DT2 A, ADPSET CMD ; Address Pointer 5 Line, 8 Column LD CALL A, AWRON CMD ; SET DATA AUTO WRITE LD LD B, 06H DE, EXPRT1 ; 6 Character LD CALL INC DJNZ A, (DE) ADT DE TXLP2 ; WRITE DATA LD CALL A, AWROFF CMD ; AUTO RESET TXLP2: ; 41 2007-05-15 T6963CFG 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : ; ; WRITE TEXT DISPLAY DATA (EXTERNAL CG lower part) LD CALL LD CALL HL, 006BH DT2 A, ADPSET CMD ; Address Pointer 6 Line, 8 Column LD CALL A, AWRON CMD ; SET DATA AUTO WRITE LD LD B, 06H DE, EXPRT2 ; 6 Character LD CALL INC DJNZ A, (DE) ADT DE TXLP3 ; WRITE DATA LD CALL A, AWROFF CMD ; AUTO RESET TXLP3: PEND: JP PEND ; ; Subroutine start ; ; COMMAND WRITE ROUTINE ; CMD: PUSH AF CMD1: IN A, (CMDP) AND 03H CP 03H JR NZ, CMD1 POP AF OUT (CMDP), A RET ; ; DATA WRITE (1 byte) ROUTINE ; DT1: ; PROGRAM END ; STATUS CHECK ; WRITE COMMAND 42 2007-05-15 T6963CFG 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : DT11: PUSH IN AND CP JR POP OUT RET AF A, (CMDP) 03H 03H NZ, DT11 AF (DP), A ; STATUS CHECK ; WRITE DATA ; ; DATA WRITE (2 byte) ROUTINE ; DT2: IN A, (CMDP) AND 03H CP 03H JR NZ, DT2 LD A, L OUT (DP), A DT21: IN A, (CMDP) AND 03H CP 03H JR NZ, DT21 LD OUT RET ; STATUS CHECK ; WRITE DATA (D1) ; STATUS CHECK A, H (DP), A ; WRITE DATA (D2) ; ; AUTO WRITE MODE ROUTINE ; ADT: PUSH AF ADT1: IN A, (CMDP) AND 08H CP 08H JR NZ, ADT1 POP AF OUT (DP), A RET ; ; STATUS CHECK ; WRITE DATA 43 2007-05-15 T6963CFG 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : ; Subroutine end ; ; TEXT DISPLAY CHARACTER CODE ; TXPRT: DEFB 34H, 00H, 2FH, 00H, 33H, 00H ; INTERNAL CG CODE DEFB 28H, 00H, 29H, 00H, 22H, 00H, 21H EXPRT1: DEFB 80H, 81H, 00H, 00H, 84H, 85H ; EXTERNAL CG CODE EXPRT2: DEFB 82H, 83H, 00H, 00H, 86H, 87H ; ; EXTERNAL CG FONT DATA ; EXTCG: ; ; upper / left CHARACTER CODE 80H DEFB 01H, 01H, 0FFH, 01H, 3FH, 21H, 3FH, 21H ; upper / right CHARACTER CODE 81H DEFB 00H, 00H, 0FFH, 00H, 0FCH, 04H, 0FCH, 04H ; lower/left CHARACTER CODE 82H DEFB 21H, 3FH, 05H, 0DH, 19H, 31H, 0E1H, 01H ; lower/right CHARACTER CODE 83H DEFB 04H, 0FCH, 40H, 60H, 30H, 1CH, 07H, 00H ; upper/left CHARACTER CODE 84H DEFB 08H, 08H, 0FFH, 08H, 09H, 01H, 01H, 7FH ; upper/right CHARACTER CODE 85H DEFB 10H, 10H, 0FFH, 10H, 10H, 00H, 00H, 0FCH ; lower/left CHARACTER CODE 86H DEFB 00H, 00H, 00H, 01H, 07H, 3CH, 0E7H, 00H ; lower/right CHARACTER CODE 87H DEFB 18H, 30H, 60H, 0C0H, 00H, 00H, 0E0H, 3FH ; END 44 2007-05-15 T6963CFG Display Sample 45 2007-05-15 T6963CFG Package Dimensions 46 2007-05-15 T6963CFG • About solderability, following conditions were confirmed ● Solderability (1) Use of Sn-37Pb solder Bath • solder bath temperature = 230°C • dipping time = 5 seconds • the number of times = once • use of R-type flux (2) Use of Sn-3.0Ag-0.5Cu solder Bath • solder bath temperature = 245°C • dipping time = 5 seconds • the number of times = once • use of R-type flux RESTRICTIONS ON PRODUCT USE • The information contained herein is subject to change without notice. 021023_D • TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. 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No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. 021023_C • Please use this product in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances. Toshiba assumes no liability for damage or losses occurring as a result of noncompliance with applicable laws and regulations. • The products described in this document are subject to foreign exchange and foreign trade control laws. 021023_E 47 2007-05-15