TOSHIBA TMP86FH47UG

TMP86FH47
♦
10-bit successive approximation type AD converter
•
♦
Analog input: 8 ch
16-bit timer counter: 1 ch
•
Timer, event counter, pulse width measurment, programmable pulse generator (PPG),
external-triggered timer, window modes
♦
Key-on wakeup: 4 ch
♦
Dual clock operation
•
♦
♦
Single/dual-clock mode
Nine power saving operating modes
•
STOP mode:
Oscillation stops. Battery/capacitor backup.
Port output hold/high-impedance.
•
SLOW 1, 2 mode: Low power consumption operation using low-frequency clock (32.768 kHz)
•
IDLE 0 mode:
CPU stops, and peripherals operate using high-frequency clock of timebase-timer. Release by INTTBT interrupt.
•
IDLE 1 mode:
CPU stops, and peripherals operate using high-frequency clock.
Release by interrupts.
•
IDLE 2 mode:
CPU stops, and peripherals operate using high and low frequency clock.
Release by interrupts.
•
SLEEP 0 mode:
CPU stops, and peripherals operate using low-frequency clock of timebase-timer. Release by INTTBT interrupt.
•
SLEEP 1 mode:
CPU stops, and peripherals operate using low-frequency clock.
Release by interrupts.
•
SLEEP 2 mode:
CPU stops, and peripherals operate using high and low frequency clock.
Release by interrupts.
Wide operating voltage: 4.5 to 5.5 V at 16 MHz/32.768 kHz
2.7 to 5.5 V at 8 MHz/32.768 kHz
Note: The operating voltage, the operating temperature and the operating current are different
between TMP86FH47 and TMP86C845/847/H47.
About details, please refer to electrical characteristics of each products.
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TMP86FH47
Difference Between TMP86C845 and TMP86Cx47
TMP86C847U
TMP86Cx47U
TMP86CH47U
TMP86CM47U
ROM (Byte)
8K
16 K
32 K
8K
RAM (Byte)
512
512
1K
256
I/O
TMP86C845U
35
35
QFP44 (10 × 10 mm)
QFP44 (10 × 10 mm)
Min instruction
0.25 µs (at 16 MHz)
0.5 µs (at 8 MHz)
Supply voltage
1.8 to 5.5 V at 4.2 MHz/32.768 kHz
2.7 to 5.5 V at 8.0 MHz/32.768 kHz
4.5 to 5.5 V at 16 MHz/32.768 kHz
2.7 to 5.5 V at 8.0 MHz/
32.768 kHz
Package (Body size)
16-bit timer/counter
1 ch
–
8-bit timer/counter
2 ch
2 ch
Time base timer
1 ch
1 ch
Watchdog timer
1 ch
1 ch
AD converter
Serial I/O
Key on wakeup
8 ch
Clocked synchronous: 1 ch
4 ch
–
6
4
P0, P1, P2 port
Port2, P00, P05, P06, P07,
P10, P11, P12, P15 pin
CMOS
input
P3, P4 port
Port3, Port4, P01, P02, P03,
P04, P13, P14, P16, P17 pin
RESET
Watchdog timer, Adress trap, System clock reset output
Input only
−40 to 85°C
−40 to 85°C
Warm-up counter
I/O
Circuitry
8 ch
Clocked synchronous: 1 ch, UART: 1 ch
Hysteresis
input
Operation Temp.
are difference points between TMP86C845 and TMP86Cx47.
Please refer to “Input/Output Circutry” of TMP86C847/H47/M47 and TMP86C845 for details.
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2007-08-07
34
AVDD
AVSS
P40
P41
P42
P43
P44
P45
P46
P47
35
36
37
38
39
40
41
42
43
44
(STOP/INT5) P20
(INT0) P00
(TC4/PDO4/PPG4/PWM4) P01
VAREF
1
2
3
4
5
6
7
8
9
10
11
33
32
31
30
29
28
27
26
25
24
23
P37 (AIN7/STOP5)
P36 (AIN6/STOP4)
P35 (AIN5/STOP3)
P34 (AIN4/STOP2)
P33 (AIN3)
P32 (AIN2)
P31 (AIN1)
P30 (AIN0)
P10 (PWM3/TC3/PDO3)/BOOT1 (RXD)
P11 (INT1)/BOOT2 (TXD)
P12 (INT2/TC1)
P-LQFP44-1010-0.80A
RESET
VSS
XIN
XOUT
TEST
VDD
(XTIN) P21
(XTOUT) P22
TMP86FH47
Pin Assignments (Top view)
Top view
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22
21
20
19
18
17
16
15
14
13
12
P13 (DVO)
P14 (PPG)
P15 (INT3)
P16
P17
P07 (INT4)
P06 (SCK)
P05 (SI)
P04 (SO)
P03 (TXD)
P02 (RXD)
2007-08-07
TMP86FH47
Block Diagram
Program memory
(Flash memory)
Address/data bus
TLCS-870/C
CPU
Flash memory I/F
Data memory
(RAM)
Standby control
circuit
RESET
TEST
Interrupt controller
System control
circuit
Timing generator
XIN
XOUT
Boot program
(ROM)
High
frequency
Low
frequency
Time base
timer
Clock
generator
16-bit
timer/counter
Watchdog
timer
TC1
8-bit
timer/counter
TC3
SIO
10-bit AD
converter
UART
TC4
Address/data bus
P2
P1
P4
P22 to P20
P17 to P10
P47 to P40
P0
P07 to P00
P3
P37 to P30
AVSS
AVDD
VAREF
I/O ports
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2007-08-07
TMP86FH47
Pin Function
The TMP86FH47 has MCU mode and serial PROM mode.
(1) MCU mode
In the MCU mode, the TMP86FH47 is a pin compatible with the TMP86C845/847/H47 (Make
sure to fix the TEST pin to low level).
(2) Serial PROM mode
The serial PROM mode is set by fixing TEST pin, P10 and P11 at “high” respectively when
RESET pin is fixed “low”.
After release of reset, the built-in BOOT ROM program is activated and the built-in flash
memory is rewritten by serial I/F (UART).
Pin Name
(Serial PROM mode)
Input/
Output
BOOT1/RXD
Input/Input
BOOT2/TXD
Input/Output
TEST
Input
RESET
I/O
VDD, AVDD
VSS, AVSS
VAREF
P07 to P00, P17 to P12, P22 to P20,
P37 to P30, P47 to P40
XIN
XOUT
Power supply
Pin Name
(MCU mode)
Functions
Fix “High” during reset. This pin is used as
RXD pin after releasing reset.
Fix “High” during reset. This pin is used as
TXD pin after releasing reset.
P10
P11
Fix to “High”.
Reset signal input or an internal error reset output.
5V
0V
Leave open or apply reference voltage.
Fix to “Low” or “High”.
Input
Output
Self oscillation with resonator (2 MHz, 4 MHz, 8 MHz, 16 MHz)
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2007-08-07
TMP86FH47
Operation
This section describes the functions and basic operational blocks of TMP86FH47.
The TMP86FH47 has flash memory in place of the mask ROM which is included in the
TMP86C845/847/H47. The configuration and function are the same as the TMP86C847/H47. For
TMP86C845, however, some functions have been partially changed or deleted. For the functions of
TMP86FH47 in details, see the section of TMP86C845/847/H47.
1. Operating Mode
The TMP86FH47 has MCU mode and serial PROM mode.
1.1
MCU Mode
The MCU mode is set by fixing the TEST pin to the low level.
In the MCU mode, the operation is the same as the TMP86C845/847/H47.
1.1.1
Program memory
The TMP86FH47 has a 16-Kbyte built-in flash memory (addresses C000H to FFFFH in the
MCU mode).
When using TMP86FH47 for evaluation of TMP86C845/847/H47, the program is written by the
serial PROM mode.
= #
#
!"
= Figure 1.1.1 Program Memory Area
Note: The area that is not in use should be set data to FFH.
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TMP86FH47
1.1.2
Data Memory
TMP86FH47 has a built-in 512-byte data memory (Static RAM).
1.1.3
Input/Output Circuitry
(1) Control pins
The control pins of the TMP86FH47 are the same as those of the TMP86C847/H47.
The RESET pin of TMP86C845 is not sink open-drain output (Address-trap-reset or
watchdog-timer-reset or system clock reset output).
Please refer to “Difference between TMP86C845 are TMP86Cx47” for details.
(2) I/O ports
The I/O circuitries of TMP86FH47 I/O ports are the same as the those of TMP86C847/H47.
The I/O circuitries of TMP86C845 are different from the those of TMP86FH47.
Please refer to “Difference between TMP86C845 and TMP86Cx47” for details.
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2007-08-07
TMP86FH47
2. Serial PROM Mode
2.1
Outline
The TMP86FH47 has a 2-Kbyte BOOT ROM for programming to flash memory. This BOOT ROM
is a mask ROM that contains a program to write the flash memory on-board. The BOOT ROM is
available in a serial PROM mode and it is controlled by TEST pin and RESET pin and 2 I/O pins,
and is communicated with UART. There are four operation modes in a serial PROM mode: flash
memory writing mode, RAM loader mode, flash memory SUM output mode and product
discrimination code output mode. Operating area of serial PROM mode differs from that of MCU
mode. The operating area of serial PROM mode shows in Table 2.1.1.
Table 2.1.1 Operating Area of Serial PROM Mode
2.2
Parameter
Symbol
Min
Max
Unit
Operating voltage
VDD
4.5
5.5
V
High frequency
fc
2, 4, 8, 16
MHz
Temperature
Topr
25 ± 5
°C
Memory Mapping
The BOOT ROM is mapped in address F800H to FFFFH. The BOOT ROM can’t be accessed in
MCU mode. The Figure 2.2.1 shows a memory mapping.
0000H
SFR
003FH
0040H
RAM
0000H
64 bytes
SFR
512 bytes
RAM
023FH
003FH
0040H
64 bytes
512 bytes
023FH
C000H
Flash
memory
16384 bytes
F800H
2048 bytes
BOOT ROM
FFFFH
FFFFH
MCU mode
Serial PROM mode
Figure 2.2.1 Memory Address Maps
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2007-08-07
TMP86FH47
2.3
Serial PROM Mode Setting
2.3.1
Serial PROM Mode Control Pins
To execute on-board programming, start the TMP86FH47 in serial PROM mode. Setting of a
serial PROM mode is shown in Table 2.3.1.
Table 2.3.1 Serial PROM Mode Setting
Pin
Setting
TEST pin
High
BOOT1 (RXD)
(Note)
High
BOOT2 (TXD)
(Note)
High
RESET pin
Note: BOOT1 is RXD pin and BOOT2 is TXD pin during a serial PROM mode.
2.3.2
Pin Function
In the serial PROM mode, TXD (P11) and RXD (P10) pins are used as a serial interface pin.
Therefore, if the programming is executed on-board after mounting, these pins should be released
from the other devices for communication in serial PROM mode.
Pin Name
(Serial PROM mode)
Input/
Output
Functions
BOOT1/RXD
Input/Input
Fix “High” during reset. This pin is used as
RXD pin after releasing reset.
P10
BOOT2/TXD
Input/Output
Fix “High” during reset. This pin is used as
TXD pin after releasing reset.
P11
TEST
Input
RESET
I/O
VDD, AVDD
VSS, AVSS
Fix to “High”.
Reset signal input or an internal error reset output.
5V
Power supply
0V
VAREF
Leave open or apply reference voltage.
P07 to P00, P17 to P12, P22 to P20,
P37 to P30, P47 to P40
Fix to “low” or “high”.
XIN
XOUT
Pin Name
(MCU mode)
Input
Output
Self oscillation with resonator (2 MHz, 4 MHz, 8 MHz, 16 MHz)
Note: When the device is used as on-board writing and other parts are already mounted in place, be
careful not to affect these communication control pins.
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TMP86FH47
To set a serial PROM mode, connect device pins as shown in Figure 2.3.1.
TMP86FH47
VDD(4.5 V to 5.5 V)
VDD
AVDD
TEST
XIN
P10
BOOT1/RXD
P11
BOOT2/TXD
RESET
VAREF
XOUT
OPEN or analog reference voltage.
AVSS
VSS
: Pull up
Figure 2.3.1 Serial PROM Mode Port Setting
2.3.3
Activating Serial PROM Mode
The following is a procedure of setting of serial PROM mode. Figure 2.3.2 shows a serial PROM
mode timing.
(1) Turn on the power to the VDD pin.
(2) Set the RESET to low level.
(3) Set the TEST, BOOT1 and BOOT2 pin to high level.
(4) Wait until the power supply and clock sufficiently stabilize.
(5) Release the RESET (Set to high level).
(6) Input a matching data (5AH) to BOOT1/RXD pin after waiting for setup sequence. For details
of the setup timing, refer to 2.14 “UART Timing”.
VDD
TEST (Input)
RESET (Input)
Program
Indeterminate
Reset mode
BOOT1 (Input)/
RXD (Input)
Serial PROM mode
Setup time for serial PROM mode (Rxsup)
Fixed to high level by pull up
Matching
data input
BOOT2 (Input)/
TXD (Output)
Figure 2.3.2 Serial PROM Mode Timing
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TMP86FH47
2.4
Interface Specifications for UART
The following shows the UART communication format used in serial PROM mode.
Before on-board programming can be executed, the communication format on the external
controller side must also be setup in the same way as for this product.
Note that although the default baud rate is 9,600 bps, it can be changed to other values as shown
in Table 2.4.1. The Table 2.4.2 shows an operating frequency and baud rate in serial PROM mode.
Except frequency which is not described in Table 2.4.2 can not use in serial PROM mode.
Baud rate (Default): 9,600 bps
Data length: 8 bits
Parity addition: None
Stop bit length: 1 bit
Table 2.4.1 Baud Rate Modification Data
Baud rate modification data
Baud rate (bps)
04H
05H
07H
0AH
18H
28H
76800
62500
38400
31250
19200
9600
Table 2.4.2 Operating Frequency and Baud Rate in Serial PROM Mode
Reference Baud
76800
Rate (Baud)
Baud Rate
04H
Modification Data
Reference
Frequency
(bps) (%)
(MHz)
2
4
8
16
Note:
2.5
–
–
–
76923
–
–
–
+0.16
62500
38400
31250
19200
9600
05H
07H
0AH
18H
28H
(bps)
(%)
(bps)
(%)
(bps)
(%)
(bps)
–
–
62500
62500
–
–
0.00
0.00
–
–
38462
38462
–
–
+0.16
+0.16
–
31250
31250
31250
–
0.00
0.00
0.00
–
19231
19231
19231
(%)
(bps)
(%)
–
9615
9615
9615
9615
+0.16
+0.16
+0.16
+0.16
+0.16
+0.16
+0.16
“Reference Frequency” shows the high-frequency area supported in serial PROM mode.
Except the above frequency can not be supported in serial PROM mode.
Command
There are five commands in serial PROM mode. After reset release, the TMP86FH47 waits a
matching data (5AH).
Table 2.5.1 Command in Serial PROM Mode
Command Data
Operation Mode
Remarks
5AH
30H
60H
Setup
Flash memory writing
RAM loader
90H
Flash memory SUM output
C0H
Product discrimination code output
Matching data. Always start with this command after reset release.
Writing to area from C000H to FFFFH is enable.
Writing to area from 0050H to 0230H is enable.
The checksum of entire flash memory area (from C000H to FFFFH)
is output in order of the upper byte and the lower byte.
Product discrimination code, that is expressed by 13 bytes data, is
output.
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TMP86FH47
2.6
Operation Mode
There are four operating modes in serial PROM mode: Flash memory writing mode, RAM loader
mode, flash memory SUM output mode and product discrimination code output mode. For details
about these modes, refer to (1) Flash memory writing mode through (4) Product discrimination code
output mode.
(1) Flash memory writing mode
The data are written to the specified flash memory addresses. The controller should send the
write data in the Intel Hex format (Binary). For details of writing data format, refer to 2.7
“Flash Memory Writing Data Format”.
If no errors are encountered till the end record, the SUM of 16 Kbytes of flash memory is
calculated and the result is returned to the controller.
To execute the flash memory writing mode, the TMP86FH47 checks the passwords except a
blank product. If the passwords did not match, the program is not executed.
(2) RAM loader mode
The RAM loader transfers the data into the internal RAM that has been sent from the
controller in Intel Hex format. When the transfer has terminated normally, the RAM loader
calculates the SUM and sends the result to the controller before it starts executing the user
program. After sending of SUM, the program jumps to the start address of RAM in which the
first transferred data has been written. This RAM loader function provides the user's own way
to control on-board programming.
To execute the RAM loader mode, the TMP86FH47 checks the passwords except a blank
product. If the passwords did not match, the program is not executed.
(3) Flash memory SUM output mode
The SUM of 16 Kbytes of flash memory is calculated and the result is returned to the
controller.
The BOOT ROM does not support the reading function of the flash memory. Instead, it has
this SUM command to use. By reading the SUM, it is possible to manage Revisions of
application programs.
(4) Product discrimination code output mode
The product discrimination code is output as a 13-byte data, that includes the start address
and the end address of ROM. (In case of TMP86FH47, the start address is C000H and the end
address is FFFFH.) Therefore, the controller can recognize the device information by using this
function.
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TMP86FH47
2.6.1
Flash Memory Writing Mode (Operation command: 30H)
Table 2.6.1 shows flash memory writing mode process.
Table 2.6.1 Flash Memory Writing Mode Process
Transfer Data from
External Controller to
TMP86FH47
Number of
Bytes
Transferred
BOOT
ROM
Baud Rate
1st byte
2nd byte
Matching data (5AH)
−
9600 bps
9600 bps
3rd byte
9600 bps
4th byte
Baud rate modification data
(See Table 2.4.1)
−
5th byte
6th byte
Operation command data (30H)
−
Changed new baud rate
Changed new baud rate
7th byte
8th byte
Address 15 to 08 in which to
store Password count (Note 4)
Changed new baud rate
Changed new baud rate
9th byte
10th byte
Address 07 to 00 in which to
store Password count (Note 4)
Changed new baud rate
Changed new baud rate
11th byte
12th byte
Address 15 to 08 in which to
start Password comparison
(Note 4)
Address 07 to 00 in which to
start Password comparison
(Note 4)
Password string (Note 5)
Changed new baud rate
Changed new baud rate
Changed new baud rate
−
Changed new baud rate
m'th + 1 byte
:
n'th − 2 byte
n'th − 1 byte
Extended Intel format (binary)
(Note 2, 6)
Changed new baud rate
−
Changed new baud rate
n'th byte
−
Changed new baud rate
n'th + 1 byte
(Wait for the next operation)
(Command data)
Changed new baud rate
13th byte
14th byte
15th byte
:
m'th byte
9600 bps
Changed new baud rate
Changed new baud rate
Transfer Data from
TMP86FH47 to External
Controller
− (Baud rate auto set)
OK: Echo back data (5AH)
Error: Nothing transmitted
−
OK: Echo back data
Error: A1H × 3, A3H × 3, 62H × 3
(Note 1)
−
OK: Echo back data (30H)
Error: A1H × 3, A3H × 3, 63H × 3
(Note 1)
−
OK: Nothing transmitted
Error: Nothing transmitted
−
OK: Nothing transmitted
Error: Nothing transmitted
−
OK: Nothing transmitted
Error: Nothing transmitted
−
OK: Nothing transmitted
Error: Nothing transmitted
−
OK: Nothing transmitted
Error: Nothing transmitted
−
OK: SUM (High) (Note 3)
Error: Nothing transmitted
OK: SUM (Low) (Note 3)
Error: Nothing transmitted
−
Note 1: “xxH × 3” denotes that operation stops after sending 3 bytes of xxH. For details, refer to 2.8
“Error Code”.
Note 2: Refer to 2.10 “Intel Hex Format (Binary)”.
Note 3: Refer to 2.9 “Checksum (SUM)”.
Note 4: Refer to 2.11 “Passwords”.
Note 5: If all data of vector area are “00H” or “FFH”, the passwords comparison is not executed
because the device is considered as blank product. However, it is necessary to specify the
password count storage addresses and the password comparison start address even though
it is a blank product. If a password error occurs, the UART function of TMP86FH47 stops
without returning error code to the controller. Therefore, when a password error occurs, the
TMP86FH47 should be reset by RESET pin input.
Note 6: The time between data records needs over 1 ms.
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TMP86FH47
Description of flash memory writing mode
1.
The receive data in the 1st byte is the matching data. When the boot program starts in serial
PROM mode, TMP86FH47 (Mentioned as “device” hereafter) waits for the matching data
(5AH) to receive. Upon receiving the matching data, it automatically adjusts the UART’s
initial baud rate to 9,600bps.
2.
When the device has received the matching data, the device transmits the data “5AH” as an
echo back to the controller. If the device can not receive the matching data, the device does not
transmit the echo back data and waits for the matching data again with changing baud rate.
Therefore, the controller should send the matching data continuously until the device
transmits the echo back data.
3.
The receive data in the 3rd byte is the baud rate modification data. The six kinds of baud rate
modification data shown in Table 2.4.1 are available. Even if baud rate changing is no need,
be sure to send the initial baud rate data (28H: 9,600 bps). The changing of baud rate is
executed after transmitting the echo back data.
4.
When the 3rd byte data is one of the baud rate modification data corresponding to the device's
operating frequency, the device sends the echo back data which is the same as received baud
rate modification data. Then the baud rate is changed. If the 3rd byte data does not
correspond to the baud rate modification data, the device stops UART function after sending
3 bytes of baud rate modification error code: (62H).
5.
The receive data in the 5th byte is the command data (30H) to write the flash memory.
6.
When the 5th byte is one of the operation command data shown in Table 2.5.1, the device
sends the echo back data which is the same as received operation command data (in this case,
30H). If the 5th byte data does not correspond to the operation command data, the device
stops UART function after sending 3 bytes of operation command error code: (63H).
7.
The 7th byte is used as an upper bit (Bit15 to bit8) of the password count storage address.
When the receiving is executed correctly (No error), the device does not send any data. If the
receiving error or password error occur, the device does not send any data and stops UART
function.
8.
The 9th byte is used as a lower bit (Bit7 to bit0) of the password count storage address. When
the receiving is executed correctly (No error), the device does not send any data. If the
receiving error or password error occur, the device does not send any data and stops UART
function.
9.
The 11th byte is used as an upper bit (Bit15 to bit8) of the password comparison start
address. When the receiving is executed correctly (No error), the device does not send any
data. If the receiving error or password error occur, the device does not send any data and
stops UART function.
10. The 13th byte is used as a lower bit (Bit7 to bit0) of the password comparison start address.
When the receiving is executed correctly (No error), the device does not send any data. If the
receiving error or password error occur, the device does not send any data and stops UART
function.
11. The 15th through the m’th bytes are the password data. The number of passwords is the data
(N) indicated by the password count storage address. The password data are compared for N
entries beginning with the password comparison start address. The controller should send N
bytes of password data to the device. If the passwords do not match, the device stops UART
function without returning error code to the controller. If the data of vector addresses (FFE0H
to FFFFH) are all “FFH”, the comparison of passwords is not executed because the device is
considered as a blank product.
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TMP86FH47
12. The receive data in the m’th + 1 through n’th − 2 byte are received as binary data in Intel Hex
format. No received data are echoed back to the controller. The data which is not the start
mark (3AH for “:”) in Intel Hex format is ignored and does not send an error code to the
controller until the device receives the start mark. After receiving the start mark, the device
receives the data record, that consists of length of data, address, record type, writing data and
checksum. After receiving the checksum of data record, the device waits the start mark data
(3AH) again. The data of data record is temporarily stored to RAM and then, is written to
specified flash memory by page (32 bytes) writing. For details of an organization of flash
memory, refer to 2. “Serial PROM Mode”. Since after receiving an end record, the device starts
to calculate the SUM, the controller should wait the SUM after sending the end record. If
receive error or Intel Hex format error occurs, the device stops UART function without
returning error code to the controller.
13. The n’th − 1 and the n’th bytes are the SUM value that is sent to the controller in order of the
upper byte and the lower byte. For details on how to calculate the SUM, refer to 2.9
“Checksum (SUM)”. The SUM calculation is performed after detecting the end record, but the
calculation is not executed when receive error or Intel Hex format error has occurred. The
time required to calculate the SUM of the 16 Kbytes of Flash memory area is approximately
100 ms at fc = 16 MHz. After the SUM calculation, the device sends the SUM data to the
controller. After sending the end record, the controller can judge that the transmission has
been terminated correctly by receiving the checksum.
14. After sending the SUM, the device waits for the next operation command data.
86FH47-16
2007-08-07
TMP86FH47
2.6.2
RAM Loader Mode (Operation command: 60H)
Table 2.6.2 shows RAM loader mode process.
Table 2.6.2 RAM Loader Mode Process
Transfer Data from
External Controller to
TMP86FH47
Number of
Bytes
Transferred
Baud Rate
Transfer Data from
TMP86FH47 to External
Controller
1st byte
Matching data (5AH)
9600 bps
− (Baud rate auto set)
2nd byte
−
9600 bps
OK: Echo back data (5AH)
3rd byte
Baud rate modification data
9600 bps
Error: Nothing transmitted
−
4th byte
−
9600 bps
OK: Echo back data
(See Table 2.4.1)
5th byte
Operation command data (60H)
6th byte
−
7th byte
Address 15 to 08 in which to
store Password count (Note 4)
Changed new baud rate
Changed new baud rate
Address 07 to 00 in which to
store Password count (Note 4)
Changed new baud rate
Changed new baud rate
Address 15 to 08 in which to
start Password comparison
(Note 4)
Changed new baud rate
Changed new baud rate
14th byte
Address 07 to 00 in which to
start Password comparison
(Note 4)
Changed new baud rate
Changed new baud rate
15th byte
Password string (Note 5)
Changed new baud rate
m'th byte
−
Changed new baud rate
m'th + 1 byte
Extended Intel format (Binary)
Changed new baud rate
8th byte
9th byte
BOOT
ROM
10th byte
11th byte
12th byte
13th byte
:
:
n'th − 2 byte
n'th − 1 byte
RAM
Changed new baud rate
Changed new baud rate
Error:A1H × 3, A3H × 3, 62H × 3
(Note 1)
−
OK: Echo back data (60H)
Error: A1H × 3, A3H × 3, 63H × 3
(Note 1)
−
OK: Nothing transmitted
Error: Nothing transmitted
−
OK: Nothing transmitted
Error: Nothing transmitted
−
OK: Nothing transmitted
Error: Nothing transmitted
−
OK: Nothing transmitted
Error: Nothing transmitted
−
OK: Nothing transmitted
Error: Nothing transmitted
−
(Note 2)
−
Changed new baud rate
OK: SUM (High) (Note 3)
Changed new baud rate
Error: Nothing transmitted
OK: SUM (Low) (Note 3)
n'th byte
−
−
Error: Nothing transmitted
The program jumps to the start address of RAM in which the first transferred data has been written.
Note 1: “xxH × 3” denotes that operation stops after sending 3 bytes of xxH. For details, refer to 2.8
“Error Code”.
Note 2: Refer to 2.10 “Intel Hex Format (Binary)”.
Note 3: Refer to 2.9 “Checksum (SUM)”.
Note 4: Refer to 2.11 “Passwords”.
86FH47-17
2007-08-07
TMP86FH47
Note 5: If all data of vector area are “00H” or “FFH”, the passwords comparison is not executed
because the device is considered as blank product. However, it is necessary to specify the
password count storage addresses and the password comparison start address even though
it is a blank product. If a password error occurs, the UART function of TMP86FH47 stops
without returning error code to the controller. Therefore, when a password error occurs, the
TMP86FH47 should be reset by RESET pin input.
Note 6: Do not send only end record after transferring of password string. If the TMP86FH47 receives
the end record only after reception of password string, it does not operate correctly.
Description of RAM loader mode
1.
The process of the 1st byte through the 4th byte are the same as flash memory writing mode.
2.
The receive data in the 5th byte is the RAM loader command data (60H) to write the user’s
program to RAM.
3.
When the 5th byte is one of the operation command data shown in Table 2.5.1, the device
sends the echo back data which is the same as received operation command data (in this case,
60H). If the 5th byte data does not correspond to the operation command data, the device
stops UART function after sending 3 bytes of operation command error code: (63H).
4.
The process of the 7th byte through the m’th byte are the same as flash memory writing
mode.
5.
The receive data in the m’th + 1 through n’th − 2byte are received as binary data in Intel Hex
format. No received data are echoed back to the controller.
The data which is not the start mark (3AH for “:”) in Intel Hex format is ignored and does not
send an error code to the controller until the device receives the start mark. After receiving
the start mark, the device receives the data record, that consists of length of data, address,
record type, writing data and checksum. After receiving the checksum of data record, the
device waits the start mark data (3AH) again. The data of data record is written to specified
RAM by the receiving data. Since after receiving an end record, the device starts to calculate
the SUM, the controller should wait the SUM after sending the end record. If receive error or
Intel Hex format error occurs, the UART function of TMP86FH47 stops without returning
error code to the controller.
6.
The n’th − 1 and the n’th bytes are the SUM value that is sent to the controller in order of the
upper byte and the lower byte. For details on how to calculate the SUM, refer to 2.9
“Checksum (SUM)”. The SUM calculation is performed after detecting the end record, but the
calculation is not executed when receive error or Intel Hex format error has occurred.
The SUM is calculated by the data written to RAM, but the length of data, address, record
type and checksum in Intel Hex format are not included in SUM.
7.
The boot program jumps to the first address that is received as data in Intel Hex format after
sending the SUM to the controller.
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2007-08-07
TMP86FH47
2.6.3
Flash Memory Memory SUM Output Mode (Operation command: 90H)
Table 2.6.3 shows flash memory SUM output mode process.
Table 2.6.3 Flash Memory Memory SUM Output Process
Transfer Data from
External Controller to
TMP86FH47
Number of
Bytes
Transferred
1st byte
2nd byte
Matching data (5AH)
−
9600 bps
9600 bps
3rd byte
Baud rate modification data
(See Table 2.4.1)
−
9600 bps
5th byte
6th byte
Operation command data
(90H)
−
Changed new baud rate
Changed new baud rate
7th byte
−
Changed new baud rate
8th byte
−
Changed new baud rate
9th byte
(Wait for the next operation)
(Command data)
Changed new baud rate
4th byte
BOOT
ROM
Baud Rate
9600 bps
Transfer Data from
TMP86FH47 to External
Controller
− (Baud rate auto set)
OK: Echo back data (5AH)
Error: Nothing transmitted
−
OK: Echo back data
Error: A1H × 3, A3H × 3, 62H × 3
(Note 1)
−
OK: Echo back data (90H)
Error: A1H × 3, A3H × 3, 63H × 3
(Note 1)
OK: SUM (High) (Note 2)
Error: Nothing transmitted
OK: SUM (Low) (Note 2)
Error: Nothing transmitted
−
Note 1: “xxH × 3” denotes that operation stops after sending 3 bytes of xxH. For details, refer to 2.8
“Error Code”.
Note 2: Refer to 2.9 “Checksum (SUM)”
Description of flash memory SUM output mode
1.
The process of the 1st byte through the 4th byte are the same as flash memory writing mode.
2.
The receive data in the 5th byte is the flash memory SUM command data (90H) to calculate
the entire flash memory.
3.
When the 5th byte is one of the operation command data shown in Table 2.5.1, the device
sends the echo back data which is the same as received operation command data (in this case,
90H). If the 5th byte data does not correspond to the operation command data, the device
stops UART function after sending 3 bytes of operation command error code: (63H).
4.
The 7th and the 8th bytes are the SUM value that is sent to the controller in order of the
upper byte and the lower byte. For details on how to calculate the SUM, refer to 2.9
“Checksum (SUM)”.
5.
After sending the SUM, the device waits for the next operation command data.
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2007-08-07
TMP86FH47
2.6.4
Product Discrimination Code Output Mode (Operation command: C0H)
Table 2.6.4 shows product discrimination code output mode process.
Table 2.6.4 Product Discrimination Code Output Process
Number of
Bytes
Transferred
Baud Rate
1st byte
2nd byte
Matching data (5AH)
−
9600 bps
9600 bps
3rd byte
Baud rate modification data
(See Table 2.4.1)
−
9600 bps
4th byte
5th byte
6th byte
BOOT
ROM
Transfer Data from
External Controller to
TMP86FH47
Operation
(C0H)
−
command
9600 bps
data
Changed new baud rate
Changed new baud rate
7th byte
8th byte
Changed new baud rate
Changed new baud rate
9th byte
10th byte
11th byte
12th byte
13th byte
14th byte
Changed new baud rate
Changed new baud rate
Changed new baud rate
Changed new baud rate
Changed new baud rate
Changed new baud rate
15th byte
Changed new baud rate
16th byte
Changed new baud rate
17th byte
Changed new baud rate
18th byte
Changed new baud rate
19th byte
Changed new baud rate
20th byte
(Wait for the next operation)
(Command data)
Changed new baud rate
Transfer Data from
TMP86FH47 to External
Controller
− (Baud rate auto set)
OK: Echo back data (5AH)
Error: Nothing transmitted
−
OK: Echo back data
Error: A1H × 3, A3H × 3, 62H × 3
(Note 1)
−
OK: Echo back data (C0H)
Error: A1H × 3, A3H × 3, 63H × 3
(Note 1)
3AH
Start mark
0AH
The number of transfer
data (from 9th to 18th byte)
02H
Length of address (2 bytes)
03H
Reserved data
00H
Reserved data
00H
Reserved data
00H
Reserved data
01H
The number of ROM block
(1 block)
C0H
First address of ROM
(Upper 8 bits)
00H
First address of ROM
(Lower 8 bits)
FFH
End address of ROM
(Upper 8 bits)
FFH
End address of ROM
(Lower 8 bits)
3CH
Checksum of transferred
data (from 9th to 18th byte)
−
Note: “xxH × 3” denotes that operation stops after sending 3 bytes of xxH. For details, refer to 2.8
“Error Code”.
Description of product discrimination code output mode
1.
The process of the 1st byte through the 4th byte are the same as flash memory writing mode.
2.
The receive data in the 5th byte is the product discrimination code output command data
(C0H).
3.
When the 5th byte is one of the operation command data shown in Table 2.5.1, the device
sends the echo back data which is the same as received operation command data (in this case,
C0H). If the 5th byte data does not correspond to the operation command data, the device
stops UART function after sending 3 bytes of operation command error code: (63H).
4.
The 9th and the 19th bytes are the product discrimination code. For details, refer to 2.12
“Product Discrimination Code”.
5.
After sending the SUM, the device waits for the next operation command data.
86FH47-20
2007-08-07
TMP86FH47
2.7
Flash Memory Writing Data Format
Flash memory area of TMP86FH47 consists of 512 pages and one page size is 32 bytes.
Writing to flash memory is executed by page writing. Therefore, it is necessary to send 32 bytes
data (for one page) even though only a few bytes data are written. Figure 2.7.1 shows an
organization of flash memory area. When the controller sends the writing data to the device, be
sure to keep the format described below.
1.
The address of data after receiving the flash memory writing command should be the first
address of page. For example, in case of page 2, the first address should be C040H.
2.
If the last data’s address of data record is not end address of page, the address of the next data
record should be the address + 1 and the last data’s address must point to the last address of
this page. For example, if the last data’s address is C00FH (Page0), the address of the next data
record should be C010H (Page0) and the address of the last data should be C01FH (Page0).
3.
The last data’s address of data record immediately before sending the end record should be the
last address of page. For example, in case of page 1, the last data’s address of data record should
be C03FH.
Note: Do not write only the vector area (FFF0H to FFFFH) when all data of flash memory are the
same data. If the vector area is only written, the next operation can not be executed because of
password error.
Address
0
C000H
C010H
C020H
F
F
C030H
C040H
C050H
F
C060H
C070H
F
C080H
C090H
F
C0A0H
C0B0H
F
C0C0H
:
:
FF70H
F
FF80H
FF90H
F
FFA0H
FFB0H
F
FFC0H
FFD0H
F
FFE0H
FFF0H
F
1
2
3
4
5
6
7
8
9
A
B
C
D
Page0
Page1
Page2
Page3
Page4
Page5
E
F
E
E
E
E
E
E
E
Page508
Page509
Page510
Page511
E
E
E
E
Note: “F” shows the first address of each page and “E” shows the last address of each page.
Figure 2.7.1 Organization of Flash Memory Area
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2007-08-07
TMP86FH47
2.8
Error Code
When the device detects an error, the error codes are sent to the controller.
Table 2.8.1 Error Code
Transmit Data
62H, 62H, 62H
63H, 63H, 63H
A1H, A1H, A1H
A3H, A3H, A3H
2.9
Meaning of Transmit Data
Baud rate modification error occurred.
Operating command error occurred.
Framing error in received data occurred.
Overrun error in received data occurred.
Checksum (SUM)
(1) Calculation method
SUM consists of byte + byte.... + byte, the checksum of which is returned in word as the
result.
Namely, data is read out in byte and checksum of which is calculated, with the result
returned in word.
Example:
A1H
B2H
C3H
D4H
If the data to be calculated consists of the four bytes shown to the
left, SUM of the data is
A1H + B2H + C3H + D4H = 02EAH
= 02H
SUM (HIGH)
SUM (LOW)
= EAH
The SUM returned when executing the flash memory write command, RAM
loader command, or flash memory SUM command is calculated in the manner
shown above.
(2) Calculation data
The data from which SUM is calculated are listed in Table 2.9.1 below.
Table 2.9.1 Checksum Calculation Data
Operating Mode
Calculation Data
Remarks
Even when written to part of the flash memory area,
Flash memory writing mode
data in the entire memory area (16 Kbytes) is
Data in the entire area (16 Kbytes) of flash
calculated.
memory
Flash memory Checksum output
The length of data, address, record type and
mode
checksum in Intel Hex format are not included in SUM.
The length of data, address, record type and
RAM loader mode
Data written to RAM
checksum in Intel Hex format are not included in SUM.
Product discrimination code out- Checksum of transferred data (from 9th to For details, refer to “2.6.4 Product Discrimination
put mode
18th byte)
Code Output Mode”.
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2007-08-07
TMP86FH47
2.10 Intel Hex Format (Binary)
1.
After receiving the SUM of a record, the device waits for the start mark data (3AH for “:”) of the
next record. Therefore, the device ignores the data, which does not match the start mark data
after receiving the SUM of a record.
2.
Make sure that once the controller program has finished sending the SUM of the end record, it
does not send anything and waits for two bytes of data to be received (Upper and lower bytes of
SUM). This is because after receiving the SUM of the end record, the boot program calculates
the SUM and returns the calculated SUM in two bytes to the controller.
3.
If a receive error or Intel Hex format error occurs, the UART function of TMP86FH47 stops
without returning error code to the controller. In the following cases, an Intel Hex format error
occurs:
•
When the record type is not 00H, 01H, or 02H
•
When a SUM error occurred
•
When the data length of an extended record (Type = 02H) is not 02H
•
When the address of an extended record (Type = 02H) is larger than 1000H and after that,
receives the data record
•
When the data length of the end record (Type = 01H) is not 00H
2.11 Passwords
The area in which passwords can be specified is located at addresses C000H to FF9FH. The
vector area (from FFA0H to FFFFH) can not be specified as passwords area. The device compares
the stored passwords with the passwords, which are received from the controller. If all data of
vector area are “00H” or “FFH”, the passwords comparison is not executed because the device is
considered as blank product. It is necessary to specify the password count storage addresses and
the password comparison start address even though it is a blank product.
Table 2.11.1 Password Setting in the Blank Product and Non Blank Product
Password
Blank Product(Note 1)
Non Blank Product
PNSA
(Password count storage addresses)
PCSA
(Password comparison start address)
N
(Password count)
Setting of password
C000H ≤ PNSA ≤ FF9FH
C000H ≤ PNSA ≤ FF9FH
C000H ≤ PCSA ≤ FF9FH
C000H ≤ PCSA ≤ FFA0−N
*
8≤N
No need
Need (Note 2)
Note 1: When all data of addresses from FFE0H to FFFFH area are “00H” or “FFH”, the device is
judged as blank product.
Note 2: The same three or more bytes consecutive data can not be used as password.
When the password includes the same consecutive data (three or more bytes), the password
error occurs. If the password error occured, the UART function of device stops without
returning error code.
Note 3: *: Don’t care.
Note 4: When the password doesn’t match the above condition, the password error occurs. If the
password error occured, the UART function of device stops without returning error code.
Note 5: In case of the blank product, the device receives Intel Hex Format immediately after receiving
PCSA without receiving password strings. In this time, because the device ignores the data
86FH47-23
2007-08-07
TMP86FH47
except the start mark data (3AH for “:”) as Intel Hex Format data, even if external controller
transmitted dummy password strings, process operates correctly. However, if the dummy
password strings contain data “3AH”, the device detects it as start mark data mistakenly, and
device stops process without returning error doce. Therefore, if these process becomes
issue, the external controller should not transmit the dummy password strings.
UART
RXD pin
F0H 12H F1H 07H 01H 02H 03H 04H 05H 06H 07H
PNSA
08H
Password string
PCSA
Flash memory
F012H
Example)
PNSA = F012H
PCSA = F107H
Password string = 01H,02H,03H,04H,05H,
06H,07H,08H
08H
F107H
01H
F108H
02H
F109H
03H
F10AH
04H
F10BH
05H
F10CH
06H
F10DH
07H
F10EH
08H
"08H" is treated
as the number of
password.
Comparison
8 bytes
Figure 2.11.1Password Comparison Example
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2007-08-07
TMP86FH47
3.
Password string
A password string sent from the controller is compared with the specified data in the flash
memory. If the password string does not match the specified data in the flash memory, a
password error occurs and the TMP86FH47 stops operating.
4.
Handling of password error
If a password error occurs, the UART function of TMP86FH47 stops without returning error
code to the controller. Therefore, when a password error occurs, the TMP86FH47 should be
reset by RESET pin input.
2.12 Product Discrimination Code
The product discrimination code is a 13-byte data, that includes the start address and the end
address of ROM. Table 2.12.1 shows the product discrimination code format.
Table 2.12.1 Product Discrimination Code Format
Data
The Meaning of Data
In Case of TMP86FH47
1st
2nd
3rd
4th
5th
6th
7th
8th
9th
10th
11th
12th
13th
Start mark (3AH)
The number of transfer data (from 3rd to 13th byte)
Length of address
Reserved data
Reserved data
Reserved data
Reserved data
The number of ROM block
The upper byte of the first address of ROM
The lower byte of the first address of ROM
The upper byte of the end address of ROM
The lower byte of the end address of ROM
Checksum of transferred data (from 3rd to 12th byte)
3AH
0AH
02H
03H
00H
00H
00H
01H
C0H (Depends on the product)
00H (Depends on the product)
FFH (Depends on the product)
FFH (Depends on the product)
3CH (Depends on the product)
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2007-08-07
TMP86FH47
2.14 UART Timing
Table 2.14.1 UART Timing-1 (VDD = 4.5 V to 5.5 V, fc = 2 MHz, 4 MHz, 8 MHz, 16 MHz, Topr = 20 to 30°C)
Parameter
Time from the reception of a matching data until the
output of an echo back
Time from the reception of a baud rate modification
data until the output of an echo back
Time from the reception of an operation command until
the output of an echo back
Calculation time of checksum
Required Minimum Time
At fc = 16
At fc = 2 MHz
MHz
Symbol
The Number of
Clock (fc)
CMeb1
Approx. 600
300 µs
37.5 µs
CMeb2
Approx. 500
250 µs
31.3 µs
CMeb3
Approx. 500
250 µs
31.3 µs
CKsm
Approx.
1573000
786.5 ms
98.3 ms
Table 2.14.2 UART Timing-2 (VDD = 4.5 V to 5.5 V, fc = 2 MHz, 4 MHz, 8 MHz, 16 MHz, Topr = 20 to 30°C)
Required Minimum Time
At fc = 16
At fc = 2 MHz
MHz
Parameter
Symbol
The
Number of
Clock (fc)
Time from reset release until acceptance of start bit of RXD pin
Time between a matching data and the next matching data
Time from the echo back of matching data until the acceptance
of baud rate modification data
Time from the output of echo back of baud rate modification
data until the acceptance of an operation command
Time from the output of echo back of operation command until
the acceptance of Password count storage addresses
RXsup
CMtr1
25000
28500
12.5 ms
14.3 ms
1.56 ms
1.8 ms
CMtr2
400
200 µs
25 µs
CMtr3
500
250 µs
31.3 µs
CMtr4
2600
1.3 ms
163 µs
Table 2.14.3 UART Timing-3 (VDD = 4.5 V to 5.5 V, fc = 2 MHz, 4 MHz, 8 MHz, 16 MHz, Topr = 20 to 30°C)
Parameter
Symbol
Min.
Max.
Unit
Time from the stop bit of the previous data record to start bit of
the next data record
tSU; ST
1
−
ms
CMtr2
RXsup
RESET pin
(TMP86FH47)
(5A)
CMtr3
(28)
CMtr4
(30)
RXD pin (TMP86FH47)
(5A)
(28)
(30)
TXD pin (TMP86FH47)
CMeb1
CMeb2
(5A)
(5A)
CMeb3
(5A)
RXD pin (TMP86FH47)
TXD pin (TMP86FH47)
CMtr1
The end byte of a data record
STOP bit
START bit
RXD pin (TMP86FH47)
TXD pin (TMP86FH47)
tSU; ST
86FH47-27
2007-08-07
TMP86FH47
Electrical Characteristics
Absolute Maximum Ratings
Parameter
(VSS = 0 V)
Symbol
Pins
Rating
Supply voltage
VDD
−0.3 to 5.5
Input voltage
VIN
−0.3 to VDD + 0.3
Output voltage
VOUT
−0.3 to VDD + 0.3
Output current (Per 1 pin)
Output current (Total)
IOUT1 IOH
P1, P3, P4 ports
−1.8
IOUT2 IOL
P1, P3 ports
3.2
IOUT3 IOL
P0, P2, P4 ports
30
ΣIOUT1
P1, P3 ports
60
ΣIOUT2
P0, P2, P4 ports
PD
250
Soldering temperature (time)
Tsld
260 (10 s)
Storage temperature
Tstg
−55 to 125
−40 to 85 (MCU mode)
Topr
V
mA
80
Power dissipation [Topr = 70°C]
Operating temperature
Unit
mW
°C
20 to 30 (Serial PROM mode)
Note: The absolute maximum ratings are rated values which must not be exceeded during operation,
even for an instant. Any one of the ratings must not be exceeded. If any absolute maximum
rating is exceeded, a device may break down or its performance may be degraded, causing it
to catch fire or explode resulting in injury to the user. Thus, when designing products which
include this device, ensure that no absolute maximum rating value will ever be exceeded.
86FH47-28
2007-08-07
TMP86FH47
Recommended Operating Condition
1)
MCU mode (VSS = 0 V, Topr = −40 to 85ºC)
Parameter
Supply voltage
Symbol
Pins
VDD
Condition
fc = 16 MHz
NORMAL1, 2 mode
fc = 8 MHz
NORMAL1, 2 mode
IDLE0, 1, 2 mode
IDLE0, 1, 2 mode
Min
Max
Unit
4.5
5.5
2.7
STOP mode
Input high level
VIH1
Except hysteresis input
VIH2
Hysteresis input
VIL1
Except hysteresis input
VIL2
Hysteresis input
2)
fc
XIN, XOUT
fs
XTIN, XTOUT
V
VDD
VDD × 0.90
VDD × 0.30
VDD ≥ 4.5 V
0
VDD < 4.5 V
VIL3
Clock frequency
VDD × 0.75
VDD < 4.5 V
VIH3
Input low level
VDD × 0.70
VDD ≥ 4.5 V
VDD × 0.25
VDD × 0.10
VDD = 4.5 to 5.5 V
VDD = 2.7 to 5.5 V
1.0
16.0
8.0
MHz
30.0
34.0
kHz
Condition
Min
Max
Unit
fc = 2 MHz, 4 MHz, 8 MHz, 16 MHz
4.5
5.5
Serial PROM mode (VSS = 0 V, Topr = 20 to 30ºC)
Parameter
Supply voltage
Input high level
Input low level
Clock frequency
Symbol
Pins
VDD
VIH1
Except hysteresis input
VIH2
Hysteresis input
VIL1
Except hysteresis input
VIL2
Hysteresis input
fc
XIN, XOUT
VDD = 4.5 to 5.5 V
VDD = 4.5 to 5.5 V
VDD = 4.5 to 5.5 V
VDD × 0.70
VDD × 0.75
0
2.0, 4.0, 8.0, 16
VDD
V
VDD × 0.30
VDD × 0.25
MHz
Note: The recommended operating conditions for a device are operating conditions under which it
can be guaranteed that the device will operate as specified. If the device is used under
operating conditions other than the recommended operating conditions (Supply voltage,
operating temperature range, specified AC/DC values etc.), malfunction may occur. Thus,
when designing products which include this device, ensure that the recommended operating
conditions for the device are always adhered to.
86FH47-29
2007-08-07
TMP86FH47
(VSS = 0 V, Topr = −40 to 85°C)
DC Characteristics
Parameter
Symbol
Pins
Condition
Min
Typ.
Max
Unit
−
0.9
−
V
−
−
±2
µA
VHS
Hysteresis input
IIN1
TEST
IIN2
Sink open drain, tri-state
IIN3
RESET, STOP
RIN1
TEST pull down
−
70
−
RIN2
RESET pull up
100
200
450
Output leakage
current
ILO1
Sink open drain
VDD = 5.5 V, VOUT = 5.5 V
−
−
2
ILO2
Tri-state
VDD = 5.5 V, VOUT = 5.5/0 V
−
−
±2
Output high voltage
VOH
Tri-state
VDD = 4.5 V, lOH = −0.7 mA
4.1
−
−
Output low voltage
VOL
Except XOUT, P0, P2
and P4 ports
VDD = 4.5 V, IOL = 1.6 mA
−
−
0.4
Output low current
IOL
High current port
(P0, P2, P4 port)
VDD = 4.5 V, VOL = 1.0 V
−
20
−
−
8.0
12.5
−
6.0
9.0
−
4.5
9.0
When a program
operates on
flash memory
−
300
600
When a program
operates on
RAM
−
8.0
27
−
7.0
25
−
6.0
24
−
0.5
10
Hysteresis voltage
Input current
Input resistance
Supply current in
NORMAL 1, 2 mode
VDD = 5.5 V
VIN = 5.3 V/0.2 V
Supply current in
IDLE1, 2 mode
IDD
VDD = 3.0 V
VIN = 2.8 V/0.2 V
fs = 32.768 kHz
Supply current in
SLEEP1 mode
Supply current in
SLEEP0 mode
Supply current in
STOP mode
kΩ
µA
V
mA
fc = 16 MHz
fs = 32.768 kHz
Supply current in
IDLE0 mode
Supply current in
SLOW1 mode
VDD = 5.5 V, VIN = 5.5/0 V
VDD = 5.0 V
VIN = 5.3 V/0.2 V
µA
Note 1: Typical values show those at Topr = 25°C, VDD = 5 V.
Note 2: Input current (IIN1, IIN3); The current through pull-down or pull-up resistor is not included.
Note 3: IDD does not include IREF current.
86FH47-30
2007-08-07
TMP86FH47
AD Conversion Characteristics
Parameter
Symbol
Analog reference voltage
VAREF
Power supply voltage of analog
control circuit
AVDD
Analog reference voltage range
(Note 4)
∆VAREF
Analog input voltage
VAIN
Power supply current of analog
reference voltage
(VSS = 0 V, 4.5 V ≤ VDD ≤ 5.5 V, Topr = −40 to 85°C)
Condition
Min
Typ.
Max
AVDD − 1.0
−
AVDD
Unit
VDD
V
IREF
Non linearity error
VDD = AVDD = VAREF = 5.5 V
VSS = AVSS = 0.0 V
VDD = AVDD = 5.0 V
Zero point error
VSS = AVSS = 0.0 V
Full scale error
VAREF = 5.0 V
Total error
3.5
−
−
VSS
−
VAREF
−
0.6
1.0
−
−
±2
−
−
±2
−
−
±2
−
−
±2
mA
LSB
(VSS = 0 V, 2.7 V ≤ VDD < 4.5 V, Topr = −40 to 85°C)
Parameter
Symbol
Analog reference voltage
VAREF
Power supply voltage of analog
control circuit
AVDD
Analog reference voltage range
(Note 4)
∆VAREF
Analog input voltage
VAIN
Power supply current of analog
reference voltage
Non linearity error
Zero point error
Full scale error
Total error
Condition
Min
Typ.
Max
AVDD − 1.0
−
AVDD
Unit
VDD
V
IREF
VDD = AVDD = VAREF = 4.5V
VSS = AVSS = 0.0 V
VDD = AVDD = 2.7 V
VSS = 0.0 V
VAREF = 2.7 V
2.5
−
−
VSS
−
VAREF
−
0.5
0.8
−
−
±2
−
−
±2
−
−
±2
−
−
±2
mA
LSB
Note 1: The total error includes all errors except a quantization error, and is defined as a maximum
deviation from the ideal conversion line.
Note 2: Conversion time is different in recommended value by power supply voltage.
About conversion time, please refer to “10-Bit AD Converter”.
Note 3: Please use input voltage to AIN input pin in limit of VAREF − VSS.
When voltage of range outside is input, conversion value becomes unsettled and gives affect
to other channel conversion value.
Note 4: Analog reference voltage range: ∆VAREF = VAREF − VSS
Note 5: The AVDD pin should be fixed on the VDD level even though AD converter is not used.
86FH47-31
2007-08-07
TMP86FH47
Recommended Oscillating Conditions
XIN
C1
XOUT
C2
High-frequency oscillation
XTIN
C1
XTOUT
C2
Low-frequency oscillation
Note 1: When using the device (Oscillator) in places exposed to high electric fields such as cathoderay tubes, we recommend electrically shielding the package in order to maintain normal
operating condition.
Note 2: To ensure stable oscillation, the resonator position, load capacitance, etc. must be
appropriate. Because there factors are greatly affected by board patterns, please be sure to
evaluate operation on the board on which the device will actually be mounted.
Note 3: The product numbers and specifications of the resonators by Murata Manufacturing Co., Ltd.
are subject to change. For up-to-date information, please refer to the following URL:
http://www.murata.com
86FH47-33
2007-08-07
Point of note about solderability of lead free products (attach “G” to package name)
Test
Test condition
Note
Use of Sn-37Pb solder Bath
Pass:
Solder bath temperature = 230°C, Dipping time = 5 seconds
solderability rate until forming
The number of times = one, Use of R-type flux
≥ 95%
parameter
Solderability
Use of Sn-3.0Ag-0.5Cu solder bath
Solder bath temperature =245°C, Dipping time = 5 seconds
The number of times = one, Use of R-type flux (use of lead free)