4 Mbit (512K x8) SuperFlash EEPROM SST28SF040A / SST28VF040A Data Sheet SST28SF / VF040A4Mb (x8) Byte-Program, Small Erase Sector flash memories FEATURES: • Single Voltage Read and Write Operations – 4.5-5.5V-only for SST28SF040A – 2.7-3.6V for SST28VF040A • Superior Reliability – Endurance: 100,000 Cycles (typical) – Greater than 100 years Data Retention • Memory Organization: 512K x8 • Sector-Erase Capability: 256 Bytes per Sector • Low Power Consumption – Active Current: 15 mA (typical) for 5.0V and 10 mA (typical) for 2.7-3.6V – Standby Current: 5 µA (typical) • Fast Sector-Erase/Byte-Program Operation – Byte-Program Time: 35 µs (typical) – Sector-Erase Time: 2 ms (typical) – Complete Memory Rewrite: 20 sec (typical) • Fast Read Access Time – 4.5-5.5V-only operation: 90 and 120 ns – 2.7-3.6V operation: 150 and 200 ns • Latched Address and Data • Hardware and Software Data Protection – 7-Read-Cycle-Sequence Software Data Protection • End-of-Write Detection – Toggle Bit – Data# Polling • TTL I/O Compatibility • JEDEC Standard – Flash EEPROM Pinouts • Packages Available – 32-lead PLCC – 32-lead TSOP (8mm x 20mm) – 32-pin PDIP PRODUCT DESCRIPTION The SST28SF/VF040A are 512K x8 bit CMOS SectorErase, Byte-Program EEPROMs. The SST28SF/VF040A are manufactured using SST’s proprietary, high performance CMOS SuperFlash EEPROM Technology. The split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared with alternative approaches. The SST28SF/VF040A erase and program with a single power supply. The SST28SF/ VF040A conform to JEDEC standard pinouts for byte wide memories and are compatible with existing industry standard flash EEPROM pinouts. Featuring high performance programming, the SST28SF/ VF040A typically Byte-Program in 35 µs. The SST28SF/ VF040A typically Sector-Erase in 2 ms. Both Program and Erase times can be optimized using interface features such as Toggle bit or Data# Polling to indicate the completion of the Write cycle. To protect against an inadvertent write, the SST28SF/VF040A have on chip hardware and Software Data Protection schemes. Designed, manufactured, and tested for a wide spectrum of applications, the SST28SF/ VF040A are offered with a guaranteed sector endurance of 10,000 cycles. Data retention is rated greater than 100 years. The SST28SF/VF040A are best suited for applications that require re-programmable nonvolatile mass storage of program, configuration, or data memory. For all system appli©2003 Silicon Storage Technology, Inc. S71077-05-000 3/03 310 1 cations, the SST28SF/VF040A significantly improve performance and reliability, while lowering power consumption when compared with floppy diskettes or EPROM approaches. Flash EEPROM technology makes possible convenient and economical updating of codes and control programs on-line. The SST28SF/VF040A improve flexibility, while lowering the cost of program and configuration storage application. The functional block diagram shows the functional blocks of the SST28SF/VF040A. Figures 1, 2, and 3 show the pin assignments for the 32-lead PLCC, 32-lead TSOP, and 32pin PDIP packages. Pin descriptions and operation modes are described in Tables 2 through 5. Device Operation Commands are used to initiate the memory operation functions of the device. Commands are written to the device using standard microprocessor write sequences. A command is written by asserting WE# low while keeping CE# low. The address bus is latched on the falling edge of WE# or CE#, whichever occurs last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first. Note, during the Software Data Protection sequence the addresses are latched on the rising edge of OE# or CE#, whichever occurs first. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. SSF is a trademark of Silicon Storage Technology, Inc. These specifications are subject to change without notice. 4 Mbit SuperFlash EEPROM SST28SF040A / SST28VF040A Data Sheet Command Definitions command can be reissued as many times as necessary to complete the Chip-Erase operation. The SST28SF/ VF040A cannot be over-erased. (See Figure 8) Table 4 contains a command list and a brief summary of the commands. The following is a detailed description of the operations initiated by each command. Byte-Program Sector-Erase The Byte-Program operation is initiated by writing the setup command (10H). Once the program setup is performed, programming is executed by the next WE# pulse. See Figures 5 and 6 for timing waveforms. The address bus is latched on the falling edge of WE# or CE#, whichever occurs last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first, and begins the Program operation. The Program operation is terminated automatically by an internal timer. See Figure 16 for the programming flowchart. The Sector-Erase operation erases all bytes within a sector and is initiated by a setup command and an execute command. A sector contains 256 Bytes. This sector erasability enhances the flexibility and usefulness of the SST28SF/ VF040A, since most applications only need to change a small number of bytes or sectors, not the entire chip. The setup command is performed by writing 20H to the device. The execute command is performed by writing D0H to the device. The Erase operation begins with the rising edge of the WE# or CE#, whichever occurs first and terminates automatically by using an internal timer. The End-of-Erase can be determined using either Data# Polling, Toggle Bit, or Successive Reads detection methods. See Figure 9 for timing waveforms. The two-step sequence of a setup command followed by an execute command ensures that only the addressed byte is programmed and other bytes are not inadvertently programmed. The Byte-Program Flowchart Description The two-step sequence of a setup command followed by an execute command ensures that only memory contents within the addressed sector are erased and other sectors are not inadvertently erased. Programming data into the SST28SF/VF040A is accomplished by following the Byte-Program flowchart shown in Figure 16. The Byte-Program command sets up the byte for programming. The address bus is latched on the falling edge of WE# or CE#, whichever occurs last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first and begins the Program operation. The end of program can be detected using either the Data# Polling, Toggle bit, or Successive reads. Sector-Erase Flowchart Description Fast and reliable erasing of the memory contents within a sector is accomplished by following the Sector-Erase flowchart as shown in Figure 18. The entire procedure consists of the execution of two commands. The Sector-Erase operation will terminate after a maximum of 4 ms. A Reset command can be executed to terminate the Sector-Erase operation; however, if the Erase operation is terminated prior to the 4 ms time-out, the sector may not be fully erased. A Sector-Erase command can be reissued as many times as necessary to complete the Erase operation. The SST28SF/VF040A cannot be over-erased. Reset The Reset command is provided as a means to safely abort the Erase or Program command sequences. Following either setup command (Erase or Program) with a write of FFH will safely abort the operation. Memory contents will not be altered. After the Reset command, the device returns to the Read mode. The Reset command does not enable Software Data Protection. See Figure 7 for timing waveforms. Chip-Erase The Chip-Erase operation is initiated by a setup command (30H) and an execute command (30H). The Chip-Erase operation allows the entire array of the SST28SF/VF040A to be erased in one operation, as opposed to 2048 SectorErase operations. Using the Chip-Erase operation will minimize the time to rewrite the entire memory array. The ChipErase operation will terminate after a maximum of 20 ms. A Reset command can be executed to terminate the Erase operation; however, if the Chip-Erase operation is terminated prior to the 20 ms time-out, the chip may not be completely erased. If an erase error occurs a Chip-Erase Read The Read operation is initiated by setting CE#, and OE# to logic low and setting WE# to logic high (See Table 3). See Figure 4 for Read cycle timing waveform. The Read operation from the host retrieves data from the array. The device remains enabled for Read until another operation mode is accessed. During initial power-up, the device is in the Read mode and is Software Data protected. The device must be unprotected to execute a Write command. ©2003 Silicon Storage Technology, Inc. S71077-05-000 3/03 2 310 4 Mbit SuperFlash EEPROM SST28SF040A / SST28VF040A Data Sheet The Read operation of the SST28SF/VF040A are controlled by OE# and CE# at logic low. When CE # is high, the chip is deselected and only standby power will be consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when CE# or OE# are high. rising edge of OE# or CE#, whichever occurs first. A similar seven read sequence of 1823H, 1820H, 1822H, 0418H, 041BH, 0419H, 040AH will protect the device. Also refer to Figures 10 and 11 for the 7 Read cycle sequence Software Data Protection. The I/O pins can be in any state (i.e., high, low, or tri-state). Read-ID Write Operation Status Detection The Read-ID operation is initiated by writing a single command (90H). A read of address 0000H will output the manufacturer’s ID (BFH). A read of address 0001H will output the device ID (04H). Any other valid command will terminate this operation. The SST28SF/VF040A provide three means to detect the completion of a Write operation, in order to optimize the system Write operation. The end of a Write operation (Erase or Program) can be detected by three means: 1) monitoring the Data# Polling bit, 2) monitoring the Toggle bit, or 3) by two successive reads of the same data. These three detection mechanisms are described below. Data Protection The actual completion of the nonvolatile Write is asynchronous with the system; therefore, either a Data# Polling or Toggle Bit read may be simultaneous with the completion of the Write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with the DQ used. In order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. If both Reads are valid, then the device has completed the Write cycle, otherwise the rejection is valid. In order to protect the integrity of nonvolatile data storage, the SST28SF/VF040A provide both hardware and software features to prevent inadvertent writes to the device, for example, during system power-up or power-down. Such provisions are described below. Hardware Data Protection The SST28SF/VF040A are designed with hardware features to prevent inadvertent writes. This is done in the following ways: 1. Write Cycle Inhibit Mode: OE# low, CE#, or WE# high will inhibit the Write operation. Data# Polling (DQ7) The SST28SF/VF040A feature Data# Polling to indicate the Write operation status. During a Write operation, any attempt to read the last byte loaded during the byte-load cycle will receive the complement of the true data on DQ7. Once the Write cycle is completed, DQ7 will show true data. Note that even though DQ7 may have valid data immediately following the completion of an internal Write operation, the remaining data outputs may still be invalid: valid data on the entire data bus will appear in subsequent successive Read cycles after an interval of 1 µs. See Figure 12 for Data# Polling timing waveforms. In order for Data# Polling to function correctly, the byte being polled must be erased prior to programming. 2. Noise/Glitch Protection: A WE# pulse width of less than 5 ns will not initiate a Write cycle. 3. VDD Power Up/Down Detection: The Write operation is inhibited when VDD is less than 2.0V. 4. After power-up, the device is in the Read mode and the device is in the Software Data Protect state. Software Data Protection (SDP) The SST28SF/VF040A have software methods to further prevent inadvertent writes. In order to perform an Erase or Program operation, a two-step command sequence consisting of a set-up command followed by an execute command avoids inadvertent erasing and programming of the device. Toggle Bit (DQ6) An alternative means for determining the Write operation status is by monitoring the Toggle Bit, DQ6. During a Write operation, consecutive attempts to read data from the device will result in DQ6 toggling between logic 0 (low) and logic 1 (high). When the Write cycle is completed, the toggling will stop. The device is then ready for the next operation. See Figure 13 for Toggle Bit timing waveforms. The SST28SF/VF040A will default to Software Data Protection after power up. A sequence of seven consecutive reads at specific addresses will unprotect the device The address sequence is 1823H, 1820H, 1822H, 0418H, 041BH, 0419H, 041AH. The address bus is latched on the ©2003 Silicon Storage Technology, Inc. S71077-05-000 3/03 3 310 4 Mbit SuperFlash EEPROM SST28SF040A / SST28VF040A Data Sheet Successive Reads to use the software operation to identify the device (i.e., using the device ID). For details see Table 3 for the hardware operation and Figure 19 for the software operation. The manufacturer’s and device IDs are the same for both operations. An Alternative means for determining an end of a Write operation is by reading the same address for two consecutive data matches. Product Identification TABLE 1: PRODUCT IDENTIFICATION The Product Identification mode identifies the device as SST28SF/VF040A and the manufacturer as SST. This mode may be accessed by hardware and software operations. The hardware operation is typically used by an external programmer to identify the correct algorithm for the SST28SF/VF040A. Users may wish Manufacturer’s ID Address Data 0000H BFH 0001H 04H Device ID SST28SF/VF040A T1.1 310 FUNCTIONAL BLOCK DIAGRAM SuperFlash Memory X-Decoder A18 - A0 Address Buffer & Latches Y-Decoder CE# OE# WE# Control Logic I/O Buffers and Data Latches DQ7 - DQ0 A18 VDD 4 3 2 1 32 31 30 29 A17 A16 A6 A15 5 A12 A7 WE# 310 ILL B1.1 28 A13 A5 7 27 A8 A4 8 26 A9 A3 9 25 A11 A2 10 24 OE# A1 11 23 A10 A0 12 22 CE# DQ0 13 21 14 15 16 17 18 19 20 DQ7 DQ5 DQ4 DQ3 VSS DQ2 DQ1 32-lead PLCC Top View DQ6 A14 6 310 ILL F02.3 FIGURE 1: PIN ASSIGNMENTS FOR 32-LEAD PLCC ©2003 Silicon Storage Technology, Inc. S71077-05-000 3/03 4 310 4 Mbit SuperFlash EEPROM SST28SF040A / SST28VF040A Data Sheet A11 A9 A8 A13 A14 A17 WE# VDD A18 A16 A15 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 Standard Pinout Top View Die Up OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3 310 ILL F01.2 FIGURE 2: PIN ASSIGNMENTS FOR 32-LEAD TSOP A18 A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 1 2 3 4 5 32-pin 6 PDIP 7 8 Top View 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VDD WE# A17 A14 A13 A8 A9 A11 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 310 ILL F19.0 FIGURE 3: PIN ASSIGNMENTS FOR 32-PIN PDIP TABLE 2: PIN DESCRIPTION Symbol Pin Name Functions A18-A8 Row Address Inputs To provide memory addresses. Row addresses define a sector. A7-A0 Column Address Inputs Selects the byte within the sector DQ7-DQ0 Data Input/output To output data during Read cycles and receive input data during Write cycles. Data is internally latched during a Write cycle. The outputs are in tri-state when OE# or CE# is high. CE# Chip Enable To activate the device when CE# is low.1 OE# Output Enable To gate the data output buffers. WE# Write Enable To control the Write operations.1 VDD Power Supply To provide: VSS Ground 5.0V supply (4.5-5.5V) for SST28SF040A 2.7V supply (2.7-3.6V) for SST28VF040A T2.2 310 1. This pin has an internal pull-up resistor. ©2003 Silicon Storage Technology, Inc. S71077-05-000 3/03 5 310 4 Mbit SuperFlash EEPROM SST28SF040A / SST28VF040A Data Sheet TABLE 3: OPERATION MODES SELECTION Mode CE# OE# WE# DQ Address Read VIL VIL VIH DOUT AIN Byte-Program VIL VIH VIL DIN AIN, See Table 4 Sector-Erase VIL VIH VIL DIN AIN, See Table 4 VIH X1 X High Z X X VIL X High Z/ DOUT X Standby Write Inhibit Software Chip-Erase X X VIH High Z/ DOUT X VIL VIH VIL DIN See Table 4 VIL VIL VIH Manufacturer’s ID (BFH) Device ID (04H) A18-A1=VIL, A9=VH, A0=VIL A18-A1=VIL, A9=VH, A0=VIH Product Identification Hardware Mode Software Mode VIL VIL VIH See Table 4 SDP Enable & Disable Mode VIL VIL VIH See Table 4 Reset VIL VIH VIL See Table 4 T3.4 310 1. X can be VIL or VIH, but no other value. TABLE 4: SOFTWARE COMMAND SUMMARY Required Command Summary Cycle(s) Setup Command Cycle Type1 Addr2,3 Data4 Execute Command Cycle Type1 Addr2,3 Data4 SDP5 Sector-Erase 2 W X 20H W SA D0H N Byte-Program 2 W X 10H W PA PD N Chip-Erase6 2 W X 30H W X 30H N Reset 1 W X FFH R 7 7 Read-ID 2 W X Software Data Protect 7 R 8 Software Data Unprotect 7 R 9 90H Y Y T4.4 310 1. 2. 3. 4. 5. 6. 7. 8. 9. Type definition: W = Write, R = Read, X can be VIL or VIH, but no other value. Addr (Address) definition: SA = Sector Address = A18-A8, sector size = 256 Bytes; A7-A0 = X for this command. Addr (Address) definition: PA = Program Address = A18-A0. Data definition: PD = Program Data, H = number in hex. SDP = Software Data Protect mode using 7 Read Cycle Sequence. a) Y = the operation can be executed with protection enabled b) N = the operation cannot be executed with protection enabled The Chip-Erase function is not supported on industrial temperature parts. Address 0000H retrieves the Manufacturer’s ID of BFH and address 0001H retrieves the Device ID of 04H. Refer to Figure 11 for the 7 Read Cycle sequence for Software-Data-Protect. Refer to Figure 10 for the 7 Read Cycle sequence for Software-Data-Unprotect. TABLE 5: MEMORY ARRAY DETAIL Sector Select Byte Select A18 - A8 A7 - A0 T5.0 310 ©2003 Silicon Storage Technology, Inc. S71077-05-000 3/03 6 310 4 Mbit SuperFlash EEPROM SST28SF040A / SST28VF040A Data Sheet Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0V to VDD+2.0V Voltage on A9 Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 14.0V Package Power Dissipation Capability (Ta = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W Through Hold Lead Soldering Temperature (10 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C Surface Mount Lead Soldering Temperature (3 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240°C Output Short Circuit Current1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA 1. Outputs shorted for no more than one second. No more than one output shorted at a time. OPERATING RANGE FOR Range Ambient Temp Commercial Industrial OPERATING RANGE Commercial Industrial OF VDD 0°C to +70°C 4.5-5.5V -40°C to +85°C 4.5-5.5V FOR Range AC CONDITIONS SST28SF040A SST28VF040A Ambient Temp VDD 0°C to +70°C 2.7-3.6V -40°C to +85°C 2.7-3.6V TEST Input Rise/Fall Time . . . . . . . . . . . . . . 10 ns Output Load . . . . . . . . . . . . . . . . . . . . . 1 TTL Gate andCL = 100 pF for SST28SF040A CL = 100 pF for SST28VF040A See Figures 14 and 15 ©2003 Silicon Storage Technology, Inc. S71077-05-000 3/03 7 310 4 Mbit SuperFlash EEPROM SST28SF040A / SST28VF040A Data Sheet TABLE 6: DC OPERATING CHARACTERISTICS FOR SST28SF040A Limits Symbol Parameter IDD Power Supply Current Min Max Units Test Conditions Address input=VILT/VIHT, at f=1/TRC Min, VDD=VDD Max Read 32 mA CE#=OE#=VIL, WE#=VIH, all I/Os open Program and Erase 40 mA CE#=WE#=VIL, OE#=VIH, VDD=VDD Max ISB1 Standby VDD Current (TTL input) 3 mA CE#=VIH, VDD=VDD Max ISB2 Standby VDD Current (CMOS input) 20 µA CE#=VDD-0.3V, VDD=VDD Max ILI Input Leakage Current 1 µA VIN=GND to VDD, VDD=VDD Max ILO Output Leakage Current 10 µA VOUT=GND to VDD, VDD=VDD Max VIL Input Low Voltage VIH Input High Voltage 0.8 V VDD=VDD Min V VDD=VDD Max V IOL=2.1 mA, VDD=VDD Min V IOH=-400 µA, VDD=VDD Min 12.4 V CE#=OE#=VIL, WE#=VIH 200 µA CE#=OE#=VIL, WE#=VIH, A9=VH Max 2.0 VOL Output Low Voltage VOH Output High Voltage 2.4 0.4 VH Supervoltage for A9 11.6 IH Supervoltage Current for A9 T6.5 310 TABLE 7: DC OPERATING CHARACTERISTICS FOR SST28VF040A Limits Symbol Parameter IDD Power Supply Current Min Max Units Test Conditions Address input=VILT/VIHT, at f=1/TRC Min, VDD=VDD Max Read 10 mA CE#=OE#=VIL, WE#=VIH, all I/Os open Program and Erase 25 mA CE#=WE#=VIL, OE#=VIH, VDD=VDD Max ISB2 Standby VDD Current (CMOS input) 20 µA CE#=OE#=WE#=VDD-0.3V, VDD=VDD Max ILI Input Leakage Current 1 µA VIN=GND to VDD, VDD=VDD Max ILO Output Leakage Current 10 µA VOUT=GND to VDD, VDD=VDD Max VIL Input Low Voltage VIH Input High Voltage 0.8 V VDD=VDD Min V VDD=VDD Max V IOL=100 µA, VDD=VDD Min V IOH=-100 µA, VDD=VDD Min 12.4 V CE#=OE#=VIL, WE#=VIH 200 µA CE#=OE#=VIL, WE#=VIH, A9=VH Max 2.0 VOL Output Low Voltage VOH Output High Voltage 2.4 0.4 VH Supervoltage for A9 11.6 IH Supervoltage Current for A9 T7.5 310 ©2003 Silicon Storage Technology, Inc. S71077-05-000 3/03 8 310 4 Mbit SuperFlash EEPROM SST28SF040A / SST28VF040A Data Sheet TABLE 8: RECOMMENDED SYSTEM POWER-UP TIMINGS Symbol Parameter Minimum Units TPU-READ1 Power-up to Read Operation 10 ms Power-up to Write Operation 10 ms TPU-WRITE 1 T8.4 310 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 9: CAPACITANCE (Ta = 25°C, f=1 Mhz, other pins open) Parameter Description Test Condition Maximum CI/O1 I/O Pin Capacitance VI/O = 0V 12 pF Input Capacitance VIN = 0V 6 pF CIN 1 T9.0 310 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 10: RELIABILITY CHARACTERISTICS Symbol NEND 1 Parameter Minimum Specification Endurance TDR1 Data Retention ILTH1 Latch Up Units Test Method 10,000 Cycles JEDEC Standard A117 100 Years JEDEC Standard A103 100 + IDD mA JEDEC Standard 78 T10.7 310 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. ©2003 Silicon Storage Technology, Inc. S71077-05-000 3/03 9 310 4 Mbit SuperFlash EEPROM SST28SF040A / SST28VF040A Data Sheet AC CHARACTERISTICS TABLE 11: READ CYCLE TIMING PARAMETERS FOR SST28SF040A SST28SF040A-90 SST28SF040A-120 IEEE Symbol Industry Symbol Parameter Min tAVAV TRC Read Cycle Time 90 tAVQV TAA Address Access Time 90 120 ns tELQV TCE Chip Enable Access Time 90 120 ns tGLQV TOE Output Enable Access Time 45 50 ns Max Min Max 120 Units ns tEHQZ TCLZ 1 CE# Low to Active Output 0 0 ns tGHQZ TOLZ1 OE# Low to Active Output 0 0 ns tELQX TCHZ1 CE# High to High-Z Output 20 30 ns tGLQX TOHZ 1 OE# High to High-Z Output 20 30 ns tAXQX 1 TOH Output Hold from Address Change 0 0 ns T11.6 310 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 12: READ CYCLE TIMING PARAMETERS FOR SST28VF040A SST28VF040A-150 SST28VF040A-200 IEEE Symbol Industry Symbol Parameter Min tAVAV TRC Read Cycle Time 150 tAVQV TAA Address Access Time 150 200 ns tELQV TCE Chip Enable Access Time 150 200 ns tGLQV TOE Output Enable Access Time 100 ns tEHQZ TCLZ1 CE# Low to Active Output 0 tGHQZ TOLZ1 TCHZ1 TOHZ1 TOH1 OE# Low to Active Output 0 tELQX tGLQX tAXQX Max Min 75 CE# High to High-Z Output 0 ns 0 ns 60 40 Output Hold from Address Change Units ns 0 40 OE# High to High-Z Output Max 200 60 0 ns ns ns T12.5 310 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. ©2003 Silicon Storage Technology, Inc. S71077-05-000 3/03 10 310 4 Mbit SuperFlash EEPROM SST28SF040A / SST28VF040A Data Sheet TABLE 13: ERASE/PROGRAM CYCLE TIMING PARAMETERS SST28SF040A SST28VF040A Min Min IEEE Symbol Industry Symbol Parameter tAVA TBP Byte-Program Cycle Time tWLWH TWP Write Pulse Width (WE#) 90 100 ns tAVWL TAS Address Setup Time 10 10 ns tWLAX TAH Address Hold Time 50 100 ns tELWL TCS CE# Setup Time 0 0 ns tWHEX TCH CE# Hold Time 0 0 ns tGHWL TOES OE# High Setup Time 10 20 ns tWGL TOEH OE# High Hold Time 10 20 ns tWLEH TCP Write Pulse Width (CE#) 90 100 ns tDVWH TDS Data Setup Time 50 100 ns tWHDX TDH Data Hold Time 10 20 ns tWHWL2 TSE Sector-Erase Cycle Time 4 4 ms TRST1 Reset Command Recovery Time 4 4 µs tWHWL3 TSCE Software Chip-Erase Cycle Time 20 ms tEHEL TCPH CE# High Pulse Width 50 50 ns tWHWL1 TWPH WE# High Pulse Width 50 50 ns TPCP1 Protect CE# or OE# Pulse Width 50 50 ns Protect CE# or OE# High Time 50 50 ns Protect Address Setup Time 40 40 ns Protect Address Hold Time 0 0 TPCH 1 TPAS1 TPAH 1 Max 40 20 Max Units 40 µs ns T13.6 310 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. ©2003 Silicon Storage Technology, Inc. S71077-05-000 3/03 11 310 4 Mbit SuperFlash EEPROM SST28SF040A / SST28VF040A Data Sheet TRC TAA ADDRESS A18-0 TCHZ TCE CE# TOHZ TOE OE# TOLZ WE# TOH TCLZ DATA VALID DQ 7-0 DATA VALID 310 ILL F03.2 FIGURE 4: READ CYCLE TIMING DIAGRAM TAS TAH ADDRESS A18-0 TCH TCS CE# TOEH TOES OE# TWP TWPH WE# TDH DQ 7-0 TDS I0H DATA VALID TDH TDS TBP BYTE-PROGRAM SETUP COMMAND 310 ILL F04.1 FIGURE 5: WE# CONTROLLED BYTE-PROGRAM CYCLE TIMING DIAGRAM ©2003 Silicon Storage Technology, Inc. S71077-05-000 3/03 12 310 4 Mbit SuperFlash EEPROM SST28SF040A / SST28VF040A Data Sheet TAH TAS ADDRESS A18-0 TCP TCPH CE# TOEH TOES OE# TCH TCS WE# TDS TDH DQ 7-0 DATA VALID I0H TDH TDS TBP BYTE-PROGRAM SETUP COMMAND 310 ILL F05.1 FIGURE 6: CE# CONTROLLED BYTE-PROGRAM CYCLE TIMING DIAGRAM ADDRESS A18-0 CE# OE# WE# TDS DQ 7-0 FFH TDH TRST 310 ILL F06.0 FIGURE 7: RESET COMMAND TIMING DIAGRAM ©2003 Silicon Storage Technology, Inc. S71077-05-000 3/03 13 310 4 Mbit SuperFlash EEPROM SST28SF040A / SST28VF040A Data Sheet ADDRESS A18-0 CE# OE# WE# TDH TDS DQ 7-0 TDH TDS 30H 30H TSCE SETUP COMMAND EXECUTE COMMAND 310 ILL F07.0 FIGURE 8: CHIP-ERASE TIMING DIAGRAM AIN ADDRESS A18-0 TAS TAH CE# OE# WE# TDH TDS DQ 7-0 20H TDH TDS D0H TSE SETUP COMMAND EXECUTE COMMAND 310 ILL F08.0 FIGURE 9: SECTOR-ERASE TIMING DIAGRAM ©2003 Silicon Storage Technology, Inc. S71077-05-000 3/03 14 310 4 Mbit SuperFlash EEPROM SST28SF040A / SST28VF040A Data Sheet OE# TPCH TPCP CE# WE# ADDRESS 1823 1820 1822 0418 041B 0419 041A TPAH TPAS NOTE: A. ADDRESSES ARE LATCHED INTERNALLY ON THE RISING EDGE OF: 1. OE# IF CE# IS KEPT AT LOW ALL TIME. 2. CE# IF OE# IS KEPT AT LOW ALL TIME. 3. THE FIRST PIN TO GO HIGH IF BOTH ARE TOGGLED. B. ABOVE ADDRESS VALUES ARE IN HEX. C. ADDRESSES > A12 ARE "DON'T CARE" 310 ILL F09.4 FIGURE 10: SOFTWARE DATA UNPROTECT DISABLE TIMING DIAGRAM OE# TPCH TPCP CE# WE# ADDRESS 1823 1820 1822 0418 041B 0419 040A TPAH TPAS NOTE: A. ADDRESSES ARE LATCHED INTERNALLY ON THE RISING EDGE OF: 1. OE# IF CE# IS KEPT AT LOW ALL TIME. 2. CE# IF OE# IS KEPT AT LOW ALL TIME. 3. THE FIRST PIN TO GO HIGH IF BOTH ARE TOGGLED. B. ABOVE ADDRESS VALUES ARE IN HEX. C. ADDRESSES > A12 ARE "DON'T CARE" 310 ILL F10.4 FIGURE 11: SOFTWARE DATA PROTECT DISABLE TIMING DIAGRAM ©2003 Silicon Storage Technology, Inc. S71077-05-000 3/03 15 310 4 Mbit SuperFlash EEPROM SST28SF040A / SST28VF040A Data Sheet ADDRESS A18-0 TCE CE# TOES TOEH OE# TOE WE# D# D# D D DQ 7-0 NOTE 310 ILL F11.0 NOTE: THIS TIME INTERVAL SIGNAL CAN BE TSE or TBP DEPENDING UPON THE SELECTED OPERATION MODE. FIGURE 12: DATA# POLLING TIMING DIAGRAM ADDRESS A18-0 TCE TCE CE# TOES TOEH OE# TOE TOE WE# DQ6 NOTE TWO READ CYCLES WITH SAME OUTPUTS NOTE: THIS TIME INTERVAL SIGNAL CAN BE TSE or TBP DEPENDING UPON THE SELECTED OPERATION MODE. 310 ILL F12.0 FIGURE 13: TOGGLE BIT TIMING DIAGRAM ©2003 Silicon Storage Technology, Inc. S71077-05-000 3/03 16 310 4 Mbit SuperFlash EEPROM SST28SF040A / SST28VF040A Data Sheet VIHT VHT INPUT VHT REFERENCE POINTS OUTPUT VLT VLT VILT 310 ILL F13.1 AC test inputs are driven at VIHT (2.4V) for a logic “1” and VILT (0.4 V) for a logic “0”. Measurement reference points for inputs and outputs are VHT (2.0 V) and VLT (0.8 V). Input rise and fall times (10% ↔ 90%) are <10 ns. Note: VHT - VHIGH Test VLT - VLOW Test VIHT - VINPUT HIGH Test VILT - VINPUT LOW Test FIGURE 14: AC INPUT/OUTPUT REFERENCE WAVEFORMS VDD TO TESTER RL HIGH TO DUT CL RL LOW 310 ILL F14.2 FIGURE 15: A TEST LOAD EXAMPLE ©2003 Silicon Storage Technology, Inc. S71077-05-000 3/03 17 310 4 Mbit SuperFlash EEPROM SST28SF040A / SST28VF040A Data Sheet Start Initialize Address Execute ByteProgram Setup Command Load Address and Data & Start Programming Read End-of-Write Detection Programming Completed? No Yes Data Verifies? Next Address No Programming Failure Yes No Last Address Yes Programming Completed 310 ILL F15.3 FIGURE 16: BYTE-PROGRAM FLOWCHART ©2003 Silicon Storage Technology, Inc. S71077-05-000 3/03 18 310 4 Mbit SuperFlash EEPROM SST28SF040A / SST28VF040A Data Sheet Internal Timer Toggle Bit Data# Polling Program/Erase Initiated Program/Erase Initiated Program/Erase Initiated Wait TBP or TSE Read byte Read DQ7 Program/Erase Completed Read same byte No Is DQ7 = true data? Yes No Does DQ6 match? Program/Erase Completed Yes Program/Erase Completed 310 ILL F16.2 FIGURE 17: WRITE WAIT OPTIONS ©2003 Silicon Storage Technology, Inc. S71077-05-000 3/03 19 310 4 Mbit SuperFlash EEPROM SST28SF040A / SST28VF040A Data Sheet Start Initialize Sector Address Execute Two Step Sector-Erase Command End-of-Write Detection Erase completed? No Yes Read FFH from Selected Byte Address Verify FFH No Yes Increment Byte Address No Last Address? Yes Next Sector Address Sector-Erase Completed No Erase Error Last Sector? Yes Device Erased 310 ILL F17.5 FIGURE 18: SECTOR-ERASE FLOWCHARTS ©2003 Silicon Storage Technology, Inc. S71077-05-000 3/03 20 310 4 Mbit SuperFlash EEPROM SST28SF040A / SST28VF040A Data Sheet Execute Read ID Command (90H) to Enter Read-ID mode Read Address 0000H MFG's ID = SST (BFH) Read Address 0001H Device ID = 28SF040 (04H) Execute Reset Command (FFH) to Exit from Read-ID mode 310 ILL F18.5 FIGURE 19: SOFTWARE PRODUCT ID FLOW ©2003 Silicon Storage Technology, Inc. S71077-05-000 3/03 21 310 4 Mbit SuperFlash EEPROM SST28SF040A / SST28VF040A Data Sheet PRODUCT ORDERING INFORMATION Device Speed SST28xF040A - XXX Suffix1 - XX Suffix2 - XX Package Modifier H = 32 leads or pins Package Type E = TSOP (type 1, die up, 8mm x 20mm) N = PLCC P = PDIP Temperature Range C = Commercial = 0°C to +70°C I = Industrial = -40°C to +85°C Minimum Endurance 4 = 10,000 cycles Read Access Speed 200 = 200 ns 150 = 150 ns 120 = 120 ns 90 = 90 ns Function F = Chip- or Sector-Erase Byte- or Word-Program Voltage S = 4.5-5.5V V = 2.7-3.6V Valid combinations for SST28SF040A SST28SF040A-90-4C-NH SST28SF040A-90-4C-EH SST28SF040A-120-4C-NH SST28SF040A-120-4C-EH SST28SF040A-90-4C-PH SST28SF040A-120-4I-NH‡ SST28SF040A-120-4I-EH‡ Valid combinations for SST28VF040A SST28VF040A-150-4C-NH SST28VF040A-150-4C-EH SST28VF040A-200-4C-NH* SST28VF040A-200-4C-EH* SST28VF040A-200-4I-NH*‡ SST28VF040A-200-4I-EH*‡ Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations. * Not recommended for new designs. ‡ The software Chip-Erase function is not supported by the industrial temperature part. Please contact SST if you require this function for an industrial temperature part. Non-Pb: Several devices in this data sheet are also offered in non-Pb (no lead added) packages. The non-Pb part number is simply the standard part number with the letter “E” added to the end of the package code. The non-Pb package codes corresponding to the packages listed above are NHE and EHE. ©2003 Silicon Storage Technology, Inc. S71077-05-000 3/03 22 310 4 Mbit SuperFlash EEPROM SST28SF040A / SST28VF040A Data Sheet PACKAGING DIAGRAMS TOP VIEW Optional Pin #1 Identifier .048 .042 SIDE VIEW .495 .485 .453 .447 2 1 32 .112 .106 .020 R. MAX. .029 x 30˚ .023 .040 R. .030 .042 .048 .595 .553 .585 .547 BOTTOM VIEW .021 .013 .400 .530 BSC .490 .032 .026 .050 BSC .015 Min. .095 .075 .050 BSC .140 .125 .032 .026 Note: 1. Complies with JEDEC publication 95 MS-016 AE dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in inches (max/min). 3. Dimensions do not include mold flash. Maximum allowable mold flash is .008 inches. 4. Coplanarity: 4 mils. 32-plcc-NH-3 32-LEAD PLASTIC LEAD CHIP CARRIER (PLCC) SST PACKAGE CODE: NH ©2003 Silicon Storage Technology, Inc. S71077-05-000 3/03 23 310 4 Mbit SuperFlash EEPROM SST28SF040A / SST28VF040A Data Sheet 1.05 0.95 Pin # 1 Identifier 0.50 BSC 8.10 7.90 0.27 0.17 0.15 0.05 18.50 18.30 DETAIL 1.20 max. 0.70 0.50 20.20 19.80 0˚- 5˚ 0.70 0.50 Note: 1.Complies with JEDEC publication 95 MO-142 BD dimensions, although some dimensions may be more stringent. 2.All linear dimensions are in millimeters (max/min). 3.Coplanarity: 0.1 mm 4.Maximum allowable mold flash is 0.15 mm at the package ends, and 0.25mm between leads. 32-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) 8MM SST PACKAGE CODE: EH X ©2003 Silicon Storage Technology, Inc. 1mm 32-tsop-EH-7 20MM S71077-05-000 3/03 24 310 4 Mbit SuperFlash EEPROM SST28SF040A / SST28VF040A Data Sheet 32 CL Pin #1 Identifier 1 1.655 1.645 .075 .065 7˚ 4 PLCS. Base Plane Seating Plane .625 .600 .550 .530 .200 .170 .050 .015 .080 .070 .065 .045 .022 .016 .100 BSC .150 .120 0˚ 15˚ .012 .008 .600 BSC Note: 1. Complies with JEDEC publication 95 MO-015 AP dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in inches (max/min). 3. Dimensions do not include mold flash. Maximum allowable mold flash is .010 inches. 32-pdip-PH-3 32-PIN PLASTIC DUAL IN-LINE PINS (PDIP) SST PACKAGE CODE: PH TABLE 14: REVISION HISTORY Number Description 04 • 05 • • • Date May 2002 2002 Data Book Removed WH package Part number changes - see page 22 for additional information Clarified the Test Conditions for VDD Read Current parameter in Table 6 and Table 7 on page 8 – Address input = VILT/VIHT ©2003 Silicon Storage Technology, Inc. Mar 2003 S71077-05-000 3/03 25 310 4 Mbit SuperFlash EEPROM SST28SF040A / SST28VF040A Data Sheet Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036 www.SuperFlash.com or www.sst.com ©2003 Silicon Storage Technology, Inc. S71077-05-000 3/03 26 310