MOTOROLA Freescale Semiconductor, Inc. Order this document by MC145483/D SEMICONDUCTOR TECHNICAL DATA MC145483 Freescale Semiconductor, Inc... 3 V 13-Bit Linear PCM Codec-Filter The MC145483 is a 13–bit linear PCM Codec–Filter with 2s complement data format, and is offered in 20–pin SOG, SSOP, and TSSOP packages, and a 32–pin QFN package. This device performs the voice digitization and reconstruction as well as the band limiting and smoothing required for the voice coding in digital communication systems. This device is designed to operate in both synchronous and asynchronous applications and contains an on–chip precision reference voltage. This device has an input operational amplifier whose output is the input to the encoder section. The encoder section immediately low–pass filters the analog signal with an active R–C filter to eliminate very high frequency noise from being modulated down to the passband by the switched capacitor filter. From the active R–C filter, the analog signal is converted to a differential signal. From this point, all analog signal processing is done differentially. This allows processing of an analog signal that is twice the amplitude allowed by a single–ended design, which reduces the significance of noise to both the inverted and non–inverted signal paths. Another advantage of this differential design is that noise injected via the power supplies is a common–mode signal that is cancelled when the inverted and non–inverted signals are recombined. This dramatically improves the power supply rejection ratio. After the differential converter, a differential switched capacitor filter band– passes the analog signal from 200 Hz to 3400 Hz before the signal is digitized by the differential 13–bit linear A/D converter. The digital output is 2s complement format. The decoder digital input accepts 2s complement data and reconstructs it using a differential 13–bit linear D/A converter. The output of the D/A is low–pass filtered at 3400 Hz and sinX/X compensated by a differential switched capacitor filter. The signal is then filtered by an active R–C filter to eliminate the out–of–band energy of the switched capacitor filter. The MC145483 PCM Codec–Filter has a high–impedance VAG reference pin which allows for decoupling of the internal circuitry that generates the mid–supply VAG reference voltage to the VSS power supply ground. This reduces clock noise on the analog circuitry when external analog signals are referenced to the power supply ground. The MC145483 13–bit linear PCM Codec–Filter accepts both Short Frame Sync and Long Frame Sync clock formats, and utilizes CMOS due to its reliable low–power performance and proven capability for complex analog/digital VLSI functions. DW SUFFIX SOG PACKAGE CASE 751D 20 1 SD SUFFIX SSOP CASE 940C 20 1 DT SUFFIX TSSOP CASE 948E 20 1 1 32 FC SUFFIX QFN CASE 1311 ORDERING INFORMATION MC145483DW MC145483SD MC145483DT MC145483FC SOG Package SSOP TSSOP QFN • • • • • • • • Single 3 V Power Supply 13–Bit Linear ADC/DAC Conversions with 2s Complement Data Format Typical Power Dissipation of 8 mW, Power–Down of 0.01 mW Fully–Differential Analog Circuit Design for Lowest Noise Transmit Band–Pass and Receive Low–Pass Filters On–Chip Transmit High–Pass Filter May be Bypassed by Pin Selection Active R–C Pre–Filtering and Post–Filtering On–Chip Precision Reference Voltage of 0.886 V for a – 5 dBm TLP @ 600 Ω • 3–Terminal Input Op Amp Can be Used, or a 2–Channel Input Multiplexer • Receive Gain Control from 0 dB to – 21 dB in 3 dB Steps in Synchronous Operation • Push–Pull 300–Ω Power Drivers with External Gain Adjust REV 3 4/2003 For More Information On This Product, Go to: www.freescale.com MC145483 Freescale Semiconductor, Inc. PIN ASSIGNMENTS 20 19 18 17 16 15 14 13 12 11 VAG TI+ TI– TG HB VSS FST DT BCLKT MCLK 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 NC PI PO– NC PO+ VDD FSR NC 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 Freescale Semiconductor, Inc... NC DR BCLKR PDI MCLK BCLKT DT NC 9 10 11 12 13 14 15 16 VAG Ref RO– PI PO– PO+ VDD FSR DR BCLKR PDI 32-PIN QFN NC NC RO– VAG Ref VAG TI+ NC NC 20-PIN SOG, SSOP, and TSSOP 2 For More Information On This Product, Go to: www.freescale.com NC TI– TG HB NC VSS FST NC Freescale Semiconductor, Inc. RECEIVE SHIFT REGISTER RO – DR DAC FREQ PI – + PO – FSR BCLKR SHARED DAC SEQUENCE AND CONTROL –1 PO + VDD VDD VSS R* Freescale Semiconductor, Inc... FST R* 1 VAG MCLK BCLKT 0.886 V REF VAG Ref PDI VSS TG TI – TI + – + ADC FREQ HB TRANSMIT SHIFT REGISTER DT Figure 1. MC145483 13–Bit Linear PCM Codec–Filter Block Diagram DEVICE DESCRIPTION A PCM Codec–Filter is used for digitizing and reconstructing the human voice. These devices are used primarily for the telephone network to facilitate voice switching and transmission. Once the voice is digitized, it may be switched by digital switching methods or transmitted long distance (T1, microwave, satellites, etc.) without degradation. The name codec is an acronym from ‘‘COder’’ for the analog–to–digital converter (ADC) used to digitize voice, and ‘‘DECoder’’ for the digital–to–analog converter (DAC) used for reconstructing voice. A codec is a single device that does both the ADC and DAC conversions. To digitize intelligible voice requires a signal–to–distortion ratio of about 30 dB over a dynamic range of about 40 dB. This may be accomplished with a linear 13–bit ADC and DAC. The MC145483 satisfies these requirements and may be used as the analog front–end for voice coders using DSP technology to further compress the digital data stream. In a sampling environment, Nyquist theory says that to properly sample a continuous signal, it must be sampled at a frequency higher than twice the signal’s highest frequency component. Voice contains spectral energy above 3 kHz, but its absence is not detrimental to intelligibility. To reduce the digital data rate, which is proportional to the sampling rate, a sample rate of 8 kHz was adopted, consistent with a bandwidth of 3 kHz. This sampling requires a low–pass filter to limit the high frequency energy above 3 kHz from distorting the in–band signal. The telephone line is also subject to 50/60 Hz power line coupling, which must be attenuated from the signal by a high–pass filter before the analog–to– digital converter. The MC145483 includes a high–pass filter for compatibility with existing telephone applications, but it may be removed from the analog input signal path by the high–pass bypass pin. The digital–to–analog conversion process reconstructs a staircase version of the desired in–band signal, which has spectral images of the in–band signal modulated about the sample frequency and its harmonics. These spectral images are called aliasing components, which need to be attenuated to obtain the desired signal. The low–pass filter used to attenuate these aliasing components is typically called a reconstruction or smoothing filter. The MC145483 PCM Codec–Filter has the codec, both presampling and reconstruction filters, and a precision voltage reference on–chip. For More Information On This Product, Go to: www.freescale.com MC145483 Freescale Semiconductor, Inc. PIN DESCRIPTIONS POWER SUPPLY VDD Positive Power Supply (Pin 6) This is the most positive power supply and is typically connected to + 3 V. This pin should be decoupled to VSS with a 0.1 µF ceramic capacitor. ANALOG INTERFACE VSS Negative Power Supply (Pin 15) TI+ Transmit Analog Input (Non–Inverting) (Pin 19) This is the most negative power supply and is typically connected to 0 V. This is the non–inverting input of the transmit input gain setting operational amplifier. This pin accommodates a differential to single–ended circuit for the input gain setting op amp. This allows input signals that are referenced to the V SS pin to be level shifted to the VAG pin with minimum noise. This pin may be connected to the VAG pin for an inverting amplifier configuration if the input signal is already referenced to the VAG pin. The common mode range of the TI+ and TI– pins is from 1.2 V, to V DD minus 1.2 V. This is an FET gate input. The TI+ pin also serves as a digital input control for the transmit input multiplexer. Connecting the TI+ pin to V DD will place this amplifier’s output (TG) into a high–impedance state, and selects the TG pin to serve as a high–impedance input to the transmit filter. Connecting the TI+ pin to VSS will also place this amplifier’s output (TG) into a high–impedance state, and selects the TI– pin to serve as a high–impedance input to the transmit filter. VAG Analog Ground Output (Pin 20) Freescale Semiconductor, Inc... when a logic 1 is applied to this pin. The device goes through a power–up sequence when this pin is taken to a logic 1 state, which prevents the DT PCM output from going low impedance for at least two FST cycles. The VAG and VAG Ref circuits and the signal processing filters must settle out before the DT PCM output or the RO– receive analog output will represent a valid analog signal. This output pin provides a mid–supply analog ground. This pin should be decoupled to VSS with a 0.01 µF ceramic capacitor. All analog signal processing within this device is referenced to this pin. If the audio signals to be processed are referenced to V SS, then special precautions must be utilized to avoid noise between V SS and the VAG pin. Refer to the applications information in this document for more information. The VAG pin becomes high impedance when this device is in the powered–down mode. VAG Ref Analog Ground Reference Bypass (Pin 1) This pin is used to capacitively bypass the on–chip circuitry that generates the mid–supply voltage for the VAG output pin. This pin should be bypassed to VSS with a 0.1 µF ceramic capacitor using short, low inductance traces. The VAG Ref pin is only used for generating the reference voltage for the VAG pin. Nothing is to be connected to this pin in addition to the bypass capacitor. All analog signal processing within this device is referenced to the VAG pin. If the audio signals to be processed are referenced to VSS, then special precautions must be utilized to avoid noise between VSS and the VAG pin. Refer to the applications information in this document for more information. When this device is in the powered–down mode, the VAG Ref pin is pulled to the VDD power supply with a non–linear, high–impedance circuit. CONTROL HB Transmit High–Pass Filter Bypass (Pin 16) TI– Transmit Analog Input (Inverting) (Pin 18) This is the inverting input of the transmit gain setting operational amplifier. Gain setting resistors are usually connected from this pin to TG and from this pin to the analog signal source. The common mode range of the TI+ and TI– pins is from 1.2 V to VDD – 1.2 V. This is an FET gate input. The TI– pin also serves as one of the transmit input mulitplexer pins when the TI+ pin is connected to VSS. When TI+ is connected to VDD, this pin is ignored. See the pin descriptions for the TI+ and the TG pins for more information. TG Transmit Gain (Pin 17) This pin selects whether the transmit high–pass filter will be used or bypassed, which allows frequencies below 200 Hz to appear at the input of the ADC to be digitized. This high–pass filter is a third order filter for attenuating power line frequencies, typically 50/60 Hz. A logic low selects this filter. A logic high deselects or bypasses this filter. When the filter is bypassed, the transmit frequency response extends down to dc. This is the output of the transmit gain setting operational amplifier and the input to the transmit band–pass filter. This op amp is capable of driving a 2 kΩ load. Connecting the TI+ pin to VDD will place the TG pin into a high–impedance state, and selects the TG pin to serve as a high–impedance input to the transmit filter. All signals at this pin are referenced to the VAG pin. When TI+ is connected to VSS, this pin is ignored. See the pin descriptions for TI+ and TI– pins for more information. This pin is high impedance when the device is in the powered–down mode. PDI Power–Down Input (Pin 10) RO– Receive Analog Output (Inverting) (Pin 2) This pin puts the device into a low power dissipation mode when a logic 0 is applied. When this device is powered down, all of the clocks are gated off and all bias currents are turned off, which causes RO–, PO–, PO+, TG, VAG, and DT to become high impedance. The device will operate normally This is the inverting output of the receive smoothing filter from the digital–to–analog converter. This output is capable of driving a 2 kΩ load to 0.886 V peak referenced to the VAG pin. If the device is operated half–channel with the FST pin clocking and FSR pin held low, the receive filter input will be For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. connected to the VAG voltage. This minimizes transients at the RO– pin when full–channel operation is resumed by clocking the FSR pin. This pin is high impedance when the device is in the powered–down mode. PI Power Amplifier Input (Pin 3) This is the inverting input to the PO– amplifier. The non– inverting input to the PO– amplifier is internally tied to the VAG pin. The PI and PO– pins are used with external resistors in an inverting op amp gain circuit to set the gain of the PO+ and PO– push–pull power amplifier outputs. Connecting PI to VDD will power down the power driver amplifiers and the PO+ and PO– outputs will be high impedance. Freescale Semiconductor, Inc... PO– Power Amplifier Output (Inverting) (Pin 4) This is the inverting power amplifier output, which is used to provide a feedback signal to the PI pin to set the gain of the push–pull power amplifier outputs. This pin is capable of driving a 300 Ω load to PO+. The PO+ and PO– outputs are differential (push–pull) and capable of driving a 300 Ω load to 1.772 V peak, which is 3.544 V peak–to–peak. The bias voltage and signal reference of this output is the VAG pin. The VAG pin cannot source or sink as much current as this pin, and therefore low impedance loads must be between PO+ and PO–. The PO+ and PO– differential drivers are also capable of driving a 100 Ω resistive load or a 100 nF Piezoelectric transducer in series with a 20 Ω resister with a smalll increase in distortion. These drivers may be used to drive resistive loads of ≥ 32 Ω when the gain of PO– is set to 1/4 or less. Connecting PI to VDD will power down the power driver amplifiers, and the PO+ and PO– outputs will be high impedance. This pin is also high impedance when the device is powered down by the PDI pin. PO+ Power Amplifier Output (Non–Inverting) (Pin 5) This is the non–inverting power amplifier output, which is an inverted version of the signal at PO–. This pin is capable of driving a 300 Ω load to PO–. Connecting PI to VDD will power down the power driver amplifiers and the PO+ and PO– outputs will be high impedance. This pin is also high impedance when the device is powered down by the PDI pin. See PI and PO– for more information. DIGITAL INTERFACE MCLK Master Clock (Pin 11) This is the master clock input pin. The clock signal applied to this pin is used to generate the internal 256 kHz clock and sequencing signals for the switched–capacitor filters, ADC, and DAC. The internal prescaler logic compares the clock on this pin to the clock at FST (8 kHz) and will automatically accept 256, 512, 1536, 1544, 2048, 2560, or 4096 kHz. For MCLK frequencies of 256 and 512 kHz, MCLK must be syn- chronous and approximately rising edge aligned to FST. For optimum performance at frequencies of 1.536 MHz and higher, MCLK should be synchronous and approximately rising edge aligned to the rising edge of FST. In many applications, MCLK may be tied to the BCLKT pin. FST Frame Sync, Transmit (Pin 14) This pin accepts an 8 kHz clock that synchronizes the output of the serial PCM data at the DT pin. This input is compatible with both Long Frame Sync and Short Frame Sync. If both FST and FSR are held low for several 8 kHz frames, the device will power down. FST must be clocking for the device to power up affter being powered down by the frame syncs. BCLKT Bit Clock, Transmit (Pin 12) This pin controls the transfer rate of transmit PCM data. In the synchronous modes of sign–bit extended and receive gain adjust, the BCLKT also controls the transfer rate of the receive PCM data. This pin can accept any bit clock frequency from 256 to 4096 kHz for Long Frame Sync and Short Frame Sync timing. DT Data, Transmit (Pin 13) This pin is controlled by FST and BCLKT and is high impedance except when outputting PCM data. This pin is high impedance when the device is in the powered–down mode. FSR Frame Sync, Receive (Pin 7) This pin accepts an 8 kHz clock, which synchronizes the input of the serial PCM data at the DR pin. FSR can be asynchronous to FST in the Long Frame Sync or Short Frame Sync modes. BCLKR Bit Clock, Receive (Pin 9) This pin accepts any bit clock frequency from 256 to 4096 kHz. The BCLKR pin is also used as a mode select pin when not being clocked for several 8 kHz frames. The BCKLT pin is used to clock the receive PCM data transfers when the BCLKR pin is not being clocked. When the BCLKR pinis a logic 0, the sign–bit extended synchronous mode is selected, which uses 16–bit transfers with the first four bits being the sign bit. When the BCLKR pin is a logic 1, the receive gain adjust synchronous mode is selected, which uses a 13–bit transfer for the transmit PCM data, but uses a 16–bit transfer for the receive side, with the 13–bit voice data being first, followed by three bits which control the attenuation of the receive analog output. DR Data, Receive (Pin 8) This pin is the PCM data input. See the pin descriptions for FSR, BCLKR, and BCKLT for more information. For More Information On This Product, Go to: www.freescale.com MC145483 Freescale Semiconductor, Inc. FUNCTIONAL DESCRIPTION Freescale Semiconductor, Inc... ANALOG INTERFACE AND SIGNAL PATH The transmit portion of this device includes a low–noise, three–terminal op amp capable of driving a 2 kΩ load. This op amp has inputs of TI+ (Pin 19) and TI– (Pin 18) and its output is TG (Pin 17). This op amp is intended to be configured in an inverting gain circuit. The analog signal may be applied directly to the TG pin if this transmit op amp is independently powered down by connecting the TI+ input to the VDD power supply. The TG pin becomes high impedance when the transmit op amp is powered down. The TG pin is internally connected to a 3–pole anti–aliasing pre–filter. This pre–filter incorporates a 2–pole Butterworth active low–pass filter, followed by a single passive pole. This pre–filter is followed by a single–ended to differential converter that is clocked at 512 kHz. All subsequent analog processing utilizes fully–differential circuitry. The next section is a fully–differential, 5–pole switched–capacitor low–pass filter with a 3.4 kHz frequency cutoff. After this filter is a 3–pole switched–capacitor high–pass filter having a cutoff frequency of about 200 Hz. This high–pass stage has a transmission zero at dc that eliminates any dc coming from the analog input or from accumulated op amp offsets in the preceding filter stages. The high–pass filter may be bypassed or removed from the signal path by the HB pin. When the high– pass filter is bypassed, the frequency response extends down to include dc. The last stage of the high–pass filter is an autozeroed sample and hold amplifier. One bandgap voltage reference generator and digital–to– analog converter (DAC) are shared by the transmit and receive sections. The autozeroed, switched–capacitor bandgap reference generates precise positive and negative reference voltages that are virtually independent of temperature and power supply voltage. A capacitor array (CDAC) is combined with a resistor string (RDAC) to implement the 13–bit linear DAC structure. The encode process uses the DAC, the voltage reference, and a frame–by–frame autozeroed comparator to implement a successive approximation conversion algorithm. All of the analog circuitry involved in the data conversion (the voltage reference, RDAC, CDAC, and comparator) are implemented with a differential architecture. The receive section includes the DAC described above, a sample and hold amplifier, a 5–pole, 3400 Hz switched capacitor low–pass filter with sinX/X correction, and a 2–pole active smoothing filter to reduce the spectral components of the switched capacitor filter. The output of the smoothing filter is buffered by an amplifier, which is output at the RO– pin. This output is capable of driving a 2 kΩ load to the VAG pin. The MC145483 also has a pair of power amplifiers that are connected in a push–pull configuration. The PI pin is the inverting input to the PO– power amplifier. The non–inverting input is internally tied to the VAG pin. This allows this amplifier to be used in an inverting gain circuit with two external resistors. The PO+ amplifier has a gain of minus one, and is internally connected to the PO– output. This complete power amplifier circuit is a differential (push–pull) amplifier with adjustable gain. The power amplifier may be powered down independently of the rest of the chip by connecting the PI pin to VDD. The calibration level for both ADC and DAC of this 13–bit linear PCM Codec–Filter is referenced to Mu–Law with the same bit voltage weighting about the zero crossing. This results in the 0 dBm0 calibration level being 3.20 dB below the peak sinusoidal level before clipping. Based on the reference voltage of 0.886 V, the calibration level is 0.436 Vrms or – 5 dBm at 600 Ω. The MC145483 has the ability to attenuate the receive analog output when used in the receive gain adjust mode. This mode is accessed by applying a logic high to the BCLKR pin while the rest of the clock pins are clocked normally. This allows three additional bits that will be used to control the gain of the analog output to be clocked into the DR pin following the 13 bits of voice data. Table 1 shows the attenuation values and the corresponding digital codes. Table 1. Receive Gain Adjust Mode Coefficients and Attenuation Weightings Coefficient Attenuation in dB 000 0 001 –3 010 –6 011 –9 100 – 12 101 – 15 110 – 18 111 – 21 POWER–DOWN There are two methods of putting this device into a low power consumption mode, which makes the device nonfunctional and consumes virtually no power. PDI is the power– down input pin which, when taken low, powers down the device. Another way to power the device down is to hold both the FST and FSR pins low while the BCLKT and MCLK pins are clocked. When the chip is powered down, the VAG, TG, RO–, PO+, PO–, and DT outputs are high impedance and the VAG Ref pin is pulled to the VDD power supply with a non– linear, high–impedance circuit. To return the chip to the power–up state, PDI must be high and the FST frame sync pulse must be present while the BCLKT and MCLK pins are clocked. The DT output will remain in a high–impedance state for at least two 8 kHz FST pulses after power–up. MASTER CLOCK Since this codec–filter design has a single DAC architecture, the MCLK pin is used as the master clock for all analog signal processing including analog–to–digital conversion, digital–to–analog conversion, and for transmit and receive filtering functions of this device. The clock frequency applied to the MCLK pin may be 256 kHz, 512 kHz, 1.536 MHz, 1.544 MHz, 2.048 MHz, 2.56 MHz, or 4.096 MHz. This device has a prescaler that automatically determines the proper divide ratio to use for the MCLK input, which achieves the required 256 kHz internal sequencing clock. The clocking requirements of the MCLK input are independent of the PCM data transfer mode (i.e., Long Frame Sync, Short Frame Sync, whether the device is used in the synchronous modes or not). For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. DIGITAL I/O Table 2. PCM Codes for Zero and Full–Scale The MC145483 is a 13–bit linear device using 2s complement data format. Table 2 shows the 13–bit data word format for the maximum positive code and negative zero and full– scale. Table 3 shows the series of eight 13–bit PCM words that correspond to a digital milliwatt. The digital milliwatt is the 1 kHz calibration signal reconstructed by the DAC that defines the absolute gain or 0 dBm0 transmission level point (TLP) of the DAC. The calibration level for this 13–bit linear ADC and DAC is referenced to Mu–Law with the same bit voltage weighting about the zero crossing. This results in the 0 dBm0 calibration level being 3.20 dB below the peak sinusoidal level before clipping. Refer to Figures 2a–2d for a summary and comparison of the four PCM data interface modes of this device. Level Sign Bit Magnitude Bits + Full Scale 0 1111 1111 1111 + One Step 0 0000 0000 0001 Zero 0 0000 0000 0000 – One Step 1 1111 1111 1111 – Full Scale 1 0000 0000 0000 Table 3. PCM Codes for 1 kHz Digital Milliwatt Level Sign Bit Magnitude Bits π/8 3π/8 Freescale Semiconductor, Inc... 5π/8 7π/8 9π/8 11π/8 13π/8 15π/8 For More Information On This Product, Go to: www.freescale.com MC145483 Freescale Semiconductor, Inc. FST (FSR) BCLKT (BCLKR) DT DR DON’T CARE 1 2 3 4 5 6 7 8 9 10 11 12 13 1 2 3 4 5 6 7 8 9 10 11 12 13 DON’T CARE Figure 2a. Long Frame Sync (Transmit and Receive Have Individual Clocking) FST (FSR) Freescale Semiconductor, Inc... BCLKT (BCLKR) DT DR DON’T CARE 1 2 3 4 5 6 7 8 9 10 11 12 13 1 2 3 4 5 6 7 8 9 10 11 12 13 DON’T CARE Figure 2b. Short Frame Sync (Transmit and Receive Have Individual Clocking) FST (FSR) SHORT OR LONG FRAME SYNC BCLKT DT DR DON’T CARE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 DON’T CARE Figure 2c. Sign–Extended (BCLKR = 0) Transmit and receive both use BCLKT, and the first four data bits are the sign bit. FST may occur at a different time than FSR. FST (FSR) SHORT OR LONG FRAME SYNC BCLKT DT DR DON’T CARE 1 2 3 4 5 6 7 8 9 10 11 12 13 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 DON’T CARE Figure 2d. Receive Gain Adjust (BCLKR = 1) Transmit and receive both use BCLKT. FST may occur at a different time than FSR. Bits 14, 15, and 16, clocked into DR, are used for attenuation control for the receive analog output. Figure 2. Digital Timing Modes for the PCM Data Interface For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... PRINTED CIRCUIT BOARD LAYOUT CONSIDERATIONS The MC145483 is manufactured using high–speed CMOS VLSI technology to implement the complex analog signal processing functions of a PCM Codec–Filter. The fully–differential analog circuit design techniques used for this device result in superior performance for the switched capacitor filters, the analog–to–digital converter (ADC) and the digital– to–analog converter (DAC). Special attention was given to the design of this device to reduce the sensitivities of noise, including power supply rejection and susceptibility to radio frequency noise. This special attention to design includes a fifth order low–pass filter, followed by a third order high–pass filter whose output is converted to a digital signal with greater than 75 dB of dynamic range, all operating on a single 3 V power supply. This results in an LSB size for small audio signals of about 216 µV. The typical idle channel noise level of this device is less than one LSB. In addition to the dynamic range of the codec–filter function of this device, the input gain–setting op amp has the capability of greater than 30 dB of gain intended for an electret microphone interface. This device was designed for ease of implementation, but due to the large dynamic range and the noisy nature of the environment for this device (digital switches, radio telephones, DSP front–end, etc.) special care must be taken to assure optimum analog transmission performance. PC BOARD MOUNTING It is recommended that the device be soldered to the PC board for optimum noise performance. If the device is to be used in a socket, it should be placed in a low parasitic pin inductance (generally, low–profile) socket. POWER SUPPLY, GROUND, AND NOISE CONSIDERATIONS This device is intended to be used in switching applications which often require plugging the PC board into a rack with power applied. This is known as ‘‘hot–rack insertion.’’ In these applications care should be taken to limit the voltage on any pin from going positive of the VDD pins, or negative of the VSS pins. One method is to extend the ground and power contacts of the PCB connector. The device has input protection on all pins and may source or sink a limited amount of current without damage. Current limiting may be accomplished by series resistors between the signal pins and the connector contacts. The most important considerations for PCB layout deal with noise. This includes noise on the power supply, noise generated by the digital circuitry on the device, and cross coupling digital or radio frequency signals into the audio signals of this device. The best way to prevent noise is to: 1. Keep digital signals as far away from audio signals as possible. 2. Keep radio frequency signals as far away from the audio signals as possible. 3. Use short, low inductance traces for the audio circuitry to reduce inductive, capacitive, and radio frequency noise sensitivities. 4. Use short, low inductance traces for digital and RF circuitry to reduce inductive, capacitive, and radio frequency radiated noise. 5. Bypass capacitors should be connected from the VDD, VAG Ref, and VAG pins to VSS with minimal trace length. Ceramic monolithic capacitors of about 0.1 µF are acceptable for the VDD and VAG Ref pins to decouple the device from its own noise. The VDD capacitor helps supply the instantaneous currents of the digital circuitry in addition to decoupling the noise which may be generated by other sections of the device or other circuitry on the power supply. The VAG Ref decoupling capacitor is effecting a low–pass filter to isolate the mid–supply voltage from the power supply noise generated on–chip, as well as external to the device. The VAG decoupling capacitor should be about 0.01 µF. This helps to reduce the impedance of the VAG pin to VSS at frequencies above the bandwidth of the VAG generator, which reduces the susceptiblility to RF noise. 6. Use a short, wide, low inductance trace to connect the VSS ground pin to the power supply ground. The VSS pin is the digital ground and the most negative power supply pin for the analog circuitry. All analog signal processing is referenced to the VAG pin, but because digital and RF circuitry will probably be powered by this same ground, care must be taken to minimize high frequency noise in the VSS trace. Depending on the application, a double– sided PCB with a VSS ground plane connecting all of the digital and analog VSS pins together would be a good grounding method. A multilayer PC board with a ground plane connecting all of the digital and analog VSS pins together would be the optimal ground configuration. These methods will result in the lowest resistance and the lowest inductance in the ground circuit. This is important to reduce voltage spikes in the ground circuit resulting from the high speed digital current spikes. The magnitude of digitally induced voltage spikes may be hundreds of times larger than the analog signal the device is required to digitize. 7. Use a short, wide, low inductance trace to connect the V DD power supply pin to the 3 V power supply. Depending on the application, a double–sided PCB with VDD bypass capacitors to the VSS ground plane, as described above, may complete the low impedance coupling for the power supply. For a multilayer PC board with a power plane, connecting all of the V DD pins to the power plane would be the optimal power distribution method. The integrated circuit layout and packaging considerations for the 3 V V DD power circuit are essentially the same as for the VSS ground circuit. 8. The VAG pin is the reference for all analog signal processing. In some applications the audio signal to be digitized may be referenced to the VSS ground. To reduce the susceptibility to noise at the input of the ADC section, the three–terminal op amp may be used in a differential to single–ended circuit to provide level conversion from the VSS ground to the VAG ground with noise cancellation. The op amp may be used for more than 30 dB of gain in microphone interface circuits, which will require a compact layout with minimum trace lengths as well as isolation from noise sources. It is recommended that the layout be as symmetrical as possible to avoid any imbalances which would reduce the noise cancelling benefits of this differential op amp circuit. Refer to the application schematics for examples of this circuitry. For More Information On This Product, Go to: www.freescale.com MC145483 Freescale Semiconductor, Inc. fer to the application schematics for examples of this circuitry. The VAG pin cannot be used for ESD or line protection. Freescale Semiconductor, Inc... If possible, reference audio signals to the VAG pin instead of to the VSS pin. Handset receivers and telephone line interface circuits using transformers may be audio signal referenced completely to the VAG pin. Re- For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. MAXIMUM RATINGS (Voltages Referenced to VSS Pin) Rating Symbol Value Unit VDD – 0.5 to 6 V Voltage on Any Analog Input or Output Pin VSS – 0.3 to VDD + 0.3 V Voltage on Any Digital Input or Output Pin VSS – 0.3 to VDD + 0.3 V TA – 40 to + 85 °C Tstg – 85 to +150 °C DC Supply Voltage Operating Temperature Range Storage Temperature Range POWER SUPPLY (TA = – 40 to + 85°C) Characteristics Min Typ Max Unit 2.7 3.0 5.25 V (No Load, PI ≥ VDD – 0.5 V) (No Load, PI ≤ VDD – 1.0 V) — — 2.0 2.2 2.8 3.0 mA Power–Down Current (VIH for Logic Levels PDI = VSS Must be ≥ VDD – 0.5 V) FST and FSR = VSS, PDI = VDD — — 0.001 0.01 0.05 0.10 µA Symbol Min Max Unit DC Supply Voltage Freescale Semiconductor, Inc... Active Current Dissipation (VDD = 3 V) DIGITAL LEVELS (VDD = 2.7 to 3.6 V, VSS = 0 V, TA = – 40 to + 85°C) Characteristics Input Low Voltage VIL — 0.6 V Input High Voltage VIH 2.2 — V Output Low Voltage (DT Pin, IOL= 1.6 mA) VOL — 0.4 V Output High Voltage (DT Pin, IOH = – 1.6 mA) VOH VDD – 0.5 — V Input Low Current (VSS ≤ Vin ≤ VDD) IIL – 10 + 10 µA Input High Current (VSS ≤ Vin ≤ VDD) IIH – 10 + 10 µA Output Current in High Impedance State (VSS ≤ DT ≤ VDD) IOZ – 10 + 10 µA Cin — 10 pF Cout — 15 pF Input Capacitance of Digital Pins (Except DT) Input Capacitance of DT Pin when High–Z For More Information On This Product, Go to: www.freescale.com MC145483 Freescale Semiconductor, Inc. ANALOG ELECTRICAL CHARACTERISTICS (VDD = 2.7 to 3.6 V, VSS = 0 V, TA = – 40 to + 85°C) Min Typ Max Unit Input Current Characteristics TI+, TI– — ± 0.1 ± 1.0 µA Input Resistance to VAG (VAG – 0.3 V ≤ Vin ≤ VAG + 0.3 V) TI+, TI– 10 — — MΩ Input Capacitance TI+, TI– — — 10 pF Input Offset Voltage of TG Op Amp TI+, TI– — — ±5 mV Input Common Mode Voltage Range TI+, TI– 1.2 VDD – 1.2 V Input Common Mode Rejection Ratio TI+, TI– — 60 — dB Gain Bandwidth Product (10 kHz) of TG Op Amp (RL ≥ 10 kΩ) — 2000 — kHz DC Open Loop Gain of TG Op Amp (RL ≥ 10 kΩ) — 95 — dB Equivalent Input Noise (C–Message) Between TI+ and TI– at TG — – 28 — dBrnC Output Load Capacitance for TG Op Amp 0 — 100 pF 0.4 — VDD – 0.4 V ± 1.0 — — mA Freescale Semiconductor, Inc... Output Voltage Range for TG (RL = 2 kΩ to VAG) Output Current (0.5 V ≤ Vout ≤ VDD – 0.5 V) TG, RO– Output Load Resistance to VAG TG, RO– 2 — — kΩ Output Impedance RO– — 1 — Ω Output Load Capacitance RO– 0 — 200 pF — — ± 25 mV VDD/2 – 0.05 VDD/2 VDD/2 + 0.05 V ± 1.0 ±2 — mA 40 40 60 60 — — dBC PI — ± 0.05 ± 1.0 µA Input Resistance (VAG – 0.3 V ≤ PI ≤ VAG + 0.3 V) PI 10 — — MΩ Input Offset Voltage PI — — ± 20 mV — — ± 50 mV ± 10 — — mA PO+ or PO– Output Resistance (Inverted Unity Gain for PO–) — 1 — Ω Gain Bandwidth Product (10 kHz, Open Loop for PO–) — 1000 — kHz DC Output Offset Voltage of RO– Referenced to VAG VAG Output Voltage Referenced to VSS (No Load) VAG Output Current with ± 25 mV Change in Output Voltage Power Supply Rejection Ratio (0 to 100 kHz @100 mVrms Applied to VDD, C–Message Weighting, All Analog Signals Referenced to VAG Pin) Transmit Receive Power Drivers PI, PO+, PO– Input Current (VAG – 0.3 V ≤ PI ≤ VAG + 0.3 V) Output Offset Voltage of PO+ Relative to PO– (Inverted Unity Gain for PO–) Output Current (VSS + 0.4 V ≤ PO+ or PO– ≤ VDD – 0.4 V) Load Capacitance (PO+ or PO– to VAG, or PO+ to PO–) 0 — 1000 pF – 0.2 0 + 0.2 dB Total Signal to Distortion at PO+ and PO– with a Differential Load of: 300 Ω 100 nF in series with ≥ 20 Ω Current Limitation ± 10 mA ≥ 100 Ω 45 — — 60 40 40 — — — dBC Power Supply Rejection Ratio (0 to 25 kHz @ 50 mVrms Applied to VDD. PO– Connected to PI. Differential or Measured Referenced to VAG Pin.) 40 — 55 40 — — dB Gain of PO+ Relative to PO– (RL = 300 Ω, + 3 dBm0, 1 kHz) 0 to 4 kHz 4 to 25 kHz For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. ANALOG TRANSMISSION PERFORMANCE (VDD = 2.7 to 3.6 V, VSS = 0 V, All Analog Signals Referenced to VAG, 0 dBm0 = 0.436 Vrms = – 5 dBm @ 600 Ω, FST = FSR = 8 kHz, BCLKT = MCLK = 2.048 MHz Synchronous Operation, TA = – 40 to + 85°C, Unless Otherwise Noted) A/D Characteristics D/A Min Typ Max Min Typ Max Units – 0.25 — + 0.25 – 0.25 — + 0.25 dB — ± 0.02 ± 0.05 — ± 0.02 ± 0.05 dB — ± 0.02 ± 0.05 — ± 0.02 ± 0.05 dB + 3 dBm0 0 dBm0 – 10 dBm0 – 20 dBm0 – 30 dBm0 –40 dBm0 –50 dBm0 –60 dBm0 45 50 54 51 41 32 22 12 55 60 60 54 44 34 24 14 — — — — — — — — 50 48 45 48 45 35 25 15 60 63 60 55 47 37 27 17 — — — — — — — — dBC (C–Message Weighted) (Psophometric Weighted) — — — — 18 – 72 — — — — 14 – 76 dBr nc0 dBm0p — — — — – 1.0 – 0.20 — – 0.35 – 0.8 — — — — — — –3 — — — — — –3 — — – 40 – 30 – 26 — – 0.4 + 0.20 ± 0.20 + 0.20 0 — – 14 – 32 – 0.5 – 0.5 – 0.5 – 0.5 – 0.5 – 0.20 — – 0.35 – 0.85 — — — — — — — — — — — — –3 — — 0 0 0 0 0 + 0.20 ± 0.20 + 0.20 0 — – 14 – 30 dB Out–of–Band Spurious at VAG Ref (300 to 3400 Hz @ 0 dBm0 in) 4600 to 7600 Hz 7600 to 8400 Hz 8400 to 100,000 Hz — — — — — — — — — — — — — — — – 30 – 40 – 30 dB Idle Channel Noise Selective (8 kHz, Input = VAG, 30 Hz Bandwidth) — — — — — – 70 dBm0 Absolute Delay (1600 Hz) (HB = 0) — — 315 — — 205 µs — — — — — — — — — — — — — — 210 130 70 35 70 95 145 – 40 – 40 – 40 – 30 — — — — — — — — — — — — — — 85 110 175 µs — – 90 – 75 — – 90 – 75 dB Absolute Gain (0 dBm0 @ 1.02 kHz, TA = 25°C, VDD = 3.0 V) Absolute Gain Variation with Temperature @ 3.0 V Referenced to 25°C – 40 to + 85°C Absolute Gain Variation with Power Supply (TA = 25°C) Freescale Semiconductor, Inc... Total Distortion, 1.02 kHz Tone (C–Message Weighting) Idle Channel Noise (For A/D, See Note 1) Frequency Response (Relative to 1.02 kHz @ 0 dBm0) (HB = 0) 15 Hz 50 Hz 60 Hz 165 Hz 200 Hz 300 to 3000 Hz 3000 – 3200 Hz 3300 Hz 3400 Hz 3600 Hz 4000 Hz 4600 Hz to 100 kHz Group Delay Referenced to 1600 Hz 500 to 600 Hz 600 to 800 Hz 800 to 1000 Hz 1000 to 1600 Hz 1600 to 2600 Hz 2600 to 2800 Hz 2800 to 3000 Hz Crosstalk of 1020 Hz @ 0 dBm0 from A/D or D/A (Note 2) NOTES: 1. Extrapolated from a 1020 Hz @ – 50 dBm0 distortion measurement to correct for encoder enhancement. 2. Selectively measured while stimulated with 2667 Hz @ – 50 dBm0. For More Information On This Product, Go to: www.freescale.com MC145483 Freescale Semiconductor, Inc. DIGITAL SWITCHING CHARACTERISTICS, LONG FRAME SYNC AND SHORT FRAME SYNC (VDD = 2.7 to 3.6 V, VSS = 0 V, All Digital Signals Referenced to VSS, TA = – 40 to + 85°C, CL = 150 pF, Unless Otherwise Noted) Freescale Semiconductor, Inc... Ref. No. Characteristics Min Typ Max Unit 1 Master Clock Frequency for MCLK — — — — — — — 256 512 1536 1544 2048 2560 4096 — — — — — — — kHz 1 MCLK Duty Cycle for 256 kHz Operation 45 — 55 % 2 Minimum Pulse Width High for MCLK (Frequencies of 512 kHz or Greater) 50 — — ns 3 Minimum Pulse Width Low for MCLK (Frequencies of 512 kHz or Greater) 50 — — ns 4 Rise Time for All Digital Signals — — 50 ns 5 Fall Time for All Digital Signals — — 50 ns 6 Setup Time from MCLK Low to FST High 50 — — ns 7 Setup Time from FST High to MCLK Low 50 — — ns 8 Bit Clock Data Rate for BCLKT or BCLKR 256 — 4096 kHz 9 Minimum Pulse Width High for BCLKT or BCLKR 50 — — ns 10 Minimum Pulse Width Low for BCLKT or BCLKR 50 — — ns 11 Hold Time from BCLKT (BCLKR) Low to FST (FSR) High 20 — — ns 12 Setup Time for FST (FSR) High to BCLKT (BCLKR) Low 80 — — ns 13 Setup Time from DR Valid to BCLKR Low 0 — — ns 14 Hold Time from BCLKR Low to DR Invalid 50 — — ns LONG FRAME SPECIFIC TIMING 15 Hold Time from 2nd Period of BCLKT (BCLKR) Low to FST (FSR) Low 50 — — ns 16 Delay Time from FST or BCLKT, Whichever is Later, to DT for Valid MSB Data — — 60 ns 17 Delay Time from BCLKT High to DT for Valid Data — — 60 ns 18 Delay Time from the Later of the 13th (16th for Sign–Extended Mode) BCLKT Falling Edge, or the Falling Edge of FST to DT Output High Impedance 10 — 60 ns 19 Minimum Pulse Width Low for FST or FSR 50 — — ns SHORT FRAME SPECIFIC TIMING 20 Hold Time from BCLKT (BCLKR) Low to FST (FSR) Low 50 — — ns 21 Setup Time from FST (FSR) Low to MSB Period of BCLKT (BCLKR) Low 50 — — ns 22 Delay Time from BCLKT High to DT Data Valid 10 — 60 ns 23 Delay Time from the 13th (16th for Sign–Extended Mode) BCLKT Low to DT Output High Impedance 10 — 60 ns For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. 1 7 4 3 6 5 2 MCLK 8 1 BCLKT 2 3 4 5 12 6 7 13 14 9 11 15 10 FST 16 18 17 18 16 1 Freescale Semiconductor, Inc... DT 2 3 4 5 6 13 8 BCLKR (BCLKT) 1 2 3 11 4 5 15 6 7 13 14 9 12 10 FSR 14 13 DR 1 2 3 4 5 6 13 Figure 3. Long Frame Sync Timing For More Information On This Product, Go to: www.freescale.com MC145483 Freescale Semiconductor, Inc. 1 7 4 3 6 5 2 MCLK 12 8 1 BCLKT 2 3 4 5 6 7 13 14 9 20 21 11 10 FST 23 22 22 1 Freescale Semiconductor, Inc... DT 2 3 4 5 6 13 8 1 BCLKR 2 3 4 5 20 6 7 13 9 21 11 10 12 FSR 14 13 DR 1 2 3 4 5 6 Figure 4. Short Frame Sync Timing For More Information On This Product, Go to: www.freescale.com 13 14 Freescale Semiconductor, Inc. 1 2 0.1 µF 3 2X20 k AUDIO OUT 4 – + 5 6 +3V 7 0.1 µF 8 9 Freescale Semiconductor, Inc... 10 VAG Ref VAG RO– TI+ PI TI– 17 PO+ HB 16 FSR FST DT DR BCLKT BCLKR MCLK PDI 10 kΩ 1.0 µF ANALOG IN Y 18 TG VSS 10 kΩ 19 PO– VDD 0.01 µF 20 10 kΩ 10 kΩ 1.0 µF 15 14 8 kHz 13 PCM OUT 12 2.048 MHz 11 PCM IN Figure 5. MC145483 Test Circuit — Signals Referenced to VAG Pin 0.1 µF 1 AUDIO OUT 2 RL ≥ 2 kΩ 68 µF AUDIO OUT RL ≥ 150 Ω 2X20 k + 3 4 5 10 kΩ +3V 6 7 0.1 µF 8 9 10 VAG Ref VAG TI+ PI TI– PO– TG PO+ HB 16 VSS FSR FST DR DT BCLKR PDI BCLKT MCLK 10 kΩ 10 kΩ 19 RO– VDD 0.01 µF 20 1.0 µF 18 17 10 kΩ 10 kΩ ANALOG IN 1.0 µF 15 14 13 12 Y 8 kHz PCM OUT 2.048 MHz 11 PCM IN Figure 6. MC145483 Test Circuit — Signals Referenced to VSS For More Information On This Product, Go to: www.freescale.com MC145483 Freescale Semiconductor, Inc. +3 V 1 kΩ SIDETONE 0.01 µF 0.1 µF 68 µF 1 kΩ 420 pF 1 VAG Ref 2 3 4 REC 5 6 +3V Freescale Semiconductor, Inc... 7 0.1 µF 8 9 10 VAG 20 RO– TI+ PI TI– PO– TG PO+ HB VDD VSS FSR FST DR DT 13 BCLKT 12 BCLKR MCLK PDI 75 kΩ 1 kΩ 0.1 µF 19 17 MIC 1 kΩ 18 0.1 µF 75 kΩ 16 15 420 pF 14 8 kHz PCM OUT 2.048 MHz 11 PCM IN Figure 7. MC145483 Handset Interface 1.0 µF R0 = 600 Ω 10 kΩ 0.1 µF TIP 1 2X20 k N = 0.5 1/4 R0 2 3 4 N = 0.5 5 – 48 V N = 0.5 +3V 6 7 RING 0.1 µF 8 9 10 VAG Ref VAG RO– TI+ PI TI– PO– TG PO+ HB VDD VSS FSR FST DR DT BCLKR PDI BCLKT MCLK 20 19 18 17 0.1 µF 20 kΩ 16 15 14 13 12 8 kHz PCM OUT 2.048 MHz 11 PCM IN Figure 8. MC145483 Step–Up Transformer Line Interface For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. PACKAGE DIMENSIONS DW SUFFIX SOG PACKAGE CASE 751D–04 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.150 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. –A– 20 11 –B– 10X P 0.010 (0.25) 1 B M 10 20X Freescale Semiconductor, Inc... M D 0.010 (0.25) M T A B S DIM A B C D F G J K M P R J S F R X 45 _ C –T– 18X G SEATING PLANE MILLIMETERS MIN MAX 12.65 12.95 7.40 7.60 2.35 2.65 0.35 0.49 0.50 0.90 1.27 BSC 0.25 0.32 0.10 0.25 0_ 7_ 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.499 0.510 0.292 0.299 0.093 0.104 0.014 0.019 0.020 0.035 0.050 BSC 0.010 0.012 0.004 0.009 0_ 7_ 0.395 0.415 0.010 0.029 M K SD SUFFIX SSOP CASE 940C–02 20 NOTES: 1. CONTROLLING DIMENSION: MILLIMETER. 2. DIMENSIONS AND TOLERANCES PER ANSI Y14.5M, 1982. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15MM PER SIDE. 4. DIMENSION IS THE LENGTH OF TERMINAL FOR SOLDERING TO A SUBSTRATE. 5. TERMINAL POSITIONS ARE SHOWN FOR REFERENCE ONLY. 6. THE LEAD WIDTH DIMENSION DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08MM TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION. 11 B –R– 1 C 10 0.076 (0.003) A –P– N 0.25 (0.010) M R M L J M G H D 0.120 (0.005) F NOTE 4 M T P DIM A B C D F G H J L M N MILLIMETERS MIN MAX 7.10 7.30 5.20 5.38 1.75 1.99 0.25 0.38 0.65 1.00 0.65 BSC 0.59 0.75 0.10 0.20 7.65 7.90 0_ 8_ 0.05 0.21 INCHES MIN MAX 0.280 0.287 0.205 0.212 0.069 0.078 0.010 0.015 0.026 0.039 0.026 BSC 0.023 0.030 0.004 0.008 0.301 0.311 0_ 8_ 0.002 0.008 S For More Information On This Product, Go to: www.freescale.com MC145483 Freescale Semiconductor, Inc. DT SUFFIX TSSOP CASE 948E–02 20X 0.15 (0.006) T U K REF 0.10 (0.004) S M T U S V NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE –W–. S K K1 2X L/2 20 11 B –U– L PIN 1 IDENT J J1 ÍÍÍ ÍÍÍ ÍÍÍ SECTION N–N 1 10 0.25 (0.010) N Freescale Semiconductor, Inc... 0.15 (0.006) T U S M A –V– N F DETAIL E –W– C D 0.100 (0.004) –T– SEATING G H DETAIL E PLANE For More Information On This Product, Go to: www.freescale.com DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 6.40 6.60 4.30 4.50 1.20 ––– 0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.252 0.260 0.169 0.177 0.047 ––– 0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ Freescale Semiconductor, Inc. FC SUFFIX QFN CASE 1311–02 PIN 1 INDEX AREA 0.1 5 A 0.1 C 2X M C 0.1 C 2X G 1.0 1.00 0.8 0.75 0.05 C 5 6 (0.25) 0.05 0.00 (0.5) DETAIL G C SEATING PLANE VIEW ROTATED 90 ° CLOCKWISE Freescale Semiconductor, Inc... M B 0.1 C A B DETAIL M PIN 1 INDEX 3.25 2.95 25 EXPOSED DIE ATTACH PAD 32 24 NOTES: 1. ALL DIMENSIONS ARE IN MILLIMETERS. 2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 3. THE COMPLETE JEDEC DESIGNATOR FOR THIS PACKAGE IS: HF–PQFP–N. 4. CORNER CHAMFER MAY NOT BE PRESENT. DIMENSIONS OF OPTIONAL FEATURES ARE FOR REFERENCE ONLY. 5. COPLANARITY APPLIES TO LEADS, CORNER LEADS, AND DIE ATTACH PAD. 6. FOR ANVIL SINGULATED QFN PACKAGES, MAXIMUM DRAFT ANGLE IS 12°. 1 0.25 3.25 2.95 0.1 C A B 16 32X 0.5 28X 0.30 0.18 0.1 M C A B 0.05 M C 8 17 N 9 0.5 0.3 32X VIEW M–M (45 ° ) 0.60 0.24 (1.73) 32X 0.065 0.015 0.60 0.24 (0.25) DETAIL N DETAIL N CORNER CONFIGURATION OPTION PREFERRED CORNER CONFIGURATION 4 4 ° 1.6 1.5 DETAIL T (90 ) BACKSIDE PIN 1 INDEX 0.475 0.425 2X 0.39 0.31 R 0.25 0.15 2X 0.1 0.0 DETAIL M DETAIL M DETAIL T PREFERRED PIN 1 BACKSIDE INDEX BACKSIDE PIN 1 INDEX OPTION PREFERRED PIN 1 BACKSIDE INDEX For More Information On This Product, Go to: www.freescale.com MC145483 Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... This page intentionally left blank. For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... This page intentionally left blank. For More Information On This Product, Go to: www.freescale.com MC145483 Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. 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