Freescale Semiconductor Data Sheet: Technical Data Document Number: KL25P80M48SF0 Rev. 3, 9/19/2012 KL25P80M48SF0 KL25 Sub-Family Data Sheet Supports the following: MKL25Z32VFM4, MKL25Z64VFM4, MKL25Z128VFM4, MKL25Z32VFT4, MKL25Z64VFT4, MKL25Z128VFT4, MKL25Z32VLH4, MKL25Z64VLH4, MKL25Z128VLH4, MKL25Z32VLK4, MKL25Z64VLK4, and MKL25Z128VLK4 Features • Operating Characteristics – Voltage range: 1.71 to 3.6 V – Flash write voltage range: 1.71 to 3.6 V – Temperature range (ambient): -40 to 105°C • Performance – Up to 48 MHz ARM® Cortex-M0+ core • Memories and memory interfaces – Up to 128 KB program flash memory – Up to 16 KB RAM • Clocks – 32 kHz to 40 kHz or 3 MHz to 32 MHz crystal oscillator – Multi-purpose clock source • System peripherals – Nine low-power modes to provide power optimization based on application requirements – 4-channel DMA controller, supporting up to 63 request sources – COP Software watchdog – Low-leakage wakeup unit – SWD interface and Micro Trace buffer – Bit Manipulation Engine (BME) • Security and integrity modules – 80-bit unique identification (ID) number per chip • Human-machine interface – Low-power hardware touch sensor interface (TSI) – General-purpose input/output • Analog modules – 16-bit SAR ADC – 12-bit DAC – Analog comparator (CMP) containing a 6-bit DAC and programmable reference input • Timers – Six channel Timer/PWM (TPM) – Two 2-channel Timer/PWM (TPM) – Periodic interrupt timers – 16-bit low-power timer (LPTMR) – Real-time clock • Communication interfaces – USB full-/low-speed On-the-Go controller with onchip transceiver and 5 V to 3.3 V regulator – Two 8-bit SPI modules – Two I2C modules – One low power UART module – Two UART modules Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. © 2012 Freescale Semiconductor, Inc. Table of Contents 1 Ordering parts...........................................................................3 5.3.1 Device clock specifications...................................21 1.1 Determining valid orderable parts......................................3 5.3.2 General Switching Specifications..........................22 2 Part identification......................................................................3 5.4 Thermal specifications.......................................................22 2.1 Description.........................................................................3 5.4.1 Thermal operating requirements...........................22 2.2 Format...............................................................................3 5.4.2 Thermal attributes.................................................22 2.3 Fields.................................................................................3 6 Peripheral operating requirements and behaviors....................23 2.4 Example............................................................................4 6.1 Core modules....................................................................23 3 Terminology and guidelines......................................................4 6.1.1 SWD Electricals ...................................................23 3.1 Definition: Operating requirement......................................4 6.2 System modules................................................................25 3.2 Definition: Operating behavior...........................................4 6.3 Clock modules...................................................................25 3.3 Definition: Attribute............................................................5 6.3.1 MCG specifications...............................................25 3.4 Definition: Rating...............................................................5 6.3.2 Oscillator electrical specifications.........................27 3.5 Result of exceeding a rating..............................................6 3.6 Relationship between ratings and operating 6.4 Memories and memory interfaces.....................................29 6.4.1 Flash electrical specifications................................29 requirements......................................................................6 6.5 Security and integrity modules..........................................30 3.7 Guidelines for ratings and operating requirements............7 6.6 Analog...............................................................................31 3.8 Definition: Typical value.....................................................7 6.6.1 ADC electrical specifications.................................31 3.9 Typical Value Conditions...................................................8 6.6.2 CMP and 6-bit DAC electrical specifications.........35 4 Ratings......................................................................................8 6.6.3 12-bit DAC electrical characteristics.....................36 4.1 Thermal handling ratings...................................................8 6.7 Timers................................................................................39 4.2 Moisture handling ratings..................................................9 6.8 Communication interfaces.................................................39 4.3 ESD handling ratings.........................................................9 6.8.1 USB electrical specifications.................................39 4.4 Voltage and current operating ratings...............................9 6.8.2 USB VREG electrical specifications......................39 5 General.....................................................................................9 6.8.3 SPI switching specifications..................................40 5.1 AC electrical characteristics..............................................10 6.8.4 I2C.........................................................................44 5.2 Nonswitching electrical specifications...............................10 6.8.5 UART....................................................................44 5.2.1 Voltage and current operating requirements.........10 6.9 Human-machine interfaces (HMI)......................................45 5.2.2 LVD and POR operating requirements.................11 5.2.3 Voltage and current operating behaviors..............12 7 Dimensions...............................................................................45 5.2.4 Power mode transition operating behaviors..........13 7.1 Obtaining package dimensions.........................................45 5.2.5 Power consumption operating behaviors..............13 8 Pinout........................................................................................45 5.2.6 EMC radiated emissions operating behaviors.......20 8.1 KL25 Signal Multiplexing and Pin Assignments................45 5.2.7 Designing with radiated emissions in mind...........21 8.2 KL25 Pinouts.....................................................................48 5.2.8 Capacitance attributes..........................................21 9 Revision History........................................................................52 6.9.1 TSI electrical specifications...................................45 5.3 Switching specifications.....................................................21 KL25 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012. 2 Freescale Semiconductor, Inc. Ordering parts 1 Ordering parts 1.1 Determining valid orderable parts Valid orderable part numbers are provided on the web. To determine the orderable part numbers for this device, go to www.freescale.com and perform a part number search for the following device numbers: PKL25 and MKL25 2 Part identification 2.1 Description Part numbers for the chip have fields that identify the specific part. You can use the values of these fields to determine the specific part you have received. 2.2 Format Part numbers for this device have the following format: Q KL## A FFF R T PP CC N 2.3 Fields This table lists the possible values for each field in the part number (not all combinations are valid): Field Description Values Q Qualification status • M = Fully qualified, general market flow • P = Prequalification KL## Kinetis family • KL25 A Key attribute • Z = Cortex-M0+ FFF Program flash memory size • • • • 32 = 32 KB 64 = 64 KB 128 = 128 KB 256 = 256 KB Table continues on the next page... KL25 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012. Freescale Semiconductor, Inc. 3 Terminology and guidelines Field Description Values R Silicon revision • (Blank) = Main • A = Revision after main T Temperature range (°C) • V = –40 to 105 PP Package identifier • • • • CC Maximum CPU frequency (MHz) • 4 = 48 MHz N Packaging type • R = Tape and reel • (Blank) = Trays FM = 32 QFN (5 mm x 5 mm) FT = 48 QFN (7 mm x 7 mm) LH = 64 LQFP (10 mm x 10 mm) LK = 80 LQFP (12 mm x 12 mm) 2.4 Example This is an example part number: MKL25Z64VLK4 3 Terminology and guidelines 3.1 Definition: Operating requirement An operating requirement is a specified value or range of values for a technical characteristic that you must guarantee during operation to avoid incorrect operation and possibly decreasing the useful life of the chip. 3.1.1 Example This is an example of an operating requirement, which you must meet for the accompanying operating behaviors to be guaranteed: Symbol VDD Description 1.0 V core supply voltage Min. 0.9 Max. Unit 1.1 V KL25 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012. 4 Freescale Semiconductor, Inc. Terminology and guidelines 3.2 Definition: Operating behavior An operating behavior is a specified value or range of values for a technical characteristic that are guaranteed during operation if you meet the operating requirements and any other specified conditions. 3.2.1 Example This is an example of an operating behavior, which is guaranteed if you meet the accompanying operating requirements: Symbol IWP Description Min. Digital I/O weak pullup/ 10 pulldown current Max. 130 Unit µA 3.3 Definition: Attribute An attribute is a specified value or range of values for a technical characteristic that are guaranteed, regardless of whether you meet the operating requirements. 3.3.1 Example This is an example of an attribute: Symbol CIN_D Description Input capacitance: digital pins Min. — Max. 7 Unit pF 3.4 Definition: Rating A rating is a minimum or maximum value of a technical characteristic that, if exceeded, may cause permanent chip failure: • Operating ratings apply during operation of the chip. • Handling ratings apply when the chip is not powered. KL25 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012. Freescale Semiconductor, Inc. 5 Terminology and guidelines 3.4.1 Example This is an example of an operating rating: Symbol VDD Description Min. 1.0 V core supply voltage Max. –0.3 Unit 1.2 V 3.5 Result of exceeding a rating 40 Failures in time (ppm) 30 The likelihood of permanent chip failure increases rapidly as soon as a characteristic begins to exceed one of its operating ratings. 20 10 0 Operating rating Measured characteristic 3.6 Relationship between ratings and operating requirements ra pe tin gr g tin ( in. t (m ) n. mi a gr tin ra pe ) O O t (m e ir qu e n me gr tin O ra pe ax .) e ir qu e n me a gr tin ra pe g tin ax (m .) O Fatal range Degraded operating range Normal operating range Degraded operating range Fatal range Expected permanent failure - No permanent failure - Possible decreased life - Possible incorrect operation - No permanent failure - Correct operation - No permanent failure - Possible decreased life - Possible incorrect operation Expected permanent failure –∞ ∞ Operating (power on) n Ha ng dli ng ati ) in. (m r nd Ha g lin ing rat ax (m .) Fatal range Handling range Fatal range Expected permanent failure No permanent failure Expected permanent failure –∞ ∞ Handling (power off) KL25 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012. 6 Freescale Semiconductor, Inc. Terminology and guidelines 3.7 Guidelines for ratings and operating requirements Follow these guidelines for ratings and operating requirements: • Never exceed any of the chip’s ratings. • During normal operation, don’t exceed any of the chip’s operating requirements. • If you must exceed an operating requirement at times other than during normal operation (for example, during power sequencing), limit the duration as much as possible. 3.8 Definition: Typical value A typical value is a specified value for a technical characteristic that: • Lies within the range of values specified by the operating behavior • Given the typical manufacturing process, is representative of that characteristic during operation when you meet the typical-value conditions or other specified conditions Typical values are provided as design guidelines and are neither tested nor guaranteed. 3.8.1 Example 1 This is an example of an operating behavior that includes a typical value: Symbol IWP Description Digital I/O weak pullup/pulldown current Min. 10 Typ. 70 Max. 130 Unit µA 3.8.2 Example 2 This is an example of a chart that shows typical values for various voltage and temperature conditions: KL25 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012. Freescale Semiconductor, Inc. 7 Ratings 5000 4500 4000 TJ IDD_STOP (μA) 3500 150 °C 3000 105 °C 2500 25 °C 2000 –40 °C 1500 1000 500 0 0.90 0.95 1.00 1.05 1.10 VDD (V) 3.9 Typical Value Conditions Typical values assume you meet the following conditions (or other conditions as specified): Symbol Description Value Unit TA Ambient temperature 25 °C VDD 3.3 V supply voltage 3.3 V 4 Ratings 4.1 Thermal handling ratings Symbol Description Min. Max. Unit Notes TSTG Storage temperature –55 150 °C 1 TSDR Solder temperature, lead-free — 260 °C 2 1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life. 2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. KL25 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012. 8 Freescale Semiconductor, Inc. General 4.2 Moisture handling ratings Symbol MSL Description Moisture sensitivity level Min. Max. Unit Notes — 3 — 1 1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. 4.3 ESD handling ratings Symbol Description Min. Max. Unit Notes VHBM Electrostatic discharge voltage, human body model -2000 +2000 V 1 VCDM Electrostatic discharge voltage, charged-device model -500 +500 V 2 Latch-up current at ambient temperature of 105°C -100 +100 mA ILAT 1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM). 2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components. 4.4 Voltage and current operating ratings Symbol Description Min. Max. Unit VDD Digital supply voltage –0.3 3.8 V IDD Digital supply current — 120 mA –0.3 3.6 V –0.3 VDD + 0.3 V –25 25 mA VDIO VAIO ID Digital pin input voltage (except RESET) Analog pins1and RESET pin input voltage Instantaneous maximum current single pin limit (applies to all port pins) VDDA Analog supply voltage VDD – 0.3 VDD + 0.3 V VUSB_DP USB_DP input voltage –0.3 3.63 V VUSB_DM USB_DM input voltage –0.3 3.63 V VREGIN USB regulator input –0.3 6.0 V 1. Analog pins are defined as pins that do not have an associated general purpose I/O port function. 5 General KL25 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012. Freescale Semiconductor, Inc. 9 General 5.1 AC electrical characteristics Unless otherwise specified, propagation delays are measured from the 50% to the 50% point, and rise and fall times are measured at the 20% and 80% points, as shown in the following figure. Figure 1. Input signal measurement reference All digital I/O switching characteristics, unless otherwise specified, assumes: 1. output pins • have CL=30pF loads, • are slew rate disabled, and • are normal drive strength 5.2 Nonswitching electrical specifications 5.2.1 Voltage and current operating requirements Table 1. Voltage and current operating requirements Symbol Description Min. Max. Unit VDD Supply voltage 1.71 3.6 V VDDA Analog supply voltage 1.71 3.6 V VDD – VDDA VDD-to-VDDA differential voltage –0.1 0.1 V VSS – VSSA VSS-to-VSSA differential voltage –0.1 0.1 V • 2.7 V ≤ VDD ≤ 3.6 V 0.7 × VDD — V • 1.7 V ≤ VDD ≤ 2.7 V 0.75 × VDD — V • 2.7 V ≤ VDD ≤ 3.6 V — 0.35 × VDD V • 1.7 V ≤ VDD ≤ 2.7 V — 0.3 × VDD V VIH VIL Notes Input high voltage Input low voltage Table continues on the next page... KL25 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012. 10 Freescale Semiconductor, Inc. General Table 1. Voltage and current operating requirements (continued) Symbol Description VHYS Input hysteresis IICDIO Digital pin negative DC injection current — single pin Min. Max. Unit 0.06 × VDD — V -5 — mA 1 • VIN < VSS-0.3V IICAIO Analog2 pin DC injection current — single pin 3 mA • VIN < VSS-0.3V (Negative current injection) • VIN > VDD+0.3V (Positive current injection) IICcont Contiguous pin DC injection current —regional limit, includes sum of negative injection currents or sum of positive injection currents of 16 contiguous pins • Negative current injection • Positive current injection VRAM Notes VDD voltage required to retain RAM -5 — — +5 -25 — — +25 1.2 — mA V 1. All digital I/O pins are internally clamped to VSS through a ESD protection diode. There is no diode connection to VDD. If VIN greater than VDIO_MIN (=VSS-0.3V) is observed, then there is no need to provide current limiting resistors at the pads. If this limit cannot be observed then a current limiting resistor is required. The negative DC injection current limiting resistor is calculated as R=(VDIO_MIN-VIN)/|IIC|. 2. Analog pins are defined as pins that do not have an associated general purpose I/O port function. 3. All analog pins are internally clamped to VSS and VDD through ESD protection diodes. If VIN is greater than VAIO_MIN (=VSS-0.3V) and VIN is less than VAIO_MAX(=VDD+0.3V) is observed, then there is no need to provide current limiting resistors at the pads. If these limits cannot be observed then a current limiting resistor is required. The negative DC injection current limiting resistor is calculated as R=(VAIO_MIN-VIN)/|IIC|. The positive injection current limiting resistor is calcualted as R=(VIN-VAIO_MAX)/|IIC|. Select the larger of these two calculated resistances. 5.2.2 LVD and POR operating requirements Table 2. VDD supply LVD and POR operating requirements Symbol Description Min. Typ. Max. Unit VPOR Falling VDD POR detect voltage 0.8 1.1 1.5 V VLVDH Falling low-voltage detect threshold — high range (LVDV=01) 2.48 2.56 2.64 V Low-voltage warning thresholds — high range 1 VLVW1H • Level 1 falling (LVWV=00) 2.62 2.70 2.78 V VLVW2H • Level 2 falling (LVWV=01) 2.72 2.80 2.88 V VLVW3H • Level 3 falling (LVWV=10) 2.82 2.90 2.98 V VLVW4H • Level 4 falling (LVWV=11) 2.92 3.00 3.08 V — ±60 — mV 1.54 1.60 1.66 V VHYSH Low-voltage inhibit reset/recover hysteresis — high range VLVDL Falling low-voltage detect threshold — low range (LVDV=00) Notes Table continues on the next page... KL25 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012. Freescale Semiconductor, Inc. 11 General Table 2. VDD supply LVD and POR operating requirements (continued) Symbol Description Min. Typ. Max. Unit Low-voltage warning thresholds — low range 1 VLVW1L • Level 1 falling (LVWV=00) 1.74 1.80 1.86 V VLVW2L • Level 2 falling (LVWV=01) 1.84 1.90 1.96 V VLVW3L • Level 3 falling (LVWV=10) 1.94 2.00 2.06 V VLVW4L • Level 4 falling (LVWV=11) 2.04 2.10 2.16 V — ±40 — mV VHYSL Low-voltage inhibit reset/recover hysteresis — low range Notes VBG Bandgap voltage reference 0.97 1.00 1.03 V tLPO Internal low power oscillator period — factory trimmed 900 1000 1100 μs 1. Rising thresholds are falling threshold + hysteresis voltage 5.2.3 Voltage and current operating behaviors Table 3. Voltage and current operating behaviors Symbol VOH VOH Description Min. Unit Output high voltage — Normal drive pad VDD – 0.5 — V • 1.71 V ≤ VDD ≤ 2.7 V, IOH = -1.5 mA VDD – 0.5 — V Output high voltage — High drive pad 1 • 2.7 V ≤ VDD ≤ 3.6 V, IOH = -18 mA VDD – 0.5 — V • 1.71 V ≤ VDD ≤ 2.7 V, IOH = -6 mA VDD – 0.5 — V — 100 mA Output high current total for all ports VOL Output low voltage — Normal drive pad Notes 1 • 2.7 V ≤ VDD ≤ 3.6 V, IOH = -5 mA IOHT VOL Max. 1 • 2.7 V ≤ VDD ≤ 3.6 V, IOL = 5 mA — 0.5 V • 1.71 V ≤ VDD ≤ 2.7 V, IOL = 1.5 mA — 0.5 V Output low voltage — High drive pad 1 • 2.7 V ≤ VDD ≤ 3.6 V, IOL = 18 mA — 0.5 V • 1.71 V ≤ VDD ≤ 2.7 V, IOL = 6 mA — 0.5 V Output low current total for all ports — 100 mA IIN Input leakage current (per pin) for full temperature range — 1 μA 2 IIN Input leakage current (per pin) at 25 °C — 0.025 μA 2 IIN Input leakage current (total all pins) for full temperature range — 65 μA 2 IOZ Hi-Z (off-state) leakage current (per pin) — 1 μA IOLT Table continues on the next page... KL25 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012. 12 Freescale Semiconductor, Inc. General Table 3. Voltage and current operating behaviors (continued) Symbol Description Min. Max. Unit Notes RPU Internal pullup resistors 20 50 kΩ 3 RPD Internal pulldown resistors 20 50 kΩ 4 1. PTB0, PTB1, PTD6, and PTD7 I/O have both high drive and normal drive capability selected by the associated PTx_PCRn[DSE] control bit. All other GPIOs are normal drive only. 2. Measured at VDD = 3.6 V 3. Measured at VDD supply voltage = VDD min and Vinput = VSS 4. Measured at VDD supply voltage = VDD min and Vinput = VDD 5.2.4 Power mode transition operating behaviors All specifications except tPOR and VLLSx→RUN recovery times in the following table assume this clock configuration: • CPU and system clocks = 48 MHz • Bus and flash clock = 24 MHz • FEI clock mode Table 4. Power mode transition operating behaviors Symbol tPOR Description After a POR event, amount of time from the point VDD reaches 1.8 V to execution of the first instruction across the operating temperature range of the chip. Min. Typ. Max. Unit — — 300 μs — 95 115 μs — 93 115 μs — 42 53 μs — 4 4.6 μs — 4 4.4 μs — 4 4.4 μs Notes • VLLS0 → RUN • VLLS1 → RUN • VLLS3 → RUN • LLS → RUN • VLPS → RUN • STOP → RUN KL25 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012. Freescale Semiconductor, Inc. 13 General 5.2.5 Power consumption operating behaviors Table 5. Power consumption operating behaviors Symbol IDDA Description Analog supply current IDD_RUNCO_ Run mode current in compute operation - 48 MHz core / 24 MHz flash/ bus disabled, LPTMR CM running using 4MHz internal reference clock, CoreMark® benchmark code executing from flash Min. Typ. Max. Unit Notes — — See note mA 1 2 — 6.4 — mA • at 3.0 V IDD_RUNCO Run mode current in compute operation - 48 MHz core / 24 MHz flash / bus clock disabled, code of while(1) loop executing from flash — • at 3.0 V IDD_RUN 4.1 5.2 mA Run mode current - 48 MHz core / 24 MHz bus and flash, all peripheral clocks disabled, code of while(1) loop executing from flash 3 — • at 3.0 V IDD_RUN 3 5.1 6.3 mA Run mode current - 48 MHz core / 24 MHz bus and flash, all peripheral clocks enabled, code of while(1) loop executing from flash 3, 4, • at 3.0 V • at 25 °C • at 125 °C IDD_WAIT Wait mode current - core disabled / 48 MHz system / 24 MHz bus / flash disabled (flash doze enabled), all peripheral clocks disabled • at 3.0 V IDD_WAIT Wait mode current - core disabled / 24 MHz system / 24 MHz bus / flash disabled (flash doze enabled), all peripheral clocks disabled • at 3.0 V IDD_PSTOP2 Stop mode current with partial stop 2 clocking option - core and system disabled / 10.5 MHz bus • at 3.0 V IDD_VLPRCO Very low power run mode current in compute operation - 4 MHz core / 0.8 MHz flash / bus clock disabled, code of while(1) loop executing from flash • at 3.0 V IDD_VLPR Very low power run mode current - 4 MHz core / 0.8 MHz bus and flash, all peripheral clocks disabled, code of while(1) loop executing from flash • at 3.0 V — 6.4 7.8 mA — 6.8 8.3 mA — 3.7 5.0 mA — 2.9 4.2 mA — 2.5 3.7 mA — 188 570 μA — 224 613 μA 3 3 3 5 5 Table continues on the next page... KL25 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012. 14 Freescale Semiconductor, Inc. General Table 5. Power consumption operating behaviors (continued) Symbol Description IDD_VLPR Very low power run mode current - 4 MHz core / 0.8 MHz bus and flash, all peripheral clocks enabled, code of while(1) loop executing from flash • at 3.0 V IDD_VLPW Very low power wait mode current - core disabled / 4 MHz system / 0.8 MHz bus / flash disabled (flash doze enabled), all peripheral clocks disabled • at 3.0 V IDD_STOP Stop mode current at 3.0 V IDD_VLPS IDD_LLS IDD_VLLS3 IDD_VLLS1 Min. Typ. Max. Unit — 300 745 μA — 135 496 μA at 25 °C — 345 490 at 50 °C — 357 827 at 70 °C — 392 869 at 85 °C — 438 927 at 105 °C — 551 1065 at 25 °C — 4.4 16 at 50 °C — 10 35 at 70 °C — 20 50 at 85 °C — 37 112 at 105 °C — 81 201 at 25 °C — 1.9 3.7 at 50 °C — 3.6 39 at 70 °C — 6.5 43 at 85 °C — 13 49 at 105 °C — 30 69 at 25 °C — 1.4 3.2 at 50 °C — 2.5 19 at 70 °C — 5.1 21 at 85 °C — 9.2 26 at 105 °C — 21 38 at 25°C — 0.7 1.4 at 50°C — 1.3 13 at 70°C — 2.3 14 at 85°C — 5.1 17 at 105°C — 13 25 Notes 5, 4 5 μA Very-low-power stop mode current at 3.0 V μA Low leakage stop mode current at 3.0 V μA Very low-leakage stop mode 3 current at 3.0 V μA Very low-leakage stop mode 1 current at 3.0V μA Table continues on the next page... KL25 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012. Freescale Semiconductor, Inc. 15 General Table 5. Power consumption operating behaviors (continued) Symbol IDD_VLLS0 Description Very low-leakage stop mode 0 current (SMC_STOPCTRL[PORPO] = 0) at 3.0 V at 25 °C at 50 °C at 70 °C at 85 °C Min. Typ. Max. — 381 943 — 956 11760 — 2370 13260 — 4800 15700 — 12410 23480 Unit Notes nA at 105 °C IDD_VLLS0 Very low-leakage stop mode 0 current (SMC_STOPCTRL[PORPO] = 1) at 3.0 V at 25 °C at 50 °C at 70 °C at 85 °C 6 — 176 860 — 760 3577 — 2120 11660 — 4500 18450 — 12130 22441 nA at 105 °C 1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See each module's specification for its supply current. 2. MCG configured for PEE mode. CoreMark benchmark compiled using Keil 4.54 with optimization level 3, optimized for time. 3. MCG configured for FEI mode. 4. Incremental current consumption from peripheral activity is not included. 5. MCG configured for BLPI mode. 6. No brownout Table 6. Low power mode peripheral adders — typical value Symbol Description Temperature (°C) Unit -40 25 50 70 85 105 IIREFSTEN4MHz 4 MHz internal reference clock (IRC) adder. Measured by entering STOP or VLPS mode with 4 MHz IRC enabled. 56 56 56 56 56 56 µA IIREFSTEN32KHz 32 kHz internal reference clock (IRC) adder. Measured by entering STOP mode with the 32 kHz IRC enabled. 52 52 52 52 52 52 µA IEREFSTEN4MHz External 4MHz crystal clock adder. Measured by entering STOP or VLPS mode with the crystal enabled. 206 228 237 245 251 258 uA Table continues on the next page... KL25 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012. 16 Freescale Semiconductor, Inc. General Table 6. Low power mode peripheral adders — typical value (continued) Symbol IEREFSTEN32KHz Description Temperature (°C) External 32 kHz crystal clock adder by means of the OSC0_CR[EREFSTEN and EREFSTEN] bits. Measured by entering all modes with the crystal enabled. VLLS1 VLLS3 LLS Unit -40 25 50 70 85 105 440 490 540 560 570 580 440 490 540 560 570 580 490 490 540 560 570 680 510 560 560 560 610 680 510 560 560 560 610 680 nA VLPS STOP ICMP CMP peripheral adder measured by placing the device in VLLS1 mode with CMP enabled using the 6-bit DAC and a single external input for compare. Includes 6-bit DAC power consumption. 22 22 22 22 22 22 µA IRTC RTC peripheral adder measured by placing the device in VLLS1 mode with external 32 kHz crystal enabled by means of the RTC_CR[OSCE] bit and the RTC ALARM set for 1 minute. Includes ERCLK32K (32 kHz external crystal) power consumption. 432 357 388 475 532 810 nA IUART UART peripheral adder measured by placing the device in STOP or VLPS mode with selected clock source waiting for RX data at 115200 baud rate. Includes selected clock source power consumption. 66 66 66 66 66 66 µA 214 237 246 254 260 268 MCGIRCLK (4MHz internal reference clock) OSCERCLK (4MHz external crystal) ITPM TPM peripheral adder measured by placing the device in STOP or VLPS mode with selected clock source configured for output compare generating 100Hz clock signal. No load is placed on the I/O generating the clock signal. Includes selected clock source and I/O switching currents. MCGIRCLK (4MHz internal reference clock) OSCERCLK (4MHz external crystal) IBG Bandgap adder when BGEN bit is set and device is placed in VLPx, LLS, or VLLSx mode. µA 86 86 86 86 86 86 235 256 265 274 280 287 45 45 45 45 45 45 µA Table continues on the next page... KL25 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012. Freescale Semiconductor, Inc. 17 General Table 6. Low power mode peripheral adders — typical value (continued) Symbol IADC 5.2.5.1 Description ADC peripheral adder combining the measured values at VDD and VDDA by placing the device in STOP or VLPS mode. ADC is configured for low power mode using the internal clock and continuous conversions. Temperature (°C) Unit -40 25 50 70 85 105 366 366 366 366 366 366 µA Diagram: Typical IDD_RUN operating behavior The following data was measured under these conditions: • • • • • MCG in FBE for run mode, and BLPE for VLPR mode USB regulator disabled No GPIOs toggled Code execution from flash with cache enabled For the ALLOFF curve, all peripheral clocks are disabled except FTFA KL25 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012. 18 Freescale Semiconductor, Inc. General Run Mode Current Vs Core Frequency Temperature = 25, VDD = 3, CACHE = Enable, Code Residence = Flash, Clocking Mode = FBE 8.00E-03 7.00E-03 Current Consumption on VDD(A) 6.00E-03 5.00E-03 All Peripheral CLK Gates 4.00E-03 All Off All On 3.00E-03 2.00E-03 1.00E-03 000.00E+00 '1-1 '1-1 '1-1 '1-1 '1-1 '1-1 '1-1 '1-2 1 2 3 4 6 12 24 48 CLK Ratio Flash-Core Core Freq (MHz) Figure 2. Run mode supply current vs. core frequency KL25 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012. Freescale Semiconductor, Inc. 19 General VLPR Mode Current Vs Core Frequency Temperature = 25, V DD = 3, CACHE = Enable, Code Residence = Flash, Clocking Mode = BLPE 400.00E-06 Current Consumption on VDD (A) 350.00E-06 300.00E-06 250.00E-06 All Peripheral CLK Gates 200.00E-06 All Off All On 150.00E-06 100.00E-06 50.00E-06 000.00E+00 '1-1 '1-2 1 '1-2 '1-4 2 4 CLK Ratio Flash-Core Core Freq (MHz) Figure 3. VLPR mode current vs. core frequency 5.2.6 EMC radiated emissions operating behaviors Table 7. EMC radiated emissions operating behaviors for 64-pin LQFP package Symbol Description Frequency band (MHz) Typ. Unit Notes 1, 2 VRE1 Radiated emissions voltage, band 1 0.15–50 13 dBμV VRE2 Radiated emissions voltage, band 2 50–150 15 dBμV VRE3 Radiated emissions voltage, band 3 150–500 12 dBμV VRE4 Radiated emissions voltage, band 4 500–1000 7 dBμV IEC level 0.15–1000 M — VRE_IEC 2, 3 1. Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions, 150 kHz to 1 GHz Part 1: General Conditions and Definitions and IEC Standard 61967-2, Integrated Circuits - Measurement of Electromagnetic Emissions, 150 kHz to 1 GHz Part 2: Measurement of Radiated Emissions—TEM Cell and Wideband TEM Cell Method. Measurements were made while the microcontroller was running basic application code. The reported emission level is the value of the maximum measured emission, rounded up to the next whole number, from among the measured orientations in each frequency range. KL25 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012. 20 Freescale Semiconductor, Inc. General 2. VDD = 3.3 V, TA = 25 °C, fOSC = 8 MHz (crystal), fSYS = 48 MHz, fBUS = 48 MHz 3. Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and Wideband TEM Cell Method 5.2.7 Designing with radiated emissions in mind To find application notes that provide guidance on designing your system to minimize interference from radiated emissions: 1. Go to www.freescale.com. 2. Perform a keyword search for “EMC design.” 5.2.8 Capacitance attributes Table 8. Capacitance attributes Symbol Description Min. Max. Unit CIN_A Input capacitance: analog pins — 7 pF CIN_D Input capacitance: digital pins — 7 pF 5.3 Switching specifications 5.3.1 Device clock specifications Symbol Description Min. Max. Unit Notes Normal run mode fSYS System and core clock — 48 MHz fBUS Bus clock — 24 MHz Flash clock — 24 MHz System and core clock when Full Speed USB in operation 20 — MHz — 24 MHz fFLASH fSYS_USB fLPTMR LPTMR clock VLPR mode1 fSYS System and core clock — 4 MHz fBUS Bus clock — 1 MHz fFLASH Flash clock — 1 MHz fLPTMR LPTMR clock — 24 MHz fERCLK External reference clock — 16 MHz LPTMR clock — 24 MHz fLPTMR_pin Table continues on the next page... KL25 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012. Freescale Semiconductor, Inc. 21 General Symbol Description Min. Max. Unit — 16 MHz Oscillator crystal or resonator frequency — high frequency mode (high range) (MCG_C2[RANGE]=1x) — 16 MHz TPM asynchronous clock — 8 MHz UART0 asynchronous clock — 8 MHz fLPTMR_ERCL LPTMR external reference clock Notes K fosc_hi_2 fTPM fUART0 1. The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for any other module. 5.3.2 General Switching Specifications These general purpose specifications apply to all signals configured for GPIO, UART, and I2C signals. Symbol Description Min. Max. Unit Notes GPIO pin interrupt pulse width (digital glitch filter disabled) — Synchronous path 1.5 — Bus clock cycles 1 External RESET and NMI pin interrupt pulse width — Asynchronous path 100 — ns 2 GPIO pin interrupt pulse width — Asynchronous path 16 — ns 2 Port rise and fall time 3 — 36 ns 1. The greater synchronous and asynchronous timing must be met. 2. This is the shortest pulse that is guaranteed to be recognized. 3. 75 pF load 5.4 Thermal specifications 5.4.1 Thermal operating requirements Table 9. Thermal operating requirements Symbol Description Min. Max. Unit TJ Die junction temperature –40 125 °C TA Ambient temperature –40 105 °C KL25 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012. 22 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors 5.4.2 Thermal attributes Table 10. Thermal attributes Board type Symbol Single-layer (1S) RθJA Four-layer (2s2p) Description 80 LQFP 64 LQFP 48 QFN 32 QFN Unit Notes Thermal resistance, junction to ambient (natural convection) 70 71 84 92 °C/W 1 RθJA Thermal resistance, junction to ambient (natural convection) 53 52 28 33 °C/W Single-layer (1S) RθJMA Thermal resistance, junction to ambient (200 ft./min. air speed) — 59 69 75 °C/W Four-layer (2s2p) RθJMA Thermal resistance, junction to ambient (200 ft./min. air speed) — 46 22 27 °C/W — RθJB Thermal resistance, junction to board 34 34 10 12 °C/W 2 — RθJC Thermal resistance, junction to case 15 20 2.0 1.8 °C/W 3 — ΨJT Thermal characterization parameter, junction to package top outside center (natural convection) 0.6 5 5.0 8 °C/W 4 1. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions —Natural Convection (Still Air), or EIA/JEDEC Standard JESD51-6, Integrated Circuit Thermal Test Method Environmental Conditions—Forced Convection (Moving Air). 2. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental Conditions —Junction-to-Board. 3. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate temperature used for the case temperature. The value includes the thermal resistance of the interface material between the top of the package and the cold plate. 4. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions —Natural Convection (Still Air). 6 Peripheral operating requirements and behaviors 6.1 Core modules 6.1.1 SWD Electricals Table 11. SWD full voltage range electricals Symbol Description Min. Max. Unit Operating voltage 1.71 3.6 V Table continues on the next page... KL25 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012. Freescale Semiconductor, Inc. 23 Peripheral operating requirements and behaviors Table 11. SWD full voltage range electricals (continued) Symbol J1 Description Min. Max. Unit 0 25 MHz 1/J1 — ns 20 — ns SWD_CLK frequency of operation • Serial wire debug J2 SWD_CLK cycle period J3 SWD_CLK clock pulse width • Serial wire debug J4 SWD_CLK rise and fall times — 3 ns J9 SWD_DIO input data setup time to SWD_CLK rise 10 — ns J10 SWD_DIO input data hold time after SWD_CLK rise 0 — ns J11 SWD_CLK high to SWD_DIO data valid — 32 ns J12 SWD_CLK high to SWD_DIO high-Z 5 — ns J2 J3 J3 SWD_CLK (input) J4 J4 Figure 4. Serial wire clock input timing SWD_CLK J9 SWD_DIO J10 Input data valid J11 SWD_DIO Output data valid J12 SWD_DIO J11 SWD_DIO Output data valid Figure 5. Serial wire data timing KL25 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012. 24 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors 6.2 System modules There are no specifications necessary for the device's system modules. 6.3 Clock modules 6.3.1 MCG specifications Table 12. MCG specifications Symbol Description fints_ft Internal reference frequency (slow clock) — factory trimmed at nominal VDD and 25 °C fints_t Internal reference frequency (slow clock) — user trimmed Δfdco_res_t Resolution of trimmed average DCO output frequency at fixed voltage and temperature — using SCTRIM and SCFTRIM Min. Typ. Max. Unit Notes — 32.768 — kHz 31.25 — 39.0625 kHz — ± 0.3 ± 0.6 %fdco 1 Δfdco_t Total deviation of trimmed average DCO output frequency over voltage and temperature — +0.5/-0.7 ±3 %fdco 1, 2 Δfdco_t Total deviation of trimmed average DCO output frequency over fixed voltage and temperature range of 0 - 70 °C — ± 0.4 ± 1.5 %fdco 1, 2 Internal reference frequency (fast clock) — factory trimmed at nominal VDD and 25 °C — 4 — MHz Δfintf_ft Frequency deviation of internal reference clock (fast clock) over temperature and voltage --factory trimmed at nominal VDD and 25 °C — +1/-2 ±3 %fintf_ft fintf_t Internal reference frequency (fast clock) — user trimmed at nominal VDD and 25 °C 3 — 5 MHz fintf_ft floc_low Loss of external clock minimum frequency — RANGE = 00 (3/5) x fints_t — — kHz floc_high Loss of external clock minimum frequency — RANGE = 01, 10, or 11 (16/5) x fints_t — — kHz 31.25 — 39.0625 kHz 20 20.97 25 MHz 40 41.94 48 MHz 2 FLL ffll_ref fdco FLL reference frequency range DCO output frequency range Low range (DRS = 00) 3, 4 640 × ffll_ref Mid range (DRS = 01) 1280 × ffll_ref Table continues on the next page... KL25 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012. Freescale Semiconductor, Inc. 25 Peripheral operating requirements and behaviors Table 12. MCG specifications (continued) Symbol Description fdco_t_DMX32 DCO output frequency Low range (DRS = 00) Min. Typ. Max. Unit Notes — 23.99 — MHz 5, 6 — 47.97 — MHz — 180 — ps 7 — — 1 ms 8 48.0 — 100 MHz — 1060 — µA — 600 — µA 2.0 — 4.0 MHz 732 × ffll_ref Mid range (DRS = 01) 1464 × ffll_ref Jcyc_fll FLL period jitter • fVCO = 48 MHz tfll_acquire FLL target frequency acquisition time PLL fvco VCO operating frequency Ipll PLL operating current • PLL at 96 MHz (fosc_hi_1 = 8 MHz, fpll_ref = 2 MHz, VDIV multiplier = 48) Ipll PLL operating current • PLL at 48 MHz (fosc_hi_1 = 8 MHz, fpll_ref = 2 MHz, VDIV multiplier = 24) fpll_ref PLL reference frequency range Jcyc_pll PLL period jitter (RMS) Jacc_pll • fvco = 48 MHz — 120 — ps • fvco = 100 MHz — 50 — ps PLL accumulated jitter over 1µs (RMS) 10 • fvco = 48 MHz — 1350 — ps • fvco = 100 MHz — 600 — ps Lock entry frequency tolerance ± 1.49 — ± 2.98 % Dunl Lock exit frequency tolerance ± 4.47 — ± 5.97 % Lock detector detection time 9 10 Dlock tpll_lock 9 — — 10-6 150 × + 1075(1/ fpll_ref) s 11 1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock mode). 2. The deviation is relative to the factory trimmed frequency at nominal VDD and 25 °C, fints_ft. 3. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32 = 0. 4. The resulting system clock frequencies must not exceed their maximum specified values. The DCO frequency deviation (Δfdco_t) over voltage and temperature must be considered. 5. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32 = 1. 6. The resulting clock frequency must not exceed the maximum specified clock frequency of the device. 7. This specification is based on standard deviation (RMS) of period or frequency. 8. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed, DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running. 9. Excludes any oscillator currents that are also consuming power while PLL is in operation. 10. This specification was obtained using a Freescale developed PCB. PLL jitter is dependent on the noise characteristics of each PCB and results will vary. 11. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled (BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes it is already running. KL25 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012. 26 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors 6.3.2 Oscillator electrical specifications This section provides the electrical characteristics of the module. 6.3.2.1 Oscillator DC electrical specifications Table 13. Oscillator DC electrical specifications Symbol Description Min. Typ. Max. Unit VDD Supply voltage 1.71 — 3.6 V IDDOSC IDDOSC Supply current — low-power mode (HGO=0) Notes 1 • 32 kHz — 500 — nA • 4 MHz — 200 — μA • 8 MHz (RANGE=01) — 300 — μA • 16 MHz — 950 — μA • 24 MHz — 1.2 — mA • 32 MHz — 1.5 — mA Supply current — high gain mode (HGO=1) 1 • 32 kHz — 25 — μA • 4 MHz — 400 — μA • 8 MHz (RANGE=01) — 500 — μA • 16 MHz — 2.5 — mA • 24 MHz — 3 — mA • 32 MHz — 4 — mA Cx EXTAL load capacitance — — — 2, 3 Cy XTAL load capacitance — — — 2, 3 RF Feedback resistor — low-frequency, low-power mode (HGO=0) — — — MΩ Feedback resistor — low-frequency, high-gain mode (HGO=1) — 10 — MΩ Feedback resistor — high-frequency, low-power mode (HGO=0) — — — MΩ Feedback resistor — high-frequency, high-gain mode (HGO=1) — 1 — MΩ 2, 4 Table continues on the next page... KL25 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012. Freescale Semiconductor, Inc. 27 Peripheral operating requirements and behaviors Table 13. Oscillator DC electrical specifications (continued) Symbol RS Description Min. Typ. Max. Unit Series resistor — low-frequency, low-power mode (HGO=0) — — — kΩ Series resistor — low-frequency, high-gain mode (HGO=1) — 200 — kΩ Series resistor — high-frequency, low-power mode (HGO=0) — — — kΩ Notes Series resistor — high-frequency, high-gain mode (HGO=1) Vpp5 — 0 — kΩ Peak-to-peak amplitude of oscillation (oscillator mode) — low-frequency, low-power mode (HGO=0) — 0.6 — V Peak-to-peak amplitude of oscillation (oscillator mode) — low-frequency, high-gain mode (HGO=1) — VDD — V Peak-to-peak amplitude of oscillation (oscillator mode) — high-frequency, low-power mode (HGO=0) — 0.6 — V Peak-to-peak amplitude of oscillation (oscillator mode) — high-frequency, high-gain mode (HGO=1) — VDD — V 1. VDD=3.3 V, Temperature =25 °C 2. See crystal or resonator manufacturer's recommendation 3. Cx,Cy can be provided by using the integrated capacitors when the low frequency oscillator (RANGE = 00) is used. For all other cases external capacitors must be used.. 4. When low power mode is selected, RF is integrated and must not be attached externally. 5. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to any other devices. 6.3.2.2 Symbol Oscillator frequency specifications Table 14. Oscillator frequency specifications Description Min. Typ. Max. Unit fosc_lo Oscillator crystal or resonator frequency — low frequency mode (MCG_C2[RANGE]=00) 32 — 40 kHz fosc_hi_1 Oscillator crystal or resonator frequency — high frequency mode (low range) (MCG_C2[RANGE]=01) 3 — 8 MHz fosc_hi_2 Oscillator crystal or resonator frequency — high frequency mode (high range) (MCG_C2[RANGE]=1x) 8 — 32 MHz fec_extal Input clock frequency (external clock mode) — — 48 MHz tdc_extal Input clock duty cycle (external clock mode) 40 50 60 % Notes 1, 2 Table continues on the next page... KL25 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012. 28 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Table 14. Oscillator frequency specifications (continued) Symbol tcst Description Min. Typ. Max. Unit Notes Crystal startup time — 32 kHz low-frequency, low-power mode (HGO=0) — 750 — ms 3, 4 Crystal startup time — 32 kHz low-frequency, high-gain mode (HGO=1) — 250 — ms Crystal startup time — 8 MHz high-frequency (MCG_C2[RANGE]=01), low-power mode (HGO=0) — 0.6 — ms Crystal startup time — 8 MHz high-frequency (MCG_C2[RANGE]=01), high-gain mode (HGO=1) — 1 — ms 1. Other frequency limits may apply when external clock is being used as a reference for the FLL or PLL. 2. When transitioning from FBE to FEI mode, restrict the frequency of the input clock so that, when it is divided by FRDIV, it remains within the limits of the DCO input clock frequency. 3. Proper PC board layout procedures must be followed to achieve specifications. 4. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S register being set. 6.4 Memories and memory interfaces 6.4.1 Flash electrical specifications This section describes the electrical characteristics of the flash memory module. 6.4.1.1 Flash timing specifications — program and erase The following specifications represent the amount of time the internal charge pumps are active and do not include command overhead. Table 15. NVM program/erase timing specifications Symbol Description Min. Typ. Max. Unit thvpgm4 Notes Longword Program high-voltage time — 7.5 18 μs thversscr Sector Erase high-voltage time — 13 113 ms 1 thversall Erase All high-voltage time — 52 452 ms 1 1. Maximum time based on expectations at cycling end-of-life. KL25 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012. Freescale Semiconductor, Inc. 29 Peripheral operating requirements and behaviors 6.4.1.2 Flash timing specifications — commands Table 16. Flash command timing specifications Symbol Description Min. Typ. Max. Unit Notes trd1sec1k Read 1s Section execution time (flash sector) — — 60 μs 1 tpgmchk Program Check execution time — — 45 μs 1 trdrsrc Read Resource execution time — — 30 μs 1 tpgm4 Program Longword execution time — 65 145 μs tersscr Erase Flash Sector execution time — 14 114 ms trd1all Read 1s All Blocks execution time — — 1.8 ms trdonce Read Once execution time — — 25 μs Program Once execution time — 65 — μs tersall Erase All Blocks execution time — 62 500 ms 2 tvfykey Verify Backdoor Access Key execution time — — 30 μs 1 tpgmonce 2 1 1. Assumes 25MHz flash clock frequency. 2. Maximum times for erase parameters based on expectations at cycling end-of-life. 6.4.1.3 Flash high voltage current behaviors Table 17. Flash high voltage current behaviors Symbol Description IDD_PGM IDD_ERS 6.4.1.4 Symbol Min. Typ. Max. Unit Average current adder during high voltage flash programming operation — 2.5 6.0 mA Average current adder during high voltage flash erase operation — 1.5 4.0 mA Reliability specifications Table 18. NVM reliability specifications Description Min. Typ.1 Max. Unit Notes Program Flash tnvmretp10k Data retention after up to 10 K cycles 5 50 — years tnvmretp1k Data retention after up to 1 K cycles 20 100 — years nnvmcycp Cycling endurance 10 K 50 K — cycles 2 1. Typical data retention values are based on measured response accelerated at high temperature and derated to a constant 25°C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in Engineering Bulletin EB619. 2. Cycling endurance represents number of program/erase cycles at -40°C ≤ Tj ≤ 125°C. KL25 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012. 30 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors 6.5 Security and integrity modules There are no specifications necessary for the device's security and integrity modules. 6.6 Analog 6.6.1 ADC electrical specifications The 16-bit accuracy specifications listed in Table 19 and Table 20 are achievable on the differential pins ADCx_DP0, ADCx_DM0. All other ADC channels meet the 13-bit differential/12-bit single-ended accuracy specifications. 6.6.1.1 16-bit ADC operating conditions Table 19. 16-bit ADC operating conditions Symbol Description Conditions Min. Typ.1 Max. Unit VDDA Supply voltage Absolute 1.71 — 3.6 V ΔVDDA Supply voltage Delta to VDD (VDD-VDDA) -100 0 +100 mV 2 ΔVSSA Ground voltage Delta to VSS (VSS - VSSA) -100 0 +100 mV 2 VREFH ADC reference voltage high 1.13 VDDA VDDA V 3 VREFL ADC reference voltage low VSSA VSSA VSSA V 3 VADIN Input voltage VREFL — VREFH V CADIN Input capacitance • 16-bit mode — 8 10 pF • 8-/10-/12-bit modes — 4 5 — 2 5 RADIN RAS Input resistance Notes kΩ Analog source resistance 13-/12-bit modes fADCK < 4 MHz — — 5 kΩ fADCK ADC conversion clock frequency ≤ 13-bit mode 1.0 — 18.0 MHz 5 fADCK ADC conversion clock frequency 16-bit mode 2.0 — 12.0 MHz 5 Crate ADC conversion rate ≤ 13 bit modes No ADC hardware averaging 4 6 20.000 — 818.330 Ksps Continuous conversions enabled, subsequent conversion time Table continues on the next page... KL25 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012. Freescale Semiconductor, Inc. 31 Peripheral operating requirements and behaviors Table 19. 16-bit ADC operating conditions (continued) Symbol Crate Description Conditions ADC conversion rate 16-bit mode Min. Typ.1 Max. Unit Notes 6 No ADC hardware averaging 37.037 — 461.467 Ksps Continuous conversions enabled, subsequent conversion time 1. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 2. DC potential difference. 3. For packages without dedicated VREFH and VREFL pins, VREFH is internally tied to VDDA, and VREFL is internally tied to VSSA. 4. This resistance is external to MCU. The analog source resistance must be kept as low as possible to achieve the best results. The results in this data sheet were derived from a system which has < 8 Ω analog source resistance. The RAS/CAS time constant should be kept to < 1ns. 5. To use the maximum ADC conversion clock frequency, the ADHSC bit must be set and the ADLPC bit must be clear. 6. For guidelines and examples of conversion rate calculation, download the ADC calculator tool SIMPLIFIED INPUT PIN EQUIVALENT CIRCUIT Z ADIN SIMPLIFIED CHANNEL SELECT CIRCUIT Pad leakage due to input protection Z AS R AS ADC SAR ENGINE R ADIN V ADIN C AS V AS R ADIN INPUT PIN R ADIN INPUT PIN R ADIN INPUT PIN C ADIN Figure 6. ADC input impedance equivalency diagram 6.6.1.2 16-bit ADC electrical characteristics Table 20. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) Symbol Description IDDA_ADC Supply current Conditions1 Min. Typ.2 Max. Unit Notes 0.215 — 1.7 mA 3 Table continues on the next page... KL25 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012. 32 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Table 20. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued) Symbol fADACK Conditions1 Description ADC asynchronous clock source Sample Time TUE DNL INL EFS Min. Typ.2 Max. Unit Notes • ADLPC = 1, ADHSC = 0 1.2 2.4 3.9 MHz • ADLPC = 1, ADHSC = 1 2.4 4.0 6.1 MHz tADACK = 1/ fADACK • ADLPC = 0, ADHSC = 0 3.0 5.2 7.3 MHz • ADLPC = 0, ADHSC = 1 4.4 6.2 9.5 MHz LSB4 5 LSB4 5 LSB4 5 LSB4 VADIN = VDDA See Reference Manual chapter for sample times Total unadjusted error • 12-bit modes — ±4 ±6.8 • <12-bit modes — ±1.4 ±2.1 Differential nonlinearity • 12-bit modes — ±0.7 -1.1 to +1.9 Integral nonlinearity -0.3 to 0.5 • <12-bit modes — ±0.2 • 12-bit modes — ±1.0 -2.7 to +1.9 -0.7 to +0.5 Full-scale error • <12-bit modes — ±0.5 • 12-bit modes — -4 -5.4 • <12-bit modes — -1.4 -1.8 5 EQ ENOB Quantization error • 16-bit modes — -1 to 0 — • ≤13-bit modes — — ±0.5 Effective number 16-bit differential mode of bits • Avg = 32 • Avg = 4 LSB4 6 12.8 14.5 — bits 11.9 13.8 — bits 12.2 13.9 — bits 11.4 13.1 — bits 16-bit single-ended mode • Avg = 32 • Avg = 4 SINAD THD Signal-to-noise plus distortion See ENOB Total harmonic distortion 16-bit differential mode 6.02 × ENOB + 1.76 • Avg = 32 16-bit single-ended mode • Avg = 32 SFDR Spurious free dynamic range dB 7 — –94 — dB — -85 — dB 16-bit differential mode • Avg = 32 16-bit single-ended mode • Avg = 32 7 82 95 — dB 78 90 — dB Table continues on the next page... KL25 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012. Freescale Semiconductor, Inc. 33 Peripheral operating requirements and behaviors Table 20. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued) Symbol Description EIL Input leakage error Conditions1 Min. Typ.2 Max. IIn × RAS Unit Notes mV IIn = leakage current (refer to the MCU's voltage and current operating ratings) VTEMP25 Temp sensor slope Across the full temperature range of the device — 1.715 — mV/°C Temp sensor voltage 25 °C — 719 — mV 1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA 2. Typical values assume VDDA = 3.0 V, Temp = 25°C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and the ADLPC bit (low power). For lowest power operation the ADLPC bit must be set, the HSC bit must be clear with 1 MHz ADC conversion clock speed. 4. 1 LSB = (VREFH - VREFL)/2N 5. ADC conversion clock < 16 MHz, Max hardware averaging (AVGE = %1, AVGS = %11) 6. Input data is 100 Hz sine wave. ADC conversion clock < 12 MHz. 7. Input data is 1 kHz sine wave. ADC conversion clock < 12 MHz. Figure 7. Typical ENOB vs. ADC_CLK for 16-bit differential mode KL25 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012. 34 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Figure 8. Typical ENOB vs. ADC_CLK for 16-bit single-ended mode 6.6.2 CMP and 6-bit DAC electrical specifications Table 21. Comparator and 6-bit DAC electrical specifications Symbol Description Min. Typ. Max. Unit VDD Supply voltage 1.71 — 3.6 V IDDHS Supply current, high-speed mode (EN = 1, PMODE = 1) — — 200 μA IDDLS Supply current, low-speed mode (EN = 1, PMODE = 0) — — 20 μA VAIN Analog input voltage VSS — VDD V VAIO Analog input offset voltage — — 20 mV • CR0[HYSTCTR] = 00 — 5 — mV • CR0[HYSTCTR] = 01 — 10 — mV • CR0[HYSTCTR] = 10 — 20 — mV • CR0[HYSTCTR] = 11 — 30 — mV VH Analog comparator hysteresis1 VCMPOh Output high VDD – 0.5 — — V VCMPOl Output low — — 0.5 V tDHS Propagation delay, high-speed mode (EN = 1, PMODE = 1) 20 50 200 ns tDLS Propagation delay, low-speed mode (EN = 1, PMODE = 0) 80 250 600 ns Table continues on the next page... KL25 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012. Freescale Semiconductor, Inc. 35 Peripheral operating requirements and behaviors Table 21. Comparator and 6-bit DAC electrical specifications (continued) Symbol IDAC6b Description Min. Typ. Max. Unit Analog comparator initialization delay2 — — 40 μs 6-bit DAC current adder (enabled) — 7 — μA INL 6-bit DAC integral non-linearity –0.5 — 0.5 LSB3 DNL 6-bit DAC differential non-linearity –0.3 — 0.3 LSB 1. Typical hysteresis is measured with input voltage range limited to 0.7 to VDD – 0.7 V. 2. Comparator initialization delay is defined as the time between software writes to change control inputs (writes to DACEN, VRSEL, PSEL, MSEL, VOSEL) and the comparator output settling to a stable level. 3. 1 LSB = Vreference/64 CMP Hysteresis vs Vinn 90.00E-03 80.00E-03 70.00E-03 CMP Hysteresis (V) 60.00E-03 HYSTCTR Setting 50.00E-03 0 1 40.00E-03 2 3 30.00E-03 20.00E-03 10.00E-03 000.00E+00 0.1 0.4 0.7 1 1.3 1.6 1.9 2.2 2.5 2.8 3.1 Vinn (V) Figure 9. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0) CMP Hysteresis vs Vinn 180.00E-03 160.00E-03 140.00E-03 CMP Hysteresis (V) 120.00E-03 HYSTCTR Setting 100.00E-03 0 1 80.00E-03 2 3 60.00E-03 40.00E-03 20.00E-03 000.00E+00 0.1 -20.00E-03 0.4 0.7 1 1.3 1.6 1.9 2.2 2.5 2.8 3.1 Vinn (V) Figure 10. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1) 6.6.3 12-bit DAC electrical characteristics KL25 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012. 36 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors 6.6.3.1 Symbol 12-bit DAC operating requirements Table 22. 12-bit DAC operating requirements Desciption Min. Max. Unit VDDA Supply voltage 1.71 3.6 V VDACR Reference voltage 1.13 3.6 V TA Temperature Operating temperature range of the device CL Output load capacitance — 100 pF IL Output load current — 1 mA Notes 1 °C 2 1. The DAC reference can be selected to be VDDA or the voltage output of the VREF module (VREF_OUT) 2. A small load capacitance (47 pF) can improve the bandwidth performance of the DAC 6.6.3.2 Symbol 12-bit DAC operating behaviors Table 23. 12-bit DAC operating behaviors Description IDDA_DACL Supply current — low-power mode Min. Typ. Max. Unit — — 250 μA — — 900 μA Notes P IDDA_DACH Supply current — high-speed mode P tDACLP Full-scale settling time (0x080 to 0xF7F) — low-power mode — 100 200 μs 1 tDACHP Full-scale settling time (0x080 to 0xF7F) — high-power mode — 15 30 μs 1 — 0.7 1 μs 1 — — 100 mV tCCDACLP Code-to-code settling time (0xBF8 to 0xC08) — low-power mode and high-speed mode Vdacoutl DAC output voltage range low — high-speed mode, no load, DAC set to 0x000 Vdacouth DAC output voltage range high — highspeed mode, no load, DAC set to 0xFFF VDACR −100 — VDACR mV INL Integral non-linearity error — high speed mode — — ±8 LSB 2 DNL Differential non-linearity error — VDACR > 2 V — — ±1 LSB 3 DNL Differential non-linearity error — VDACR = VREF_OUT — — ±1 LSB 4 — ±0.4 ±0.8 %FSR 5 Gain error — ±0.1 ±0.6 %FSR 5 Power supply rejection ratio, VDDA ≥ 2.4 V 60 — 90 dB TCO Temperature coefficient offset voltage — 3.7 — μV/C TGE Temperature coefficient gain error — 0.000421 — %FSR/C Rop Output resistance load = 3 kΩ — — 250 Ω VOFFSET Offset error EG PSRR 6 Table continues on the next page... KL25 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012. Freescale Semiconductor, Inc. 37 Peripheral operating requirements and behaviors Table 23. 12-bit DAC operating behaviors (continued) Symbol SR BW 1. 2. 3. 4. 5. 6. Description Min. Typ. Max. Unit Slew rate -80h→ F7Fh→ 80h Notes V/μs • High power (SPHP) 1.2 1.7 — • Low power (SPLP) 0.05 0.12 — 3dB bandwidth kHz • High power (SPHP) 550 — — • Low power (SPLP) 40 — — Settling within ±1 LSB The INL is measured for 0 + 100 mV to VDACR −100 mV The DNL is measured for 0 + 100 mV to VDACR −100 mV The DNL is measured for 0 + 100 mV to VDACR −100 mV with VDDA > 2.4 V Calculated by a best fit curve from VSS + 100 mV to VDACR − 100 mV VDDA = 3.0 V, reference select set for VDDA (DACx_CO:DACRFS = 1), high power mode (DACx_C0:LPEN = 0), DAC set to 0x800, temperature range is across the full range of the device Figure 11. Typical INL error vs. digital code KL25 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012. 38 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Figure 12. Offset at half scale vs. temperature 6.7 Timers See General switching specifications. 6.8 Communication interfaces 6.8.1 USB electrical specifications The USB electricals for the USB On-the-Go module conform to the standards documented by the Universal Serial Bus Implementers Forum. For the most up-to-date standards, visit http://www.usb.org. KL25 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012. Freescale Semiconductor, Inc. 39 Peripheral operating requirements and behaviors 6.8.2 USB VREG electrical specifications Table 24. USB VREG electrical specifications Symbol Description Min. Typ.1 Max. Unit VREGIN Input supply voltage 2.7 — 5.5 V IDDon Quiescent current — Run mode, load current equal zero, input supply (VREGIN) > 3.6 V — 120 186 μA IDDstby Quiescent current — Standby mode, load current equal zero — 1.1 10 μA IDDoff Quiescent current — Shutdown mode — 650 — nA — — 4 μA • VREGIN = 5.0 V and temperature=25C • Across operating voltage and temperature ILOADrun Maximum load current — Run mode — — 120 mA ILOADstby Maximum load current — Standby mode — — 1 mA VReg33out Regulator output voltage — Input supply (VREGIN) > 3.6 V 3 3.3 3.6 V • Run mode • Standby mode 2.1 2.8 3.6 V Regulator output voltage — Input supply (VREGIN) < 3.6 V, pass-through mode 2.1 — 3.6 V COUT External output capacitor 1.76 2.2 8.16 μF ESR External output capacitor equivalent series resistance 1 — 100 mΩ ILIM Short circuit current — 290 — mA VReg33out Notes 2 1. Typical values assume VREGIN = 5.0 V, Temp = 25 °C unless otherwise stated. 2. Operating in pass-through mode: regulator output voltage equal to the input voltage minus a drop proportional to ILoad. 6.8.3 SPI switching specifications The Serial Peripheral Interface (SPI) provides a synchronous serial bus with master and slave operations. Many of the transfer attributes are programmable. The following tables provide timing characteristics for classic SPI timing modes. See the SPI chapter of the chip's Reference Manual for information about the modified transfer formats used for communicating with slower peripheral devices. All timing is shown with respect to 20% VDD and 80% VDD thresholds, unless noted, as well as input signal transitions of 3 ns and a 30 pF maximum load on all SPI pins. Table 25. SPI master mode timing on slew rate disabled pads Num. Symbol 1 fop Description Frequency of operation Min. Max. Unit Note fperiph/2048 fperiph/2 Hz 1 Table continues on the next page... KL25 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012. 40 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Table 25. SPI master mode timing on slew rate disabled pads (continued) Num. Symbol Description Min. Max. Unit Note 2 tSPSCK SPSCK period 2 x tperiph 2048 x tperiph ns 2 3 tLead Enable lead time 1/2 — tSPSCK — 4 tLag Enable lag time 1/2 — tSPSCK — 5 tWSPSCK tperiph - 30 1024 x tperiph ns — 6 tSU Data setup time (inputs) 16 — ns — 7 tHI Data hold time (inputs) 0 — ns — 8 tv Data valid (after SPSCK edge) — 10 ns — 9 tHO Data hold time (outputs) 0 — ns — 10 tRI Rise time input — tperiph - 25 ns — tFI Fall time input tRO Rise time output — 25 ns — tFO Fall time output 11 Clock (SPSCK) high or low time 1. For SPI0 fperiph is the bus clock (fBUS). For SPI1 fperiph is the system clock (fSYS). 2. tperiph = 1/fperiph Table 26. SPI master mode timing on slew rate enabled pads Num. Symbol 1 fop 2 tSPSCK 3 tLead 4 tLag 5 tWSPSCK 6 tSU 7 tHI 8 tv 9 10 11 Description Min. Max. Unit Note fperiph/2048 fperiph/2 Hz 1 2 x tperiph 2048 x tperiph ns 2 Enable lead time 1/2 — tSPSCK — Enable lag time 1/2 — tSPSCK — tperiph - 30 1024 x tperiph ns — Data setup time (inputs) 96 — ns — Data hold time (inputs) 0 — ns — Data valid (after SPSCK edge) — 52 ns — tHO Data hold time (outputs) 0 — ns — tRI Rise time input — tperiph - 25 ns — tFI Fall time input tRO Rise time output — 36 ns — tFO Fall time output Frequency of operation SPSCK period Clock (SPSCK) high or low time 1. For SPI0 fperiph is the bus clock (fBUS). For SPI1 fperiph is the system clock (fSYS). 2. tperiph = 1/fperiph KL25 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012. Freescale Semiconductor, Inc. 41 Peripheral operating requirements and behaviors SS1 (OUTPUT) 3 2 SPSCK (CPOL = 0) (OUTPUT) 10 11 10 11 4 5 5 SPSCK (CPOL = 1) (OUTPUT) 6 7 MISO (INPUT) MSB IN2 BIT 6 . . . 1 LSB IN 8 MOSI (OUTPUT) MSB OUT2 9 BIT 6 . . . 1 LSB OUT 1. If configured as an output. 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. Figure 13. SPI master mode timing (CPHA = 0) SS1 (OUTPUT) 2 3 SPSCK (CPOL = 0) (OUTPUT) 5 SPSCK (CPOL = 1) (OUTPUT) 5 6 MISO (INPUT) 10 11 10 11 4 7 MSB IN2 BIT 6 . . . 1 8 MOSI 2 (OUTPUT)PORT DATA MASTER MSB OUT LSB IN 9 BIT 6 . . . 1 MASTER LSB OUT PORT DATA 1.If configured as output 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. Figure 14. SPI master mode timing (CPHA = 1) Table 27. SPI slave mode timing on slew rate disabled pads Num. Symbol 1 fop 2 tSPSCK 3 tLead 4 tLag 5 tWSPSCK Description Frequency of operation Min. Max. Unit Note 0 fperiph/4 Hz 1 4 x tperiph — ns 2 Enable lead time 1 — tperiph — Enable lag time 1 — tperiph — tperiph - 30 — ns — SPSCK period Clock (SPSCK) high or low time Table continues on the next page... KL25 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012. 42 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Table 27. SPI slave mode timing on slew rate disabled pads (continued) 1. 2. 3. 4. Num. Symbol 6 tSU 7 Description Min. Max. Unit Note Data setup time (inputs) 2 — ns — tHI Data hold time (inputs) 7 — ns — 8 ta Slave access time — tperiph ns 3 9 tdis Slave MISO disable time — tperiph ns 4 10 tv Data valid (after SPSCK edge) — 22 ns — 11 tHO Data hold time (outputs) 0 — ns — 12 tRI Rise time input — tperiph - 25 ns — tFI Fall time input 13 tRO Rise time output — 25 ns — tFO Fall time output For SPI0 fperiph is the bus clock (fBUS). For SPI1 fperiph is the system clock (fSYS). tperiph = 1/fperiph Time to data active from high-impedance state Hold time to high-impedance state Table 28. SPI slave mode timing on slew rate enabled pads Num. Symbol 1 fop 2 tSPSCK 3 tLead Enable lead time 4 tLag Enable lag time 5 tWSPSCK 6 tSU 7 Min. Max. Unit Note 0 fperiph/4 Hz 1 4 x tperiph — ns 2 1 — tperiph — Frequency of operation SPSCK period 1 — tperiph — tperiph - 30 — ns — Data setup time (inputs) 2 — ns — tHI Data hold time (inputs) 7 — ns — 8 ta Slave access time — tperiph ns 3 9 tdis Slave MISO disable time — tperiph ns 4 10 tv Data valid (after SPSCK edge) — 122 ns — 11 tHO Data hold time (outputs) 0 — ns — 12 tRI Rise time input — tperiph - 25 ns — tFI Fall time input tRO Rise time output — 36 ns — tFO Fall time output 13 1. 2. 3. 4. Description Clock (SPSCK) high or low time For SPI0 fperiph is the bus clock (fBUS). For SPI1 fperiph is the system clock (fSYS). tperiph = 1/fperiph Time to data active from high-impedance state Hold time to high-impedance state KL25 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012. Freescale Semiconductor, Inc. 43 Peripheral operating requirements and behaviors SS (INPUT) 2 SPSCK (CPOL = 0) (INPUT) 5 3 SPSCK (CPOL = 1) (INPUT) 5 13 4 12 13 9 8 MISO (OUTPUT) 12 10 see note SLAVE MSB 6 11 11 BIT 6 . . . 1 SLAVE LSB OUT SEE NOTE 7 MOSI (INPUT) BIT 6 . . . 1 MSB IN LSB IN NOTE: Not defined! Figure 15. SPI slave mode timing (CPHA = 0) SS (INPUT) 4 2 3 SPSCK (CPOL = 0) (INPUT) 5 SPSCK (CPOL = 1) (INPUT) 5 see note 8 MOSI (INPUT) SLAVE 13 12 13 9 11 10 MISO (OUTPUT) 12 MSB OUT 6 BIT 6 . . . 1 SLAVE LSB OUT 7 MSB IN BIT 6 . . . 1 LSB IN NOTE: Not defined! Figure 16. SPI slave mode timing (CPHA = 1) 6.8.4 I2C See General switching specifications. 6.8.5 UART See General switching specifications. KL25 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012. 44 Freescale Semiconductor, Inc. Dimensions 6.9 Human-machine interfaces (HMI) 6.9.1 TSI electrical specifications Table 29. TSI electrical specifications Symbol Description Min. Type Max Unit TSI_RUNF Fixed power consumption in run mode — 100 — µA TSI_RUNV Variable power consumption in run mode (depends on oscillator's current selection) 1.0 — 128 µA TSI_EN Power consumption in enable mode — 100 — µA TSI_DIS Power consumption in disable mode — 1.2 — µA TSI_TEN TSI analog enable time — 66 — µs TSI_CREF TSI reference capacitor — 1.0 — pF TSI_DVOLT Voltage variation of VP & VM around nominal values 0.19 — 1.03 V 7 Dimensions 7.1 Obtaining package dimensions Package dimensions are provided in package drawings. To find a package drawing, go to www.freescale.com and perform a keyword search for the drawing’s document number: If you want the drawing for this package Then use this document number 32-pin QFN 98ASA00473D 48-pin QFN 98ASA00466D 64-pin LQFP 98ASS23234W 80-pin LQFP 98ASS23174W 8 Pinout KL25 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012. Freescale Semiconductor, Inc. 45 Pinout 8.1 KL25 Signal Multiplexing and Pin Assignments The following table shows the signals available on each pin and the locations of these pins on the devices supported by this document. The Port Control Module is responsible for selecting which ALT functionality is available on each pin. 80 64 LQFP LQFP 48 QFN 32 QFN Pin Name Default ALT0 ALT1 ALT2 1 1 — 1 PTE0 DISABLED PTE0 2 2 — — PTE1 DISABLED PTE1 SPI1_MOSI 3 — — — PTE2 DISABLED PTE2 SPI1_SCK 4 — — — PTE3 DISABLED PTE3 SPI1_MISO 5 — — — PTE4 DISABLED PTE4 SPI1_PCS0 6 — — — PTE5 DISABLED PTE5 7 3 1 — VDD VDD VDD 8 4 2 2 VSS VSS VSS ALT3 ALT4 ALT5 UART1_TX RTC_CLKOUT CMP0_OUT I2C1_SDA UART1_RX SPI1_MISO I2C1_SCL ALT7 SPI1_MOSI 9 5 3 3 USB0_DP USB0_DP USB0_DP 10 6 4 4 USB0_DM USB0_DM USB0_DM 11 7 5 5 VOUT33 VOUT33 VOUT33 12 8 6 6 VREGIN VREGIN VREGIN 13 9 7 — PTE20 ADC0_DP0/ ADC0_SE0 ADC0_DP0/ ADC0_SE0 PTE20 TPM1_CH0 UART0_TX 14 10 8 — PTE21 ADC0_DM0/ ADC0_SE4a ADC0_DM0/ ADC0_SE4a PTE21 TPM1_CH1 UART0_RX 15 11 — — PTE22 ADC0_DP3/ ADC0_SE3 ADC0_DP3/ ADC0_SE3 PTE22 TPM2_CH0 UART2_TX 16 12 — — PTE23 ADC0_DM3/ ADC0_SE7a ADC0_DM3/ ADC0_SE7a PTE23 TPM2_CH1 UART2_RX 17 13 9 7 VDDA VDDA VDDA 18 14 10 — VREFH VREFH VREFH 19 15 11 — VREFL VREFL VREFL 20 16 12 8 VSSA VSSA VSSA 21 17 13 — PTE29 CMP0_IN5/ ADC0_SE4b CMP0_IN5/ ADC0_SE4b PTE29 TPM0_CH2 TPM_CLKIN0 22 18 14 9 PTE30 DAC0_OUT/ ADC0_SE23/ CMP0_IN4 DAC0_OUT/ ADC0_SE23/ CMP0_IN4 PTE30 TPM0_CH3 TPM_CLKIN1 23 19 — — PTE31 DISABLED PTE31 TPM0_CH4 24 20 15 — PTE24 DISABLED PTE24 TPM0_CH0 I2C0_SCL 25 21 16 — PTE25 DISABLED PTE25 TPM0_CH1 I2C0_SDA 26 22 17 10 PTA0 SWD_CLK PTA0 TPM0_CH5 TSI0_CH1 ALT6 SWD_CLK 27 23 18 11 PTA1 DISABLED TSI0_CH2 PTA1 UART0_RX TPM2_CH0 28 24 19 12 PTA2 DISABLED TSI0_CH3 PTA2 UART0_TX TPM2_CH1 29 25 20 13 PTA3 SWD_DIO TSI0_CH4 PTA3 I2C1_SCL TPM0_CH0 SWD_DIO 30 26 21 14 PTA4 NMI_b TSI0_CH5 PTA4 I2C1_SDA TPM0_CH1 NMI_b 31 27 — — PTA5 DISABLED PTA5 USB_CLKIN TPM0_CH2 KL25 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012. 46 Freescale Semiconductor, Inc. Pinout 80 64 LQFP LQFP 48 QFN 32 QFN Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 32 28 — — PTA12 DISABLED PTA12 TPM1_CH0 33 29 — — PTA13 DISABLED PTA13 TPM1_CH1 34 — — — PTA14 DISABLED PTA14 SPI0_PCS0 UART0_TX 35 — — — PTA15 DISABLED PTA15 SPI0_SCK UART0_RX 36 — — — PTA16 DISABLED PTA16 SPI0_MOSI SPI0_MISO PTA17 SPI0_MISO SPI0_MOSI 37 — — — PTA17 DISABLED 38 30 22 15 VDD VDD VDD 39 31 23 16 VSS VSS VSS 40 32 24 17 PTA18 EXTAL0 EXTAL0 PTA18 UART1_RX TPM_CLKIN0 41 33 25 18 PTA19 XTAL0 XTAL0 PTA19 UART1_TX TPM_CLKIN1 42 34 26 19 RESET_b RESET_b 43 35 27 20 PTB0/ LLWU_P5 ADC0_SE8/ TSI0_CH0 ADC0_SE8/ TSI0_CH0 PTB0/ LLWU_P5 I2C0_SCL TPM1_CH0 44 36 28 21 PTB1 ADC0_SE9/ TSI0_CH6 ADC0_SE9/ TSI0_CH6 PTB1 I2C0_SDA TPM1_CH1 45 37 29 — PTB2 ADC0_SE12/ TSI0_CH7 ADC0_SE12/ TSI0_CH7 PTB2 I2C0_SCL TPM2_CH0 46 38 30 — PTB3 ADC0_SE13/ TSI0_CH8 ADC0_SE13/ TSI0_CH8 PTB3 I2C0_SDA TPM2_CH1 47 — — — PTB8 DISABLED PTB8 48 — — — PTB9 DISABLED PTB9 49 — — — PTB10 DISABLED PTB10 SPI1_PCS0 50 — — — PTB11 DISABLED PTB11 SPI1_SCK ALT6 ALT7 LPTMR0_ ALT1 PTA20 EXTRG_IN 51 39 31 — PTB16 TSI0_CH9 TSI0_CH9 PTB16 SPI1_MOSI UART0_RX TPM_CLKIN0 SPI1_MISO 52 40 32 — PTB17 TSI0_CH10 TSI0_CH10 PTB17 SPI1_MISO UART0_TX TPM_CLKIN1 SPI1_MOSI 53 41 — — PTB18 TSI0_CH11 TSI0_CH11 PTB18 TPM2_CH0 54 42 — — PTB19 TSI0_CH12 TSI0_CH12 PTB19 TPM2_CH1 55 43 33 — PTC0 ADC0_SE14/ TSI0_CH13 ADC0_SE14/ TSI0_CH13 PTC0 EXTRG_IN 56 44 34 22 PTC1/ LLWU_P6/ RTC_CLKIN ADC0_SE15/ TSI0_CH14 ADC0_SE15/ TSI0_CH14 PTC1/ LLWU_P6/ RTC_CLKIN I2C1_SCL TPM0_CH0 57 45 35 23 PTC2 ADC0_SE11/ TSI0_CH15 ADC0_SE11/ TSI0_CH15 PTC2 I2C1_SDA TPM0_CH1 58 46 36 24 PTC3/ LLWU_P7 DISABLED 59 47 — — VSS VSS VSS 60 48 — — VDD VDD VDD 61 49 37 25 PTC4/ LLWU_P8 DISABLED PTC4/ LLWU_P8 62 50 38 26 PTC5/ LLWU_P9 DISABLED 63 51 39 27 PTC6/ LLWU_P10 CMP0_IN0 PTC3/ LLWU_P7 CMP0_IN0 CMP0_OUT UART1_RX TPM0_CH2 SPI0_PCS0 UART1_TX TPM0_CH3 PTC5/ LLWU_P9 SPI0_SCK LPTMR0_ ALT2 PTC6/ LLWU_P10 SPI0_MOSI EXTRG_IN CLKOUT CMP0_OUT SPI0_MISO KL25 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012. Freescale Semiconductor, Inc. 47 Pinout 80 64 LQFP LQFP 48 QFN 32 QFN Pin Name Default ALT0 ALT1 ALT2 ALT3 64 52 40 28 PTC7 CMP0_IN1 CMP0_IN1 PTC7 SPI0_MISO 65 53 — — PTC8 CMP0_IN2 CMP0_IN2 PTC8 I2C0_SCL TPM0_CH4 66 54 — — PTC9 CMP0_IN3 CMP0_IN3 PTC9 I2C0_SDA TPM0_CH5 67 55 — — PTC10 DISABLED PTC10 I2C1_SCL 68 56 — — PTC11 DISABLED PTC11 I2C1_SDA ALT4 ALT5 ALT7 SPI0_MOSI 69 — — — PTC12 DISABLED PTC12 TPM_CLKIN0 70 — — — PTC13 DISABLED PTC13 TPM_CLKIN1 71 — — — PTC16 DISABLED PTC16 72 — — — PTC17 DISABLED PTC17 73 57 41 — PTD0 DISABLED PTD0 SPI0_PCS0 TPM0_CH0 74 58 42 — PTD1 ADC0_SE5b PTD1 SPI0_SCK TPM0_CH1 75 59 43 — PTD2 DISABLED PTD2 SPI0_MOSI UART2_RX TPM0_CH2 SPI0_MISO 76 60 44 — PTD3 DISABLED PTD3 SPI0_MISO UART2_TX TPM0_CH3 SPI0_MOSI 77 61 45 29 PTD4/ LLWU_P14 DISABLED PTD4/ LLWU_P14 SPI1_PCS0 UART2_RX TPM0_CH4 78 62 46 30 PTD5 ADC0_SE6b ADC0_SE6b PTD5 SPI1_SCK UART2_TX TPM0_CH5 79 63 47 31 PTD6/ LLWU_P15 ADC0_SE7b ADC0_SE7b PTD6/ LLWU_P15 SPI1_MOSI UART0_RX SPI1_MISO 80 64 48 32 PTD7 DISABLED PTD7 SPI1_MISO UART0_TX SPI1_MOSI ADC0_SE5b ALT6 8.2 KL25 Pinouts The below figures show the pinout diagrams for the devices supported by this document. Many signals may be multiplexed onto a single pin. To determine what signals can be used on which pin, see the previous section. KL25 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012. 48 Freescale Semiconductor, Inc. PTD7 PTD6/LLWU_P15 PTD5 PTD4/LLWU_P14 PTD3 PTD2 PTD1 PTD0 PTC17 PTC16 PTC13 PTC12 PTC11 PTC10 PTC9 PTC8 PTC7 PTC6/LLWU_P10 PTC5/LLWU_P9 PTC4/LLWU_P8 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 Pinout VOUT33 11 50 PTB11 VREGIN 12 49 PTB10 PTE20 13 48 PTB9 PTE21 14 47 PTB8 PTE22 15 46 PTB3 PTE23 16 45 PTB2 VDDA 17 44 PTB1 VREFH 18 43 PTB0/LLWU_P5 VREFL 19 42 RESET_b VSSA 20 41 PTA19 40 PTB16 PTA18 51 39 10 VSS USB0_DM 38 PTB17 VDD 52 37 9 PTA17 USB0_DP 36 PTB18 PTA16 53 35 8 PTA15 VSS 34 PTB19 PTA14 54 33 7 PTA13 VDD PTA12 PTC0 32 55 31 6 PTA5 PTE5 30 PTC1/LLWU_P6/RTC_CLKIN PTA4 56 29 5 PTA3 PTE4 28 PTC2 PTA2 57 27 4 PTA1 PTE3 26 PTC3/LLWU_P7 PTA0 58 25 3 PTE25 PTE2 24 VSS PTE24 59 23 2 PTE31 PTE1 22 VDD PTE30 60 21 1 PTE29 PTE0 Figure 17. KL25 80-pin LQFP pinout diagram KL25 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012. Freescale Semiconductor, Inc. 49 PTD7 PTD6/LLWU_P15 PTD5 PTD4/LLWU_P14 PTD3 PTD2 PTD1 PTD0 PTC11 PTC10 PTC9 PTC8 PTC7 PTC6/LLWU_P10 PTC5/LLWU_P9 PTC4/LLWU_P8 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 Pinout PTB18 PTE20 9 40 PTB17 PTE21 10 39 PTB16 PTE22 11 38 PTB3 PTE23 12 37 PTB2 VDDA 13 36 PTB1 VREFH 14 35 PTB0/LLWU_P5 VREFL 15 34 RESET_b VSSA 16 33 PTA19 PTA18 32 41 31 8 VSS VREGIN 30 PTB19 VDD 42 29 7 PTA13 VOUT33 28 PTC0 PTA12 43 27 6 PTA5 USB0_DM 26 PTC1/LLWU_P6/RTC_CLKIN PTA4 44 25 5 PTA3 USB0_DP 24 PTC2 PTA2 45 23 4 PTA1 VSS 22 PTC3/LLWU_P7 PTA0 46 21 3 PTE25 VDD 20 VSS PTE24 47 19 2 PTE31 PTE1 18 VDD PTE30 48 17 1 PTE29 PTE0 Figure 18. KL25 64-pin LQFP pinout diagram KL25 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012. 50 Freescale Semiconductor, Inc. PTD7 PTD6/LLWU_P15 PTD5 PTD4/LLWU_P14 PTD3 PTD2 PTD1 PTD0 PTC7 PTC6/LLWU_P10 PTC5/LLWU_P9 PTC4/LLWU_P8 48 47 46 45 44 43 42 41 40 39 38 37 Pinout PTE20 7 30 PTB3 PTE21 8 29 PTB2 VDDA 9 28 PTB1 VREFH 10 27 PTB0/LLWU_P5 VREFL 11 26 RESET_b VSSA 12 25 PTA19 24 PTB16 PTA18 31 23 6 VSS VREGIN 22 PTB17 VDD 32 21 5 PTA4 VOUT33 20 PTC0 PTA3 33 19 4 PTA2 USB0_DM 18 PTC1/LLWU_P6/RTC_CLKIN PTA1 34 17 3 PTA0 USB0_DP 16 PTC2 PTE25 35 15 2 PTE24 VSS 14 PTC3/LLWU_P7 PTE30 36 13 1 PTE29 VDD Figure 19. KL25 48-pin QFN pinout diagram KL25 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012. Freescale Semiconductor, Inc. 51 PTD7 PTD6/LLWU_P15 PTD5 PTD4/LLWU_P14 PTC7 PTC6/LLWU_P10 PTC5/LLWU_P9 PTC4/LLWU_P8 32 31 30 29 28 27 26 25 Revision History 21 PTB1 VOUT33 5 20 PTB0/LLWU_P5 VREGIN 6 19 RESET_b VDDA 7 18 PTA19 VSSA 8 17 PTA18 PTA0 PTE30 16 4 VSS USB0_DM 15 PTC1/LLWU_P6/RTC_CLKIN VDD 22 14 3 PTA4 USB0_DP 13 PTC2 PTA3 23 12 2 PTA2 VSS 11 PTC3/LLWU_P7 PTA1 24 10 1 9 PTE0 Figure 20. KL25 32-pin QFN pinout diagram 9 Revision History The following table provides a revision history for this document. Table 30. Revision History Rev. No. Date Substantial Changes 1 7/2012 Initial NDA release. 2 9/2012 Completed all the TBDs, initial public release. 3 9/2012 Updated Signal Multiplexing and Pin Assignments table to add UART2 signals. KL25 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012. 52 Freescale Semiconductor, Inc. How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, EL516 2100 East Elliot Road Tempe, Arizona 85284 +1-800-521-6274 or +1-480-768-2130 www.freescale.com/support Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) www.freescale.com/support Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku, Tokyo 153-0064 Japan 0120 191014 or +81 3 5437 9125 [email protected] Asia/Pacific: Freescale Semiconductor China Ltd. Exchange Building 23F No. 118 Jianguo Road Chaoyang District Beijing 100022 China +86 10 5879 8000 [email protected] Document Number: KL25P80M48SF0 Rev. 3, 9/19/2012 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductors products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any liability, including without limitation consequential or incidental damages. "Typical" parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals", must be validated for each customer application by customer's technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claims alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. RoHS-compliant and/or Pb-free versions of Freescale products have the functionality and electrical characteristics as their non-RoHS-complaint and/or non-Pb-free counterparts. For further information, see http://www.freescale.com or contact your Freescale sales representative. For information on Freescale's Environmental Products program, go to http://www.freescale.com/epp. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.