FREESCALE MPC565MVR56

Freescale Semiconductor, Inc.
Product Brief
MPC565PB/D
Rev. 3, 2/2003
Freescale Semiconductor, Inc...
MPC565/MPC566
Product Brief
This document provides an overview of the MPC565/MPC566 microcontrollers, including a
block diagram showing the major modular components, sections that list the major features,
and differences between the MPC565/MPC566 and the MPC555. The MPC565 and MPC566
devices are members of the Motorola MPC500 RISC Microcontroller family. The parts herein
will be referred to only as MPC565 unless specific parts need to be referenced.
Table 1. MPC565/MPC566 Features
1
Device
Flash
Code Compression
MPC565
1 Mbyte
Code compression not supported
MPC566
1 Mbyte
Code compression supported
Introduction
The MPC565 device offers the following features:
•
•
•
•
•
•
•
•
PowerPC™ core with a floating point unit (FPU) and a burst buffer controller (BBC)
Unified system integration unit (USIU), a flexible memory controller, and improved
interrupt controller
1 Mbyte of Flash memory (UC3F)
— Typical endurance of 100,000 write/erase cycles @ 25ºC
— Typical data retention of 100 years @ 25ºC
36 Kbytes of static RAM (two CALRAM modules)
— 8 Kbytes of normal access or overlay access (sixteen 512-byte regions)
— 4 Kbytes in CALRAM A, 4 Kbytes in CALRAM B
Three time processor units (TPU3)
— TPU3 A and TPU3 B are connected to DPTRAM AB (6 Kbytes)
— TPU3 C is connected to DPTRAM C (4 Kbytes)
A 22-timer channel modular I/O system (MIOS14)
— Same as MIOS1 plus a real-time clock sub-module (MRTCSM), 4 counter
sub-modules (MCSM), and 4 PWM sub-modules (MPWMSM)
Three TouCAN modules (TouCAN_A, TouCAN_B, and TouCAN_C)
Two enhanced queued analog to digital converters (QADC64E A, QADC64E B)
with analog multiplexers (AMUX) for 40 total analog channels. These modules are
configured so each module can access all 40 of the analog inputs to the part.
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Block Diagram
•
Two queued serial multi-channel modules (QSMCM A, QSMCM B), each of which contains a
queued serial peripheral interface (QSPI) and two serial controller interfaces (SCI/UART)
•
-40°C – 125°C ambient temperature, -40°C – 85°C for suffix C devices, -55°C– 125°C for
suffix A devices
•
Debug features:
— A J1850 (DLCMD2) communications module
— A Nexus debug port (class 3) – IEEE-ISTO 5001-1999
— JTAG and background debug mode (BDM)
•
Freescale Semiconductor, Inc...
1.1
Packaging and Electrical
Block Diagram
Figure 1 is a block diagram of the MPC565.
JTAG
Burst
Buffer
Controller 2
512 Kbytes
Flash
512 Kbytes
Flash
U-Bus
DECRAM
(4Kbytes)
PowerPC
4 Kbyte CALRAM B
Core
+
FP
E-Bus
USIU
READI
4 Kbyte Overlay
L2U
L-Bus
32 Kbyte CALRAM A
28 Kbytes SRAM
No Overlay
4 Kbyte Overlay
QADC64E
w/AMUX
QADC64E
w/AMUX
QSMCM
UIMB
I/F
QSMCM
DLCMD2
IMB3
TPU3
6 Kbytes
DPTRAM
TPU3
TPU3
4 Kbytes
DPTRAM
Tou
CAN
Tou
CAN
Tou
CAN
MIOS14
Figure 1. MPC565 Block Diagram
2
MPC565/MPC566 Product Brief
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
Freescale Semiconductor, Inc.
1.2
Detailed Feature List
Detailed Feature List
The MPC565 key features are explained in the following sections.
1.2.1
•
•
1.2.2
Freescale Semiconductor, Inc...
•
1.2.3
•
•
•
•
•
•
•
•
•
1.2.4
•
High Performance CPU System
Fully static design
Four major power saving modes
— On, doze, sleep, deep-sleep and power-down
RISC MCU Central Processing Unit (RCPU)
High-performance core
— PowerPC single issue integer core
— Precise exception model
— Floating point
— Code compression (MPC566 only)
– Compression reduces usage of internal or external Flash memory
– Compression optimized for automotive (non-cached) applications
– New compression scheme decreases code size to 40% –50% of source
MPC500 System Interface (USIU)
MPC500 system interface (USIU, BBC, L2U)
Periodic interrupt timer, bus monitor, clocks, decrementer and time base
Clock synthesizer, power management, reset controller
External bus tolerates 5-V inputs, provides 2.6-V outputs
Enhanced interrupt controller supports a separate interrupt vector for up to eight external and 40
internal interrupts
IEEE 1149.1 JTAG test access port
Bus supports multiple master designs
USIU supports dual-mapping of Flash to move part of internal Flash memory to external bus for
development
External bus, supporting non-wraparound burst for instruction fetches, with up to 8 instructions
per memory cycle
Burst Buffer Controller (BBC) Module
Exception vector table relocation features allow exception table to be relocated to following
locations:
— 0x0000 0000 - 0x0000 1FFF (normal MPC500 exception table location)
— 0x0001 0000 - 0x0001 1FFF (0 + 64 Kbytes; second page of internal Flash)
— Second internal Flash module
— Internal SRAM
— 0x0FFF_0100 (external memory space; normal MPC500 exception table location)
MOTOROLA
MPC565/MPC566 Product Brief
For More Information On This Product,
Go to: www.freescale.com
3
Detailed Feature List
1.2.5
•
•
•
Freescale Semiconductor, Inc...
1.2.6
•
•
•
•
•
•
•
•
•
1.2.7
•
Freescale Semiconductor, Inc.
Flexible Memory Protection Unit
Flexible memory protection units in BBC (IMPU) and L2U (DMPU)
Default attributes available in one global entry
Attribute support for speculative accesses
Memory Controller
Flexible chip selects via memory controller
24-bit address and 32-bit data buses
4- to 16-Mbyte (data) or 4-Gbyte (instruction) region size support
Four-beat transfer bursts, two-clock minimum bus transactions
Use with SRAM, EPROM, Flash and other peripherals
Byte selects or write enables
32-bit address decodes with bit masks
Four instruction regions
Four data regions
1 Mbyte of CDR3 Flash EEPROM Memory (UC3F)
•
•
•
•
•
1 Mbyte Flash
— Two UC3F modules, 512 Kbytes each
Page mode read
Block (64-Kbyte) erasable
External 4.75- to 5.25-V VPP program and erase power supply
Typical endurance of 100,000 write/erase cycles @ 25ºC
Typical data retention of 100 years @ 25ºC
1.2.8
36-Kbyte Static RAM (CALRAM)
•
36-Kbyte static calibration RAM
— Composed of 4-Kbyte and 32-Kbyte CALRAM modules
Fast access: one clock
Keep-alive power
Soft defect detection (SDD)
4 Kbyte calibration (overlay) RAM per module (8 Kbytes total)
Eight 512-byte overlay regions per module (16 regions total)
•
•
•
•
•
1.2.9
•
•
•
•
•
4
General Purpose I/O Support (GPIO)
General-purpose I/O support
Address (24) and data (32) pins can be used as GPIO in single-chip mode
16 GPIO in MIOS14
Many peripheral pins can be used as GPIO when not used as primary functions
5-V outputs with slew rate control
MPC565/MPC566 Product Brief
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
Freescale Semiconductor, Inc.
Detailed Feature List
1.2.10 Debug Features
•
•
•
•
Extensive system debug support
On-chip watchpoints and breakpoints
Program flow tracking
Background debug mode (BDM)
1.2.10.1 Nexus Debug Port (Class 3)
•
•
Nexus/IEEE – ISTO 5001-1999 debug port (Class 3)
Nine- or 16-pin interface
Freescale Semiconductor, Inc...
1.2.10.2 Message Data Link Controller (DLCMD2) Module
•
Two pins muxed with QSMCMB pins. Muxing controlled by QSMCMB PCS3 pin assignment
register
•
SAE J1850 Class B data communications network interface compatible and ISO compatible for
low-speed (<125 Kbps) serial data communications in automotive applications
•
10.4 Kbps variable pulse width (VPW) bit format
•
Digital noise filter, collision detection
•
Hardware cyclical redundancy check (CRC) generation and checking
•
Block mode receive and transmit supported
•
4x receive mode supported (41.6 Kbps)
•
Digital loopback mode
•
In-frame response (IFR) types 0, 1, 2, and 3 supported
•
Dedicated register for symbol timing adjustments
•
Inter-module bus 3 (IMB3) slave interface
•
Power-saving IMB3 stop mode with automatic wakeup on network activity
•
Power-saving IMB3 CLOCKDIS mode
•
Debug mode available through IMB3 FREEZE signal or user controllable SOFT_FRZ bit
•
Polling and IMB3 interrupt generation with vector lookup available
1.2.11 Integrated I/O System
•
True 5-V I/O
1.2.11.1 Time Processor Units (TPU3)
•
Three time processing units (TPU3)
— 16 channels each
•
Each TPU3 is a microcoded timer subsystem
•
One 6-Kbyte and one 4-Kbyte dual-port TPU RAM (DPTRAM), one (6-Kbyte) shared by two
TPU3 modules for TPU microcode and the 4-Kbyte dedicated to the third TPU3 for microcode.
MOTOROLA
MPC565/MPC566 Product Brief
For More Information On This Product,
Go to: www.freescale.com
5
Detailed Feature List
Freescale Semiconductor, Inc.
1.2.11.2 22-Channel Modular I/O System (MIOS14)
•
•
•
•
Freescale Semiconductor, Inc...
•
22-channel MIOS timer (MIOS14)
Six modulus counter submodules (MCSM)
— Four additional MCSM submodules compared to MIOS1
10 double action submodules (DASM).
12 dedicated PWM submodules (PWMSM)
— Four additional PWM submodules compared to MIOS1 (shared with MIOS GPIO pins)
MIOS real-time clock submodule (MRTCSM) provides low power clock/counter
— Requires external 32-KHz crystal
— Uses four pins: two for 32-KHz crystal, two for power/ground.
1.2.12 Two Enhanced Queued Analog-to-Digital Converter
Modules (QADC64E)
•
•
•
•
•
•
Two enhanced queued analog to digital converters (QADC64E A, QADC64E B) with AMUXes
for 40 total analog channels.
10 bit A/D converter with internal sample/hold
— Typical conversion time is 4 µs (250-Kbyte samples/sec)
— Two conversion command queues of variable length
Automated queue modes initiated by:
— External edge trigger/level gate
— Software command
— Periodic/interval timer, assignable to both queue 1 and 2
64 result registers in each QADC64E module
— Output data is right or left justified, signed or unsigned
Synchronized clock mode allows both QADC64Es to see the same conversion clock. This allows
the two modules to look like one large QADC with four queues.
Conversions alternate reference (ALTREF) pin. This pin can be connected to a different reference
voltage
1.2.13 Three CAN 2.0B Controller (TouCAN) Modules
•
•
•
•
•
•
•
•
•
•
6
Three TouCAN modules (TouCAN_A, TouCAN_B, and TouCAN_C)
16 message buffers each, programmable I/O modes
Maskable interrupts
Programmable loopback for self-test operation
Independent of the transmission medium (external transceiver is assumed)
Open network architecture, multimaster concept
High immunity to EMI
Short latency time for high-priority messages
Low power sleep mode, with programmable wake up on bus activity
TouCAN_C pins shared with MIOS14 GPIO pins
MPC565/MPC566 Product Brief
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
Freescale Semiconductor, Inc.
Detailed Feature List
1.2.14 Queued Serial Multi-Channel Modules (QSMCM)
•
Freescale Semiconductor, Inc...
•
•
Two queued serial modules with one queued-SPI and two SCI each (QSMCM_A, QSMCM_B)
— QSMCM_A matches full MPC555 QSMCM functionality
— QSMCM_B has pins muxed with DLCMD2 module
– Two pins are muxed with DLCMD2 (J1850) transmit and receive pins
(B_PCS3_J1850_TX and B_RXD2_J1850_RX)
– QSMCM B vs J1850 mux control provided by QPAPCS3 bit in QSMCM pin assignment
register (PQSPAR)
Queued-SPI
— Provides full-duplex communication port for peripheral expansion or interprocessor
communication
— Up to 32 preprogrammed transfers, reducing overhead
— Synchronous serial interface with baud rate of up to system clock / 4
— Four programmable peripheral-select pins support up to 16 devices
— Special wrap-around mode allows continuous sampling of a serial peripheral for efficient
interfacing to serial analog-to-digital (A/D) converters
SCI
— UART mode provides NRZ format and half- or full-duplex interface
— 16 register receive buffer and 16 register transmit buffer on one SCI
— Advanced error detection, and optional parity generation and detection
— Word length programmable as 8 or 9 bits
— Separate transmitter and receiver enable bits, and double buffering of data
— Wake-up functions allow the CPU to run uninterrupted until either a true idle line is detected,
or a new address byte is received
1.2.15 Electrical Specifications and Packaging
•
•
40 MHz operation (56 MHz operation is optional for the MPC566)
-40°C – 125°C ambient temperature, -40°C – 85°C for suffix C device, -55°C– 125°C for suffix A
devices
•
2.6 V ± 0.1 V external bus
— External bus is compatible with external memory devices operating from 2.5 V to 3.4 V.
— Extended voltage range (2.7 – 3.4 V) degrades data drive timing by 1.1 ns on date writes.
2.6 ± 0.1 V internal logic
5-V I/O (5.0 ± 0.25 V)
Available in package or bumped die
•
•
•
•
•
Plastic ball grid array (PBGA) packaging
– 388 ball PBGA
– 27 mm x 27 mm body size
1.0 mm ball pitch
MOTOROLA
MPC565/MPC566 Product Brief
For More Information On This Product,
Go to: www.freescale.com
7
Freescale Semiconductor, Inc.
MPC565 Optional Features
1.3
MPC565 Optional Features
The following features of the MPC565 are optional features and may not appear in certain configurations:
2
•
56-MHz operation (40-MHz is default)
•
MPC566 supports code compression
Differences between the MPC565 and the MPC555
The MPC565 is an enhanced version of the MPC555. Most functional features of the MPC555 are
unchanged on the MPC565. Table 2 shows the high level differences.
Table 2. Differences Between Modules of the MPC555 and the MPC565
Freescale Semiconductor, Inc...
Module
MPC555
MPC565
CPU Core
No Change
BBC
BBC with improved code compression 1
BBC
L2U
No Change
SRAM
26-Kbytes
36-Kbyte CALRAM with overlay features
Flash
448-Kbyte CMF
1-Mbyte UC3F
(new programming, etc.)
USIU
USIU
USIU with enhanced interrupt controller
JTAG
No Change
READI
None
New Module
UIMB
QADC64
No Change
2 QADC64 (16 channels on each QADC
for 32 total channels)
QSMCM
2 QADC64E w/AMUXes
( 40 channels accessible from either
QADC64E)
(1) No Change (2)
DLCMD2 (J1850)
None
1
MIOS
MIOS1
MIOS14: MIOS1 with real-time clock
(MRTCSM), 4 more PWMSMs and 4 more
MCSMs
TouCAN
(2) No Change (3)
TPU3
(2) No Change (3)
DPTRAM
(6-Kbytes) No Change (6-Kbytes, 4-Kbytes)
Power Supplies
—
1
8
40 MHz with two power supplies:
nominal 3.3-V to 5.0-V power supplies
56 MHz with two power supplies:
5.0-V I/O, 2.6-V internal logic
Available on some options.
MPC565/MPC566 Product Brief
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
Freescale Semiconductor, Inc.
Additional MPC565 Differences
2.1
Additional MPC565 Differences
The following are additional differences between the MPC555 and the MPC565.
•
Freescale Semiconductor, Inc...
•
•
•
•
•
•
•
•
•
•
•
•
SPI (MISO, MOSI, and SCK) pin drive.
— MPC565 provides 21-ns rise/fall with 200-pf load using CMOS (20%/70%) levels
GPIO on MODCK1 pin outputs only 2.6 V
— MODCK1 pin is in keep-alive power section with no 5-V rail available
— 5.0-V compatibility modes
– Input is 5-V friendly
– 2.6-V output has less slew rate control
– 2.6-V: VOH = 2.3 V
Power supplies for external bus pins
— QVDDL is quiet supply to hold non-switching outputs quiet even when noisy supply
(NVDDL) sags
— QVDDL supplies pre-drive and other pad logic
— NVDDL only supplies final PMOS driver stage
— QVDDL and NVDDL shorted on customer board after filtering
Pull-up and pull-down changes during PORESET and HRESET
— All 2.6-V/5-V pads (external bus: address/data/control) pull down at reset
— All 5-V pads pull up at reset
— Additional control granularity in the PDMCR register
No pull-ups on QSMCM SCI receive pads
A_RXD1_QGPI1, A_RXD2_QGPI2, B_RXD1_QGPI1 pins do not have weak pull-up during
reset or any other time
CLKOUT has 3 drive strength options
— Better matches drive to requirements to reduce EMI
— 25, 50, 100 pf instead of 45 and 90 pf
Change reset value of ENGCLK to maximum divide (crystal/128)
— For a 4-MHz crystal, this is 31.25 KHz
– ENGCLK is selectable between 2.6 V and 5 V
A daisy chain between UC3F modules allows either module to provide the reset configuration
word (RCW)
Censorship operation
— A RCW bit controls whether or not the entire UC3F can be erased while censorship is violated
BBC SPRs (PPC regs) access in two clocks instead of one clock
CALRAM internal protection block size is 8 Kbytes
— Instead of 4 Kbytes on MPC555 LRAM
CALRAM causes machine check exception instead of data storage interrupt (DSI) exception in
certain cases
— For non-overlay CPU core accesses, a DSI exception is taken
— For overlay accesses and any non-core access (slave mode), a machine check exception is
taken
MOTOROLA
MPC565/MPC566 Product Brief
For More Information On This Product,
Go to: www.freescale.com
9
Freescale Semiconductor, Inc.
Additional MPC565 Differences
•
CALRAM causes DSI exception only if the data relocation (DR) bit in the core machine state
register, MSR[DR], is set.
— L2U on MPC555 already followed this protocol, but the LRAM did not. Now all L-bus
peripherals follow this protocol.
— The MSR[DR] bit is described in the reference manual for more information.
•
Four additional PRDS control bits were added to the USIU to allow more granularity of PRDS
control on a part
•
BBC includes a 4-Kbyte DECRAM that can be used if compression is not used or is not available.
Freescale Semiconductor, Inc...
3
SRAM Keep-Alive Power Behavior
The SRAM has three keep-alive power pins (VDDSRAM1, VDDSRAM2, and VDDSRAM3). These pins
provide keep-alive power to the SRAM arrays in the CALRAM modules and the DPTRAM modules.
The VDDSRAM1 pin powers the 32-Kbyte CALRAM A during keep-alive while power is off to the
MPC565 (except for the keep-alive power supplies). CALRAM A keeps all of its 32 Kbytes powered during
power down.
The VDDSRAM2 pin powers the 4-Kbyte CALRAM B module. The VDDSRAM3 pin powers the
DPTRAM modules during keep-alive as well as during normal operation. The CALRAM modules only
power their arrays from the VDDSRAM pins during keep-alive. During normal operation, they are powered
by the normal internal VDD of the part.
The DPTRAM modules (6 Kbytes and 4 Kbytes) and the 4-Kbyte DECRAM in the BBC module power their
arrays via the VDDSRAM3 pin during keep-alive and are supplied by VDD during normal operation.
4
MPC565 Memory Map
The internal memory map is organized as a single 4-Mbyte block. This is shown in Figure 3. This block can
be moved to one of eight different locations. The internal memory space is divided into the following
sections:
•
Flash memory (1 Mbyte) — U-bus memory
•
Static RAM memory (36 Kbytes CALRAM) — L-bus memory
•
Control registers and IMB3 modules (64 Kbytes), partitioned as
— USIU and flash control registers
— UIMB interface and IMB3 modules
— CALRAM and READI control registers (L-bus control register space)
The internal memory block can reside in one of eight possible 4-Mbyte memory spaces. These eight
locations are the first eight 4-Mbyte memory blocks starting with address 0x0000 0000, as shown in
Figure 2. There is a user programmable register in the USIU to configure the internal memory map to one
of the eight possible locations. Programmability of internal memory map location allows multiple chip
system.
The IMB3 address space block in Figure 3 shows memory allocation for IMB3 modules. It does not show
the actual memory space required for individual modules. All modules are mapped to the low address,
numerically, of the memory allocated for that module in the IMB3 address space.
10
MPC565/MPC566 Product Brief
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
Freescale Semiconductor, Inc.
Additional MPC565 Differences
Internal 4-Mbyte Memory Block
(Resides in one of eight locations)
0x0000 0000
0x003F FFFF
0x0040 0000
0x007F FFFF
0x0080 0000
0x00BF FFFF
0x00C0 0000
Freescale Semiconductor, Inc...
0x00FF FFFF
0x0100 0000
0x013F FFFF
0x0140 0000
0x017F FFFF
0x0180 0000
0x01BF FFFF
0x01C0 0000
0x01FF FFFF
0xFFFF FFFF
Figure 2. Memory Map
MOTOROLA
MPC565/MPC566 Product Brief
For More Information On This Product,
Go to: www.freescale.com
11
Freescale Semiconductor, Inc.
Additional MPC565 Differences
0x00 0000
0x07 FFFF
0x08 0000
0x0F FFFF
0x10 0000
0x2F 7FFF
Ox2F 8000
0x2F 8FFF
0x2F 9000
0x2F 9FFF
0x2F A000
UC3F_A Flash
512 Kbytes
UC3F_B Flash
512 Kbytes
Reserved for Flash
(2,016 Kbytes)
DECRAM
4 Kbytes
Reserved
Freescale Semiconductor, Inc...
BBC Control Registers
8 Kbytes
0x2F BFFF
0x2F C000
USIU & Flash Control
0x2F FFFF
16 Kbytes
0x30 0000
UIMB I/F & IMB
Modules
32 Kbytes
0x30 7FFF
0x30 8000
0x37 FFFF
0x38 0000
0x38 00FF
0x38 0100
0x38 3FFF
0x38 4000
Reserved for IMB
480 Kbytes
CALRAM/
Readi Control
256 bytes
Reserved (L-bus Control)
~32 Kbytes
Reserved (L-bus Mem)
444 Kbytes
USIU Control Registers
0x2F C000
UC3F_A Control
(64 bytes)
0x2F C800
UC3F_B Control
(64 bytes)
0x2F C840
DPTRAM_AB
Registers (64 bytes)
DPTRAM_C
Registers (64 bytes)
0x3F 7FFF
0x3F 8000
All 4-Kbytes can be
Overlay Section
CALRAM_B (4 Kbyte)
CALRAM_A
0x3F FFFF
(32 Kbyte)
4-Kbyte Overlay Section
0x30 0000
0x30 0040
DLCMD2 (16 bytes)
0x30 0080
Reserved (3952 bytes)
0x30 0090
DPTRAM_C (4 Kbytes)
0x30 1000
DPTRAM_AB (6 Kbytes)
0x30 2000
Reserved (2 Kbytes)
0x30 3800
TPU3_A (1 Kbytes)
0x30 4000
TPU3_B (1 Kbytes)
0x30 4400
QADC64_A (1 Kbytes)
0x30 4800
QADC64_B (1 Kbytes)
0x30 4C00
QSMCM_A (1 Kbytes)
0x30 5000
QSMCM_B (1 Kbytes)
0x30 5400
Reserved (1 Kbytes)
0x30 5800
TPU3_C (1 Kbytes)
0x30 5C00
MIOS14 (4 Kbytes)
0x3F 6FFF
0x3F 7000
0x2F C87F
0x30 6000
TOUCAN_A (1 Kbytes)
0x30 7000
TOUCAN_B (1 Kbytes)
0x30 7400
TOUCAN_C (1 Kbytes)
0x30 7800
Reserved (896 bytes)
0x30 7900
UIMB Control Registers
(128 bytes)
0x30 7F80
0x30 7FFF
Figure 3. Internal Memory Block
12
MPC565/MPC566 Product Brief
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
MOTOROLA
AN55_A_
PQA3
PQA5
11
12
13
AN59_A_
PQA7
AN79_B_
PQA7
AN71_B_
PQB7
14
AN70_B_
PQB6
AN66_B_
PQB2
AN65_B_
PQB1
AN74_B_ AN68_B_
AN78_B_ MA2_PQA2
PQB4
PQA6
AN75_B_
PQA3
AN73_B_ AN69_B_
AN77_B_ MA1_PQA1
PQB5
PQA5
AN72_B_ AN67_B_
AN76_B_ MA0_PQA0
PQB3
PQA4
15
QVDDL
QVDDL
QVDDL
QVDDL
16
17
A_TPUCH4
VDDH
A_TPUCH3
ETRIG1 B_CNRX0
ETRIG2 A_TPUCH5
A_TPUCH2
18
19
20
21
22
23
24
A_T2CLK
B_TPUCH3
B_TPUCH6
MDO_5_
MPIO32B9
MDO_4_ MDO_6_
MPIO32B10 MPIO32B8
MPC565/MPC566 Product Brief
For More Information On This Product,
Go to: www.freescale.com
VSS
1
2
3
DATA_
SGPIOD0
4
5
DATA_
DATA_
SGPIOD2 SGPIOD4
6
7
8
9
10
11
12
13
14
15
DATA_SGPIOD1
DATA_ DATA_SGPIOD1
DATA_ IRQ1_B_RSV_B_
BG_B_VF0
DATA_
DATA_ DATA_SGPIOD1
0
2
SGPIOD14
6
SGPIOD18
SGPIOC1 _LWP1 BR_B_VF1
SGPIOD6 SGPIOD8
_IWP2
RD_WR_B
WE_B_AT0
16
17
IRQ0_B_
SGPIOC0 WE_B_AT3
OE_B
18
CS2_B
CS0_B
19
TSIZ1
BURST_B
TSIZ0
20
TA_B
TS_B
B0EPEE
NC
VDD
21
22
BUCLK
EPEE ENGCLK_
BDIP_B
CLKOUT
VDD
DATA_SGPIOD1
DATA_
DATA_
DATA_
DATA_
DATA_ DATA_SGPIOD9
BB_B_
1
SGPIOD13 SGPIOD15 SGPIOD17 _RETRY_B_
SGPIOC3 VF2_IWP3
SGPIOD5 SGPIOD7
CS1_B
VSS
DATA_
DATA_
SGPIOD1 SGPIOD3
TEA_B IRQ2_B_CR_B_S
GPIOC2 WE_B_AT2
AF
VDD
IRQ3_B_KR_B
_SGPIOC4
VSS
VDD
DATA_
DATA_
DATA_
DATA_
DATA_
DATA_
DATA_
DATA_ IRQ4_B_AT2
SGPIOD31 SGPIOD30 SGPIOD28 SGPIOD26 SGPIOD25 SGPIOD23 SGPIOD21 SGPIOD19
QVDDL
VSS
NC
AE
CS3_B BI_B_STS_B
QVDDL
WE_B_AT1 NVDDL
ADDR_
SGPIOA29
NVDDL
AD
SGPIOC7_
IRQO
UT_B_LWP0
AC
NVDDL
VSS
NC
ADDR_
SGPIOA28
AB
DATA_
DATA_
DATA_
NVDDL SGPIOD24
SGPIOD22 SGPIOD20
QVDDL
ADDR_
ADDR_
ADDR_
SGPIOA26 SGPIOA27 SGPIOA31
QVDDL
ADDR_
ADDR_
ADDR_
ADDR_
SGPIOA24 SGPIOA25 SGPIOA15 SGPIOA30
AA
23
NC
VDD
VSS
VSSF
24
VDD
VSS
QVDDL
25
VSS
QVDDL
IRQ5_B_
SGPIOC5_
MODCK1
IRQ7_B_
MODCK3
IRQ6_B_ RSTCONF_
MODCK2 B_TEXP
A_CNRXO
QVDDL SRESET_B
HRESET_B
PORESET_B
_TRST_B
EXTCLK A_CNTXO
AB
AA
Y
W
V
26
QVDDL
VDDSYN
XFC
AF
AE
AD
VSSSYN AC
EXTAL
XTAL
KAPWR
VFLASH A_PCS1_ PULLSEL
QGPIO1
A_RXD2_
B_RXD1_
QPI2
(C3F_SUP2) QGPI1
U
R
T
B_TXD2_
QGPO2
P
A_RXD1_
A_PCS3_
A_MOSI_
QPI1
QGPIO5 QGPIO3
(C3F_IOUT)
(C3F_SUP1)
B_TXD1_
QGPO1
B_PCS3_ B_MOSI_
J1850_TX QGPIO5
N
M
L
A_SCK_
B_RXD2_
J1850_RX QGPIO6
(C3F_CLK)
A_MISO_
QGPIO4
B_PCS2_
QGPIO2
B_MISO_
QGPIO4
VFLS1_ B_PCS0_SS B_PCS1_
MPIO32B4 __BQGPIO0 QGPIO1
A_PCS0_
SS_B_ A_TXD2_
QGPIO0 QGPO2
A_PCS2_
QGPIO2
A_TXD1_
QGPO1
B_SCK_
QGPIO6
B_ECK
VDDH
VDDF
ADDR_
SGPIOA10
VF0_
MPIO32B0
MPWM4_
VFLS0_
VF1_
VF2_
MPIO32B5 MPIO32B3
MPIO32B1 MPIO32B2
Y
VSS
VSS
VSS
J
G
F
MPWM20_
MPWM16 MPIO32B11
MDA29
MDA13
H
C_CNRX0_
MPIO32B14 MPIO32B15 MPWM19
ADDR_
ADDR_
ADDR_
ADDR_
SGPIOA22 SGPIOA23 SGPIOA13 SGPIOA14
VSS
VSS
VSS
VSS
VSS
VSS
NVDDL
VSS
VSS
VSS
VSS
VSS
VSS
ADDR_
ADDR_
ADDR_
ADDR_
SGPIOA20 SGPIOA21 SGPIOA11 SGPIOA12
VSS
VSS
VSS
VSS
VSS
VSS
W
VSS
VSS
VSS
VSS
VSS
VSS
ADDR_
ADDR_
SGPIOA18 SGPIOA19 ADDR_
SGPIOA9
VSS
VSS
VSS
VSS
VSS
VSS
V
NVDDL
SGPIOC6_
FRZ_
PTR_B
IWP1_
VFLS1
MDO_0
VSS
VSS
VSS
U
IWP0_
VFLS0
MDO_2
MDO_1 TDO_DSDO
MDO_3 MSEO_B
MCKO
JCOMP
MDO_7_
MPIO32B7
TMS
MSEI_B
RSTI_B
EVTI_B
TDI_DSDI
MCKI
MDI_1
MDI_0 TCK_DSCK
C_TPUCH4
C_TPUCH0
C_TPUCH1
C_TPUCH2
ADDR_
ADDR_
SGPIOA16 SGPIOA17 ADDR_
SGPIOA8
T
R
P
N
M
L
K
C_TPUCH3 C_TPUCH13
MDA15
MPWM2
MPWM3
C_TPUCH5
C_TPUCH6
J
D
C
B
MPWM17 E
B_TPUCH0
B_TPUCH15
VDD
A
MPWM1
MPWM0
MDA28
MDA11
B_T2CLK
B_TPUCH2
VDD
VSS
VSS
26
MPWM21_ C_CNTX0_
MDA14 MPIO32B12
MPIO32B13 K
MDA31
C_T2CLK
MDA30
C_TPUCH8
VSSRTC C_TPUCH14 C_TPUCH15
MPWM18
B_TPUCH1
VDD
C_TPUCH7
VDD
VSS
C_TPUCH9
VDD
NVDDL
H
VDDH
A_TPUCH7 A_TPUCH13 A_TPUCH0 B_TPUCH9
VSS
B_TPUCH7 B_TPUCH13
A_TPUCH9 A_TPUCH12 A_TPUCH15 B_TPUCH4 B_TPUCH11 B_TPUCH8
A_TPUCH8 A_TPUCH11
MDA27
F
25
A_TPUCH6 A_TPUCH10 A_TPUCH14 A_TPUCH1 B_TPUCH5 B_TPUCH10 B_TPUCH12 B_TPUCH14
NOTE: This is a top down view of the balls.
PQB7
AN47_ANZ_ AN51_A_
A_PQB3
DATA_
DATA_
SGPIOD29 SGPIOD27
AN82
PQB6
AN46_ANY_ AN50_A_ AN54_A_ AN57_A_
A_PQB2
MA2_PQA2
AN58_A_
PQA6
AN52_A_ AN56_A_
AN49_A_ MA0_PQA0
PQB5
PQA4
10
VSSA
9
VDDA
MDA12
VDDH
8
C_TPUCH10 C_TPUCH11 C_TPUCH12 VDDSRAM3
VDD
AN86
AN83
AN81
7
AN53_A_
AN48_A_ MA1_PQA1
PQB4
G
VSS
VDDH
6
AN80
MPWM5_
MPIO32B6
B_CNTX0 VDDSRAM1
VSS
VDD
AN87
AN45_ANX_
A_PQB1
VDD
AN85
ALTREF
AN44_ANW_
A_PQB0
5
AN84
NVDDL
XTAL32
E
VDDSRAM2
VSS
VDDRTC
C
EXTAL32
VDD
VSS
B
4
VRL
3
VRH
5
D
2
AN64_B_
PQB0
1
VDD
A
Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc.
Additional MPC565 Differences
MPC565 Pinout Diagram
Figure 4 shows the pinout for the MPC565.
Figure 4. MPC565 Pinout Diagram
13
Freescale Semiconductor, Inc.
Additional MPC565 Differences
Freescale Semiconductor, Inc...
THIS PAGE INTENTIONALLY LEFT BLANK
14
MPC565/MPC566 Product Brief
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
Freescale Semiconductor, Inc.
Additional MPC565 Differences
Freescale Semiconductor, Inc...
THIS PAGE INTENTIONALLY LEFT BLANK
MOTOROLA
MPC565/MPC566 Product Brief
For More Information On This Product,
Go to: www.freescale.com
15
Freescale Semiconductor, Inc.
HOW TO REACH US:
USA/EUROPE/LOCATIONS NOT LISTED:
Motorola Literature Distribution
P.O. Box 5405, Denver, Colorado 80217
1-303-675-2140 or 1-800-441-2447
JAPAN:
Freescale Semiconductor, Inc...
Motorola Japan Ltd.
SPS, Technical Information Center
3-20-1, Minami-Azabu Minato-ku
Tokyo 106-8573 Japan
81-3-3440-3569
Information in this document is provided solely to enable system and software implementers to use
ASIA/PACIFIC:
Motorola products. There are no express or implied copyright licenses granted hereunder to design
Motorola Semiconductors H.K. Ltd.
Silicon Harbour Centre, 2 Dai King Street
Tai Po Industrial Estate, Tai Po, N.T., Hong Kong
852-26668334
or fabricate any integrated circuits or integrated circuits based on the information in this document.
TECHNICAL INFORMATION CENTER:
use of any product or circuit, and specifically disclaims any and all liability, including without
1-800-521-6274
limitation consequential or incidental damages. “Typical” parameters which may be provided in
HOME PAGE:
http://www.motorola.com/semiconductors
Motorola reserves the right to make changes without further notice to any products herein.
Motorola makes no warranty, representation or guarantee regarding the suitability of its products
for any particular purpose, nor does Motorola assume any liability arising out of the application or
Motorola data sheets and/or specifications can and do vary in different applications and actual
performance may vary over time. All operating parameters, including “Typicals” must be validated
for each customer application by customer’s technical experts. Motorola does not convey any
license under its patent rights nor the rights of others. Motorola products are not designed,
intended, or authorized for use as components in systems intended for surgical implant into the
body, or other applications intended to support or sustain life, or for any other application in which
the failure of the Motorola product could create a situation where personal injury or death may
occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized
application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries,
affiliates, and distributors harmless against all claims, costs, damages, and expenses, and
reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that Motorola was
negligent regarding the design or manufacture of the part.
Motorola and the Stylized M Logo are registered in the U.S. Patent and Trademark Office.
digital dna is a trademark of Motorola, Inc. The described product contains a PowerPC processor
core. The PowerPC name is a trademark of IBM Corp. and used under license. All other product
or service names are the property of their respective owners. Motorola, Inc. is an Equal
Opportunity/Affirmative Action Employer.
© Motorola, Inc. 2003
MPC565PB/D
For More Information On This Product,
Go to: www.freescale.com