PHILIPS SAA7201H

INTEGRATED CIRCUITS
DATA SHEET
SAA7201
Integrated MPEG2 AVG decoder
Objective specification
File under Integrated Circuits, IC02
1997 Jan 29
Philips Semiconductors
Objective specification
Integrated MPEG2 AVG decoder
SAA7201
FEATURES
MPEG2 audio
General
• Decoding of 2 channel, layer I and II MPEG audio;
support for mono, stereo, intensity stereo and dual
channel mode
• Uses single external Synchronous DRAM (SDRAM)
organized as 1M × 16 interfacing at 81 MHz; compatible
with the SDRAM ‘lite’ or ‘PC’
• Constant and variable bit rates up to 448 kbit/s
• Audio sampling frequencies: 48, 44.1, 32, 24, 22.05 and
16 kHz
• Fast external CPU interface; 16-bit data + 8-bit address
• Dedicated input for audio and video data in PES or ES
format; data input rate: ≤9 Mbytes/s in byte mode;
≤20 Mbit/s in bit serial mode; audio and/or video data
can also serve as input via CPU interface
• CRC error detection
• Selectable output channel in dual channel mode
• Independent volume control for both channels and
programmable inter-channel crosstalk control through a
baseband audio processing unit
• Single 27 MHz external clock for time base reference
and internal processing; all required decoding and
presentation clocks are generated internally
• Storage ancillary data up to 54 bytes
• Internal system time base at 90 kHz can be
synchronized via CPU port
• Dynamic range control at output
• Muting possibility via external controller; automatic
muting in case of errors
• Flexible memory allocation under control of the external
CPU enables optimized partitioning of memory for
different tasks
• Generation of ‘beeps’ with programmable tone height,
duration and amplitude
• Boundary scan (JTAG) plus external SDRAM self test
implemented
• Serial two channel digital audio output with 16, 18, 20 or
22 bits per sample, compatible with either I2S or
Japanese formats
• Supply voltage 3.3 V
• Package 160 QFP.
• Serial SPDIF audio output
• Clock output 256 or 384 × fs for external D/A converter
CPU relation
• Audio input buffer in external SDRAM with
programmable size (default is 64 kbit)
• 16-bit data, 8-bit address, or 16-bit multiplexed bus;
Motorola and Intel mode supported
• Programmable processing delay compensation
• Support for fast DMA transfer to either internal registers
or external SDRAM
• Software controlled stop, pause, restricted skip, and
restart functions.
• Maximum sustained rate to the external SDRAM is
9 Mbytes/s.
MPEG2 video
MPEG2 system
• Decoding of MPEG2 video up to main level, main profile
• Parsing of MPEG2 PES and MPEG1 packet streams
• Nominal video input buffer size equals 2.6 Mbit for Video
Main Profile and Main Level (MP@ML)
• Double System Time Clock (STC) counters for
discontinuity handling
• Output picture format: CCIR-601 4 : 2 : 2 interlaced
pictures; picture format 720 × 576 at 50 Hz or 720 × 480
at 60 Hz
• Time stamps or CPU controlled audio/video
synchronization
• 3 : 2 pull-down supported with 24 and 30 Hz sequences
• Support for seamless time base change (edition)
• Support of constant and variable bit rates up to 15 Mbit/s
• Processing of errors flagged by channel decoding or
demux section
• Output interface at 8-bit wide, 27 MHz UYVY
multiplexed bus
• Support for retrieval of PES header and PES private
data.
1997 Jan 29
• Horizontal and vertical pan and scan allows the
extraction of a window from the coded picture
2
Philips Semiconductors
Objective specification
Integrated MPEG2 AVG decoder
SAA7201
• Flexible horizontal continuous scaling from 0.5 up to 4
allows easy aspect ratio conversion including support
for 2.21 : 1 aspect ratio movies
• Support of 2, 4, 8 bits/pixel bit-maps in fixed bit-maps or
coded in accordance to the DVB variable/run length
standard for region bases graphics
• Vertical scaling with fixed factors 0.5, 1 or 2 to support
picture scaling and up-sampling
• Optimized memory control in MPEG video decoding
allows for storage of graphical bit-maps up to 1.2 Mbit in
50 Hz and 2.0 Mbit in 60 Hz systems
• Scaling of incoming pictures to 25% of their original size
with anti-aliasing filtering to free screen space for
graphics applications like electronic program guides
• VL/RL encoding enables full screen graphics at
8 bit/pixel in 50 Hz
• Non-full screen MPEG pictures will be displayed in a box
of which position and background colour are adjustable
by the external CPU
• Fast CPU access enables full bit-map updates within a
display field period
• Display colours are obtained via colour look-up tables;
CLUT output is YUVT at 8-bit for each signal component
thus enabling 16M different colours and 6-bit for T
(transparency) which gives 64 mixing levels with video
• Video output may be slaved to internally (master)
generated or externally (slave) supplied HV
synchronization signals; the position of active video is
programmable; MPEG timebase changes do not
affected the display phase
• Bit-map table mechanism to specify a sub-set of entries
if the CLUT is larger than required by the coded bit
pattern; supported bit-map tables are 16 to 256,
4 to 256 and 4 to 16
• Video output direct connectable to SAA718X encoder
family
• Various trick modes under control of external CPU:
• Graphics boxes may not overlap vertically; if 256 entry
CLUT has to be down loaded, a vertical separation of
1 field line is mandatory
– Freeze I or P pictures; restart on I picture
– Freeze on B pictures; restart at any moment
• Internal support for fast block moves in the external
SDRAM during MPEG decoding
– Scanning and decoding of I or I and P pictures
– Single step mode
• Graphics mechanism can be used for signal generation
in the vertical blanking interval; useful for teletext, wide
screen signalling, closed caption etc.
– Repeat/Skip field for time base correction.
Graphics
• Support for a single down-loadable cursor of 1 kpixel
with programmable shape; supported shapes are
8 × 128, 16 × 64, 32 × 32, 64 × 16 and 128 × 8
• Graphics is region based and presented in boxes
independent of video format
• Cursor colours are determined via a 4-entry CLUT with
YUVT at 6, 4, 4 respectively 2 bits; mixing of cursor with
video + graphics in 4 levels
• Screen arrangement of boxes is determined by display
list mechanism which allows for multiple boxes,
background loading, fast switching, scrolling and fading
of regions
1997 Jan 29
• Cursor can be moved freely across the screen without
overlapping restrictions.
3
Philips Semiconductors
Objective specification
Integrated MPEG2 AVG decoder
SAA7201
Due to an optimized architecture for audio and video
decoding, maximum capacity in the external memory and
processing power from the external CPU is available for
the support for graphics.
GENERAL DESCRIPTION
The SAA7201 is an MPEG2 decoder which combines
audio decoding and video decoding. Additionally to these
basic MPEG functions it also provides means for
enhanced graphics and/or on-screen display.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
MIN.
VCC
pad supply voltage
3.0
3.3
3.6
V
IDD(tot)
total supply current at VDD = 3.3 V
−
tbf
−
mA
fCLK
clock frequency
−
27.0
−
−30 ×
10−6
−
3.6
UNIT
functional supply voltage
frequency deviation
3.3
MAX.
VDD
∆fCLK
3.0
TYP.
+30 ×
V
MHz
10−6
ORDERING INFORMATION
PACKAGE
TYPE
NUMBER
NAME
SAA7201H
QFP160
1997 Jan 29
DESCRIPTION
plastic quad flat package; 160 leads (lead length 1.95 mm);
body 28 × 28 × 3.4 mm; high stand-off height
4
VERSION
SOT322-4
Philips Semiconductors
Objective specification
Integrated MPEG2 AVG decoder
SAA7201
BLOCK DIAGRAM
VDDCO1 to
VDDCO4
handbook, full pagewidth
SDRAM_WE
SDRAM_CAS
SDRAM_UDQ
SDRAM_ADDR
(11 to 0)
SDRAM_RAS
77
SDRAM_DATA
(15 to 0)
75
74
78
4
12
READI
CP81M
16
VDDA
CP81MEXT
84
VDD1 to
VDD16
READO
83
81
80
121
16
MEMORY
INTERFACE
A_STROBE
V_STROBE
159
148
8
AV_DATA(0 to 7)
ERROR
VIDEO INPUT
BUFFER & SYNC
AUDIO/VIDEO
INTERFACE
147
VIDEO
DECODER
SYSTEM TIME
BASE UNIT
CPU_TYPE
MUX
CS
DS
AS
R/W
DTACK
ADDRESS(8 to 1)
2
1
8
9
SAA7201
106
DISPLAY
UNIT
10
11
12
8
16
DMA_REQ
DMA_ACK
DMA_RDY
DMA_DONE
CLK
RESET
GRAPHICS
UNIT
5
AUDIO
DECODER
124
CLOCK
GENERATION
4
YUV(7 to 0)
119
143
142
145
146
139
AUDIO INPUT
BUFFER & SYNC
JTAG
16
122
MGD322
VSSCO1 to VSSCO4
VSS1 to VSS16
VSSA
Fig.1 Block diagram.
1997 Jan 29
VS
8
4
4
3
6
138
HS
HOST
INTERFACE
DATA(15 to 0)
IRQ(3 to 0)
107
5
GRPH
SD
SCLK
WS
SPDIF
FSCLK
Philips Semiconductors
Objective specification
Integrated MPEG2 AVG decoder
SAA7201
PINNING
SYMBOL
PIN
DESCRIPTION
V
I/O
MUX
1
multiplexed/non-multiplexed (active LOW) bus input
5.0
I
CPU_TYPE
2
Intel/Motorola (active LOW) selection input
5.0
I
DMA_ACK
3
DMA acknowledge input
3.3
I
DMA_REQ
4
DMA request input and output
3.3
I/O
DMA_DONE
5
DMA end input
3.3
I
DMA_RDY
6
DMA ready output
3.3
O/Z
VSS1
7
ground for pad ring
3.3
−
CS
8
chip select input
5.0
I
DS
9
data strobe input
5.0
I
AS
10
address strobe input
5.0
I
R/W
11
read/write (active LOW) input
5.0
I
DTACK
12
data acknowledge output
5.0
O/Z
VDD1
13
supply for pad ring
3.3
−
IRQ0
14
individually maskable interrupts
3.3
O/Z
IRQ1
15
individually maskable interrupts
3.3
O/Z
IRQ2
16
individually maskable interrupts
3.3
O/Z
IRQ3
17
individually maskable interrupts
3.3
O/Z
VSS2
18
ground for pad ring
−
−
VSSCO1
19
ground for core logic
−
−
VDDCO1
20
supply for core logic
3.3
−
DATA0
21
CPU data interface
5.0
I/O
DATA1
22
CPU data interface
5.0
I/O
DATA2
23
CPU data interface
5.0
I/O
DATA3
24
CPU data interface
5.0
I/O
VDD2
25
supply for pad ring
3.3
−
DATA4
26
CPU data interface
5.0
I/O
DATA5
27
CPU data interface
5.0
I/O
DATA6
28
CPU data interface
5.0
I/O
DATA7
29
CPU data interface
5.0
I/O
VSS3
30
ground for pad ring
−
−
DATA8
31
CPU data interface
5.0
I/O
DATA9
32
CPU data interface
5.0
I/O
DATA10
33
CPU data interface
5.0
I/O
DATA11
34
CPU data interface
5.0
I/O
VDD3
35
supply for pad ring
−
−
DATA12
36
CPU data interface
5.0
I/O
DATA13
37
CPU data interface
5.0
I/O
DATA14
38
CPU data interface
5.0
I/O
DATA15
39
CPU data interface
5.0
I/O
VSS4
40
ground for pad ring
−
−
1997 Jan 29
6
Philips Semiconductors
Objective specification
Integrated MPEG2 AVG decoder
SYMBOL
PIN
SAA7201
DESCRIPTION
V
I/O
ADDRESS1
41
CPU address interface
5.0
I
ADDRESS2
42
CPU address interface
5.0
I
ADDRESS3
43
CPU address interface
5.0
I
ADDRESS4
44
CPU address interface
5.0
I
VDD4
45
supply for pad ring
3.3
−
ADDRESS5
46
CPU address interface
5.0
I
ADDRESS6
47
CPU address interface
5.0
I
ADDRESS7
48
CPU address interface
5.0
I
ADDRESS8
49
CPU address interface
5.0
I
VSS5
50
ground for pad ring
−
−
VSSCO2
51
ground for core logic
−
−
VDDCO2
52
supply for core logic
3.3
−
SDRAM_DATA0
53
memory data interface
3.3
I/O
SDRAM_DATA15
54
memory data interface
3.3
I/O
SDRAM_DATA1
55
memory data interface
3.3
I/O
VDD5
56
supply for pad ring
3.3
−
SDRAM_DATA14
57
memory data interface
3.3
I/O
SDRAM_DATA2
58
memory data interface
3.3
I/O
SDRAM_DATA13
59
memory data interface
3.3
I/O
VSS6
60
ground for pad ring
−
−
SDRAM_DATA3
61
memory data interface
3.3
I/O
SDRAM_DATA12
62
memory data interface
3.3
I/O
SDRAM_DATA4
63
memory data interface
3.3
I/O
VDD6
64
supply for pad ring
3.3
−
SDRAM_DATA11
65
memory data interface
3.3
I/O
SDRAM_DATA5
66
memory data interface
3.3
I/O
SDRAM_DATA10
67
memory data interface
3.3
I/O
VSS7
68
ground for pad ring
−
−
SDRAM_DATA6
69
memory data interface
3.3
I/O
SDRAM_DATA9
70
memory data interface
3.3
I/O
SDRAM_DATA7
71
memory data interface
3.3
I/O
VDD7
72
supply for pad ring
3.3
−
SDRAM_DATA8
73
memory data interface
3.3
I/O
SDRAM_WE
74
SDRAM write enable output
3.3
O
SDRAM_CAS
75
SDRAM column address strobe output
3.3
O
VSS8
76
ground for pad ring
−
−
SDRAM_RAS
77
SDRAM row address strobe output
3.3
O
SDRAM_UDQ
78
SDRAM write mask output
3.3
O
VDD8
79
supply for pad ring
3.3
−
READI
80
read command input
3.3
I
1997 Jan 29
7
Philips Semiconductors
Objective specification
Integrated MPEG2 AVG decoder
SYMBOL
PIN
SAA7201
DESCRIPTION
V
I/O
READO
81
read command output
3.3
O
VSS9
82
ground for pad ring
−
−
CP81MEXT
83
81 MHz clock return path input
3.3
I
CP81M
84
81 MHz memory clock output
3.3
O
VDD9
85
supply for pad ring
3.3
−
SDRAM_ADDR8
86
memory address
3.3
O
SDRAM_ADDR9
87
memory address
3.3
O
SDRAM_ADDR11 88
memory address
3.3
O
VSS10
89
ground for pad ring
−
−
SDRAM_ADDR7
90
memory address
3.3
O
SDRAM_ADDR10 91
memory address
3.3
O
SDRAM_ADDR6
92
memory address
3.3
O
VDD10
93
supply for pad ring
3.3
−
SDRAM_ADDR0
94
memory address
3.3
O
SDRAM_ADDR5
95
memory address
3.3
O
SDRAM_ADDR1
96
memory address
3.3
O
VSS11
97
ground for pad ring
−
−
SDRAM_ADDR4
98
memory address
3.3
O
SDRAM_ADDR2
99
memory address
3.3
O
SDRAM_ADDR3
100
memory address
3.3
O
VSSCO3
101
ground for core logic
−
−
VDDCO3
102
supply for core logic
3.3
−
VDD11
103
supply for pad ring
3.3
−
TEST8
104
IC test interface
3.3
I/O
TEST7
105
IC test interface
3.3
I/O
HS
106
horizontal synchronization input and output
3.3
I/O
VS
107
vertical synchronization input and output
3.3
I/O
VSS12
108
ground for pad ring
−
−
YUV0
109
YUV video output at 27 MHz
3.3
O/Z
YUV1
110
YUV video output at 27 MHz
3.3
O/Z
YUV2
111
YUV video output at 27 MHz
3.3
O/Z
YUV3
112
YUV video output at 27 MHz
3.3
O/Z
VDD12
113
supply for pad ring
3.3
−
YUV4
114
YUV video output at 27 MHz
3.3
O/Z
YUV5
115
YUV video output at 27 MHz
3.3
O/Z
YUV6
116
YUV video output at 27 MHz
3.3
O/Z
YUV7
117
YUV video output at 27 MHz
3.3
O/Z
TEST6
118
IC test interface
3.3
I/O
GRPH
119
indicator for graphics information output
3.3
O
TEST5
120
IC test interface
3.3
I/O
1997 Jan 29
8
Philips Semiconductors
Objective specification
Integrated MPEG2 AVG decoder
SYMBOL
PIN
SAA7201
DESCRIPTION
V
I/O
VDDA
121
supply for analogue blocks
3.3
−
VSSA
122
ground for analogue blocks
−
−
VSS13
123
ground for pad ring
−
−
CLK
124
27 MHz clock input
3.3
I
VSS14
125
ground for pad ring
−
−
TCLK
126
boundary scan test clock input
3.3
I
TRST
127
boundary scan test reset input
3.3
I
TMS
128
boundary scan test mode select input
3.3
I
TDO
129
boundary scan test data output
3.3
O
TDI
130
boundary scan test data input
3.3
I
VDD13
131
supply for pad ring
3.3
−
TEST4
132
IC test interface
3.3
I/O
TEST3
133
IC test interface
3.3
I/O
TEST2
134
IC test interface
3.3
I/O
TEST1
135
IC test interface
3.3
I/O
TEST0
136
IC test interface
3.3
I/O
VDD14
137
supply for pad ring
3.3
−
RESET
138
hard reset input (active LOW)
3.3
I
FSCLK
139
256 or 384 fs (audio sampling) output
3.3
O/Z
VDDCO4
140
supply for core logic
3.3
−
VSSCO4
141
ground for core logic
−
−
SCLK
142
serial audio clock output
3.3
O/Z
SD
143
serial audio data output
3.3
O/Z
VSS15
144
ground for pad ring
−
−
WS
145
word select output
3.3
O/Z
SPDIF
146
digital audio output
3.3
O/Z
ERROR
147
flag for bitstream error input
5.0
I
V_STROBE
148
video strobe input
5.0
I
VDD15
149
supply for pad ring
3.3
−
AV_DATA0
150
MPEG input port for PES data
5.0
I
AV_DATA1
151
MPEG input port for PES data
5.0
I
AV_DATA2
152
MPEG input port for PES data
5.0
I
AV_DATA3
153
MPEG input port for PES data
5.0
I
VSS16
154
ground for pad ring
−
−
AV_DATA4
155
MPEG input port for PES data
5.0
I
AV_DATA5
156
MPEG input port for PES data
5.0
I
AV_DATA6
157
MPEG input port for PES data
5.0
I
AV_DATA7
158
MPEG input port for PES data
5.0
I
A_STROBE
159
audio strobe input
5.0
I
VDD16
160
supply for pad ring
3.3
−
1997 Jan 29
9
Philips Semiconductors
Objective specification
123 VSS13
122 VSSA
121 VDDA
124 CLK
126 TCLK
125 VSS14
127 TRST
128 TMS
130 TDI
129 TDO
132 TEST4
131 VDD13
133 TEST3
134 TEST2
135 TEST1
136 TEST0
138 RESET
137 VDD14
139 FSCLK
142 SCLK
141 VSSCO4
140 VDDCO4
SAA7201
143 SD
145 WS
144 VSS15
146 SPDIF
148 V_STROBE
147 ERROR
150 AV_DATA0
149 VDD15
151 AV_DATA1
152 AV_DATA2
153 AV_DATA3
155 AV_DATA4
154 VSS16
156 AV_DATA5
157 AV_DATA6
158 AV_DATA7
159 A_STROBE
handbook, full pagewidth
160 VDD16
Integrated MPEG2 AVG decoder
MUX
1
120 TEST5
CPU_TYPE
2
119 GRPH
DMA_ACK
3
118 TEST6
DMA_REQ
4
117 YUV7
DMA_DONE
5
116 YUV6
DMA_RDY
VSS1
6
115 YUV5
7
CS
8
114 YUV4
113 VDD12
DS
9
112 YUV3
AS
10
111 YUV2
R/W
11
110 YUV1
DTACK
VDD1
12
13
109 YUV0
108 VSS12
IRQ0
14
107 VS
IRQ1
15
106 HS
IRQ2
16
105 TEST7
IRQ3
VSS2
17
104 TEST8
18
VSSCO1
19
VDDCO1
20
103 VDD11
102 VDDCO3
101 VSSCO3
DATA0
21
DATA1
22
99
SDRAM_ADDR2
DATA2
23
98
DATA3
VDD2
24
97
SDRAM_ADDR4
VSS11
25
96
SDRAM_ADDR1
DATA4
26
95
SDRAM_ADDR5
DATA5
27
94
DATA6
28
93
SDRAM_ADDR0
VDD10
DATA7
VSS3
29
92
30
91
SDRAM_ADDR6
SDRAM_ADDR10
DATA8
31
90
SDRAM_ADDR7
DATA9
32
89
VSS10
DATA10
33
88
SDRAM_ADDR11
DATA11
VDD3
34
87
SDRAM_ADDR9
35
86
DATA12
36
85
SDRAM_ADDR8
VDD9
DATA13
37
84
CP81M
DATA14
38
83
CP81MEXT
DATA15
VSS4
39
82
VSS9
40
81
READO
1997 Jan 29
80
READI
78
79
77
SDRAM_RAS
SDRAM_UDQ
VDD8
76
74
SDRAM_WE
SDRAM_CAS
VSS8
75
73
SDRAM_DATA8
67
SDRAM_DATA10
VSS7
72
66
SDRAM_DATA5
71
65
SDRAM_DATA11
SDRAM_DATA7
VDD7
64
70
63
69
62
SDRAM_DATA4
VDD6
10
SDRAM_DATA6
SDRAM_DATA9
61
SDRAM_DATA3
SDRAM_DATA12
Fig.2 Pin configuration.
68
60
57
SDRAM_DATA14
59
56
58
55
SDRAM_DATA1
VDD5
SDRAM_DATA2
54
100 SDRAM_ADDR3
SDRAM_DATA13
VSS6
53
SDRAM_DATA0
SDRAM_DATA15
52
51
49
ADDRESS8
VSS5
VSSCO2
VDDCO2
48
ADDRESS7
50
47
44
ADDRESS4
VDD4
46
43
ADDRESS3
ADDRESS5
ADDRESS6
42
ADDRESS2
45
41
ADDRESS1
SAA7201
MGD321
Philips Semiconductors
Objective specification
Integrated MPEG2 AVG decoder
SAA7201
be supplied with bit-maps, determining the contents of the
graphical regions and by a simple set of instructions
determining the appearance of the graphical data on the
screen. Most graphical information should be stored in the
external memory which implies multiple data transfers
between CPU and the external memory. By performing
these data transfers on a direct memory access (DMA)
basis, full bit-maps can be transferred within one video
frame period.
FUNCTIONAL DESCRIPTION
General
The SAA7201 is an MPEG2 decoder which combines
audio decoding, video decoding and enhanced region
based graphics. The decoder operates with a single
16 Mbit external synchronous dynamic random access
memory (SDRAM) and runs from a single external 27 MHz
clock. Due to the optimized memory control for MPEG2
decoding, more than 1 Mbit is available for graphics in
50 Hz systems.
The video output, containing a mix of MPEG video and
graphical data, is at a YUV multiplexed format which can
be directly connected to an external composite video
encoder. The audio output, containing a mix of MPEG
audio and programmable ‘beeps’, is in a serial, I2S or
Japanese format which can be directly supplied to most
commercially available up-sampling audio DA converters.
MPEG2 data can be accepted up to 9 Mbytes/s through a
dedicated byte wide interface. The data on this interface
can be either in PES (Packetized Elementary Stream),
MPEG1 packet or ES (Elementary Stream) format as
described in Chapter “References”. Two additional strobe
signals distinguish between audio and video data.
A functional block diagram of the decoder is given in Fig.1.
Its application environment is depicted in Fig.24. In the
following sections, a brief description of the individual
internal blocks of the MPEG2 decoder will be given.
The internal video decoder is capable of decoding all
MPEG compliant streams up to main level main profile as
specified in Chapter “References”. The audio decoder
implements 2 channel audio decoding according to the
standards in Chapter “References”.
Audio/video interface
In a basic set-top box application the SAA7201 receives
audio and video PES data in a byte wide format at rates up
to 9 Mbytes/s. A timing diagram is shown in Fig.3. Next to
the 8-bit wide data bus an audio and video strobe is
expected at the input. Erroneous data may be flagged via
the error indicator.
All real time audio/video decoding and synchronization
tasks are performed autonomously, so the external
microcontroller only needs to perform high-level tasks like
initialization, status monitoring and trick mode control.
The main support task of the external microcontroller
concerns the control of the graphical unit. This unit should
handbook,
full pagewidth
AV_DATA
video byte (n)
(0 to 7)
≥25 ns
video byte (n + 1)
audio byte (m)
≥25 ns
V_STROBE
≥111 ns
A_STROBE
ERROR
MGD323
Fig.3 Timing diagram of parallel input mode.
1997 Jan 29
11
Philips Semiconductors
Objective specification
Integrated MPEG2 AVG decoder
handbook, full pagewidth
AV_DATA0
SAA7201
video bit (n + 6)
≥25 ns
video bit (n + 7)
audio bit (m + 0)
first bit of a byte
≥25 ns
V_STROBE
≥50 ns
A_STROBE
MGD324
Fig.4 Timing diagram of serial input mode.
Alternatively data can be received in a 1-bit serial format at
rates up to 20 Mbit/s. In this mode, data is input at the LSB
input of the AV_DATA bus. Audio and video data must be
input in multiples of 8 bits. The first bit after switching from
audio to video (or the other way around) must be the first
bit of a byte since this transition will be used for the internal
bit-to-byte conversion.
Clock generation
The clock generation unit generates all the internal
processing clocks, the clock for the system time base
counter and the audio oversampling clock for the audio
DAC. For this purpose a non-integer divider plus a PLL is
implemented. In order to get reliable audio and video
decoding the 27 MHz input clock should be locked
externally to the MPEG time base.
Audio/video data can also be received via the CPU
interface in 8 or 16-bit mode. The peak rate is 27 Mbytes/s
in bursts of ≤128 bytes with a sustained rate up to
9 Mbytes/s. However, the MPEG bit rate is still limited to
15 Mbit/s for video and 448 kbit/s for audio.
Host interface system
The host interface system handles the communication
between on one side the SAA7201 plus SDRAM and on
the other side the external CPU. The interface consists of
a 16-bit wide data bus plus 8 address lines. It is compatible
with both Motorola’s 68xxx and Intel’s x86 family.
An optimized interface with the SAA7208 is also
supported. Via this interface a fast direct access to a large
number of internal status and data registers can be
achieved. Moreover, the external SDRAM can be
accessed via a specific register in combination with an
internally implemented auto increment counter.
The access to the external SDRAM is guaranteed up to a
sustained data rate of 9 Mbyte per second. However, in
practice the achievable data rate can be much higher.
Independent of the input mode all audio and video input
data are stored sequentially in the audio or video input
buffer area of the external memory. The audio and video
data can be either in MPEG2 PES, MPEG1 packet or ES
format.
Memory interface unit
The memory interface takes care of addressing and
control of the 16-Mbit external SDRAM. The SDRAM
should be either JEDEC compliant either the ‘lite/PC’
version.
Due to memory communication requirements this interface
runs at 81 MHz. The SDRAM types used with the
SAA7201 should be organized as 1M × 16, split internally
in two banks, each having 2048 pages of 256 words of
16 bits.
Next to the data and address lines, 4 interrupt lines are
part of the host interface bus. Each interrupt line can
monitor up to 32 internal events which all can be masked
individually. Examples of internal events are audio/video
bit stream information, decoder status, internal error
conditions and input buffer occupation. The latter may be
very useful in interactive applications to serve as input data
request line.
The target SDRAM type is NEC µPD 4516161G5-A12-7FJ
(83 MHz JEDEC version) or NEC
µPD 4516421G5-A83-7FJ-PC (83 Mhz PC version).
1997 Jan 29
12
Philips Semiconductors
Objective specification
Integrated MPEG2 AVG decoder
SAA7201
Data retrieval from the input buffer can be controlled by
DTS time stamps parsed from the PES or MPEG1 packet
stream. For those frames where no DTS time stamp is
present in the video bitstream a DTS is emulated by the
SAA7201.
System time base unit
The system time base unit serves as a timing master for all
internal processes. It consists of two 24-bit wide System
Time Clock (STC) counters, running at 90 kHz. The STCs
will be used as internal synchronization reference for audio
and video.The contents of the STC can be loaded by the
external CPU which should insure that the phase of the
SAA7201 internal STC is identical to the main system time
clock in the system demultiplexer. The CPU should correct
for possible latency problems.
Obviously this emulation mode can also be used when the
input stream is a video elementary stream (ES). The latter
case should be handled by start and stop decode
commands from the CPU.
The external CPU can select to retrieve the video PES
header and/or video PES private data for further software
processing.
Because two counters are implemented, the previous time
base reference which might still be required as reference
for some time in case of time base discontinuity, can be
maintained. Thus all information for audio/video
synchronization is available in the decoder chip and only
minor support of the external controller is required.
Audio input buffer and synchronization control
The audio input buffer and synchronization control
basically behaves identical to its video counter part.
The default buffer size is 64 kbit in this case.
Synchronization will be controlled by PTS time stamps in
the audio Packetized Elementary Stream. Also in this case
an PTS emulation or a free running start/stop controlled
mode are supported.
The synchronization of graphics for e.g. subtitling, should
be controlled by the external CPU.
Video input buffer and synchronization control
The size and position of the video input buffer in the
external SDRAM is programmable. By default 2.6 Mbit/s
are reserved for the video input buffer but in principle any
other value can be programmed. The current fullness of
the video input buffer can be monitored by the CPU and an
internal interrupt will be generated is case of either near
over- or near underflow.
handbook, full pagewidth
Audio decoder
A functional block diagram for the audio decoding part is
depicted in Fig.5.
BUFFER AND
SYNC UNIT
MPEG
AUDIO
DECODER
AUDIO
CLOCK
GENERATOR
AUDIO
BEEP
+
OUTPUT
INTERFACE
Sony or
I2S-bus
SPDIF
DRAM-bus
81 MHz
Audio decoding unit
Fig.5 Audio decoding unit.
1997 Jan 29
13
MGD325
Philips Semiconductors
Objective specification
Integrated MPEG2 AVG decoder
SAA7201
Audio decoding will be performed at a clock locked to the
video decoding clock and only the output interface is
running on the audio oversampling clock.
The output of the audio decoder unit can be mixed with
square waveform audio signals which are generated by a
beep generator. Programmable parameters for the beep
generator are amplitude, frequency and duration.
The audio decoder unit performs the decoding of the
selected MPEG audio stream in a range from 8 up to
448 kbit/s in a fixed or variable bit rate format. Decoding is
restricted to 2 channel, layer I, II MPEG audio at sampling
frequency of 48.0, 44.1, 32.0, 24.0, 22.05 or 16.0 kHz.
The audio output interface module produces stereo base
band output samples on two different outputs at the same
time:
• Serial digital audio in I2S-bus or in Japanese format in
16, 18, 20 or 22-bit
The audio decoder support the stop, mute, and skip
function to support insertion
• SPDIF (Sony/Philips Digital Interface).
Apart from basic MPEG processing the audio decoder
core contain also:
Any of the two outputs may be enabled or set to high
impedance mode. The I2S-bus format with 18-bit sample
precision is shown in Fig.6.
• Support for: stop, mute and skip function.
• Fully parameterized dynamic range compression unit to
decrease the dynamic range of the output signal on
audio frame basis. Depending on the power level a
programmable amplification and offset may be applied.
The difference between I2S-bus and the Japanese format
is that I2S-bus is MSB aligned whereas the Japanese
format is LSB aligned.
The 1-bit serial interface SPDIF contains 64-bit per audio
sample period. Complete frames must be transmitted at
the audio sample rate. Not only left/right information but
also validity flags, channel status, user data and parity
information is contained in an SPDIF frame (see Chapter
“References”).
• Fully programmable base band audio processing unit to
control the gain in both output channels independently
and/or to mix both channels.
• MPEG de-emphasis filtering on the output data, thus
avoiding the need of external analog de-emphasis filter
circuitry.
• Storage buffer for the last 54 bytes of each audio frame.
The CPU can retrieve eventual ancillary data from this
buffer.
handbook, full pagewidth
SCLK
WS
SD
0
31
b17
b0
left sample n
32
63
b17
b0
right sample n
b17
left sample n + 1
MSB aligned
Fig.6 I2S-bus format with 18-bit sample precision.
1997 Jan 29
14
b0
MGD326
Philips Semiconductors
Objective specification
Integrated MPEG2 AVG decoder
SAA7201
The Frame Buffer Management unit (FBM) manages the
allocation of frame buffers in external SDRAM for both
video decoding and display unit and can be programmed
to use less memory in not fully MP@ML bitstreams:
smaller pictures (e.g. 544 × 576), simple profile, etc.
Video decoder
The video decoding unit provides all actions required for
compliant decoding of MPEG2 main level, main profile
coded video bit streams. The decoding process consists of
fixed and variable length decoding, run length decoding,
inverse quantization, inverse discrete cosine
transformation, motion compensation and interpolation.
Apart from decoding compliant MPEG video streams the
decoder deals with some trick modes. Supported are field
or frame freeze at I or P pictures or freeze field on
B-pictures. In the latter case decoding will continue as a
background process and the output can be restarted at
any moment. When receiving non-compliant MPEG
streams the decoder can be switched to a scanning mode
in which only I or I + P frames are decoded while skipping
all other pictures. In the single step mode, the decoder
decodes just one frame and awaits a next step command.
In general the arithmetic decoding result is stored as
reference picture in the external memory.
Decoded B-frames are only stored for the conversion from
the frame coded macro block (MB) to the scanning line
format. In many cases a field storage is sufficient for this
conversion but in some cases the user might decide to use
a full frame storage to enable chroma frame up-conversion
or full performance 3 : 2 pull-down in 60 Hz systems.
Obviously when using less memory for the video decoding
process more memory is available for non-video decoding
tasks.
handbook, full pagewidth
from
input
buffer
VLD
IZZ
The functional diagram of the video decoding unit is shown
in Fig.7.
IQ
IDCT
INTERP
to external
memory
FBM
to display
unit
FLD
MC
from reference
memory
MGD327
Fig.7 Video decoding unit.
1997 Jan 29
15
Philips Semiconductors
Objective specification
Integrated MPEG2 AVG decoder
SAA7201
• The top-field and bottom-field descriptor contain a pixel
based bit-map for the contents of that region for both
fields independently. The bit-maps can be stored in
either straight forward or in a compressed bit-map
format.
Graphics unit
The SAA7201 incorporates the display support for pixel
based graphics. Possible applications are the user
interface, logos and subtitling. Graphical data should be
grouped logically in regions and will be displayed in boxes
at the screen.
• The table-data descriptor defines the tables to be used
for the transformation of bit-maps to display colours.
The definition of each region in the decoder consists of
four parts being a region descriptor, a top-field descriptor,
a bottom-field descriptor and a table-data descriptor:
All descriptors should be loaded under control of the
external CPU in the external memory.
• The region descriptor contains information relevant for
the full region like format, size, position and pointers to
the other descriptors.
The appearance of graphical data at the display is
determined by the assembly of region descriptors in a so
called display list. An example of such a display list for the
4 regions example is shown in Fig.9.
H-start (2)
handbook, full pagewidth
H-size (2)
REGION-1 (VBI-SIGNALS)
V-start (2)
V-size (2)
REGION-2
active
video
REGION-3 (256 ENTRY CLUT)
REGION-4
active
video
MGD328
Fig.8 Graphics unit.
handbook, full pagewidth
128 bit
gfx
anchor
address
position, size, format
pointers to locations in SDRAM
DESCRIPTOR 1
DESCRIPTOR 2
PIXEL
DATA
DESCRIPTOR 3
DESCRIPTOR 4
eodl
CLUT
table
data
bottom-field
top-field
MAP
Fig.9 Display list.
1997 Jan 29
PIXEL
DATA
16
MGD329
Philips Semiconductors
Objective specification
Integrated MPEG2 AVG decoder
SAA7201
The tables are retrieved from the external memory just
before the region is going to be displayed. One table per
region can be updated and for small tables this occurs
during the horizontal blanking interval. However, updating
a 256 entry CLUT may take about one line period which
means that a spatial separation of one line with the
previous region is mandatory in this case. If the required
tables for a certain region are already stored in the local
memory, the table down load action can be skipped.
Basically there is no restriction on the number of different
regions but because regions may not vertically overlap the
practical limit will be the number of lines within a field.
However, one should realize that each region requires its
own 128-bit region descriptor.
The display list will be scanned twice per frame, once for
each display field. The region descriptors should be
ordered properly in the external SDRAM, starting from the
graphics anchor address. The last descriptor in the list
must have the end of display list indicator set.
Additionally some special bits can be set in the region
descriptor.
Multiple pixel bit-maps, CLUTs and map tables may be
stored in the external memory but per region only two
bit-maps (one for each fields) and two tables
(CLUT + map table) may be used. Obviously bit-maps and
tables may be shared by multiple regions.
• Transparency shift: this parameter overrules the pixel
based transparency in order to support fading of the
entire graphical region.
• Zoom: this parameter initiates horizontal pixel repetition.
It should be noted that a copy of pixels in vertical
direction can be achieved by pointing to a single bit-map
for both fields.
Pixel data bit-maps can be described in 2, 4 or 8 bit/pixel
in either a direct bit-map or coded in a one-dimensional (H)
variable and run length encoded format according the
pixel-data-sub-block syntax as specified in Chapter
“References” and illustrated in Chapter “Appendix”.
The actual coding format is specified in the region
descriptor for each region thus allowing different coding
schemes within a picture.
Regions can also be defined in the vertical blanking
interval. In combination with 8 bit/pixel coding, arbitrary
test signals on 13.5 MHz grid can be programmed.
Possible application areas are teletext, closed caption,
wide screen signalling bits, Video Programming Signals
(VPS) and Vertical Interval Test Signals (VITS).
During display the 2, 4 and 8 bit/pixel bit-maps will be
transformed, eventually with run length decoding, via a
table look-up mechanism into a 4, 16 or 256 different YUV
colours with 8-bit resolution for each component plus a
factor T for mixing of graphics and MPEG video.
As indicated above multiple regions can be specified in a
display list which will be scanned sequentially every frame.
In case of stationary graphics no updates of the display list
are required, but the external CPU can update it
dynamically to achieve scrolling and/or fading of one or
more graphical boxes. The display list mechanism also
allows for non real time transfer of large bit-maps by
keeping that region out of the display list during loading.
In order to obtain maximum flexibility two cascaded tables
are active in this bit-map to pixel conversion as indicated
in Fig.10.
8 LSBs
handbook, full pagewidth
4 LSBs
8
4 LSBs
MAP
TABLE 4 to 8
8
8
8
8
2 LSBs
MAP
TABLE 2 to 8
CLUT
8
8
U
V
T
MGD330
2 LSBs
Fig.10 Bit-map to pixel conversion.
1997 Jan 29
8
Y
17
Philips Semiconductors
Objective specification
Integrated MPEG2 AVG decoder
SAA7201
• In case the resulting number of pixels per line does not
match the 720 pixels/line output format a horizontal
scaler can be activated. This scaling unit can transform
any number of bits below 720 to the required output
format. Internally a poly-phase filter is used which
performs a 64 phases interpolation. Not only
up-conversion but also down-conversion is supported
up to a scaling by a factor 2. Thus horizontal scaling can
be performed in a range from 0.5 up to 64. In practice
the maximum up-conversion factor will be less or equal
to 4.
CURSOR PROCESSING
Additionally to the above defined graphics boxes one
cursor can be activated on the screen. Since the cursor
data is fully stored locally, no overlapping restriction apply
to this box so the cursor can moved over the entire screen.
The cursor can be as large as 1 kpixel with a 2 bits/pixel
colour depth. Obviously data transfer can be done on DMA
basis and need only be performed when a cursor is
required or when its contents must be modified.
The cursor XY dimensions (where the Y dimension refers
to frame lines) can be selected between 8 × 128, 16 × 64,
32 × 32, 64 × 16 and 128 × 8. On top of these shapes, a
zoom with a factor 2 can be applied in both directions
independently.
• In vertical direction the picture can be expanded or
scaled down, in both cases by a factor 2. Expansion with
a factor 2 might be relevant for the up-conversion of SIF
resolution pictures to full screen. The factor 2 scaling, if
combined with the appropriate horizontal scaling, results
is 1⁄4 picture thus freeing-up a large screen area for
graphics. This might be very useful for electronic
program guide applications. It should be noted that in
case of picture compression an anti-aliasing filter can be
activated.
The cursor pixels will be translated via a 4-entry CLUT to
YUV colours and a transparency factor T. The resolution
of the YUV parameters is 6, 4, 4 bits respectively.
The T parameter is coded in 2 bits to enable the mixing
with video and graphics in 4 steps being 100% (cursor
only), 50%, 25% and 0% (fully transparent cursor).
• Shifting: when the resulting MPEG picture is smaller
than the 720 × 576 (480) display format, this picture can
be located anywhere on the display screen.
Moreover, the non-covered area can be given any
background colour.
Display unit
Before feeding the MPEG decoded and graphical data to
the output, a display unit re-formats the MPEG specific
4 : 2 : 0 format to CCIR-601 4 : 2 : 2 format and performs
a mixing between video and graphics where required.
The output picture can be up to 720 × 576 pixels at 50 Hz
or 720 × 480 pixels at 60 Hz.
• Clipping: the amplitude of the MPEG decoded and
re-scaled video signal is kept within the range 16 to 235
for luminance and 16 to 240 for both chrominance
components.
A schematic representation of this unit is shown in Fig.11.
• In a first step a selected window can be retrieved from
the decoded MPEG data. This might be useful for e.g.
pan and scan operations for aspect ratio conversion.
handbook, full pagewidth
MPEG
decoded
picture
WINDOW
EXTRACTION
CHROMA
UP-CONVERSION
SCALING
SHIFTING
64 STEP
MIXER
4 STEP
MIXER
GRAPHICS
CURSOR
CLIPPING
OUTPUT
FORMAT
MGD331
Fig.11 Display unit.
1997 Jan 29
18
to digital
CVBS
encoder
Philips Semiconductors
Objective specification
Integrated MPEG2 AVG decoder
SAA7201
• The chroma up-conversion unit converts the MPEG
4 : 2 : 0 format into the at the output required
4 : 2 : 2 format. This vertical up-conversion is performed
by a simple 8-phase interpolation between two adjacent
lines.
Since the decoder can operate in master or slave mode,
the synchronization signals can be generated by the
decoder or should be delivered by an external device.
In both cases the length and polarity should be
programmed internally.
• The mixer units combine MPEG video with graphics and
cursor information in two steps. In a first step the MPEG
decoded information is mixed with graphical information.
Mixing can be done at pixel basis in 64 steps and is
controlled by the internally implemented colour look up
table. In a second step, the video plus graphics can be
mixed in 4 steps with the internally generated cursor.
The video output samples are supplied in a multiplexed
YUV format to the output. Next to this byte wide YUV
stream, which can directly be supplied to most
commercially available composite video encoder ICs,
three additional signals are delivered at the output.
HREF indicates all active samples; CREF can flag any
combination of pixels: U, V, Yodd and/or Yeven; GRPH
flags all the pixels inside a graphical box.
• The output formatting unit performs two main tasks, i.e.
synchronization and formatting. Synchronization is
characterized by three signals being horizontal (H),
vertical (V) and field parity (FP), all having
programmable length and polarity.
Additionally the full YUV bus can be set to a HIGH
impedance state under control of the signal YUV_ENA.
This might be useful for multiplexing the MPEG decoder
output with any other signal source on static basis.
handbook, full pagewidth
CLK
YUV
'128'
'16'
U0
Y0
V0
Y2
HREF
CREF
(example)
GRPH
MGD332
Fig.12 Timing diagram of graphics information output.
1997 Jan 29
19
Philips Semiconductors
Objective specification
Integrated MPEG2 AVG decoder
SAA7201
Obviously for graphics-only applications all 16 Mbit can be
used for the storage of bit-maps and look-up tables.
JTAG
The SAA7201 supports the standard Boundary Scan test
instructions: bypass, extest, sample, intest, runbist,
idcode.
In Table 1 an overview is given of the required memory
capacity for some user defined modes.
In 50 Hz systems memory capacity can be saved by
restricting the chroma vertical interpolation to field
interpolation. This mode would only bring some extra
chroma resolution in case the input stream contains
progressive coded pictures.
Memory requirements
As indicated before the MPEG source decoder operates
with 16 Mbit of external memory. Several processes
require access to the external memory, mostly being the
video decoding process. In normal main level, main profile
video applications about 1.2 Mbit of memory space is free
for non-video processes. In practice most of this capacity
will be used for graphics. In combination with the internal
variable length decoding, full screen graphics at 8-bit per
pixel is feasible. Moreover, by having introduced a flexible
memory allocation procedure the available memory
capacity for graphics may be enlarged when decoding
lower resolution MPEG pictures or when the input bit rate
is less than 15 Mbit/s.
Table 1
In 60 Hz systems the reduction of storage capacity for
B-frames to field capacity has not only consequences for
the chroma vertical interpolation but also for the
3 : 2 pull-down operation mode. The operation
repeat-first-field is not possible in all cases and a modified
3 : 2 pull-down is performed under the control of the
SAA7201. The user may decide to use this modified
3 : 2 pull-down mode in order to have more memory
available for OSD or graphics.
Required memory capacity for some user defined modes
System
50 Hz
Bit rate (R)
15 Mbit/s
60 Hz
15 Mbit/s
9 Mbit/s
Chroma interpolation
frame
field
field
frame
field
field
3 : 2 pull-down
n.a.
n.a.
n.a.
full MPEG
modified
modified
Picture format
720 × 576
720 × 576
544 × 576
720 × 480
720 × 480
720 × 480
64 kbit
64 kbit
64 kbit
64 kbit
64 kbit
64 kbit
Audio input buffer
Video input buffer
1835 kbit
1835 kbit
1835 kbit
1835 kbit
1835 kbit
1835 kbit
Video implementation buffer (R/P)
600 kbit
600 kbit
400 kbit
500 kbit
500 kbit
300 kbit
Slave synchronization buffer (R/2P)
300 kbit
300 kbit
200 kbit
250 kbit
250 kbit
150 kbit
Reference and decoded picture
13456 kbit
12719 kbit
9609 kbit
12441 kbit
10634 kbit
8042 kbit
Total for video + audio
16255 kbit
15518 kbit
12108 kbit
15090 kbit
13292 kbit
10391 kbit
Remains for OSDG (224 = 16777 kbit)
522 kbit
1259 kbit
4669 kbit
1687 kbit
3485 kbit
6386 kbit
1997 Jan 29
20
Philips Semiconductors
Objective specification
Integrated MPEG2 AVG decoder
SAA7201
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC134).
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VDD
supply voltage (on all supply pins)
3.0
3.6
V
Vmax
maximum voltage on all pins
0
5.5
V
Ptot
total power dissipation
−
tbf
W
Tstg
storage temperature
−55
+150
°C
Tamb
operating ambient temperature
0
+70
°C
Tamb = 25 °C
THERMAL CHARACTERISTICS
SYMBOL
Rth j-a
1997 Jan 29
PARAMETER
thermal resistance from junction to ambient in free air
21
VALUE
UNIT
30
K/W
Philips Semiconductors
Objective specification
Integrated MPEG2 AVG decoder
SAA7201
CHARACTERISTICS
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
Supply
VDD
supply voltage
3.0
3.3
3.6
V
IDD
supply current
−
tbf
−
mA
VIH
HIGH level input voltage
2.0
−
VDD + 2.0
V
Inputs
VIL
LOW level input voltage
−0.5
−
0.8
V
ILI
leakage current
−
−
20
mA
Ci
input capacitance
0
−
10
pF
VOH
HIGH level output voltage
2.4
−
−
V
VOL
LOW level output voltage
−
−
0.4
V
TC
cycle time
37.036
37.037
37.038
ns
δ
duty factor
40
−
60
%
tr
rise time
2
−
4
ns
tf
fall time
2
−
4
ns
Outputs
CLK timing
Input timing with respect to CLK rising edge
tsu
set-up time
8
−
−
ns
th
hold time
0
−
−
ns
Timing (see Figs. 13, 14, 15, 16, 17, 18, 19, 20, 21, 21 and 21)
tsu(A-CS)
address/CS set-up time
20
−
−
ns
th(A-CS)
address/CS hold time
75
−
−
ns
tsu(D-W)
data write set-up time
20
−
−
ns
tsu(D-R)
data read set-up time
20
−
−
ns
trel(D)
data release time
0
−
10
ns
th(CT)
control signal hold time
0
−
−
ns
tW(ACK)
acknowledge pulse width
25
−
−
ns
trel(ACK)
acknowledge release time
0
−
10
ns
td(ACK-R)
delay time for acknowledge read
96
−
125
ns
td(ACK-W)
delay time for acknowledge write
48
−
75
ns
tW(RW)
write/read pulse width
25
−
−
ns
Output timing with respect to CLK rising edge
th
hold time
3
−
td
ns
td
delay time
th
−
20
ns
CL
load capacitance
10
−
30
pF
1997 Jan 29
22
Philips Semiconductors
Objective specification
Integrated MPEG2 AVG decoder
SAA7201
handbook, full pagewidth
ADDRESS
(8 to 1)
ADDRESS
tsu(A-CS)
th(A-CS)
CS
R/W
tW(RW)
trel
DS
td(ACK-W)
trel(ACK)
DTACK
th(D)
tsu(D-W)
DATA
(15 to 0)
tW(ACK)
DATA
MGD333
Fig.13 Motorola write timing (non-multiplexed).
handbook, full pagewidth
ADDRESS
(8 to 1)
ADDRESS
tsu(A-CS)
th(A-CS)
CS
R/W
tW(RW)
trel
DS
td(ACK-R)
tW(ACK)
trel(ACK)
DTACK
tAR
trel(D)
tsu(D-R)
DATA
(15 to 0)
DATA
MGD334
Fig.14 Motorola read timing (non-multiplexed).
1997 Jan 29
23
Philips Semiconductors
Objective specification
Integrated MPEG2 AVG decoder
SAA7201
handbook, full pagewidth
ADDRESS
(8 to 1)
ADDRESS
tsu(A-CS)
th(A-CS)
CS
tW(RW)
trel
R/W
td(ACK-W)
RDY
trel(ACK)
th(D)
tsu(D-W)
DATA
(15 to 0)
DATA
MGD335
Fig.15 Intel write timing (non-multiplexed).
handbook, full pagewidth
ADDRESS
(8 to 1)
ADDRESS
tsu(A-CS)
th(A-CS)
CS
tW(RW)
trel
R/W
td(ACK-R)
tsu(D-R)
RDY
trel(ACK)
tAR
trel(D)
DATA
(15 to 0)
DATA
MGD336
Fig.16 Intel read timing (non-multiplexed).
1997 Jan 29
24
Philips Semiconductors
Objective specification
Integrated MPEG2 AVG decoder
SAA7201
handbook, full pagewidth
CS
tsu(A-CS)
th(A-CS)
DMA_REQ
tW(RW)
trel
DMA_ACK
td(ACK-W)
trel(ACK)
DMA_RDY
th(D)
tsu(D-W)
DATA
(15 to 0)
DATA
MGD337
Fig.17 DMA read access.
handbook, full pagewidth
CS
tsu(A-CS)
th(A-CS)
DMA_REQ
tW(RW)
trel
DMA_ACK
td(ACK-R)
trel(ACK)
DMA_RDY
tAR
trel(D)
tsu(D-R)
DATA
(15 to 0)
DATA
MGD338
Fig.18 DMA write access.
1997 Jan 29
25
Philips Semiconductors
Objective specification
Integrated MPEG2 AVG decoder
SAA7201
handbook, full pagewidth
DMA_REQ
DMA_ACK
tsu(A-CS)
th(A-CS)
DMA_DONE
MGD339
Fig.19 DMA_DONE timing.
handbook, full pagewidth
DATA
(15 to 0)
DATA
tsu(SDR-D)
trel(D)
RDY
tW(ALE)
tsu(ALE-SDR)
tW(SDR)
ALE
tsu(A-CS)
ADDRESS
(8 to 0)
th(A-CS)
ADDRESS
th(CS-ALE)
th(CS)
CS
SYSRD
MGD919
Fig.20 SAA7208 mode; read timing.
1997 Jan 29
26
Philips Semiconductors
Objective specification
Integrated MPEG2 AVG decoder
SAA7201
handbook, full pagewidth
DATA
(15 to 0)
DATA
tW(D-SDR)
th(D-SDR)
RDY
tW(ALE)
tW(SDR)
ALE
tsu(A-CS)
ADDRESS
(8 to 0)
th(A-CS)
ADDRESS
th(CS-ALE)
th(CS)
CS
SYSRD
MGD918
Fig.21 SAA7208 mode; write timing.
1997 Jan 29
27
Philips Semiconductors
Objective specification
Integrated MPEG2 AVG decoder
SAA7201
handbook, full pagewidth
DATA
(15 to 0)
DATA
tsu(D-SDR)
DATA
th(D-SDR)
tsu(D-SDR)
th(D-SDR)
RDY
tW(SDR)
tW(ALE)
tW(SDR)
trel(SDR)
ALE
tsu(A-SDR)
ADDRESS
(8 to 0)
th(A-SDR)
tsu(A-SDR)
ADDRESS
th(A-SDR)
ADDRESS
th(CS-ALE)
th(CS)
CS
SYSRD
MGD920
Fig.22 SAA7208 mode; burst write timing.
1997 Jan 29
28
Philips Semiconductors
Objective specification
Integrated MPEG2 AVG decoder
SAA7201
handbook, full pagewidth
ADDRESS
AD(read)
DATA
tAR
AD(write)
ADDRESS
tsu(A-S)
tsu(D-R)
DATA
th(A-CS)
tsu(D-W)
th(D)
CS
tW(ACK)
RDY
trel(ACK)
tW(A-CS)
ALE
trel(D)
RD
tW(RW)
trel
WR
MGD341
Fig.23 Intel read/write timing multiplexed.
REFERENCES
1. MPEG ISO/IEC 11172-1 International standard; MPEG-1 systems.
2. MPEG ISO/IEC 13818-1 International standard; MPEG-2 systems.
3. MPEG ISO/IEC 11172-2 International standard; MPEG-1 Video.
4. MPEG ISO/IEC 13818-2 International standard; MPEG-2 Video.
5. MPEG ISO/IEC 11172-3 International standard; MPEG-1 Audio.
6. MPEG ISO/IEC 13818-3 International standard; MPEG-2 Audio.
7. DVB subtitling system; working draft 2.0; TM 1398 rev 2.
1997 Jan 29
29
Philips Semiconductors
Objective specification
Integrated MPEG2 AVG decoder
SAA7201
APPLICATION INFORMATION
handbook, full pagewidth
4 Mbit
EPROM
4 Mbit
DRAM
16 Mbit
SDRAM
address data
12
16
control
16
8+3
INT
SAA7208
(DEMUX/MIPS)
I2C-bus
8
SAA7201
L
AUDIO
DA
R
strobe
27.0
MHz
H,V valid
YUV
27 MHz
H, V, FP
TTX/TTXRQ
high
speed
data
CVBS
SAA7183
(EURO-DENC)
RGB
I2C-bus
Fig.24 Application diagram.
1997 Jan 29
Y/C
30
MGD342
Philips Semiconductors
Objective specification
Integrated MPEG2 AVG decoder
SAA7201
APPENDIX
Syntax of pixel-data-sub-block
data type
2 bit/pixel
0001 0000
pixel-code-string of N-coded words
01
1 pixel in colour 1
10
1 pixel in colour 2
11
1 pixel in colour 3
00 01
1 pixel in colour 0
00 00 01
2 pixels in colour 0
00 1L LL CC
L pixels (3 to 10) in colour C
00 00 10 LL LL CC
L pixels (12 to 27) in colour C
end of string
00 00 00
00 00 11 LL LL LL LL CC
L pixels (29 to 284) in colour C
4 bit/pixel
0001
1 pixel in colour 1
↓
↓
↓
↓
0001 0001
1111
1 pixel in colour 15
0000 0000
0000 1100
1 pixel in colour 0
0000 1101
2 pixels in colour 0
0000 0LLL (L>0)
L pixels (3 to 9) in colour 0
0000 10LL CCCC
L pixels (4 to 7) in colour C
0000 1110 LLLL CCCC
L pixels (9 to 24) in colour C
0000 1111 LLLL LL11 CCCC
L pixels (25 to 280) in colour C
8 bit/pixel
00000001
1 pixel in colour 1
00000000-- --00000000
↓
↓
↓
↓
0001 0010
11111111
1 pixel in colour 255
1997 Jan 29
00000000 0LLLLLLL
L pixels (1 to 127) in colour 0
00000000 1LLLLLLL CCCCCCCC
L pixels (3 to 127) in colour C
31
Philips Semiconductors
Objective specification
Integrated MPEG2 AVG decoder
SAA7201
PACKAGE OUTLINE
QFP160: plastic quad flat package;
160 leads (lead length 1.95 mm); body 28 x 28 x 3.4 mm; high stand-off height
SOT322-1
c
y
X
A
120
121
81
80
ZE
e
Q
E HE
A
A2
(A 3)
A1
θ
wM
Lp
bp
L
pin 1 index
detail X
41
160
1
40
ZD
wM
bp
e
v M A
D
B
HD
v M B
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HD
HE
L
Lp
Q
v
w
y
mm
3.95
0.40
0.25
3.70
3.15
0.25
0.40
0.25
0.23
0.13
28.1
27.9
28.1
27.9
0.65
32.2
31.6
32.2
31.6
1.95
1.1
0.7
1.70
1.55
0.3
0.15
0.1
Z D(1) Z E (1)
1.5
1.1
1.5
1.1
θ
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT322-1
1997 Jan 29
REFERENCES
IEC
JEDEC
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
93-08-25
95-02-04
MO112DD1
32
o
8
0o
Philips Semiconductors
Objective specification
Integrated MPEG2 AVG decoder
SAA7201
SOLDERING
Wave soldering
Introduction
Wave soldering is not recommended for QFP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
If wave soldering cannot be avoided, the following
conditions must be observed:
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave)
soldering technique should be used.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “IC Package Databook” (order code 9398 652 90011).
• The footprint must be at an angle of 45° to the board
direction and must incorporate solder thieves
downstream and at the side corners.
Reflow soldering
Even with these conditions, do not consider wave
soldering the following packages: QFP52 (SOT379-1),
QFP100 (SOT317-1), QFP100 (SOT317-2),
QFP100 (SOT382-1) or QFP160 (SOT322-1).
Reflow soldering techniques are suitable for all QFP
packages.
The choice of heating method may be influenced by larger
plastic QFP packages (44 leads, or more). If infrared or
vapour phase heating is used and the large packages are
not absolutely dry (less than 0.1% moisture content by
weight), vaporization of the small amount of moisture in
them can cause cracking of the plastic body. For more
information, refer to the Drypack chapter in our “Quality
Reference Handbook” (order code 9397 750 00192).
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.
Repairing soldered joints
Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.
1997 Jan 29
33
Philips Semiconductors
Objective specification
Integrated MPEG2 AVG decoder
SAA7201
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1997 Jan 29
34
Philips Semiconductors
Objective specification
Integrated MPEG2 AVG decoder
SAA7201
NOTES
1997 Jan 29
35
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TAIPEI, Taiwan Tel. +886 2 2134 2870, Fax. +886 2 2134 2874
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For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications,
Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
Internet: http://www.semiconductors.philips.com
© Philips Electronics N.V. 1997
SCA53
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
547047/1200/01/pp36
Date of release: 1997 Jan 29
Document order number:
9397 750 00989