QorIQ™ Communications Platforms P4 Series P4080 multicore processor Freescale QorIQ™ communications platforms are the next-generation evolution of our leading PowerQUICC communications ® processors. Built using high-performance Power Architecture® cores, QorIQ platforms enable a new era of networking innovation where the reliability, security and quality of service for every connection matters. QorIQ P4080 Multicore Processor The QorIQ P4080 multicore processor, the first product offered in the QorIQ P4 platform series, delivers industry-leading performance in the under 30-watt power category. It combines eight Power Architecture e500mc cores operating at frequencies up to 1.5 GHz with high-performance datapath acceleration logic, as well as networking I/O and other peripheral bus interfaces. Key Features The P4080, built in 45 nm technology, is designed to deliver high-performance, next-generation networking services in a very low power envelope. The QorIQ P4080 processor is designed for combined control and dataplane processing, enabling high-performance layers 2–7 processing. Its high level of integration offers significant performance benefits compared to multiple discrete devices, while also greatly simplifying board design. The processor is well-suited for applications that are highly compute-intensive, I/O-intensive or both. This makes it ideal for applications such as enterprise and service provider routers, switches, media gateways, base station controllers, radio network controllers (RNCs), access gateways for Long Term Evolution (LTE) and general-purpose embedded computing systems in the networking, telecom, industrial, aerospace and defense markets. Freescale delivers a groundbreaking threetiered cache hierarchy on the QorIQ P4 platform. Each core has an integrated Level 1 (L1) cache as well as a dedicated Level 2 (L2) backside cache that can significantly improve performance. Finally, a multi-megabyte Level 3 (L3) cache is also provided for those tasks for which a shared cache is desirable. The CoreNet™ coherency fabric is a key design component of the QorIQ P4 platform. It manages full coherency of the caches and provides scalable on-chip, point-to-point connectivity supporting concurrent traffic to and from multiple resources connected to the fabric, eliminating single-point bottlenecks for non-competing resources. This eliminates bus contention and latency issues associated with scaling shared bus/shared memory architectures that are common in other multicore approaches. QorIQ™ P4080 Block Diagram RegEx Pattern Encryption Matching Engine Buffer Manager 128 KB Backside L2 Cache Queue Manager Power Architecture® e500mc Core 32 KB 32 KB L1 I-Cache L1 D-Cache CoreNet™ Coherency Fabric Frame Manager Frame Manager 1 x 10 Gbps 4 x 1 Gbps Ethernet Ethernet 1 x 10 Gbps 4 x 1 Gbps Ethernet Ethernet Acceleration Interface DDR2/DDR3 SDRAM Controller 1024 KB Frontside L3 Cache DDR2/DDR3 SDRAM Controller Enhanced Local Bus Controller (eLBC) 2 x DUART, 4 x I2C, Interrupt Control, GPIO, SD/MMC, SPI, 2 x USB 2.0/ULPI On-Chip Network 3 x PCI RapidIO Message Unit (RMU) Express® 18-lane SerDes Core 1024 KB Frontside L3 Cache 2 x Serial RapidIO® 2 x 4-ch. DMA Real-Time Debug The QorIQ P4080 multicore processor is To this end, Freescale has partnered with 800 Gbps coherent read bandwidth extremely flexible and can be configured Virtutech to offer a robust, innovative hybrid Queue manager fabric supporting packet- to meet many system application needs. simulation environment that provides a The processor’s e500mc cores, leveraging controlled, deterministic and fully reversible advanced virtualization technology, can environment for the development, debugging work as eight symmetric multiprocessing and benchmarking of software for complex (SMP) cores, or eight completely asymmetric multicore-based architectures. The hybrid multiprocessing (AMP) cores, or they simulator combines Virtutech’s fast, functional can be operated with varying degrees of Simics™ model, with a detailed performance independence with a combination of SMP and model of the platform. This combination AMP groupings. Full processor independence, enables fast hardware concept testing and including the ability to independently boot evaluation, as well as performance verification and reset each e500mc core, is a defining and helps accelerate your development cycle, characteristic of the device. The ability of provide more flexible debug capability and the cores to run different operating systems improve the overall quality of your software. (OSes), or run OS-less, provides the user with significant flexibility in partitioning between control, datapath and applications processing. It also simplifies consolidation of functions previously spread across multiple discrete level queue management and quality of service scheduling • Two 64-bit DDR2/DDR3 SDRAM memory controllers with ECC and interleaving support • Datapath Acceleration Architecture incorporating acceleration for the following functions: Packet parsing, classification and distribution Queue management for scheduling, packet sequencing and congestion management Freescale has also engineered capabilities Hardware Buffer Management for buffer into the QorIQ P4080 to enable advanced allocation and de-allocation debugging while working in tandem with its Cryptographic Security Acceleration ecosystem partners to assure availability processors onto a single device. of tools that can take advantage of these Advanced virtualization technology brings a instruction trace, watchpoint triggers, cross- new level of hardware partitioning through event triggers, performance monitoring an embedded hypervisor that allows system and other debug features as defined by the developers to ensure software running on any Power® ISA. These features enable dynamic CPU only accesses the resources (memory, debug essential for providing visibility into peripherals, etc.) that it is explicitly authorized complex interactions that may occur among to access. The embedded hypervisor enables tasks running on different cores. features. These capabilities include integrated (SEC 4.0) RegEx Pattern Matching (PME 2.0) • Ethernet interfaces Two 10 Gbps Ethernet (XAUI) controllers Eight 1 Gbps Ethernet (SGMII) controllers • High-speed peripheral interfaces Three PCI Express® V2.0 controllers/ports running at up to 5 GHz Two Serial RapidIO® 1.2 controllers/ports safe and autonomous operation of multiple running at up to 3.125 GHz individual operating systems, allowing them to QorIQ P4080 Technical Specifications share system resources, including processor • Eight high-performance Power Architecture cores, memory and other on-chip functions. • Additional peripheral interfaces Two USB controllers with ULPI interface e500mc cores, each with a 32 KB to external PHY instruction and data L1 cache and a private Ecosystem and Developer Environment Developers creating solutions with Power Architecture technology have long benefited from a vibrant support ecosystem, including high-quality tools, OSes and network protocol stacks. Freescale has collaborated with our 128 KB L2 cache SPI controller Three levels of instruction: user, Four I2C controllers supervisor and hypervisor Two dual UARTs Independent boot and reset Secure boot capability partners on the QorIQ P4080 processor to • 2 MB shared L3 CoreNet platform cache continue our strong ecosystem heritage. This • Hierarchical interconnect fabric helps to ensure that the best enablement SD/MMC CoreNet fabric supporting coherent tools are available to cost-effectively meet the and non-coherent transactions with unique development challenges of multicore prioritization and bandwidth allocation architectures and speed your time to market. amongst CoreNet end-points Learn More: Enhanced local bus controller (eLBC) • Multicore programmable interrupt controller (PIC) • Two 4-channel DMA engines For more information about Virtutech Simics, please visit www.virtutech.com. For current information about Freescale products and documentation, please visit www.freescale.com/multicore. Freescale, QorIQ, CoreNet and the Freescale logo are trademarks or registered trademarks of Freescale Semiconductor, Inc. in the U.S. and other countries. All other product or service names are the property of their respective owners. The Power Architecture and Power.org word marks and the Power and Power.org logos and related marks are trademarks and service marks licensed by Power.org. © Freescale Semiconductor, Inc. 2008. Document Number: QP4080FS REV 1