NCP1072, NCP1075 High-Voltage Switcher for Low Power Offline SMPS The NCP1072/NCP1075 products integrate a fixed frequency current mode controller with a 700 V MOSFET. Available in a PDIP−7 or SOT−223 package, the NCP1072/5 offer a high level of integration, including soft−start, frequency−jittering, short−circuit protection, skip−cycle, a maximum peak current set point, ramp compensation, and a Dynamic Self−Supply (eliminating the need for an auxiliary winding). Unlike other monolithic solutions, the NCP1072/5 is quiet by nature: during nominal load operation, the part switches at one of the available frequencies (65, 100 or 130 kHz). When the output power demand diminishes, the IC automatically enters frequency foldback mode and provides excellent efficiency at light loads. When the power demand reduces further, it enters into a skip mode to reduce the standby consumption down to a no load condition. Protection features include: a timer to detect an overload or a short−circuit event, Overvoltage Protection with auto−recovery and AC input line voltage detection. For improved standby performance, the connection of an auxiliary winding stops the DSS operation and helps to reduce input power consumption below 50 mW at high line. http://onsemi.com MARKING DIAGRAMS SOT−223 ST SUFFIX CASE 318E AYW 107xyG G 1 PDIP−7 P SUFFIX CASE 626A P107xPyyy AWL YYWWG x y = Current Limit (2 or 5) = Oscillator Frequency =A (65 kHz), B (100 kHz), C (130 kHz) yyy = 065, 100, 130 A = Assembly Location WL = Wafer Lot Y, YY = Year W, WW = Work Week G or G = Pb−Free Package ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 24 of this data sheet. Features • Built−in 700 V MOSFET with RDS(on) of 11 W • Large Creepage Distance Between High−voltage Pins • Current−Mode Fixed Frequency Operation – 65 / 100 / • Auto−Recovery Overvoltage Protection with Auxiliary • • • • • • • • • 130 kHz (NCP1072 130 kHz on demand only) Peak Current: NCP1072 with 250 mA and NCP1075 with 450 mA Fixed Ramp Compensation Skip−Cycle Operation at Low Peak Currents Only: No Acoustic Noise! Dynamic Self−Supply: No Need for an Auxiliary Winding Internal 1 ms Soft−Start Auto−Recovery Output Short Circuit Protection with Timer−Based Detection © Semiconductor Components Industries, LLC, 2012 November, 2012 − Rev. 2 • • Winding Operation Frequency Jittering for Better EMI Signature, Including Frequency Foldback Mode No Load Input Consumption < 50 mW Frequency Foldback to Improve Efficiency at Light Load Internal Temperature Shutdown These are Pb−Free Devices Typical Applications • Auxiliary / Standby Isolated Power Supplies White Goods / Smart Meter / E−Meter 1 Publication Order Number: NCP1072/D NCP1072, NCP1075 PIN CONNECTIONS VCC 1 8 GND 2 7 GND 6 DRAIN GND 3 FB 4 VCC 1 FB 2 DRAIN 3 GND 4 (Top View) (Top View) SOT−223 PDIP−7 Figure 1. Pin Connections INDICATIVE MAXIMUM OUTPUT POWER RDS(on) − IP 230 Vac 100 – 250 Vac 11 W − 450 mA DSS 14 W 7W 11 W − 450 mA Auxiliary Winding 19 W 10 W NOTE: Informative values only, with Tamb = 50°C, Fsw = 65 kHz, circuit mounted on minimum copper area as recommended. QUICK SELECTION TABLE NCP1072 NCP1075 RDS(on) (W) 11 11 Ipeak (mA) 250 450 Freq (kHz) 65 Package NOTE: 100 130 PDIP / SOT223 NCP1072 130 kHz on demand only. Figure 2. Typical Application Example http://onsemi.com 2 65 100 PDIP / SOT223 130 NCP1072, NCP1075 PIN FUNCTION DESCRIPTION Pin N5 Pin Name Function Pin Description 1 VCC Powers the internal circuitry This pin is connected to an external capacitor. The VCC includes an active shunt which serves as an auto−recovery over voltage protection. 2 NC 3 GND The IC Ground 4 FB Feedback signal input 5 Drain Drain connection 7 GND The IC Ground 8 GND The IC Ground By connecting an opto−coupler to this pin, the peak current set point is adjusted accordingly to the output power demand. The internal drain MOSFET connection 6 This un−connected pin ensures adequate creepage distance Vcc Drain I OVP Vcc OVP − Vclamp UVLO Reset Vdd Vcc Management + S 80−us filter Q SCP Q tSCP Ipflag OFF UVLO R t recovery line detection LineOK TSD UVLO LineOK Jittering Vcc OFF DRV OSC Sawtooth S Q Foldback Sawtooth Q R I FBskip Ramp compensation − SKIP + DRV SKIP = ”1” −−> shut down some blocks to reduce consumption V FB(REF) GND Dynamic LEB + − R FB(up) I FB to CS setpoint + FB I freeze − FBfault + I − Ipk(0) Ipflag 3 Soft Start Reset SS as recovering from SCP, TSD, Vcc OVP, or UVLO Figure 3. Simplified Internal Circuit Architecture http://onsemi.com Reset NCP1072, NCP1075 MAXIMUM RATINGS TABLE Symbol Value Unit Power Supply Voltage on all pins, except Pin 5(Drain) −0.3 to 10 V BVdss Drain voltage −0.3 to 700 V IDS(PK) Drain Current Peak during Transformer Saturation 2 x IIpeak(0) A I_VCC Maximum Current into Pin 1 when Activating the 8.2 V Active Clamp 15 mA RqJ−A P Suffix, Case 626A 0.36 Sq. Inch 77 °C/W Junction−to−Air, 2.0 oz Printed Circuit Copper Clad 1.0 Sq. Inch 60 ST Suffix, Plastic Package Case 318E 0.36 Sq. Inch 74 Junction−to−Air, 2.0 oz Printed Circuit Copper Clad 1.0 Sq. Inch 55 VCC RqJ−A TJMAX Rating Maximum Junction Temperature Storage Temperature Range °C/W 150 °C −60 to +150 °C 2 kV 200 V ESD Capability, HBM model (All pins except HV) ESD Capability, Machine Model Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. This device series contains ESD protection and exceeds the following tests: Human Body Model 2000 V per JEDEC JESD22−A114−F Machine Model Method 200 V per JEDEC JESD22−A115−A 2. This device contains latch−up protection and exceeds 100 mA per JEDEC Standard JESD78 ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, VCC = 8 V unless otherwise noted) Rating Symbol Pin Min Typ Max Unit SUPPLY SECTION AND VCC MANAGEMENT VCC(on) VCC increasing level at which the switcher starts operation 1 7.8 8.2 8.6 V VCC(min) VCC decreasing level at which the HV current source restarts 1 6.5 6.8 7.2 V VCC(off) VCC decreasing level at which the switcher stops operation (UVLO) 1 6.1 6.3 6.6 V VCC(reset) VCC voltage at which the internal latch is reset (guaranteed by design) 1 VCC(clamp) Offset voltage above VCC(on) at which the internal clamp activates 1 190 300 mV Internal IC consumption, MOSFET switching at 65 kHz 1 0.7 1.0 mA Internal IC consumption, FB is 0 V (No switching on MOSFET) 1 360 ICC1 ICCskip 4 130 V mA POWER SWITCH CIRCUIT Power Switch Circuit on−state resistance NCP107x (Id = 50 mA) TJ = 25°C TJ = 125°C 5 BVDSS Power Switch Circuit & Startup breakdown voltage (ID(off) = 120 mA, TJ = 25°C) 5 IDSS(off) Power Switch & Startup breakdown voltage off−state leakage current TJ = 125°C (Vds = 700 V) 5 85 Switching characteristics (RL=50 W, VDS set for Idrain = 0.7 x Ilim) Turn−on time (90% − 10%) Turn−off time (10% − 90%) 5 5 20 10 RDS(on) ton toff W 11 19 16 24 700 V mA ns INTERNAL START−UP CURRENT SOURCE Istart1 5 High−voltage current source, VCC = VCC(on) – 200 mV 5 9 12 mA 3. The final switch current is: IIPK(0) / (Vin/LP + Sa) x Vin/LP + Vin/LP x tprop, with Sa the built−in slope compensation, Vin the input voltage, LP the primary inductor in a flyback, and tprop the propagation delay.. 4. NCP1072 130 kHz on demand only. 5. Oscillator frequency is measured with disabled jittering. http://onsemi.com 4 NCP1072, NCP1075 ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, VCC = 8 V unless otherwise noted) Symbol Rating Pin Min Typ Max Unit INTERNAL START−UP CURRENT SOURCE Istart2 VCCTH High−voltage current source, VCC = 0 V 5 VCC Transient level for Istart1 to Istart2 toggling point 1 0.5 − 2.2 mA − V CURRENT COMPARATOR IIPK Maximum internal current setpoint at 50% duty cycle FB pin open, NCP1072, TJ = 25°C − 250 mA IIPK Maximum internal current setpoint at 50% duty cycle FB pin open, NCP1075, TJ = 25°C − 450 mA IIPK(0) Maximum internal current setpoint at beginning of switching cycle FB pin open, NCP1072, TJ = 25°C − IIPKSW Final switch current with a primary slope of 200 mA/ms, FSW = 65 kHz, NCP1072 (Note 3) 296 mA IIPKSW Final switch current with a primary slope of 200 mA/ms, FSW = 100 kHz, NCP1072 (Note 3) 293 mA IIPKSW Final switch current with a primary slope of 200mA/ms, FSW = 130 kHz, NCP1072 (Notes 3 and 4) 291 mA IIPK(0) Maximum internal current setpoint at beginning of switching cycle FB pin open, NCP1075, TJ = 25°C IIPKSW Final switch current with a primary slope of 200 mA/ms, FSW = 65 kHz, NCP1075 (Note 3) 510 mA IIPKSW Final switch current with a primary slope of 200 mA/ms, FSW = 100 kHz, NCP1075 (Note 3) 500 mA IIPKSW Final switch current with a primary slope of 200 mA/ms, FSW = 130 kHz, NCP1075 (Note 3) 493 mA − 254 467 282 508 310 549 mA mA TSS Soft−start duration (guaranteed by design) − 1 ms Tprop Propagation delay from current detection to drain OFF state − 100 ns INTERNAL OSCILLATOR fOSC Oscillation frequency, 65 kHz version, TJ = 25°C (Note 5) − 59 65 71 kHz fOSC Oscillation frequency, 100 kHz version, TJ = 25°C (Note 5) − 90 100 110 kHz fOSC Oscillation frequency, 130 kHz version, TJ = 25°C (Notes 4 and 5) − 117 130 143 kHz fjitter Frequency jittering in percentage of fOSC − fswing Jittering swing frequency − Dmax Maximum duty−cycle − % ±6 300 62 68 Hz 72 % FEEDBACK SECTION IFBfault FB current for which Fault is detected 4 −35 mA IFB100% FB current for which internal current set−point is 100% (IIPK(0)) 4 −44 mA IFBfreeze FB current for which internal current setpoint is 97 mA (NCP1072) or 158 mA (NCP1075) 4 −80 mA VFB(REF) Equivalent pull−up voltage in linear regulation range (Guaranteed by design) 4 3.3 V Equivalent feedback resistor in linear regulation range (Guaranteed by design) 4 19.5 kW RFB(up) 3. The final switch current is: IIPK(0) / (Vin/LP + Sa) x Vin/LP + Vin/LP x tprop, with Sa the built−in slope compensation, Vin the input voltage, LP the primary inductor in a flyback, and tprop the propagation delay.. 4. NCP1072 130 kHz on demand only. 5. Oscillator frequency is measured with disabled jittering. http://onsemi.com 5 NCP1072, NCP1075 ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, VCC = 8 V unless otherwise noted) Symbol Rating Pin Min Typ Max Unit FREQUENCY FOLDBACK & SKIP IFBfold IFBfold(end) Fmin Start of frequency foldback feedback level 4 −68 mA End of frequency foldback feedback level, Fsw = Fmin 4 −100 mA The frequency below which skip−cycle occurs − IFBskip The feedback level to enter skip mode 4 Ifreeze Ifreeze 21 25 29 kHz −120 mA Internal minimum current setpoint (IFB = −90 mA) in NCP1072 88 mA Internal minimum current setpoint (IFB = −90 mA) in NCP1075 168 mA RAMP COMPENSATION Sa(65) The internal ramp compensation in NCP1072 (65 kHz version) − 4.2 kA/s Sa(65) The internal ramp compensation in NCP1075 (65 kHz version) − 7.5 kA/s Sa(100) The internal ramp compensation in NCP1072 (100 kHz version) − 6.5 kA/s Sa(100) The internal ramp compensation in NCP1075 (100 kHz version) − 11.5 kA/s Sa(130) The internal ramp compensation in NCP1072 (130 kHz version) (Note 4) − 8.4 kA/s Sa(130) The internal ramp compensation in NCP1075 (130 kHz version) − 15 kA/s 53 ms 420 ms PROTECTIONS Fault validation further to error flag assertion − OFF phase in fault mode − IOVP VCC clamp current at which the switcher stops pulsing 1 tOVP The filter of VCC OVP comparator − The drain pin voltage above which allows MOSFET operate, which is detected after TSD, UVLO, SCP, or VCC OVP mode. 5 72 Temperature shutdown (Guaranteed by design) − 150 Hysteresis in shutdown (Guaranteed by design) − tSCP trecovery VHV(EN) 40 6.0 8.5 11 80 91 mA ms 110 V TEMPERATURE MANAGEMENT TSD °C 50 °C 3. The final switch current is: IIPK(0) / (Vin/LP + Sa) x Vin/LP + Vin/LP x tprop, with Sa the built−in slope compensation, Vin the input voltage, LP the primary inductor in a flyback, and tprop the propagation delay.. 4. NCP1072 130 kHz on demand only. 5. Oscillator frequency is measured with disabled jittering. http://onsemi.com 6 NCP1072, NCP1075 8.4 7.0 8.3 6.9 8.2 VCC(min) (V) VCC(on) (V) TYPICAL CHARACTERISTICS 8.1 8.0 −25 0 25 50 75 100 125 6.5 −50 25 50 75 100 Figure 4. VCC(on) vs. Temperature Figure 5. VCC(min) vs. Temperature 240 6.5 220 6.4 6.3 125 200 180 160 −25 0 25 50 75 100 125 140 −50 −25 0 25 50 75 100 TEMPERATURE (°C) TEMPERATURE (°C) Figure 6. VCC(off) vs. Temperature Figure 7. VCC(clamp) vs. Temperature 0.80 125 25 20 RDS(on) (W) 0.75 0.70 0.65 0.60 −50 0 TEMPERATURE (°C) 6.6 6.1 −50 −25 TEMPERATURE (°C) 6.2 ICC1 (mA) 6.7 6.6 VCC(clamp) (V) VCC(off) (V) 7.9 −50 6.8 15 10 5 −25 0 25 50 75 100 125 0 −50 −25 0 25 50 75 100 TEMPERATURE (°C) TEMPERATURE (°C) Figure 8. ICC1 vs. Temperature Figure 9. RDS(on) vs. Temperature http://onsemi.com 7 125 NCP1072, NCP1075 TYPICAL CHARACTERISTICS 12 110 11 100 Istart1 (mA) IDSS(off) (mA) 10 90 80 70 9 8 7 6 60 50 −50 5 −25 0 25 50 75 100 4 −50 125 −25 0 25 50 75 100 125 TEMPERATURE (°C) Figure 10. IDSS(off) vs. Temperature Figure 11. Istart1 vs. Temperature 0.6 550 0.5 500 450 IIPK(0) (mA) Istart2 (mA) 0.4 0.3 0.2 350 NCP1072 250 −25 0 25 50 75 100 200 −50 125 −25 0 25 50 75 100 TEMPERATURE (°C) TEMPERATURE (°C) Figure 12. Istart2 vs. Temperature Figure 13. IIPK(0) vs. Temperature 125 72 110 100 kHz 100 70 90 Dmax (%) FOSC (kHz) 400 300 0.1 0 −50 NCP1075 80 70 68 66 65 kHz 64 60 50 −50 −25 0 25 50 75 100 62 −50 125 −25 0 25 50 75 100 TEMPERATURE (°C) TEMPERATURE (°C) Figure 14. FOSC vs. Temperature Figure 15. D(max) vs. Temperature http://onsemi.com 8 125 NCP1072, NCP1075 TYPICAL CHARACTERISTICS 65 29 28 60 26 tSCP (ms) Fmin (kHz) 27 25 24 23 50 45 22 21 −50 55 −25 0 25 50 75 100 40 −50 125 −25 0 25 50 75 100 TEMPERATURE (°C) TEMPERATURE (°C) Figure 16. Fmin vs. Temperature Figure 17. tSCP vs. Temperature 125 10 510 490 9.5 9.0 IOVP (mA) 450 430 410 8.5 8.0 390 7.5 370 350 −50 −25 0 25 50 75 100 7.0 −50 125 −25 0 25 50 75 100 TEMPERATURE (°C) TEMPERATURE (°C) Figure 18. trecovery vs. Temperature Figure 19. IOVP vs. Temperature 110 105 VHV(EN) (V) trecovery (ms) 470 100 95 90 85 80 −50 −25 0 25 50 75 100 TEMPERATURE (°C) Figure 20. VHV(EN) vs. Temperature http://onsemi.com 9 125 125 NCP1072, NCP1075 APPLICATION INFORMATION Introduction The NCP1072/NCP1075 offers a complete current−mode control solution. The component integrates everything needed to build a rugged and low−cost Switch−Mode Power Supply (SMPS) featuring low standby power. The Quick Selection Table on page 2 details the differences between references, mainly peak current setpoints and operating frequency. • Current−mode operation: the controller uses current−mode control architecture. • 700 V – 11 W Power MOSFET: Due to ON Semiconductor Very High Voltage Integrated Circuit technology, the circuit hosts a high−voltage power MOSFET featuring a 11 W RDS(on) – TJ = 25°C. This value lets the designer build a power supply up to 10 W operated on universal mains. An internal current source delivers the startup current, necessary to crank the power supply. • Dynamic Self−Supply: Due to the internal high voltage current source, this device could be used in the application without the auxiliary winding to provide supply voltage. • Short circuit protection: by permanently monitoring the feedback line activity, the IC is able to detect the presence of a short−circuit, immediately reducing the output power for a total system protection. A tSCP timer is started as soon as the feedback current is below threshold, IFB(fault), which indicates the maximum peak current. If at the end of this timer the fault is still present, then the device enters a safe, auto−recovery burst mode, affected by a fixed timer recurrence, trecovery. Once the short has disappeared, the controller resumes and goes back to normal operation. • Built−in VCC Over Voltage Protection: when the auxiliary winding is used to bias the VCC pin (no DSS), an internal active clamp connected between VCC and ground limits the supply dynamics to VCC(clamp). In case the current injected in this clamp exceeds a level of 6.0 mA (minimum), the controller immediately stops switching and waits a full timer period (trecovery) before • • • • • attempting to restart. If the fault is gone, the controller resumes operation. If the fault is still there, e.g. a broken opto−coupler, the controller protects the load through a safe burst mode. Line detection: An internal comparator monitors the drain voltage as recovering from one of the following situations: ♦ Short Circuit Protection, ♦ VCC OVP is confirmed, ♦ UVLO ♦ TSD If the drain voltage is lower than the internal threshold (VHV(EN)), the internal power switch is inhibited. This avoids operating at too low ac input. This is also called brown−in function in some fields. Frequency jittering: an internal low−frequency modulation signal varies the pace at which the oscillator frequency is modulated. This helps spreading out energy in conducted noise analysis. To improve the EMI signature at low power levels, the jittering remains active in frequency foldback mode. Soft−Start: a 1 ms soft−start ensures a smooth startup sequence, reducing output overshoots. Frequency foldback capability: a continuous flow of pulses is not compatible with no−load/light−load standby power requirements. To excel in this domain, the controller observes the feedback current information and when it reaches a level of IFBfold, the oscillator then starts to reduce its switching frequency as the feedback current continues to increase (the power demand continues to reduce). It can go down to 25 kHz (typical) reached for a feedback level of IFBfold(end) (100 mA roughly). At this point, if the power continues to drop, the controller enters classical skip−cycle mode. Skip: if SMPS naturally exhibits a good efficiency at nominal load, they begin to be less efficient when the output power demand diminishes. By skipping un−needed switching cycles, the NCP1072/NCP1075 drastically reduces the power wasted during light load conditions. http://onsemi.com 10 NCP1072, NCP1075 APPLICATION INFORMATION Startup Sequence level (typically 8.2 V), the current source turns off and pulses are delivered by the output stage: the circuit is awake and activates the power MOSFET if the bulk voltage is above VHV(EN) level (91 V typically). Figure 21 details the simplified internal circuitry. When the power supply is first powered from the mains outlet, the internal current source (typically 8.0 mA) is biased and charges up the VCC capacitor from the drain pin. Once the voltage on this VCC capacitor reaches the VCC(on) Vbulk I1 Rlimit Drain 1 I2 Istart1 ICC1 Iclamp - CVCC 5 + Vclamp = 8.4 V VCC(on) VCC(min) Iclamp > 6 mA ? --> OVP fault 8 Figure 21. The Internal Arrangement of the Start−up Circuitry Being loaded by the circuit consumption, the voltage on the VCC capacitor goes down. When VCC is below VCC(min) level (6.8 V typically), it activates the internal current source to bring VCC toward VCC(on) level and stops again: a cycle takes place whose low frequency depends on the VCC capacitor and the IC consumption. A 1.4 V ripple takes place on the VCC pin whose average value equals (VCC(on) + VCC(min))/2. Figure 22 portrays a typical operation of the DSS. http://onsemi.com 11 NCP1072, NCP1075 Figure 22. The Charge/Discharge Cycle Over a 1 mF VCC Capacitor protection (OVP) circuit and immediately stops the output pulses for trecovery duration (420 ms typically). Then a new start−up attempt takes place to check whether the fault has disappeared or not. The OVP paragraph gives more design details on this particular section. As one can see, even if there is auxiliary winding to provide energy for VCC, it happens that the device is still biased by DSS during start−up time or some fault mode when the voltage on auxiliary winding is not ready yet. The VCC capacitor shall be dimensioned to avoid VCC crosses VCC(off) level, which stops operation. The DV between VCC(min) and VCC(off) is 0.4 V. There is no current source to charge VCC capacitor when driver is on, i.e. drain voltage is close to zero. Hence the VCC capacitor can be calculated using C VCC w I CC1D max f OSC @ DV Fault Condition – Short−Circuit on VCC In some fault situations, a short−circuit can purposely occur between VCC and GND. In high line conditions (VHV = 370 VDC) the current delivered by the startup device will seriously increase the junction temperature. For instance, since Istart1 equals 5 mA (the min corresponds to the highest Tj), the device would dissipate 370 x 5 m = 1.85 W. To avoid this situation, the controller includes a novel circuitry made of two startup levels, Istart1 and Istart2. At power−up, as long as VCC is below a 2.4 V level, the source delivers Istart2 (around 500 mA typical), then, when VCC reaches 2.4 V, the source smoothly transitions to Istart1 and delivers its nominal value. As a result, in case of short−circuit between VCC and GND, the power dissipation will drop to 370 x 500u = 185 mW. Figure 22 portrays this particular behavior. The first startup period is calculated by the formula C x V = I x t, which implies a 1m x 2.4 / 500u = 4.8 ms startup time for the first sequence. The second sequence is obtained by toggling the source to 8 mA with a delta V of VCC(on) – VCCTH = 8.2 – 2.4 = 5.8 V, which finally leads to a second startup time of 1m x 5.8 / 8m = 0.725 ms. The total startup time becomes 4.8m + 0.725m = 5.525 ms. Please note that this calculation is approximated by the presence of the knee in the vicinity of the transition. (eq. 1) Take the 65 kHz device as an example. CVCC should be above 0.8m @ 72% 59 kHz @ 0.4 A margin that covers the temperature drift and the voltage drop due to switching inside FET should be considered, and thus a capacitor above 0.1 mF is appropriate. The VCC capacitor has only a supply role and its value does not impact other parameters such as fault duration or the frequency sweep period for instance. As one can see on Figure 21, an internal active zener diode, protects the switcher against lethal VCC runaways. This situation can occur if the feedback loop optocoupler fails, for instance, and you would like to protect the converter against an over voltage event. In that case, the internal current increase incurred by the VCC rapid growth triggers the over voltage http://onsemi.com 12 NCP1072, NCP1075 Fault Condition – Output Short−Circuit asserted, Ipflag, indicating that the system has reached its maximum current limit set point. The assertion of this flag triggers a fault counter tSCP (53 ms typically). If at counter completion, Ipflag remains asserted, all driving pulses are stopped and the part stays off in trecovery duration (about 420 ms). A new attempt to re−start occurs and will last 53 ms providing the fault is still present. If the fault still affects the output, a safe burst mode is entered, affected by a low duty−cycle operation (11%). When the fault disappears, the power supply quickly resumes operation. Figure 23 depicts this particular mode: As soon as VCC reaches VCC(on), drive pulses are internally enabled. If everything is correct, the auxiliary winding increases the voltage on the VCC pin as the output voltage rises. During the start−sequence, the controller smoothly ramps up the peak drain current to maximum setting, i.e. IIPK, which is reached after a typical period of 1 ms. When the output voltage is not regulated, the current coming through FB pin is below IFBfault level (35 mA typically), which is not only during the startup period but also anytime an overload occurs, an internal error flag is Figure 23. In Case of Short−Circuit or Overload, the NCP107X Protects Itself and the Power Supply Via a Low Frequency Burst Mode. The VCC is Maintained by the Current Source and Self−supplies the Controller. Auto−Recovery Over Voltage Protection triggering the OVP as we discussed, but also to avoid disturbing the VCC in low / light load conditions. The below lines detail how to evaluate the Rlimit value... Self−supplying controllers in extremely low standby applications often puzzles the designer. Actually, if a SMPS operated at nominal load can deliver an auxiliary voltage of an arbitrary 16 V (Vnom), this voltage can drop below 10 V (Vstby) when entering standby. This is because the recurrence of the switching pulses expands so much that the low frequency re−fueling rate of the VCC capacitor is not enough to keep a proper auxiliary voltage. Figure 25 portrays a typical scope shot of a SMPS entering deep standby (output un−loaded). Thus, care must be taken when calculating Rlimit 1) to not trigger the VCC over current latch (by injecting 6 mA into the active clamp – always use the minimum value for worse case design) in normal operation but 2) not to drop too much voltage over Rlimit when entering standby. Otherwise, the converter will enter dynamic self supply mode (DSS mode), which increases the power dissipation. Based on these recommendations, we are able to bound Rlimit between two equations: The particular NCP107X arrangement offers a simple way to prevent output voltage runaway when the optocoupler fails. As Figure 24 shows, an active zener diode monitors and protects the VCC pin. Below its equivalent breakdown voltage, that is to say 8.4 V typical, no current flows in it. If the auxiliary VCC pushes too much current inside the zener, then the controller considers an OVP situation and stops the internal drivers. When an OVP occurs, all switching pulses are permanently disabled. After trecovery delay, it resumes the internal drivers. If the failure symptom still exists, e.g. feedback opto−coupler fails, the device keeps the auto−recovery OVP mode. Figure 24 shows that the insertion of a resistor (Rlimit ) between the auxiliary dc level and the VCC pin is mandatory a) not to damage the internal 8.4 V zener diode during an overshoot for instance (absolute maximum current is 15 mA) b) to implement the fail−safe optocoupler protection (OVP) as offered by the active clamp. Please note that there cannot be bad interaction between the clamping voltage of the internal zener and VCC(on) since this clamping voltage is actually built on top of VCC(on) with a fixed amount of offset (200 mV typical). Rlimit should be carefully selected to avoid http://onsemi.com 13 NCP1072, NCP1075 V nom * V CC(clamp) I trip v R limit v V stby * V CC(min) I CCskip This number decreases compared to normal operation since the part in standby does almost not switch. It is around 0.36 mA for the 65 kHz version. VCC(min) is the level above which the auxiliary voltage must be maintained to keep the controller away from the dynamic self supply mode (DSS mode), which is not a problem in itself if low standby power does not matter. If a further improvement on standby efficiency is concerned, it is good to obtain VCC around 8 V at no load condition in order not to re−activate the internal clamp circuit. (eq. 2) Where: Vnom is the auxiliary voltage at nominal load Vstby is the auxiliary voltage when standby is entered Itrip is the current corresponding to the nominal operation. It thus must be selected to avoid false tripping in overshoot conditions. Always use the minimum of the specification for a robust design, i.e. Itrip < IOVP. ICCskip is the controller consumption during skip mode. Figure 24. A More Detailed View of the NCP107X Offers Better Insight on How to Properly Wire an Auxiliary Winding 1.08. The OVP latch will activate when the clamp current exceeds 6 mA. This will occur when Vauxiliary grows−up to: 1. 8.4 + 0.77k x (6m + 0.8m) ≈ 13.6 V for the first boundary (Rlimit = 0.77 kW) 2. 8.4 + 2.2k x (6m +0.8m) ≈ 23.4 V for the second boundary (Rlimit = 2.2 kW) Due to a 1.08 ratio between the auxiliary VCC and the power winding, the OVP will be seen as a lower overshoot on the real output: 1. 13.6 / 1.08 ≈ 12.6 V 2. 23.4 / 1.08 ≈ 21.7 V As one can see, tweaking the Rlimit value will allow the selection of a given overvoltage output level. Theoretically predicting the auxiliary drop from nominal to standby is an Since Rlimit shall not bother the controller in standby, e.g. keep VCC to above VCC(min) (7.2 V maximum), we purposely select a Vnom well above this value. As explained before, experience shows that a 40% decrease can be seen on auxiliary windings from nominal operation down to standby mode. Let’s select a nominal auxiliary winding of 13 V to offer sufficient margin regarding 7.2 V when in standby (Rlimit also drops voltage in standby...). Plugging the values in Equation 2 gives the limits within which Rlimit shall be selected: 13 * 8.4 8 * 7.2 v R limit v 6m 0.36m that is to say: 0.77 kW < Rlimit < 2.2 kW. If we design a 65 kHz power supply delivering 12V, then the ratio between auxiliary and power must be: 13 / 12 = http://onsemi.com 14 NCP1072, NCP1075 variations but also the output voltage excursion in fault. Once properly adjusted, the fail−safe protection will preclude any lethal voltage runaways in case a problem would occur in the feedback loop. almost impossible exercise since many parameters are involved, including the converter time constants. Fine tuning of Rlimit thus requires a few iterations and experiments on a breadboard to check the auxiliary voltage Figure 25. The Burst Frequency Becomes so Low That it is Difficult to Keep an Adequate Level on the Auxiliary VCC... Figure 26 describes the main signal variations when the part operates in auto−recovery OVP: Figure 26. If the VCC Current Exceeds a Certain Threshold, an Auto−Recovery Protection is Activated http://onsemi.com 15 NCP1072, NCP1075 Improving the precision in auto−recovery OVP Soft−Start Given the OVP variations the internal trip current dispersion incur, it is sometimes more interesting to explore a different solution, improving the situation to the cost of a minimal amount of surrounding elements. Figure 27 shows that adding a simple zener diode on top of the limiting resistor, offers a better precision since what matters now is the internal 8.4 V VCC breakdown plus the zener voltage. A resistor in series with the zener diodes keeps the maximum current in the VCC pin below the maximum rating of 15 mA just before trip the OVP. The NCP107X features a 1 ms soft−start which reduces the power−on stress but also contributes to lower the output overshoot. Figure 28 shows a typical operating waveform. The NCP107X features a novel patented structure which offers a better soft−start ramp, almost ignoring the start−up pedestal inherent to traditional current−mode supplies: Vcc D1 Rlimit Laux Ground Figure 27. A Simple Zener Diode Added in Parallel VCCON Drain current Figure 28. The 1 ms soft−start sequence Jittering sawtooth is internally generated and modulates the clock up and down with a fixed frequency of 300 Hz. Figure 29 shows the relationship between the jitter ramp and the frequency deviation. It is not possible to externally disable the jitter. Frequency jittering is a method used to soften the EMI signature by spreading the energy in the vicinity of the main switching component. The NCP107X offers a ±6% deviation of the nominal switching frequency. The sweep http://onsemi.com 16 NCP1072, NCP1075 Jitter ramp 68.9kHz 65kHz Internal sawtooth 61.1kHz adjustable Figure 29. Modulation Effects on the Clock Signal by the Jittering Sawtooth Line Detection implements a switching frequency folback when the feedback current passes above a certain level, IFBfold, set around 68 mA. At this point, the oscillator enters frequency foldback and reduces its switching frequency. The internal peak current set−point is following the feedback current information until its level reaches Ifreeze. Below this value, the peak current setpoint is frozen to 88 mA (NCP1072) or 168 mA (NCP1075). The only way to further reduce the transmitted power is to diminish the operating frequency down to Fmin (25 kHz typically). This value is reached at a feedback current level of IFBfold(end) (100 mA typically). Below this point, if the output power continues to decrease, the part enters skip cycle for the best noise−free performance in no−load conditions. Figures 30 and 31 depict the adopted scheme for the part. An internal comparator monitors the drain voltage as recovering from one of the following situations: • Short Circuit Protection, • VCC OVP is confirmed, • UVLO • TSD If the drain voltage is lower than the internal threshold VHV(EN) (91 Vdc typically), the internal power switch is inhibited. This avoids operating at too low ac input. This is also called brown−in function in some fields. Frequency Foldback The reduction of no−load standby power associated with the need for improving the efficiency, requires to change the traditional fixed−frequency type of operation. This device Figure 30. By Observing the Current on the Feedback Pin, the Controller Reduces its Switching Frequency for an Improved Performance at Light Load http://onsemi.com 17 NCP1072, NCP1075 Figure 31. Ipk Set−point is Frozen at Lower Power Demand. Feedback and Skip In this linear operating range, the dynamic resistance is 19.5 kW typically (RFB(up)) and the effective pull up voltage is 3.3 V typically (VFB(REF)). When IFB is below 40 mA, the FB voltage will jump to close to 4.5 V. Figure 32 depicts the relationship between feedback voltage and current. The feedback pin operates linearly as the absolute value of feedback current (IFB) is above 40 mA. Figure 32. Feedback Voltage vs. Current comparator is minimized to lower the ripple of the auxiliary voltage for VCC pin and VOUT of power supply during skip mode. It easies the design of VCC over load range. Figure 33 depicts the skip mode block diagram. When the FB current information reaches IFBskip, the internal clock to set the flip−flop is blanked and the internal consumption of the controller is decreased. The hysteresis of internal skip http://onsemi.com 18 NCP1072, NCP1075 Figure 33. Skip Cycle Schematic Ramp Compensation and Ipk Set−point Here we got a table of the ramp compensation, the initial current set point, and the final current set−point of different versions of switcher. In order to allow the NCP107X to operate in CCM with a duty cycle above 50%, a fixed slope compensation is internally applied to the current−mode control. NCP1072 NCP1075 Fsw 65 kHz 100 kHz 130 kHz 65 kHz 100 kHz 130 kHz Sa 4.2 kA/s 6.5 kA/s 8.4 kA/s 7.5 kA/s 11.5 kA/s 15 kA/s Ipk(Duty = 50%) 250 mA 450 mA Ipk(0) 282 mA 508 mA The Figure 34 depicts the variation of IPK set−point vs. the power switcher duty ratio, which is caused by the internal ramp compensation. Figure 34. IPK Set−point Varies with Power Switch On Time, Which is Caused by the Ramp Compensation http://onsemi.com 19 NCP1072, NCP1075 Design Procedure maximum voltage that can be reflected during toff . As a result, the Flyback voltage which is reflected on the drain at the switch opening cannot be larger than the input voltage. When selecting components, you thus must adopt a turn ratio which adheres to the following equation: The design of an SMPS around a monolithic device does not differ from that of a standard circuit using a controller and a MOSFET. However, one needs to be aware of certain characteristics specific of monolithic devices. Let us follow the steps: Vin min = 90 Vac or 127 Vdc once rectified, assuming a low bulk ripple Vin max = 265 Vac or 375 Vdc Vout = 12 V Pout = 10 W Operating mode is CCM h = 0.8 1. The lateral MOSFET body−diode shall never be forward biased, either during start−up (because of a large leakage inductance) or in normal operation as shown by Figure 35. This condition sets the NǒV out ) V f Ǔ t V in,min (eq. 3) 2. In our case, since we operate from a 127 V DC rail while delivering 12 V, we can select a reflected voltage of 120 Vdc maximum. Therefore, the turn ratio Np:Ns must be smaller than V reflect V out ) V f + 120 + 9.6 12 ) 0.5 or Np:Ns < 9.6. Here we choose N = 8 in this case. We will see later on how it affects the calculation. 350 250 150 50.0 > 0 !! −50.0 1.004M 1.011M 1.018M 1.025M 1.032M Figure 35. The Drain−Source Wave Shall Always be Positive sustain the avalanche. A traditional RCD clamping network shall thus be installed to protect the MOSFET. In some low power applications, a simple capacitor can also be used since V drain,max + V in ) NǒV out ) V f Ǔ ) I peak ILavg Ǹ Lf C tot (eq. 4) where Lf is the leakage inductance, Ctot the total capacitance at the drain node (which is increased by the capacitor you will wire between drain and source), N the NP:NS turn ratio, Vout the output voltage, Vf the secondary diode forward drop and finally, Ipeak the maximum peak current. Worse case occurs when the SMPS is very close to regulation, e.g. the Vout target is almost reached and Ipeak is still pushed to the maximum. For this design, we have selected our maximum voltage around 650 V (at Vin = 375 Vdc). This voltage is given by the RCD clamp Figure 36. Primary Inductance Current Evolution in CCM 3. Lateral MOSFETs have a poorly doped body−diode which naturally limits their ability to http://onsemi.com 20 NCP1072, NCP1075 installed from the drain to the bulk voltage. We will see how to calculate it later on. 4. Calculate the maximum operating duty−cycle for this flyback converter operated in CCM: d max + NǒV out ) V fǓ NǒV out ) V fǓ ) V in,min 1 + 1) V ǒ P cond + I d,rms 2R DS(on) + 570 mW 7. Off−time and on−time switching losses can be estimated based on the following calculations: + 0.44 in,min N V If we take the maximum Rds(on) for a 125°C junction temperature, i.e. 24 W, then conduction losses worse case are: Ǔ out)V f P off + 5. To obtain the primary inductance, we have the choice between two equations: L+ ǒV indǓ 2 (eq. 6) f swKP in DI L + (127 65k 0.44) 1 V in,min @ d max I Lavg P on + + + 3.8 mH 0.44 65k 98m DI L I peak + ) + I peak + ) 2 2 0.44 d + 0.34 * 0.112 + 223 mA 6. Based on the above numbers, we can now evaluate the conduction losses: + Ǹǒ d I peak 2 * I peakDI L ) Ǹ ǒ DI L 0.111 (127 ) 100) 6 20n (eq. 8) 15.4m As in any Flyback design, it is important to limit the drain excursion to a safe value, e.g. below the MOSFET BVdss which is 700 V. Figure 37a, b, c present possible implementations: On IL, ILavg can also be calculated: I d,rms + 6T sw MOSFET protection + 335 mA 2 I valleyǒV bulk ) NǒV out ) V fǓǓt on (eq. 9) DI L DI L 15.4m P DSS + I CC1 @ V in,max + 1m @ 375 + 375 mW The peak current can be evaluated to be: I Lavg + I peak * (eq. 7) + 5.5 mW + 223 mA peak−to−peak I avg 2 10n It is noted that the overlap of voltage and current seen on MOSFET during turning on and off duration is dependent on the snubber and parasitic capacitance seen from drain pin. Therefore the toff and ton in Equations 7 and 8 have to be modified after measuring on the bench. 8. The theoretical total power is then 0.570 + 0.036 + 0.0055 = 611 mW 9. If the NCP107X operates at DSS mode, then the losses caused by DSS mode should be counted as losses of this device on the following calculation: 2 + 127 3.8 LF SW (127 ) 120 @ 2) Where, assume the Vclamp is equal to two times of reflected voltage. DI L 12.75 0.335 + 36 mW and defines the amount of ripple we want in CCM (see Figure 36). ♦ Small K: deep CCM, implying a large primary inductance, a low bandwidth and a large leakage inductance. ♦ Large K: approaching BCM where the rms losses are worse, but smaller inductance, leading to a better leakage inductance. From Equation 6, a K factor of 1 (50% ripple), gives an inductance of: L+ 2T sw + where K+ I peakǒV bulk ) V clampǓt off (eq. 5) 2 3 0.44 0.335 2 * 0.335 @ 0.223 ) 0.223 3 2 + 154 mA http://onsemi.com 21 NCP1072, NCP1075 a b c Figure 37. Different Options to Clamp the Leakage Spike behind a standard zener diode and a TVS. However, the die area is far bigger for a transient suppressor than that of zener. A 5 W zener diode like the 1N5388B will accept 180 W peak power if it lasts less than 8.3 ms. If the peak current in the worse case (e.g. when the PWM circuit maximum current limit works) multiplied by the nominal zener voltage exceeds these 180 W, then the diode will be destroyed when the supply experiences overloads. A transient suppressor like the P6KE200 still dissipates 5 W of continuous power but is able to accept surges up to 600 W @ 1 ms. Select the zener or TVS clamping level between 40 to 80 V above the reflected output voltage when the supply is heavily loaded. Figure 37a: the simple capacitor limits the voltage according to The lateral MOSFET body−diode shall never be forward biased, either during start−up (because of a large leakage inductance) or in normal operation as shown by Figure 35. This condition sets the maximum voltage that can be reflected during toff . As a result, the Flyback voltage which is reflected on the drain at the switch opening cannot be larger than the input voltage. When selecting components, you thus must adopt a turn ratio which adheres to the following equation: Equation 3. This option is only valid for low power applications, e.g. below 5 W, otherwise chances exist to destroy the MOSFET. After evaluating the leakage inductance, you can compute C with Equation 4. Typical values are between 100 pF and up to 470 pF. Large capacitors increase capacitive losses... Figure 37b: the most standard circuitry is called the RCD network. You calculate Rclamp and Cclamp using the following formulae: R clamp + 2 V clampǒV clamp * ǒV out ) V fǓNǓ L leakI peak 2F sw C clamp + V clamp V rippleF swR clamp Power Dissipation and Heatsinking The NCP107X welcomes two dissipating terms, the DSS current−source (when active) and the MOSFET. Thus, Ptot = PDSS + PMOSFET. It is mandatory to properly manage the heat generated by losses. If no precaution is taken, risks exist to trigger the internal thermal shutdown (TSD). To help dissipating the heat, the PCB designer must foresee large copper areas around the package. Take the PDIP−7 package as an example, when surrounded by a surface greater than 1.0 cm2 of 35 mm copper, it becomes possible to drop its thermal resistance junction−to−ambient, RqJA down to 75°C/W and thus dissipate more power. The maximum power the device can thus evacuate is: (eq. 10) (eq. 11) Vclamp is usually selected 50−80 V above the reflected value N x (Vout + Vf). The diode needs to be a fast one and a MUR160 represents a good choice. One major drawback of the RCD network lies in its dependency upon the peak current. Worse case occurs when Ipeak and Vin are maximum and Vout is close to reach the steady−state value. Figure 37c: this option is probably the most expensive of all three but it offers the best protection degree. If you need a very precise clamping level, you must implement a zener diode or a TVS. There are little technology differences P max + T Jmax * T ambmax R qJA (eq. 12) which gives around 930 mW for an ambient of 50°C and a maximum junction of 120°C. If the surface is not large enough, assuming the RqJA is 100°C/W, then the maximum power the device can evacuate becomes 700 mW. Figure 38 gives a possible layout to help drop the thermal resistance. http://onsemi.com 22 NCP1072, NCP1075 Figure 38. A Possible PCB Arrangement to Reduce the Thermal Resistance Junction−to−Ambient A 10 W NCP1075 based Flyback Converter Featuring Low Standby Power is made via a NCP431 whose low bias current (50 mA) helps to lower the no load standby power. Measurements have been taken from a demonstration board implementing the diagram in Figure 40 and the following results were achieved with auxiliary winding to bias the device: Figure 40 depicts a typical application showing a NCP1075−65 kHz operating in a 10 W converter. To leave more room for the MOSFET, it is recommended to disable the DSS by shorting the J3. In this application, the feedback No load consumption with auxiliary winding 100 Vac 115 Vac 230 Vac 265 Vac 26 mW 28 mW 38 mW 45 mW Figure 39. Vout = 12 V http://onsemi.com 23 NCP1072, NCP1075 R_L3 15 T1 MA5597−AL C9 10 nF Figure 40. A 12 V – 0.85 A Universal Mains Power Supply ORDERING INFORMATION Device Frequency Package Type Shipping Rds(on) ohm Ipk (mA) NCP1072STAT3G 65 kHz SOT−223 4000 / Tape & Reel 11 250 NCP1072STBT3G 100 kHz SOT−223 4000 / Tape & Reel 11 250 NCP1072P65G 65 kHz PDIP−7 50 Units / Rail 11 250 NCP1072P100G 100 kHz PDIP−7 50 Units / Rail 11 250 NCP1075STAT3G 65 kHz SOT−223 4000 / Tape & Reel 11 450 NCP1075STBT3G 100 kHz SOT−223 4000 / Tape & Reel 11 450 NCP1075STCT3G 130 kHz SOT−223 4000 / Tape & Reel 11 450 NCP1075P65G 65 kHz PDIP−7 50 Units / Rail 11 450 NCP1075P100G 100 kHz PDIP−7 50 Units / Rail 11 450 NCP1075P130G 130 kHz PDIP−7 50 Units / Rail 11 450 †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 24 NCP1072, NCP1075 PACKAGE DIMENSIONS SOT−223 (TO−261) CASE 318E−04 ISSUE N D b1 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: INCH. 4 HE E 1 2 3 b e1 e 0.08 (0003) A1 C q A DIM A A1 b b1 c D E e e1 L L1 HE q L MIN 1.50 0.02 0.60 2.90 0.24 6.30 3.30 2.20 0.85 0.20 1.50 6.70 0° MILLIMETERS NOM MAX 1.63 1.75 0.06 0.10 0.75 0.89 3.06 3.20 0.29 0.35 6.50 6.70 3.50 3.70 2.30 2.40 0.94 1.05 −−− −−− 1.75 2.00 7.00 7.30 10° − L1 SOLDERING FOOTPRINT* 3.8 0.15 2.0 0.079 2.3 0.091 2.3 0.091 6.3 0.248 2.0 0.079 1.5 0.059 SCALE 6:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 25 MIN 0.060 0.001 0.024 0.115 0.009 0.249 0.130 0.087 0.033 0.008 0.060 0.264 0° INCHES NOM 0.064 0.002 0.030 0.121 0.012 0.256 0.138 0.091 0.037 −−− 0.069 0.276 − MAX 0.068 0.004 0.035 0.126 0.014 0.263 0.145 0.094 0.041 −−− 0.078 0.287 10° NCP1072, NCP1075 PACKAGE DIMENSIONS 8 LEAD PDIP CASE 626A ISSUE A 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. PACKAGE CONTOUR OPTIONAL (ROUND OR SQUARE CORNERS). 4. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 5. DIMENSIONS A AND B ARE DATUMS. 5 B 1 L M 4 J F A NOTE 3 C −T− N SEATING PLANE D H DIM A B C D F G H J K L M N MILLIMETERS MIN MAX 9.40 10.16 6.10 6.60 3.94 4.45 0.38 0.51 1.02 1.78 2.54 BSC 0.76 1.27 0.20 0.30 2.92 3.43 7.62 BSC --10_ 0.76 1.01 INCHES MIN MAX 0.370 0.400 0.240 0.260 0.155 0.175 0.015 0.020 0.040 0.070 0.100 BSC 0.030 0.050 0.008 0.012 0.115 0.135 0.300 BSC --10_ 0.030 0.040 K G 0.13 (0.005) M T A M B M ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: [email protected] N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5817−1050 http://onsemi.com 26 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative NCP1072/D