NCP1216 PWM Current−Mode Controller for High−Power Universal Off−line Supplies Housed in a SO−8 or DIP7 package, the NCP1216 represents an enhanced version of NCP1200−based controllers. Due to its high drive capability, NCP1216 drives large gate−charge MOSFETs, which together with internal ramp compensation and built−in frequency jittering, ease the design of modern AC/DC adapters. With an internal structure operating at different fixed frequencies, the controller supplies itself from the high−voltage rail, avoiding the need of an auxiliary winding. This feature naturally eases the designer task in some particular applications, e.g. battery chargers or TV sets. Current−mode control also provides an excellent input audio−susceptibility and inherent pulse−by−pulse control. Internal ramp compensation easily prevents sub−harmonic oscillations from taking place in continuous conduction mode designs. When the current setpoint falls below a given value, e.g. the output power demand diminishes, the IC automatically enters the so−called skip cycle mode and provides excellent efficiency at light loads. Because this occurs at a user adjustable low peak current, no acoustic noise takes place. The NCP1216 features an efficient protective circuitry, which in presence of an over current condition disables the output pulses while the device enters a safe burst mode, trying to re−start. Once the default has gone, the device auto−recovers. http://onsemi.com MINIATURE PWM CONTROLLER FOR HIGH POWER AC/DC WALL ADAPTERS AND OFFLINE BATTERY CHARGERS MARKING DIAGRAMS 8 SO−8 D SUFFIX CASE 751 1 1 No Auxiliary Winding Operation Current−Mode Control with Adjustable Skip−Cycle Capability Internal Ramp Compensation Built−In Frequency Jittering for Better EMI Signature Auto−Recovery Internal Output Short−Circuit Protection Extremely Low No−Load Stand−By Power 500 mA Peak Current Capability Fixed Frequency Versions at 65 kHz, 100 kHz, 133 kHz Internal Temperature Shutdown Direct Optocoupler Connection SPICE Models Available for TRANsient and AC Analysis Pin−to−Pin Compatible with NCP1200 Series Typical Applications • • • • High Power AC/DC Converters for TVs, Set−Top Boxes, etc. Offline Adapters for Notebooks Telecom DC−DC Converters All Power Supplies Semiconductor Components Industries, LLC, 2004 February, 2004 − Rev. 5 P1216Pxxx AWL YYWW PDIP−7 P SUFFIX CASE 626B Features • • • • • • • • • • • • 16Dyy ALYW 1 xxx yy = Specific Device Code: 065, 100 or 133 = Specific Device Code (06 for 65, 10 for 100, 13 for 133) A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week PIN CONNECTIONS Adj 1 8 HV FB 2 7 NC CS 3 6 VCC Gnd 4 5 Drv ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 15 of this data sheet. Publication Order Number: NCP1216/D NCP1216 + *See Application Section NCP1216 = 35kHz 1 Fosc Adj HV 8 2 FB 7 + EMI Filter 3 CS Vcc 6 4 GNDDrv 5 Rcomp Universal Input + Rsense ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Figure 1. Typical Application Example PIN FUNCTION DESCRIPTION Pin No. Pin Name Function Pin Description 1 Adj Adjust the Skipping Peak Current This pin lets you adjust the level at which the cycle skipping process takes place. Shorting this pin to ground, permanently disables the skip cycle feature. 2 FB Sets the Peak Current Setpoint By connecting an Optocoupler to this pin, the peak current setpoint is adjusted accordingly to the output power demand. 3 CS Current Sense Input 4 GND IC Ground 5 Drv Driving Pulses The driver’s output to an external MOSFET. 6 VCC Supplies the IC This pin is connected to an external bulk capacitor of typically 22 F. 7 NC − This un−connected pin ensures adequate creepage distance. 8 HV Generates the VCC from the Line Connected to the high−voltage rail, this pin injects a constant current into the VCC bulk capacitor. This pin senses the primary current and routes it to the internal comparator via an L.E.B. By inserting a resistor in series with the pin, you control the amount of ramp compensation you need. − http://onsemi.com 2 NCP1216 Adj 1 HV Current Source 96 k FB Skip Cycle Comparator Internal VCC + − Clock Jittering 1.1 V 2 UVLO High and Low Internal Regulator 8 HV 7 NC 25 k 220 ns L.E.B 19 k Current 3 Sense GND 20 k 4 Set Q Flip−Flop Q DCmax = 75% 65 kHz 100 kHz 133kHz Ramp Compensation Reset + − Pull−up Resistor 57 k + Vref 25 k − 5V 6 VCC 500 mA 5 Drv 1V Overload? Fault Duration . . Figure 2. Internal Circuit Architecture MAXIMUM RATINGS Rating Symbol Value Unit VCC 16 V −0.3 to 10 V Maximum Voltage on Pin 8 (HV), Pin 6 (VCC) Decoupled to Ground with 10 F 500 V Maximum Voltage on Pin 8 (HV), Pin 6 (VCC) Grounded 450 V Minimum Operating Voltage on Pin 8 (HV) 30 V Maximum Current into all Pins except VCC (Pin 6) and HV (Pin 8) when 10 V ESD Diodes are Activated 5.0 mA Power Supply Voltage, VCC Pin Maximum Voltage on Low Power Pins (except Pin 8 and Pin 6) Thermal Resistance Junction−to−Air, PDIP7 Version Thermal Resistance Junction−to−Air, SO−8 Version RJ−A RJ−A 100 178 °C/W Maximum Junction Temperature TJMAX 150 °C TSD 155 °C 30 °C Temperature Shutdown Hysteresis in Shutdown −60 to +150 °C ESD Capability, HBM Model (All Pins except VCC and HV) 2.0 kV ESD Capability, Machine Model 200 V Storage Temperature Range http://onsemi.com 3 NCP1216 ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = 0°C to +125°C, Maximum TJ = 150°C, VCC = 11 V unless otherwise noted.) Characteristic Pin Symbol Min Typ Max Unit VCC Increasing Level at which the Current Source Turns Off 6 VCCOFF 11.2 12.2 13.4 (Note 1) V VCC Decreasing Level at which the Current Source Turns On 6 VCCON 9.2 10.0 11.0 (Note 1) V VCC Decreasing Level at which the Latch−off Phase Ends 6 VCClatch 5.6 Internal IC Consumption, No Output Load on Pin 5, FSW = 65 kHz 6 ICC1 990 1110 (Note 2) A Internal IC Consumption, No Output Load on Pin 5, FSW = 100 kHz 6 ICC1 1025 1180 (Note 2) A Internal IC Consumption, No Output Load on Pin 5, FSW = 133 kHz 6 ICC1 1060 1200 (Note 2) A Internal IC Consumption, 1.0 nF Output Load on Pin 5, FSW = 65 kHz 6 ICC2 1.7 2.0 (Note 2) mA Internal IC Consumption, 1.0 nF Output Load on Pin 5, FSW = 100 kHz 6 ICC2 2.1 2.4 (Note 2) mA Internal IC Consumption, 1.0 nF Output Load on Pin 5, FSW = 133 kHz 6 ICC2 2.4 2.9 (Note 2) mA Internal IC Consumption, Latch−off Phase, VCC = 6.0 V 6 ICC3 350 High−voltage Current Source, VCC = 10 V 8 IC1 High−voltage Current Source, VCC = 0 V 8 IC2 9.0 mA Output Voltage Rise−time @ CL = 1.0 nF, 10−90% of a 12 V Output Signal 5 Tr 60 ns Output voltage fall−time @ CL = 1.0 nF, 10−90% of a 12 V Output Signal 5 Tf 20 ns Source Resistance 5 ROH 15 20 35 Sink Resistance 5 ROL 5.0 10 18 Input Bias Current @ 1.0 V Input Level on Pin 3 3 IIB Maximum Internal Current Setpoint 3 ILimit Default Internal Current Setpoint for Skip Cycle Operation 3 ILskip 330 Propagation Delay from Current Detection to Gate OFF State 3 TDEL 80 Leading Edge Blanking Duration 3 TLEB 220 DYNAMIC SELF−SUPPLY V A INTERNAL START−UP CURRENT SOURCE (TJ > 0°C) 4.9 (Note 3) 8.0 11 mA DRIVE OUTPUT CURRENT COMPARATOR (Pin 5 Unloaded) 1. VCCOFF and VCCON min−max always ensure an hysteresis of 2.0 V. 2. Maximum value at TJ = 0°C. 3. Minimum value for TJ = 125°C. http://onsemi.com 4 A 0.02 0.93 1.08 1.14 V mV 130 ns ns NCP1216 ELECTRICAL CHARACTERISTICS (continued) (For typical values TJ = 25°C, for min/max values TJ = 0°C to +125°C, Maximum TJ = 150°C, VCC = 11 V unless otherwise noted.) Characteristic Pin Symbol Min Typ Max Unit Oscillation Frequency, 65 kHz Version fOSC 58.5 65 71.5 kHz Oscillation Frequency, 100 kHz Version fOSC 90 100 110 kHz Oscillation Frequency, 133 kHz Version fOSC 120 133 146 kHz Built−in Frequency Jittering in Percentage of fOSC fjitter Maximum Duty−cycle NCP1216 Dmax INTERNAL OSCILLATOR (VCC = 11 V, Pin 5 Loaded by 1.0 k) ±4.0 69 75 % 81 % FEEDBACK SECTION (VCC = 11 V, Pin 5 Loaded by 1.0 k) Internal Pull−up Resistor 2 Rup 20 Pin 2 (FB) to Internal Current Setpoint Division Ratio − Iratio 3.3 Default Skip Mode Level 1 Vskip Pin 1 Internal Output Impedance 1 Zout Internal Ramp Level @ 25°C (Note 4) 3 Vramp Internal Ramp Resistance to CS Pin 3 Rramp k SKIP CYCLE GENERATION 0.9 1.1 1.26 25 V k INTERNAL RAMP COMPENSATION 4. A 1.0 M resistor is connected to the ground for the measurement. http://onsemi.com 5 2.6 2.9 19 3.2 V k NCP1216 14.0 40 13.5 VCCOFF (V) HV PIN LEAKAGE CURRENT @ 500 V (A) TYPICAL CHARACTERISTICS 50 30 20 10 13.0 12.5 12.0 11.5 0 −25 0 25 50 75 100 125 11.0 −25 0 25 50 75 100 TEMPERATURE (°C) TEMPERATURE (°C) Figure 3. High Voltage Pin Leakage Current vs. Temperature Figure 4. VCCOFF vs. Temperature 12.0 125 1400 1300 11.5 1200 1100 ICC1 (A) VCCON (V) 11.0 10.5 10.0 133 kHz 1000 900 65 kHz 800 100 kHz 700 9.5 600 500 9.0 −25 0 25 50 75 100 125 −25 0 25 50 75 100 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 5. VCCON vs. Temperature Figure 6. ICC1 (@ VCC = 11 V) vs. Temperature 150 2.80 2.60 2.20 100 kHz FOSC (kHz) ICC2 (mA) 130 133 kHz 2.40 2.00 1.80 65 kHz 1.60 1.40 133 kHz 110 100 kHz 90 70 65 kHz 1.20 1.00 −25 0 25 50 75 TEMPERATURE (°C) 100 125 50 −25 Figure 7. ICC2 vs. Temperature 0 25 50 75 TEMPERATURE (°C) 100 Figure 8. Switching Frequency vs. Temperature http://onsemi.com 6 125 NCP1216 5.90 400 5.80 ICC3 (A) VCClatch (V) 350 5.70 5.60 300 5.50 250 5.40 5.30 −25 0 25 50 75 100 200 −25 125 0 Figure 9. VCClatch vs. Temperature 75 100 125 Figure 10. ICC3 vs. Temperature 1.13 CURRENT SENSE LIMIT (V) 30 DRIVER RESISTANCE () 50 TEMPERATURE (°C) TEMPERATURE (°C) 25 Source 20 15 10 Sink 5 0 −25 25 1.08 1.03 0.98 0.93 0 25 50 75 100 −25 125 0 25 50 75 100 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 11. Drive Sink and Source Resistance vs. Temperature Figure 12. Current Sense Limit vs. Temperature 1.20 75.0 74.5 DUTY CYCLE (%) Vskip (V) 1.15 1.10 74.0 73.5 73.0 1.05 72.5 1.00 −25 72.0 0 25 50 75 100 125 −25 0 25 50 75 100 TEMPERATURE (°C) TEMPERATURE (°C) Figure 13. Vskip vs. Temperature Figure 14. Max Duty−Cycle vs. Temperature http://onsemi.com 7 125 NCP1216 3.10 14 3.05 12 10 2.95 IC1 (mA) Vramp (V) 3.00 2.90 2.85 8 6 2.80 4 2.75 2.70 −25 0 25 50 75 100 125 2 −25 0 25 50 75 100 TEMPERATURE (°C) TEMPERATURE (°C) Figure 15. Vramp vs. Temperature Figure 16. High Voltage Current Source (@ VCC = 10 V) vs. Temperature http://onsemi.com 8 125 NCP1216 APPLICATION INFORMATION Introduction Over Current Protection (OCP): By continuously monitoring the FB line activity, NCP1216 enters burst mode as soon as the power supply undergoes an overload. The device enters a safe low power operation, which prevents from any lethal thermal runaway. As soon as the default disappears, the power supply resumes operation. Unlike other controllers, overload detection is performed independently of any auxiliary winding level. In presence of a bad coupling between both power and auxiliary windings, the short circuit detection can be severely affected. The DSS naturally shields you against these troubles. Wide Duty−Cycle Operation: Wide mains operation requires The NCP1216 implements a standard current mode architecture where the switch−off event is dictated by the peak current setpoint. This component represents the ideal candidate where low part−count is the key parameter, particularly in low−cost AC/DC adapters, TV power supplies etc. Due to its high−performance High−Voltage technology, the NCP1216 incorporates all the necessary components normally needed in UC384X based supplies: timing components, feedback devices, low−pass filter and self−supply. This later point emphasizes the fact that ON Semiconductor’s NCP1216 does NOT need an auxiliary winding to operate: the product is naturally supplied from the high−voltage rail and delivers a VCC to the IC. This system is called the Dynamic Self−Supply (DSS): Dynamic Self−Supply (DSS): Due to its Very High Voltage Integrated Circuit (VHVIC) technology, ON Semiconductor’s NCP1216 allows for a direct pin connection to the high−voltage DC rail. A dynamic current source charges up a capacitor and thus provides a fully independent VCC level to the NCP1216. As a result, there is no need for an auxiliary winding whose management is always a problem in variable output voltage designs (e.g. battery chargers). Adjustable Skip Cycle Level: By offering the ability to tailor the level at which the skip cycle takes place, the designer can make sure that the skip operation only occurs at low peak current. This point guarantees a noise−free operation with cheap transformers. Skip cycle offers a proven mean to reduce the standby power in no or light loads situations. Internal Frequency Dithering for Improved EMI Signature: By modulating the internal switching frequency with the DSS VCC ripple, natural energy spread appears and softens the controller’s EMI signature. Wide Switching − Frequency Offered with Different Options (65 kHz − 100 kHz − 133 kHz): Depending on the application, the designer can pick up the right device to help reducing magnetics or improve the EMI signature before reaching the 150 kHz starting point. Ramp Compensation: By inserting a resistor between the current−sense (CS) pin and the actual sense resistor, it becomes possible to inject a given amount of ramp compensation since the internal sawtooth clock is routed to the CS pin. Sub−harmonic oscillations in Continuous Conduction Mode (CCM) can thus be compensated via a single resistor. a large duty−cycle excursion. The NCP1216 can go up to 75% typically. For Continuous Conduction Mode (CCM) applications, the internal ramp compensation lets you fight against sub−harmonic oscillations. Low Stand−By−Power: If SMPS naturally exhibit a good efficiency at nominal load, they begin to be less efficient when the output power demand diminishes. By skipping unnecessary switching cycles, the NCP1216 drastically reduces the power wasted during light load conditions. In no−load conditions, the NPC1216 allows the total standby power to easily reach next International Energy Agency (IEA) recommendations. No Acoustic Noise While Operating: Instead of skipping cycles at high peak currents, the NCP1216 waits until the peak current demand falls below a user−adjustable 1/3rd of the maximum limit. As a result, cycle skipping can take place without having a singing transformer, one can thus select cheap magnetic components free of noise problems. External MOSFET Connection: By leaving the external MOSFET external to the IC, you can select avalanche proof devices, which in certain cases (e.g. low output powers), let you work without an active clamping network. Also, by controlling the MOSFET gate signal flow; you have an option to slow down the device commutation, therefore reducing the amount of ElectroMagnetic Interference (EMI). SPICE Model: A dedicated model to run transient cycle−by−cycle simulations is available but also an averaged version to help you closing the loop. Ready−to−use templates can be downloaded in OrCAD’s PSpice and INTUSOFT’s IsSpice from ON Semiconductor web site, in the NCP1216 related section. http://onsemi.com 9 NCP1216 Dynamic Self−Supply Application note AND8069/D details tricks to widen the NCP1216 driving implementation, in particular for large Qg MOSFETs. This document can be downloaded at www.onsemi.com/pub/Collateral/AND8069−D.PDF. The DSS principle is based on the charge/discharge of the VCC bulk capacitor from a low level up to a higher level. We can easily describe the current source operation with a bunch of simple logical equations: POWER−ON: If VCC < VCCOFF then the Current Source is ON, no output pulses If VCC decreasing > VCCON then the Current Source is OFF, output is pulsing If VCC increasing < VCCOFF then the Current Source is ON, output is pulsing Typical values are: VCCOFF = 12.2 V, VCCON = 10 V To better understand the operational principle, Figure 17 offers the necessary light: Vripple = 2.2 V Ramp Compensation Ramp compensation is a known mean to cure sub−harmonic oscillations. These oscillations take place at half the switching frequency and occur only during Continuous Conduction Mode (CCM) with a duty−cycle greater than 50%. To lower the current loop gain, one usually injects between 50% and 100% of the inductor down−slope. Figure 18 depicts how internally the ramp is generated: DCmax = 75°C 2.9V VCCOFF = 12.2 V 0V VCCON = 10 V Rcomp 19 k − + OFF, I = 0 mA ON, I = 8 mA 30 50 70 In the NCP1216, the ramp features a swing of 2.9 V with a Duty cycle max at 75%. Over a 65 kHz frequency, it corresponds to a The DSS behavior actually depends on the internal IC consumption and the MOSFET’s gate charge Qg. If we select a 600 V 10 A MOSFET featuring a 30 nC Qg, then we can compute the resulting average consumption supported by the DSS which is: 2.9 65 kHz 251 mVs ramp. 0.75 Vout Vf Np 371 mAs or37 mVs Ns Lp (eq. 2) (eq. 3) Supplied from a 350 VDC rail (250 VAC), the heat dissipated by the circuit would then be: 350 V 2.9 mA 1 W (eq. 6) when projected over an Rsense of 0.1 , for instance. If we select 75% of the down−slope as the required amount of ramp compensation, then we shall inject 27 mV/s. Our internal compensation being of 251 mV/s, the divider ratio (divratio) between Rcomp and the 19 k is 0.107. A few lines of algebra to determine Rcomp: Suppose that we select the NCP1216P065 with the above MOSFET, the total current is (30 n 65 k) 900 2.9 mA. (eq. 5) In our FLYBACK design, let’s suppose that our primary inductance Lp is 350 H, delivering 12 V with a Np : Ns ratio of 1:0.1. The OFF time primary current slope is thus given by: (eq. 1) The total IC heat dissipation incurred by the DSS only is given by: Itotal Vpin8. Rsense Figure 18. Inserting a Resistor in Series with the Current Sense Information brings Ramp Compensation 90 Figure 17. The Charge/Discharge Cycle Over a 10 F VCC Capacitor Itotal Fsw Qg ICC1. CS From Set−point Output Pulse 10 L.E.B (eq. 4) 19 k divratio 2.37 k 1 divratio As you can see, it exists a tradeoff where the dissipation capability of the NCP1216 fixes the maximum Qg that the circuit can drive, keeping its dissipation below a given target. Please see the “Power Dissipation” section for a complete design example and discover how a resistor can help to heal the NCP1216 heat equation. (eq. 7) Frequency Jittering Frequency jittering is a method used to soften the EMI signature by spreading the energy in the vicinity of the main switching component. NCP1216 offers a 4% deviation of http://onsemi.com 10 NCP1216 4 0.1 400 mW. the nominal switching frequency whose sweep is synchronized with the VCC ripple. For instance, with a 2.2 V peak−to−peak ripple, the NCP1216P065 frequency will equal 65 kHz in the middle of the ripple and will increase as VCC rises or decrease as VCC ramps down. Figure 19 portrays the behavior we have adopted: (eq. 9) To better understand how this skip cycle mode takes place, a look at the operation mode versus the FB level immediately gives the necessary insight: FB VCCOFF VCC Ripple 68 kHz 4.2 V, FB Pin Open 65 kHz Normal Current Mode Operation 3.2 V, Upper Dynamic Range 1V Skip Cycle Operation IpMIN = 333 mV / Rsense 62 kHz VCCON Figure 20. Figure 19. VCC Ripple is Used to Introduce a Frequency Jittering on the Internal Oscillator Sawtooth When FB is above the skip cycle threshold (1.0 V by default), the peak current cannot exceed 1.0 V/Rsense. When the IC enters the skip cycle mode, the peak current cannot go below Vpin1 / 3.3. The user still has the flexibility to alter this 1.0 V by either shunting pin 1 to ground through a resistor or raising it through a resistor up to the desired level. Grounding pin 1 permanently invalidates the skip cycle operation. Skipping Cycle Mode The NCP1216 automatically skips switching cycles when the output power demand drops below a given level. This is accomplished by monitoring the FB pin. In normal operation, pin 2 imposes a peak current accordingly to the load value. If the load demand decreases, the internal loop asks for less peak current. When this setpoint reaches a determined level, the IC prevents the current from decreasing further down and starts to blank the output pulses: the IC enters the so−called skip cycle mode, also named controlled burst operation. The power transfer now depends upon the width of the pulse bunches (Figure 21). Suppose we have the following component values: Lp, primary inductance = 350 H Fsw, switching frequency = 65 kHz Ip skip = 600 mA (or 333 mV / Rsense) The theoretical power transfer is therefore: 1L I 2F p p sw 4 W. 2 Power P1 Power P2 Power P3 (eq. 8) Figure 21. Output Pulses at Various Power Levels (X = 5 s/div) P1 < P2 < P3 If this IC enters skip cycle mode with a bunch length of 10 ms over a recurrent period of 100 ms, then the total power transfer is: http://onsemi.com 11 NCP1216 due to the DSS operation. In our example, at Tambient = 50°C, ICC2 is measured to be 2.9 mA with a 10 A / 600 V MOSFET. As a result, the NCP1216 will dissipate from a 250 VAC network, Max Peak Current 300 Skip Cycle Current Limit 200 350 V 2.9 mA@TA 50°C 1 W The PDIP7 package offers a junction−to−ambient thermal resistance RJ−A of 100°C/W. Adding some copper area around the PCB footprint will help decreasing this number: 12 mm x 12 mm to drop RJ−A down to 75°C/W with 35 copper thickness (1 oz.) or 6.5 mm x 6.5 mm with 70 copper thickness (2 oz.). For a SO−8, the original 178°C/W will drop to 100°C/W with the same amount of copper. With this later PDIP7 number, we can compute the maximum power dissipation that the package accepts at an ambient of 50°C: 100 0 315.4U 882.7U 1.450M 2.017M 2.585M Figure 22. The Skip Cycle Takes Place at Low Peak Currents which Guarantees Noise Free Operation T TAmax P max Jmax 1W RJ A In some cases, it might be desirable to shut off the part temporarily and authorize its re−start once the default has disappeared. This option can easily be accomplished through a single NPN bipolar transistor wired between FB and ground. By pulling FB below the Adj pin 1 level, the output pulses are disabled as long as FB is pulled below pin 1. As soon as FB is relaxed, the IC resumes its operation. Figure 23 depicts the application example: ON/OFF Q1 8 2 7 3 6 4 5 (eq. 12) which barely matches our previous budget. Several solutions exist to help improving the situation: 1− Insert a Resistor in Series with Pin 8: This resistor will take a part of the heat normally dissipated by the NCP1216. Calculations of this resistor imply that Vpin8 does not drop below 50 V in the lowest mains conditions. Therefore, Rdrop can be selected with: Non−Latching Shutdown 1 (eq. 11) V 50 V Rdrop bulkmin 8 mA (eq. 13) In our case, Vbulk minimum is 120 VDC, which leads to a dropping resistor of 8.7 k. With the above example in mind, the DSS will exhibit a duty−cycle of: 2.9 mA8 mA 36% (eq. 14) By inserting the 8.7 k resistor, we drop 8.7 k * 8 mA 69.6 V (eq. 15) during the DSS activation. The power dissipated by the NCP1216 is therefore: Pinstant * DSSduty cycle (350 69) * 8 m * 0.36 800 mW Figure 23. Another Way of Shutting Down the IC without a Definitive Latch−off State We can pass the limit and the resistor will dissipate A full latching shutdown, including over−temperature protection, is described in application note AND8069/D. 1 W 800 mW 200 mW (eq. 17) or Power Dissipation 2 pdrop 69 * 0.36 8.7 k The NCP1216 is directly supplied from the DC rail through the internal DSS circuitry. The current flowing through the DSS is therefore the direct image of the NCP1216 current consumption. The total power dissipation can be evaluated using: (VHVDC 11 V) ICC2 (eq. 16) (eq. 18) 2− Select a MOSFET with a Lower Qg : Certain MOSFETs exhibit different total gate charges depending on the technology they use. Careful selection of this component can help to significantly decrease the dissipated heat. 3− Implement Figure 3, from AN8069/D, Solution: This is another possible option to keep the DSS functionality (good short−circuit protection and EMI jittering) while driving any types of MOSFETs. This solution is recommended when the designer plans to use SO−8 controllers. (eq. 10) which is, as we saw, directly related to the MOSFET Qg. If we operate the device on a 90−250 VAC rail, the maximum rectified voltage can go up to 350 VDC. However, as the characterization curves show, the current consumption drops at a higher junction temperature, which quickly occurs http://onsemi.com 12 NCP1216 During the start−up phase, the peak current is pushed to the maximum until the output voltage reaches its target and the feedback loop takes over. This period of time depends on normal output load conditions and the maximum peak current allowed by the system. The time−out used by this IC works with the VCC decoupling capacitor: as soon as the VCC decreases from the VCCOFF level (typically 12.2 V) the device internally watches for an overload current situation. If this condition is still present when the VCCON level is reached, the controller stops the driving pulses, prevents the self−supply current source to restart and puts all the circuitry in standby, consuming as little as 350 A typical (ICC3 parameter). As a result, the VCC level slowly discharges toward 0 V. When this level crosses 5.6 V typical, the controller enters a new start−up phase by turning the current source on: VCC rises toward 12.2 V and again delivers output pulses at the VCCOFF crossing point. If the fault condition has been removed before VCCON approaches, then the IC continues its normal operation. Otherwise, a new fault cycle takes place. Figure 24 shows the evolution of the signals in presence of a fault. 4− Connect an Auxiliary Winding: If the mains conditions are such that you simply can’t match the maximum power dissipation, then you need to connect an auxiliary winding to permanently disconnect the start−up source. Overload Operation In applications where the output current is purposely not controlled (e.g. wall adapters delivering raw DC level), it is interesting to implement a true short−circuit protection. A short−circuit actually forces the output voltage to be at a low level, preventing a bias current to circulate in the Optocoupler LED. As a result, the FB pin level is pulled up to 4.2 V, as internally imposed by the IC. The peak current setpoint goes to the maximum and the supply delivers a rather high power with all the associated effects. Please note that this can also happen in case of feedback loss, e.g. a broken Optocoupler. To account for this situation, NCP1216 hosts a dedicated overload detection circuitry. Once activated, this circuitry imposes to deliver pulses in a burst manner with a low duty−cycle. The system auto−recovers when the fault condition disappears. VCC Regulation Occurs Here 12.2 V Latch−off Phase 10 V 5.6 V Time Drv VCCOFF = 12.2 V VCCON = 10 V VCClatch = 5.6 V Driver Pulses Driver Pulses Time Internal Fault Flag Fault is Relaxed Time Start−up Phase Fault Occurs Here Figure 24. If the fault is relaxed during the VCC natural fall down sequence, the IC automatically resumes. If the fault still persists when VCC reached VCCON, then the controller cuts everything off until recovery. you first apply the power to the IC. The corresponding transient fault duration due to the output capacitor charging must be less than the time needed to discharge from 12.2 V to 10 V, otherwise the supply will not properly start. The test consists in either simulating or measuring in the lab how much time the system takes to reach the regulation at full load. Let’s suppose that this time corresponds to 6ms. Therefore a VCC fall time of 10 ms could be well appropriated in order to not trigger the overload detection circuitry. If the corresponding IC consumption, including Calculating the VCC Capacitor As the above section describes, the fall down sequence depends upon the VCC level: how long does it take for the VCC line to go from 12.2 V to 10 V The required time depends on the start−up sequence of your system, i.e. when http://onsemi.com 13 NCP1216 internal parasitic SCRs are triggered, engendering irremediable damages to the IC if a low impedance path is offered between VCC and GND. If the current sense pin is often the seat of such spurious signals, the high−voltage pin can also be the source of problems in certain circumstances. During the turn−off sequence, e.g. when the user unplugs the power supply, the controller is still fed by its VCC capacitor and keeps activating the MOSFET ON and OFF with a peak current limited by Rsense. Unfortunately, if the quality coefficient Q of the resonating network formed by Lp and Cbulk is low (e.g. the MOSFET Rdson + Rsense are small), conditions are met to make the circuit resonate and thus negatively bias the controller. Since we are talking about ms pulses, the amount of injected charge, (Q = I * t), immediately latches the controller that brutally discharges its VCC capacitor. If this VCC capacitor is of sufficient value, its stored energy damages the controller. Figure 25 depicts a typical negative shot occurring on the HV pin where the brutal VCC discharge testifies for latch−up. the MOSFET drive, establishes at 2.9 mA, we can calculate the required capacitor using the following formula: t V·C i (eq. 19) with V = 2.2 V. Then for a wanted t of 30 ms, C equals 39.5 F or a 68 F for a standard value (including ±20% dispersions). When an overload condition occurs, the IC blocks its internal circuitry and its consumption drops to 350 A typical. This happens at VCC = 10 V and it remains stuck until VCC reaches 5.6 V: we are in latch−off phase. Again, using the selected 68 F and 350 A current consumption, this latch−off phase lasts: 780 ms. Protecting the Controller Against Negative Spikes As with any controller built upon a CMOS technology, it is the designer’s duty to avoid the presence of negative spikes on sensitive pins. Negative signals have the bad habit to forward bias the controller substrate and induce erratic behaviors. Sometimes, the injection can be so strong that 0 VCC 5 V/DIV Vlatch 1 V/DIV 10 ms/DIV Figure 25. A Negative Spike Takes Place on the Bulk Capacitor at the Switch−off Sequence Another option (Figure 27) consists in wiring a diode from VCC to the bulk capacitor to force VCC to reach VCCON sooner and thus stops the switching activity before the bulk capacitor gets deeply discharged. For security reasons, two diodes can be connected in series. Simple and inexpensive cures exist to prevent from internal parasitic SCR activation. One of them consists in inserting a resistor in series with the high−voltage pin to keep the negative current to the lowest when the bulk becomes negative (Figure 26). Please note that the negative spike is clamped to (−2 * Vf) due to the diode bridge. Also, the power dissipation of this resistor is extremely small since it only heats up during the start−up sequence. http://onsemi.com 14 NCP1216 Rbulk > 4.7 k + + Cbulk Cbulk 1 8 2 7 3 6 4 5 + 1 8 2 7 3 6 4 5 D3 1N4007 + CVCC Figure 26. CVCC Figure 27. A simple resistor in series avoids any latch−up in the controller or one diode forces VCC to reach VCCON sooner. ORDERING INFORMATION Device Version Marking Package Shipping NCP1216D065 65 kHz 16D06 SOIC−8 2500 / Tape & Reel NCP1216D100 100 kHz 16D10 SOIC−8 2500 / Tape & Reel NCP1216D133 133 kHz 16D13 SOIC−8 2500 / Tape & Reel NCP1216P065 65 kHz P1216P065 PDIP−7 50 Units/ Rail NCP1216P100 100 kHz P1216P100 PDIP−7 50 Units/ Rail NCP1216P133 133 kHz P1216P133 PDIP−7 50 Units/ Rail http://onsemi.com 15 NCP1216 PACKAGE DIMENSIONS SO−8 D SUFFIX CASE 751−07 ISSUE AA NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. −X− A 8 5 0.25 (0.010) S B 1 M Y M 4 K −Y− G C N X 45 SEATING PLANE −Z− 0.10 (0.004) H D 0.25 (0.010) M Z Y S X M S http://onsemi.com 16 J DIM A B C D G H J K M N S MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0 8 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 8 0.010 0.020 0.228 0.244 NCP1216 PACKAGE DIMENSIONS PDIP−7 P SUFFIX CASE 626B−01 ISSUE A J 8 5 M B 1 L NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS IN MILLIMETERS. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. PACKAGE CONTOUR OPTIONAL (ROUND OR SQUARE CORNERS). 5. DIMENSIONS A AND B ARE DATUMS. 4 DIM A B C D F G H J K L M N F A NOTE 2 C −T− N SEATING PLANE H D K G 0.13 (0.005) M T A M B M http://onsemi.com 17 MILLIMETERS MIN MAX 9.40 10.16 6.10 6.60 3.94 4.45 0.38 0.51 1.02 1.78 2.54 BSC 0.76 1.27 0.20 0.30 2.92 3.43 7.62 BSC −−− 10 ° 0.76 1.01 NCP1216 The product described herein (NCP1216), may be covered by the following U.S. patents: 6,385,060; 6,587,357. There may be other patents pending. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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