Ordering number : ENA2053 CMOS LSI LC898300XA Linear Vibrator Driver IC Overview LC898300XA is a Linear Vibrator Driver IC for a haptics and a vibrator installed in mobile equipments. The best feature is it can adjust the drive frequency to the resonance frequency of the linear vibrator automatically without external parts. As a result, the vibration power is not influenced by the difference of the resonance frequency and it is not necessary to care about the shift of resonance frequency with the lapse of time or the impact of fall. And it is possible to improve the brake performance with the automatic brake function. Moreover, it is possible to reduce the power consumption by highly effective drive. Functions Automatic adjustment to the individual resonance frequency Automatic brake function Initial drive frequency adjustment function Drive voltage adjustment with I2C IF setting Various drive pattern with I2C* IF setting (1.8V IF is available) Low driving noise Low power consumption by highly effective drive (100degree drive) Applications Linear Vibrator (Vibration and haptics) Portable Game Mobile Phone Mobile equipment with haptics function Specifications Absolute Maximum Ratings at VSS = 0V Parameter Symbol Supply voltage range VDD max Input voltage VI 1 VI2 Output voltage Conditions IO max Allowable power dissipation Pd max Operating temperature range Ta Unit -0.3 to 4.6 -0.3 to VDD+0.3 *1 VO H-bridge Drive current Ratings Ta = 85C *2 V V -0.3 to 5.8 V -0.3 to VDD+0.3 V 150 mA 170 mW -30 to 85 C Continued on next page. * I2C Bus is a trademark of Philips Corporation. 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To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer ' s products or equipment. 80812HK/41912 SY 20110920-S00002 No.A2053-1/7 LC898300XA Continued from preceding page. Parameter Symbol Storage temperature range Tstg Input or Output current II,IO Conditions Ratings Unit *3 -55 to 125 C ±20 mA *1: Input voltage without diode connection to VDD. (SDA, SCL) *2: Grass epoxy (50mm 40mm 0.9mm3, FR-4) *3: Per an I/O buffer Recommended Operating Conditions at Ta = -30 to 85C, VSS = 0V Ratings Parameter Symbol Conditions Unit min Supply voltage range VDD typ max 2.7 3.0 3.3 V 0 - VDD V Input voltage range VIN1 *1: Input voltage without diode connection to VDD. (SDA, SCL) Electrical Characteristics Ratings Parameter Symbol Conditions Applied pin Unit min typ max DC characteristics at VSS = 0V, VDD = 2.7 to 3.3V, Ta = -30 to 85C High level input voltage VIH1 CMOS TEST 0.7VDD - - V - - 0.2VDD V CMOS EN 1.5 - - V - - 0.36 V RSTB, SDA 1.5 - - V , SCL - - 0.36 V SDA - - 0.4 V RSTB, EN -10 - +10 A Low level input voltage VIL1 High level input voltage VIH2 Low level input voltage VIL2 High level input voltage VIH3 Low level input voltage VIL3 Low level output voltage VOL IOL = 4mA Input leakage current IIL VI = VDD, VSS CMOS Schmitt , SDA, SCL Analog characteristics at VSS = 0V, VDD = 3V, Ta = 25C H-bridge ON resistance Pch RONP IF = 100mA - 2.5 - H-bridge ON resistance Nch RONN IS = 100mA - 1.5 - Adjustable resonance frequency Fmo vs typ value -10 - +10 % range Package Dimensions unit : mm (typ) 3429 SIDE VIEW BOTTOM VIEW 0.205 TOP VIEW 3 0.20 2 1 0.4 C B 1.21 A 1.39 0.295 0.08 0.56 MAX SIDE VIEW (0.43) 0.4 SANYO : WLP9(1.39X1.21) No.A2053-2/7 LC898300XA Block Diagram VDD OUT1 Drive signal Generator EN Linear Vibrator H-bridge OUT2 Register setting SCL SDA OSC POR VSS TEST RSTB Pin Assignment Pin list I/O ( I: input, O: output, B: bi-direction, P: power supply, NC: not connected ) No Name I/O No Name I/O No Name I/O 1A SDA B 1B EN I 1C RSTB I 2A VDD TEST P 2B OUT2 O 2C SCL I I 3B OUT1 O 3C GND P 3A Pin layout GND OUT1 TEST 3 VDD 2 1 SCL OUT2 RSTB EN SDA C B A < Bottom View > Pin description I/O ( I: input, O: output, B: bi-direction, P: power supply, NC: not connected ) Signal name I/O OUT1 O Motor drive pin Function H-bridge output Remarks OUT2 O Motor drive pin H-bridge output RSTB I Reset and standby control L: enable, H: disable EN I Motor drive ON/OFF L: disable, H: enable SCL I I2C I/F clock pin SDA B I2C I/F data pin Open drain TEST I TEST pin L: disable, H: enable (normally Low fix) VDD VSS P Power supply pin P GND pin No.A2053-3/7 LC898300XA Timing chart Motor drive timing The Motor is driven by EN pin, and the driving time is controlled by keeping EN pin “H”. The High speed start UP time, driving power and Brake time can be modified by I2C setting. The initial driving frequency must be set by I2C I/F at the center of resonance frequency of the linear vibrators, when the initial driving frequency is inadequate. The minimum width of EN signal must be larger than the cycle of initial driving frequency setting. EN OUT1 OUT2 High speed Start UP Time Driving Time(Driving power is adjusted by driving voltage) Brake Time Stand-by Control The Stand-by mode is controlled by RSTB pin. (RSTB=”L” Stand-by mode is ON.) When the stand-by mode is “ON”, the register value is set to initial value. So, the register must be set again after the stand-by mode is “OFF”. And, the “EN” signal and I2C command must wait over 200us after “RSTB” pin is set to “H”. RSTB 30ms EN Stand-by Driving off I2 C Set registers again Driving on Brake Driving off Stand-by This period isn t need, if the brake is not used. EN Control The width of EN=High should be set at least 1 driving cycle. ex) 0x02 RESOFRQ=0x0A (175Hz) (min) 5.71ms The width of EN=Low should be kept over 30ms, if the pre-driving period is over 30ms. On the other hand, If the pre-driving period is less than 30ms, the minimum width of EN=Low is same as the pre-driving width. (min)30ms EN (min) 1 driving cycle No.A2053-4/7 LC898300XA 2 I C Serial Interface Writing format (Sequential Writing is possible) After the start condition, slave address (7bit) and “L”(Write mode) are received , the flag “ACK=L” is replied. Next, after the 8bit address is received, the flag “ACK=L” is replied. Next, after the 8bit write data is received, the flag “ACK=L” is replied. Next, when the stop condition is received, the write data can be written in the specified address. Moreover, it is possible to write data in the incremental address by the continuous input of the 8bit data confirming the flag “ACK=L” after the every 8bit write data input. START L SLAVE ADDRESS AC K AC K ADDR(N) ADDR(N) WRITE DATA AC K ADDR(N+1) WRITE DATA AC K AC K ADDR(N+2) WRITE DATA STOP SDA SCL Reading format (Sequential Reading is possible) After the dummy writing, the start condition, slave address (7bit) and “H”(Read mode) are received, the flag “ACK=L” is replied. Next, the 8bit read data is output. After them, when the stop condition is not received, and the read condition is continued, the read data of incremental address is output one by one. The read condition is end when the end condition is received after the flag “ACK=H”. Dummy writing START SLAVE ADDRESS L AC K AC K ADDR(N) START SLAVE ADDRESS H AC K ADDR(N) READ DATA AC K *1 SDA SCL *1 ADDR(N+1) READ DATA AC K ADDR(N+2) READ DATA AC K ADDR(N+3) READ DATA AC K END SDA SCL Slave Address The Slave Address is as follows. Slave Address 1001001 No.A2053-5/7 LC898300XA 2 AC Characteristics (I C Serial Interface) at VSS = 0V, VDD = 2.7 to 3.3V, Ta = -30 to 85C Parameter Symbol Pin Min Typ Max Unit SCL clock frequency fSCL SCL - - 400 kHz START condition Hold time tHD;STA 0.6 - - us SCL SDA comment SCL clock Low width tLOW SCL 1.3 - - us SCL clock High width tHIGH SCL 0.6 - - us 0.6 - - us 0 - 0.9 us 0.2 - - us *1 - 0.3 us *1 - 0.3 us *1 0.6 - - us 1.3 - - us RE-START condition SCL tSU;STA Setup time SDA Hold time tHD;DAT SDA Setup time tSU;DAT SDA, SCL Rise time tr SDA, SCL Fall time tf STOP condition Setup time tSU;STP STOP to START SDA SCL SDA SCL SDA SCL SDA SCL SDA SCL SDA SCL tBUF BUS open time SDA *1) Design Assurance (Shipment test none) 90% 90% SDA 10% 10% 10% tHD.STA tSU.STP 10% 90% 90% 10% tSU.STA tHD.DAT tSU.DAT tBUF tLOW 90% SCL tHIGH 10% tHD.STA tr 90% 90% 90% 90% 10% tf REPEATED CONDITION START CONDITION STOP CONDITION START CONDITION AC Characteristic (Power On Reset) at VSS = 0V, VDD = 2.7 to 3.3V, Ta = -30 to 85C Parameter Symbol Min Typ Max Unit comment VDD Rise Up Time tVDDUP - - 100 ms - 90% VDD 10% t VDDUP No.A2053-6/7 LC898300XA Application information 2.7 - 3.3V 1) Case-1: With standby-control 0.1F Standby control Enable control Application Processor RSTB VDD EN OUT1 OUT2 SCL SDA I2C IF GND Pull-UP LRA TEST Note) When SDA&SCL signal voltages are different from VDD, even if the RSTB pin is set to Low, the IO leak current flows. ex) In case of VDD=3.0V & SDA=SCL=1.8V, the current consumption is about 100A(typ). 2) Case-2: Without standby-control Note) In case of VDD=3.0V, the current consumption is about 1.5mA(typ). 2.7 - 3.3V 0.1F RSTB Enable control Application Processor VDD EN OUT1 OUT2 SCL SDA 2 I C IF Pull-UP GND LRA TEST SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. Regarding monolithic semiconductors, if you should intend to use this IC continuously under high temperature, high current, high voltage, or drastic temperature change, even if it is used within the range of absolute maximum ratings or operating conditions, there is a possibility of decrease reliability. Please contact us for a confirmation. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. 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Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellectual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of August, 2012. Specifications and information herein are subject to change without notice. PS No.A2053-7/7