SPANSION S25FL216K

S25FL216K
16-Mbit 3.0V Serial Flash Memory with Uniform 4 kB Sectors
Data Sheet (Preliminary)
S25FL216K Cover Sheet
Notice to Readers: This document states the current technical specifications regarding the Spansion
product(s) described herein. Each product described herein may be designated as Advance Information,
Preliminary, or Full Production. See Notice On Data Sheet Designations for definitions.
Publication Number S25FL216K_00
Revision 07
Issue Date August 9, 2012
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Notice On Data Sheet Designations
Spansion Inc. issues data sheets with Advance Information or Preliminary designations to advise readers of
product information or intended specifications throughout the product life cycle, including development,
qualification, initial production, and full production. In all cases, however, readers are encouraged to verify
that they have the latest information before finalizing their design. The following descriptions of Spansion data
sheet designations are presented here to highlight their presence and definitions.
Advance Information
The Advance Information designation indicates that Spansion Inc. is developing one or more specific
products, but has not committed any design to production. Information presented in a document with this
designation is likely to change, and in some cases, development on the product may discontinue. Spansion
Inc. therefore places the following conditions upon Advance Information content:
“This document contains information on one or more products under development at Spansion Inc.
The information is intended to help you evaluate this product. Do not design in this product without
contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed
product without notice.”
Preliminary
The Preliminary designation indicates that the product development has progressed such that a commitment
to production has taken place. This designation covers several aspects of the product life cycle, including
product qualification, initial production, and the subsequent phases in the manufacturing process that occur
before full production is achieved. Changes to the technical specifications presented in a Preliminary
document should be expected while keeping these aspects of production under consideration. Spansion
places the following conditions upon Preliminary content:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. The Preliminary status of this document indicates that product qualification has been
completed, and that initial production has begun. Due to the phases of the manufacturing process that
require maintaining efficiency and quality, this document may be revised by subsequent versions or
modifications due to changes in technical specifications.”
Combination
Some data sheets contain a combination of products with different designations (Advance Information,
Preliminary, or Full Production). This type of document distinguishes these products and their designations
wherever necessary, typically on the first page, the ordering information page, and pages with the DC
Characteristics table and the AC Erase and Program table (in the table notes). The disclaimer on the first
page refers the reader to the notice on this page.
Full Production (No Designation on Document)
When a product has been in production for a period of time such that no changes or only nominal changes
are expected, the Preliminary designation is removed from the data sheet. Nominal changes may include
those affecting the number of ordering part numbers available, such as the addition or deletion of a speed
option, temperature range, package type, or VIO range. Changes may also include those needed to clarify a
description or to correct a typographical error or incorrect specification. Spansion Inc. applies the following
conditions to documents in this category:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. Spansion Inc. deems the products to have been in sufficient production volume such
that subsequent versions of this document are not expected to change. However, typographical or
specification corrections, or modifications to the valid combinations offered may occur.”
Questions regarding these document designations may be directed to your local sales office.
2
S25FL216K_00_07 August 9, 2012
S25FL216K
16-Mbit 3.0V Serial Flash Memory with Uniform 4 kB Sectors
Data Sheet (Preliminary)
Distinctive Features
 Single power supply operation
– Full voltage range: 2.7 to 3.6V
 16-Mbit Serial Flash
– 16-Mbit/2048 kbyte/9192 pages
– 256 bytes per programmable page
– Uniform 4-kbyte Sectors/64-kbyte Blocks
–
–
–
–
–
Sector Erase (4 kB)
Block Erase (64 kB)
Page Program up to 256 bytes
100k erase/program cycles typical
20-year data retention typical
 Software and Hardware Write Protection
 Standard and Dual
–
–
–
–
 Flexible Architecture with 4 kB Sectors
Standard SPI: SCK, CS#, SI, SO, WP#, HOLD#
Dual SPI: SCK, CS#, SI/IO0, SO, WP#, HOLD#
Fast Read Dual Output instruction
Auto-increment Read capability
 High Performance
– FAST READ (Serial): 65 MHz clock rate
– DUAL OUTPUT READ: 65 MHz clock rate
 Low Power Consumption
– 12 mA typical active current
– 15 µA typical standby current
– Write Protect all or portion of memory via software
– Enable/Disable protection with WP# pin
 High Performance Program/Erase Speed
–
–
–
–
Page program time: 1.6 ms typical
Sector erase time (4 kB): 45 ms typical
Block erase time (64 kB): 450 ms typical
Chip erase time: 12 seconds typical
 Package Options
– 8-pin SOIC 150/208-mil
– All Pb-free packages are RoHS compliant
General Description
The S25FL216K device is a 16-Mbit, 2048-kbyte Serial Flash memory, with advanced write protection mechanisms. The
S25FL216K supports the standard Serial Peripheral Interface (SPI), and a high performance Dual output using SPI pins: Serial
Clock, Chip Select, Serial SI/IO0, SO, WP#, and HOLD#. SPI clock frequencies of up to 65 MHz are supported.
The S25FL216K array is organized into 8,192 programmable pages of 256 bytes each. Up to 256 bytes can be programmed at
a time. Pages can be erased in groups of 16 (4-kB Sector Erase), groups of 256 (64-kB Block Erase) or the entire chip (Chip
Erase). The S25FL216K has 512 erasable sectors and 32 erasable blocks. The small 4 kB sectors allow for greater flexibility in
applications that require data and parameter storage.
A Hold pin, Write Protect Pin and programmable write protection provide further control flexibility. Additionally, the S25FL216K
device supports JEDEC standard manufacturer and device identification.
Publication Number S25FL216K_00
Revision 07
Issue Date August 9, 2012
This document states the current technical specifications regarding the Spansion product(s) described herein. The Preliminary status of this document indicates that product qualification has been completed, and that initial production has begun. Due to the phases of the manufacturing process that require maintaining efficiency and quality, this document
may be revised by subsequent versions or modifications due to changes in technical specifications.
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Table of Contents
Distinctive Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
4
1.
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.
Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.1
Valid Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.
Memory Organizations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
6.
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.1
SPI Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.2
Dual Output SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3
Hold Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.4
Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11
11
11
11
12
7.
Write Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.1
Page Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.2
Sector Erase, Block Erase, and Chip Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.3
Polling During a Write, Program, or Erase Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.4
Active Power, Stand-by Power, and Deep Power-Down Modes . . . . . . . . . . . . . . . . . . . . . .
13
14
14
14
14
8.
Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.1
Write Enable (06h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.2
Write Disable (04h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.3
Read Status Register (05h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.4
Write Status Register (01h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.5
Read Data (03h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.6
Fast Read (0Bh). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.7
Fast Read Dual Output (3Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.8
Page Program (PP) (02h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.9
Sector Erase (SE) (20h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.10 Block Erase (BE) (D8h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.11 Chip Erase (CE) (C7h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.12 Deep Power-down (DP) (B9h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.13 Release Deep Power-down / Device ID (ABh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.14 Read Manufacturer / Device ID (90h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.15 Read Identification (RDID) (9Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14
15
16
16
17
18
18
19
20
21
22
22
23
24
25
26
9.
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.1
Power-up Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.2
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.3
Recommended Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.4
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.5
AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.6
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28
28
29
29
30
30
31
10.
Package Material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
10.1 8-Pin SOIC 150-mil Package (SOA 008) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
10.2 8-Pin SOIC 208-mil Package (SOC 008). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
11.
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
S25FL216K
S25FL216K_00_07 August 9, 2012
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Figures
Figure 2.1
Figure 5.1
Figure 6.1
Figure 6.2
Figure 8.1
Figure 8.2
Figure 8.3
Figure 8.4
Figure 8.5
Figure 8.6
Figure 8.7
Figure 8.8
Figure 8.9
Figure 8.10
Figure 8.11
Figure 8.12
Figure 8.13
Figure 8.14
Figure 8.15
Figure 8.16
Figure 9.1
Figure 9.2
Figure 9.3
Figure 9.4
Figure 9.5
August 9, 2012 S25FL216K_07
8-pin SOIC (150/208 mil) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Memory Organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
SPI Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Hold Condition Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Write Enable Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Write Disable Command Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Read Status Register Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Write Status Register Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Read Data Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Fast Read Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Fast Read Dual Output Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Page Program Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Sector Erase Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Block Erase Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Chip Erase Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Deep Power-down Command Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Release Deep Power-down Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Release Deep Power-down / Device ID Command Sequence . . . . . . . . . . . . . . . . . . . . . . . 25
Read Manufacturer / Device ID Command Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Read JEDEC ID Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Power-up Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Serial Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Hold Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
S25FL216K
5
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Tables
Table 3.1
Table 4.1
Table 6.1
Table 7.1
Table 8.1
Table 8.2
Table 9.1
Table 9.2
Table 9.3
Table 9.4
Table 9.5
Table 9.6
6
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
S25FL216K Valid Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Status Register Bit Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Protected Area Sizes Block Organization — S25FL216K . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Command Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Manufacturer and Device Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Power-up Voltage and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Recommended Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
S25FL216K
S25FL216K_00_07 August 9, 2012
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1. Block Diagram
Flash
M em ory
X -Decoder
Address
Buffers
and
Latches
Y- Decoder
I/O Buffers
and Data
Latches
Control Logic
Serial Interface
CS #
SCK
SI/IO0
SO
W P#
HO LD #
2. Connection Diagrams
Figure 2.1 8-pin SOIC (150/208 mil)
August 9, 2012 S25FL216K_00_07
CS#
1
8
VCC
SO
2
7
HOLD#
WP#
3
6
SCK
GND
4
5
SI/IO0
S25FL216K
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3. Signal Descriptions
Serial Data Input / Output (SI/IO0)
The SPI Serial Data Input/Output (SI/IO0) pin provides a means for instructions, addresses and data to be
serially written to (shifted into) the device. Data is latched on the rising edge of the Serial Clock (SCK) input
pin. The SI/IO0 pin is also used as an output pin when the Fast Read Dual Output instruction is executed.
Serial Data Output (SO)
The SPI Serial Data Output (SO) pin provides a means for data and status to be serially read from (shifted out
of) the device. Data is shifted out on the falling edge of the Serial Clock (SCK) input pin.
Serial Clock (SCK)
The SPI Serial Clock Input (SCK) pin provides the timing for serial input and output operations. See SPI
Modes on page 11.
Chip Select (CS#)
The SPI Chip Select (CS#) pin enables and disables device operation. When CS# is high the device is
deselected and the Serial Data Output pins are at high impedance.
When deselected, the device’s power consumption will be at standby levels unless an internal erase, program
or status register cycle is in progress. When CS# is brought low the device will be selected, power
consumption will increase to active levels and instructions can be written to and data read from the device.
After power-up, CS# must transition from high to low before a new instruction will be accepted.
HOLD (HOLD#)
The HOLD# pin allows the device to be paused while it is actively selected. When HOLD# is brought low,
while CS# is low, the SO pin will be at high impedance and signals on the SI and SCK pins will be ignored
(don’t care). The HOLD# function can be useful when multiple devices are sharing the same SPI signals.
Write Protect (WP#)
The Write Protect (WP#) pin can be used to prevent the Status Register from being written. Used in
conjunction with the Status Register’s Block Protect (BP0, BP1 and BP2, BP3) bits and Status Register
Protect (SRP) bits, a portion or the entire memory array can be hardware protected.
Table 3.1 Pin Descriptions
Symbol
Pin Name
SCK
Serial Clock Input
SI/IO0
Serial Data Input / Output (1)
SO
Serial Data Output
CS#
Chip Enable
WP#
Write Protect
HOLD#
Hold Input
VCC
Supply Voltage (2.7-3.6V)
GND
Ground
Note:
1. SI/IO0 output is used for Dual Output Read instruction.
8
S25FL216K
S25FL216K_00_07 August 9, 2012
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4.
S h e e t
( P r e l i m i n a r y)
Ordering Information
The ordering part number is formed by a valid combination of the following:
S25FL
216
K
0P
M
F
I
01
1
Packing Type
0
= Tray
1
= Tube
3
= 13” Tape and Reel
Model Number (Additional Ordering Options)
04 = 8-pin SO package (150 mil)
01 = 8-pin SO package (208 mil)
Temperature Range
I
=
Industrial (–40°C to +85°C)
Package Materials
F
= Lead (Pb)-free
Package Type
M
= 8-pin SO package
Speed
0P =
65 MHz
Device Technology
K
= 0.09 µm process technology
Density
216 =
16 Mbit
Device Family
S25FL
Spansion Memory 3.0 Volt-Only, Serial Peripheral Interface (SPI) Flash Memory
4.1
Valid Combinations
Table 4.1 lists the valid combinations configurations planned to be supported in volume for this device.
Table 4.1 S25FL216K Valid Combinations
S25FL216K Valid Combinations
Base Ordering
Part Number
Speed Option
Package and
Temperature
Model
Number
Packing Type
Package Marking
S25FL216K
0P
MFI
01, 04
0, 1, 3
FL216KIF
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5.
S h e e t
( P r e lim in a r y )
Memory Organizations
The memory is organized as:
 2,097,152 bytes
 Uniform Sector Architecture
– 32 blocks of 64 kB
– 512 sectors of 4 kB
 8,192 pages (256 bytes each)
Each page can be individually programmed (bits are programmed from 1 to 0). The device is Sector, Block or
Chip Erasable but not Page Erasable.
Figure 5.1 Memory Organization
xxFF00h
.
Sector 15 (4 kB)
xxF000h
xxEF00h
Sector 14 (4 kB)
xxE000h
1FFF00h
.
.
xxF0FFh
xxEFFFh
1F0000h
1FFFFFh
Block 31 (64 kB)
.
xxE0FFh
08FF00h
.
08FFFFh
Block 8 (64 kB)
…
0800FFh
07FF00h
07FFFFh
Block 7 (64 kB)
070000h
xx1F00h
Sector 1 (4 kB)
10
Sector 0 (4 kB)
...
xx0000h
.
0700FFh
xx1FFFh
xx1000h
xx0F00h
.
.
080000h
.
.
.
1F0FFFh
...
.
xxFFFFh
.
xx10FFh
xx0FFFh
00FF00h
.
.
xx00FFh
000000h
S25FL216K
00FFFFh
Block 0 (64 kB)
.
0000FFh
S25FL216K_00_07 August 9, 2012
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6.
6.1
S h e e t
( P r e l i m i n a r y)
Functional Description
SPI Modes
The S25FL216K device can be driven by an embedded microcontroller (bus master) in either of the two
following clocking modes.
 Mode 0 with Clock Polarity (CPOL) = 0 and, Clock Phase (CPHA) = 0
 Mode 3 with CPOL = 1 and, CPHA = 1
For these two modes, input data into the device is always latched in on the rising edge of the SCK signal and
the output data is always available from the falling edge of the SCK clock signal. The difference between the
two modes is the clock polarity when the bus master is in standby mode and not transferring any data.
 SCK will stay at logic low state with CPOL = 0, CPHA = 0
 SCK will stay at logic high state with CPOL = 1, CPHA = 1
Figure 6.1 SPI Modes
CS #
SCK
M ode3
M ode 3
M ode0
M ode 0
SI/IO0
B it7
B it6
B it5
B it4
B it3
B it2
B it1
B it0
D ON T C AR E
M SB
SO
H ig h Im p e d a n ce
B it7
B it6
B it5
B it4
B it3
B it2
B it1
B it0
M SB
6.2
Dual Output SPI
The S25FL216K supports Dual Output Operation when using the “Fast Read with Dual Output” (3B hex)
command. This feature allows data to be transferred from the Serial Flash at twice the rate possible with the
standard SPI. This command can be used to quickly download code from Flash to RAM upon Power-up
(Code-shadowing) or for applications that cache code-segments to RAM for execution.
The Dual Output feature simply allows the SPI data input pin (SI) to also serve as an output during this
command. All other operations use the standard SPI interface with single signal. The host keeps CS# low and
HOLD# high. The Write Protect (WP#) signal is ignored. The memory drives data on the SI/IO0 and SO
signals during the dual output cycles. The next interface state continues to be Dual Output Cycle until the host
returns CS# to high ending the command.
6.3
Hold Function
The Hold (HOLD#) signal is used to pause any serial communications with the S25FL216K device without
deselecting the device or stopping the serial clock. To enter the Hold condition, the device must be selected
by driving the CS# input to the logic low state. It is recommended that the user keep the CS# input low state
during the entire duration of the Hold condition. This is to ensure that the state of the interface logic remains
unchanged from the moment of entering the Hold condition. If the CS# input is driven to the logic high state
while the device is in the Hold condition, the interface logic of the device will be reset. To restart
communication with the device, it is necessary to drive HOLD# to the logic high state while driving the CS#
signal into the logic low state. This prevents the device from going back into the Hold condition.
The Hold condition starts on the falling edge of the Hold (HOLD#) signal, provided that this coincides with
SCK being at the logic low state. If the falling edge does not coincide with the SCK signal being at the logic
low state, the Hold condition starts whenever the SCK signal reaches the logic low state. Taking the HOLD#
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signal to the logic low state does not terminate any Write, Program or Erase operation that is currently in
progress.
During the Hold condition, SO is in high impedance and both the SI and SCK input are Don't Care. The Hold
condition ends on the rising edge of the Hold (HOLD#) signal, provided that this coincides with the SCK signal
being at the logic low state. If the rising edge does not coincide with the SCK signal being at the logic low
state, the Hold condition ends whenever the SCK signal reaches the logic low state.
Figure 6.2 Hold Condition Waveform
SCK
HO LD #
A ctive
6.4
H o ld
A ctive
H o ld
A ctive
Status Register
The Status Register contains a number of status and control bits that can be read or set (as appropriate) by
specific instructions
Table 6.1 Status Register Bit Locations
R7
R6
R5
R4
R3
R2
R1
R0
SRP
REV
BP3
BP2
BP1
BP0
WEL
WIP
 WIP (Write In Progress) is a read only bit in the status register (R0) which indicates whether the device is
performing a program, write, erase operation, or any other operation, during which a new operation
command will be ignored. When the WIP bit is set to 1, the device is busy performing an operation. When
the bit is cleared to 0, no operation is in progress.
 Write Enable Latch (WEL) is a read only bit in the status register (R1) that must be set to 1 to enable
program, write, or erase operations as a means to provide protection against inadvertent changes to
memory or register values. The Write Enable (WREN) command execution sets the Write Enable Latch to
a 1 to allow any program, erase, or write commands to execute afterwards. The Write Disable (WRDI)
command can be used to set the Write Enable Latch to a 0 to prevent all program, erase, and write
commands from execution. The WEL bit is cleared to 0 at the end of any successful program, write, or
erase operation. After a power down/power up sequence, hardware reset, or software reset, the Write
Enable Latch is set to a 0.
 Block Protect Bits (BP3, BP2, BP1, BP0) are non-volatile read/write bits in the status register (R5, R4,
R3, and R2) that define the main flash array area to be software protected against program and erase
commands. When one or more of the BP bits is set to 1, the relevant memory area is protected against
program and erase. The Chip Erase (CE) command can be executed only when the BP bits are cleared to
0’s. See Table 7.1 on page 13 for a description of how the BP bit values select the memory array area
protected. The factory default setting for all the BP bits is 0, which implies that none of array is protected.
 Reserved Bits (REV), Status register bit location R6 is reserved for future use. Current devices will read 0
for this bit location. It is recommended to mask out the reserved bit when testing the Status Register. Doing
this will ensure compatibility with future devices.
 The Status Register Protect (SRP) bit is a non-volatile read/write bit in status register (R7) that can be
used in conjunction with the Write Protect (WP#) pin to disable writes to status register. When the SRP bit
is set to a 0 state (factory default) the WP# pin has no control over status register. When the SRP pin is set
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( P r e l i m i n a r y)
to a 1, the Write Status Register instruction is locked out while the WP# pin is low. When the WP# pin is
high the Write Status Register instruction is allowed.
7. Write Protection
Some basic protection against unintended changes to stored data is provided and controlled purely by the
hardware design. These protection mechanisms in the S25FL216K device are described below:
 Power-On Reset and an internal timer (tPUW) can provide protection against inadvertent changes while the
power supply is outside the operating specification.
 Program, Erase and Write Status Register instructions are checked that they consist of a number of clock
pulses that is a multiple of eight, before they are accepted for execution.
 All instructions that modify data must be preceded by a Write Enable (WREN) instruction to set the Write
Enable Latch (WEL) bit. This bit is returned to its reset state by the following events:
– Power-up
– Write Disable (WRDI) instruction completion or Write Status Register (WRSR) instruction completion or
Page Program (PP) instruction completion or Sector Erase (SE) instruction completion or Block Erase
(BE) instruction completion or Chip Erase (CE) instruction completion
 The Block Protect (BP3, BP2, BP1, and BP0) bits allow part of the memory to be configured as read-only.
This is the Software Protected Mode (SPM).
 The Write Protect (WP#) signal allows the Block Protect (BP3, BP2, BP1, BP0) bits and Status Register
Protect (SRP) bit to be protected. This is the Hardware Protected Mode (HPM).
 In addition to the low power consumption feature, the Deep Power-down mode offers extra software
protection from inadvertent Write, Program and Erase instructions, as all instructions are ignored except
one particular instruction (the Release from Deep Power-down instruction).
Table 7.1 Protected Area Sizes Block Organization — S25FL216K
Status Bit
Protect Blocks
BP3
BP2
BP1
BP0
0
0
0
0
0 (None)
0
0
0
1
1 (1 block, block 31th)
0
0
1
0
2 (2 blocks, block 30th~31th)
0
0
1
1
3 (4 blocks, block 28th~31th)
0
1
0
0
4 (8 blocks, block 24th~31th)
0
1
0
1
5 (16 blocks, block 16th~31th)
0
1
1
0
6 (32 blocks, all)
0
1
1
1
7 (32 blocks, all)
1
0
0
0
8 (32 blocks, all)
1
0
0
1
9 (32 blocks, all)
1
0
1
0
10 (16 blocks, block 0th~15th)
1
0
1
1
11 (24 blocks, block 0th~23th)
1
1
0
0
12 (28 blocks, block 0th~27th)
1
1
0
1
13 (30 blocks, block 0th~29th)
1
1
1
0
14 (31 blocks, block 0th~30th)
1
1
1
1
15 (32 blocks, all)
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13
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7.1
S h e e t
( P r e lim in a r y )
Page Programming
To program one data byte, two instructions are required: Write Enable (WREN), which is one byte, and a
Page Program (PP) sequence, which consists of four bytes plus data. This is followed by the internal Program
cycle (of duration tPP). To spread this overhead, the Page Program (PP) instruction allows up to 256 bytes to
be programmed at a time (changing bits from 1 to 0), provided that they lie in consecutive addresses on the
same page of memory.
7.2
Sector Erase, Block Erase, and Chip Erase
The Page Program (PP) instruction allows bits to be reset from 1 to 0. Before this can be applied, the bytes of
memory need to have been erased to all 1s (FFh). This can be achieved a sector at a time, using the Sector
Erase (SE) instruction, a block at a time using the Block Erase (BE) instruction or throughout the entire
memory, using the Chip Erase (CE) instruction. This starts an internal Erase cycle (of duration tSE, tBE, or tCE).
The Erase instruction must be preceded by a Write Enable (WREN) instruction.
7.3
Polling During a Write, Program, or Erase Cycle
A further improvement in the time to Write Status Register (WRSR), Program (PP) or Erase (SE, BE, or CE)
can be achieved by not waiting for the worst case delay (tW, tPP, tSE, tBE, or tCE). The Write In Progress (WIP)
bit is provided in the Status Register so that the application program can monitor its value, polling it to
establish when the previous Write cycle, Program cycle or Erase cycle is complete.
7.4
Active Power, Stand-by Power, and Deep Power-Down Modes
When Chip Select (CS#) is Low, the device is enabled, and in the Active Power mode. When Chip Select
(CS#) is High, the device is disabled, but could remain in the Active Power mode until all internal cycles have
completed (Program, Erase, Write Status Register). The device then goes into the Standby Power mode. The
device consumption drops to ICC1.
The Deep Power-down mode is entered when the specific instruction (the Enter Deep Power-down Mode
(DP) instruction) is executed, with the device consumption at ICC2. The device remains in this mode until
another specific instruction (the Release from Deep Power-down Mode and Read Device ID (RDI) instruction)
is executed.
All other instructions are ignored while the device is in the Deep Power-down mode. This can be used as an
extra software protection mechanism, when the device is not in active use, to protect the device from
inadvertent Write, Program or Erase instructions.
8. Commands
The command set of the S25FL216K consists of fifteen basic instructions that are fully controlled through the
SPI bus (see Table 8.1). The host system must shift all commands, addresses, and data in and out of the
device, beginning with the most significant bit. On the first rising edge of SCK after CS# is driven low, the
device accepts the one-byte command on SI (all commands are one byte long), most significant bit first. Each
successive bit is latched on the rising edge of SCK.
Every command sequence begins with a one-byte command code. The command may be followed by
address, data, both, or nothing, depending on the command. CS# must be driven high after the last bit of the
command sequence has been written. All commands that write, program or erase require that CS# be driven
high at a byte boundary, otherwise the command is not executed. Since a byte is composed of eight bits, CS#
must therefore be driven high when the number of clock pulses after CS# is driven low is an exact multiple of
eight. The device ignores any attempt to access the memory array during a Write Registers, program, or
erase operation, and continues the operation uninterrupted.
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Table 8.1 Command Set
Command
Name
Byte1 Code
Write Enable
06h
write Disable
04h
Read Status
Register
05h
(S7-S0) (1)
Write Status
Register
01h
S7-S0
Read Data
03h
A23-A16
Byte2
Byte3
Byte4
Byte5
Byte6
N-bytes
(Note 2)
A15-A8
A7-A0
(D7-D0)
Fast Read
0Bh
A23-A16
A15-A8
A7-A0
dummy
Fast Read Dual
Output
3Bh
A23-A16
A15-A8
A7-A0
dummy
Page Program
02h
A23-A16
A15-A8
A7-A0
(D7-D0)
Block Erase
(64 kB)
D8h
A23-A16
A15-A8
A7-A0
Sector Erase
(4 kB)
20h
A23-A16
A15-A8
A7-A0
Chip Erase
C7h/60h
Power-down
B9h
Release
Power-down /
Device ID
ABh
dummy
dummy
dummy
(ID7-ID0) (4)
Manufacturer /
Device ID (3)
90h
dummy
dummy
00h
(M7-M0)
JEDEC ID
9Fh
(M7-M0)
manufacturer
(ID15-ID8)
Memory Type
(ID7-ID0)
Capacity
(Next byte)
continuous
(D7-D0)
(Next byte)
continuous
I/O=
(One byte per 4
(D6,D4,D2,D0)
clocks,
O=
continuous)
(D7,D5,D3,D1)
Up to 256
bytes
(Next byte)
(ID7-ID0)
Notes:
1. Data bytes are shifted with Most Significant Bit first. Byte fields with data in parenthesis “( )” indicate data being read from the device on
the SO pin.
2. The Status Register contents will repeat continuously until CS# terminates the instruction.
3. See Table 8.2, Manufacturer and Device Identification on page 15 for Device ID information.
4. The Device ID will repeat continuously until CS# terminates the instruction.
Table 8.2 Manufacturer and Device Identification
OP Code
(M7-M0)
(ID15-ID0)
ABh
8.1
(ID7-ID0)
14h
90h
01h
9Fh
01h
14h
4015h
Write Enable (06h)
The Write Enable command (Figure 8.1) sets the Write Enable Latch (WEL) bit in the Status Register to a 1,
which enables the device to accept a Write Status Register, program, or erase command.
The WEL bit must be set prior to every Page Program, Sector Erase, Block Erase, Chip Erase, and Write
Status Register command. The host system must first drive CS# low, write the WREN command, and then
drive CS# high.
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Figure 8.1 Write Enable Command Sequence
CS
0
M o d e3
SCK
1
3
2
4
5
6
7
M o d e3
M o d e0
M o d e0
Ins truc tion (06 H)
SI/IO0
H igh Im pedanc e
SO
8.2
Write Disable (04h)
The Write Disable command (Figure 8.2) resets the Write Enable Latch (WEL) bit to a 0, which disables the
device from accepting a write, program or erase command. The host system must first drive CS# low, write
the WRDI command, and then drive CS# high. The WEL bit is automatically reset after Power-up and upon
completion of the Write Status Register, Page Program, Sector Erase, Block Erase, and Chip Erase
commands.
Figure 8.2 Write Disable Command Sequence
CS
M o d e3
SCK
0
1
2
3
4
5
6
7
M o d e3
M o d e0
M o d e0
Ins truc tion (04 H)
SI/IO0
SO
8.3
H igh Im pedanc e
Read Status Register (05h)
The Read Status Register (RDSR) command outputs the state of the Status Register bits. The RDSR
command may be written at any time, even while a program, erase, or Write Registers operation is in
progress. The host system should check the Write In Progress (WIP) bit before sending a new command to
the device if an operation is already in progress. Figure 8.3 shows the RDSR command sequence, which also
shows that it is possible to read the Status Register continuously until CS# is driven high. (See Section 6.4,
Status Register on page 12).
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Figure 8.3 Read Status Register Command Sequence
CS #
SCK
Mode3
Mode0
0
1
2
3
4
5
6
7
8
9
10
11
12 13
14 15
16
17 18
19 20
21
22 23
Instruction (05 H )
SI/IO0
Status Register O ut
Status Register O ut
SO
High Im pedance
7
6
5
*
4
3
2
1
0
7
6
5
4
3
2
1
0
7
*
*=M SB
8.4
Write Status Register (01h)
The Write Status Register command allows the Status Register to be written. A Write Enable command must
previously have been executed for the device to accept the Write Status Register command (Status Register
bit WEL must equal 1). Once write enabled, the command is entered by driving CS# low, sending the
instruction code “01h”, and then writing the status register data byte as illustrated in Figure 8.4. The Status
Register bits are shown in Table 6.1 on page 12 and described in Section 6.4, Status Register on page 12.
Only non-volatile Status Register bits SRP, BP3, BP2, BP1, and BP0 (bits 7, 5, 4, 3, and 2) can be written to.
All other Status Register bit locations are read-only and will not be affected by the Write Status Register
command.
The CS# chip select input pin must be driven to the logic high state after the eighth bit of data has been
latched in. If not, the Write Status Register command is not executed. As soon as the CS# chip select input
pin is driven to the logic high state, the self-timed Write Status Register cycle is initiated. While the Write
Status Register cycle is in progress, the Status Register may still be read to check the value of the Write In
Progress (WIP) bit. The Write In Progress (WIP) bit is a 1 during the self-timed Write Status Register cycle,
and is a 0 when it is completed. When the Write Status Register cycle is completed, the Write Enable Latch
(WEL) is set to a 0.
The Write Status Register command allows the Block Protect bits (BP3, BP2, BP1, and BP0) to be set for
protecting all, a portion, or none of the memory from erase and program commands. Protected areas become
read-only (see Table 7.1 on page 13). The Write Status Register command also allows the Status Register
Protect bit (SRP) to be set. This bit is used in conjunction with the Write Protect (WP#) pin to disable writes to
the status register. When the SRP bit is set to a 0 state (factory default) the WP# pin has no control over the
status register. When the SRP pin is set to a 1, the Write Status Register command is locked out while the
WP# pin is low. When the WP# pin is high the Write Status Register command is allowed.
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Figure 8.4 Write Status Register Command Sequence
CS #
0
Mode3
SCK M o d e 0
1
2
3
4
5
6
7
8
9
10 11
12 13
14 15
5
3
1
Mode3
Mode0
In stru ctio n ( 0 1H )
SI/IO0
7
6
4
2
0
*
High Im pedance
SO
*= M SB
8.5
Read Data (03h)
The Read Data command allows one more data bytes to be sequentially read from the memory. The
command is initiated by driving the CS# pin low and then shifting the instruction code “03h” followed by a
24-bit address (A23-A0) into the SI/IO0 pin. The code and address bits are latched on the rising edge of the
SCK pin. After the address is received, the data byte of the addressed memory location will be shifted out on
the SO pin at the falling edge of SCK with most significant bit (MSB) first. The address is automatically
incremented to the next higher address after each byte of data is shifted out allowing for a continuous stream
of data. This means that the entire memory can be accessed with a single command as long as the clock
continues. The command is completed by driving CS# high.
The Read Data command sequence is shown in Figure 8.5. If a Read Data command is issued while an
Erase, Program or Write cycle is in process (WIP=1) the command is ignored and will not have any effects on
the current cycle. The Read Data command allows clock rates from D.C. to a maximum of fR. See AC
Characteristics on page 31.
Figure 8.5 Read Data Command Sequence
CS #
SCK
Mode3
Mode0
0
1
2
3
4
5
6
7
8
9
Instruction (03 H)
SI/IO0
21
High Im pedance
31
32 33
34
35
36
37
38 39
3
2
1
0
Data O ut 1
7
6
5
4
3
Data O ut 2
2
1
0
7
*
*=M SB
8.6
28 29 30
24 -Bit Address
23 22
*
SO
10
Fast Read (0Bh)
The Fast Read command is similar to the Read Data command except that it can operate at higher frequency
than the traditional Read Data command. See AC Characteristics on page 31. This is accomplished by
adding eight “dummy” clocks after the 24-bit address as shown in Figure 8.6. The dummy clocks allow the
device’s internal circuits additional time for setting up the initial address. During the dummy clocks the data
value on the SI pin is a “don’t care”.
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Figure 8.6 Fast Read Command Sequence
CS#
SCK
M o d e3
M o d e0
0
1
2
3
4
5
7
6
9
8
Instruction (0BH)
28 29 30 31
10
24-Bit Address
23 22 21
SI/IO0
2
3
*
1
0
High Im pedance
SO
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 51 53 54 55
SCK
Dum m y Clocks
SI/IO0
7
6
5
4
3
2
1
0
Data O ut 1
SO
*=M SB
8.7
7
6
*
5
4
3
Data O ut 1
2
1
0
7
*
6
5
4
3
2
1
0
7
*
Fast Read Dual Output (3Bh)
The Fast Read Dual Output (3Bh) command is similar to the standard Fast Read (0Bh) command except that
data is output on two pins, SO and SI/IO0, instead of just SO. This allows data to be transferred from the
S25FL216K at twice the rate of standard SPI devices. The Fast Read Dual Output command is ideal for
quickly downloading code from the SPI flash to RAM upon power-up or for applications that cache codesegments to RAM for execution.
Similar to the Fast Read command, the Fast Read Dual Output command can operate at higher frequencies
than the traditional Read Data command. See AC Characteristics on page 31. This is accomplished by
adding eight “dummy” clocks after the 24-bit address as shown in Figure 8.7. The dummy clocks allow the
device's internal circuits additional time for setting up the initial address. The input data during the dummy
clocks is “don’t care”. However, the SI/IO0 pin should be high-impedance prior to the falling edge of the first
data out clock.
August 9, 2012 S25FL216K_00_07
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Figure 8.7 Fast Read Dual Output Command Sequence
CS#
SCK
Mode3
Mode0
0
1
2
3
4
5
6
7
Instruction (3BH )
SI/IO0
28 29 30 31
9 10
8
24-Bit Address
23 22 21
2
3
1
0
*
High Im pedance
SO
CS#
SCK
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 51 53 54 55
SI/IO 0 switches from input to output
Dum m y Clocks
SI/IO0
6
4
2
0
SO
7
5
3
1
*=M SB
8.8
*
D ata out 1
6
4
2 0
6
4
2
0
6
4
2 0
7
5
3
7
5
3
1
7
5
3
*
D ata out 2
1
*
D ata out 3
*
D ata out 4
1
6
7
*
Page Program (PP) (02h)
The Page Program command allows up to 256 bytes of data to be programmed at previously erased to all 1s
(FFh) memory locations. A Write Enable command must be executed before the device will accept the Page
Program command (Status Register bit WEL must equal 1). The command is initiated by driving the CS# pin
low then shifting the command code “02h” followed by a 24-bit address (A23-A0) and at least one data byte,
into the SI/IO0 pin. The CS# pin must be held low for the entire length of the command while data is being
sent to the device. The Page Program command sequence is shown in Figure 8.8.
If an entire 256 byte page is to be programmed, the last address byte (the 8 least significant address bits)
should be set to 0. If the last address byte is not zero, and the number of clocks exceed the remaining page
length, the addressing will wrap to the beginning of the page. In some cases, less than 256 bytes (a partial
page) can be programmed without having any effect on other bytes within the same page. One condition to
perform a partial page program is that the number of clocks can not exceed the remaining page length. If
more than 256 bytes are sent to the device the addressing will wrap to the beginning of the page and
overwrite previously sent data.
As with the write and erase commands, the CS# pin must be driven high after the eighth bit of the last byte
has been latched. If this is not done the Page Program command will not be executed. After CS# is driven
high, the self-timed Page Program command will commence for a time duration of tPP. See AC
Characteristics on page 31. While the Page Program cycle is in progress, the Read Status Register
command may still be accessed for checking the status of the WIP bit. The WIP bit is a 1 during the Page
Program cycle and becomes a 0 when the cycle is finished and the device is ready to accept other commands
again. After the Page Program cycle has finished the Write Enable Latch (WEL) bit in the Status Register is
cleared to 0. The Page Program command will not be executed if the addressed page is protected by the
Block Protect (BP3, BP2, BP1, and BP0) bits (see Table 7.1 on page 13).
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Figure 8.8 Page Program Command Sequence
CS #
SCK
0
Mode3
Mode0
1
2
3
4
5
7
6
9
8
Instruction (02 H )
28
10
29 30 31
32
33 34 35 36
24 -Bit Address
23
SI/IO0
22
21
3
37 38
39
2
0
Data Byte 1
2
1
0
*
7
6
5
4
3
1
*
High Im pedance
SO
Data Byte 2
SI/IO0
4
3
*
SO
2
50
51
52 53 54
55
6
Data Byte 256
5 4
2
3
Data Byte 3
1
0
7
6
5
4
*
3
2
1
0
7
2 079
48 49
2 07 8
5
47
46
2 07 7
6
45
20 76
7
43 44
2 07 5
41
2 074
41
2 073
40
SCK
2 07 2
CS #
1
0
Mode3
Mode0
*
High Im pedance
*=M SB
8.9
Sector Erase (SE) (20h)
The Sector Erase command sets all bits in the addressed 4-kB sector to 1 (all bytes are FFh). Before the
Sector Erase command can be accepted by the device, a Write Enable command must be issued and
decoded by the device, which sets the Write Enable Latch bit in the Status Register to enable any write
operations. The command is initiated by driving the CS# pin low and shifting the command code “20h”
followed by a 24-bit sector address (A23-A0). The Sector Erase command sequence is shown in Figure 8.9.
The CS# pin must be driven high after the eighth bit of the last byte has been latched. If this is not done the
Sector Erase command will not be executed. After CS# is driven high, the self-timed Sector Erase command
will commence for a time duration of tSE. See AC Characteristics on page 31. While the Sector Erase cycle is
in progress, the Read Status Register command may still be accessed for checking the status of the WIP bit.
The WIP bit is a 1 during the Sector Erase cycle and becomes a 0 when the cycle is finished and the device
is ready to accept other commands again. After the Sector Erase cycle has finished the Write Enable Latch
(WEL) bit in the Status Register is cleared to 0. The Sector Erase command will not be executed if the
addressed page is protected by the Block Protect (BP3, BP2, BP1, and BP0) bits (see Table 7.1 on page 13).
August 9, 2012 S25FL216K_00_07
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Figure 8.9 Sector Erase Command Sequence
CS#
M ode 3
SCK
0
1
2
3
4
5
6
7
8
9
29
30 31
M ode 3
M ode 0
M ode 0
In stru ctio n ( 2 0H )
2 4 - B it A d d re ss
23
SI/IO0
22
2
1
0
*
High Im pedance
SO
*=M SB
8.10
Block Erase (BE) (D8h)
The Block Erase command sets all bits in the addressed 64-kB block to 1 (all bytes are FFh). Before the BE
command can be accepted by the device, a Write Enable command must be issued and decoded by the
device, which sets the Write Enable Latch in the Status Register to enable any write operations. The
command is initiated by driving the CS# pin low and shifting the command code “D8h” followed a 24-bit block
address (A23-A0). The Block Erase command sequence is shown in Figure 8.10.
The CS# pin must be driven high after the eighth bit of the last byte has been latched. If this is not done the
Block Erase command will not be executed. After CS# is driven high, the self-timed Block Erase command
will commence for a time duration of tBE. See AC Characteristics on page 31. While the Block Erase cycle is
in progress, the Read Status Register command may still be accessed for checking the status of the WIP bit.
The WIP bit is a 1 during the Block Erase cycle and becomes a 0 when the cycle is finished and the device is
ready to accept other commands again. After the Block Erase cycle has finished the Write Enable Latch
(WEL) bit in the Status Register is cleared to 0. The Block Erase command will not be executed if the
addressed page is protected by the Block Protect (BP3, BP2, BP1, and BP0) bits (see Table 7.1 on page 13).
Figure 8.10 Block Erase Command Sequence
CS#
SCK
M ode 3
M ode 0
0
1
2
3
4
5
6
7
8
29
30 31
M ode 3
M ode 0
In stru ctio n (D8)
2 4 - B it A d d re ss
23
SI/IO0
SO
9
22
2
1
0
*
High Im pedance
*=M SB
8.11
Chip Erase (CE) (C7h)
The Chip Erase command sets all bits to 1 (all bytes are FFh) inside the entire flash memory array. Before the
CE command can be accepted by the device, a Write Enable command must be issued and decoded by the
device, which sets the Write Enable Latch in the Status Register to enable any write operations. The
command is initiated by driving the CS# pin low and shifting the command code “C7h”. The Chip Erase
command sequence is shown in Figure 8.11.
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The CS# pin must be driven high after the eighth bit has been latched. If this is not done the Chip Erase
command will not be executed. After CS# is driven high, the self-timed Chip Erase command will commence
for a time duration of tCE. See AC Characteristics on page 31. While the Chip Erase cycle is in progress, the
Read Status Register command may still be accessed to check the status of the WIP bit. The WIP bit is a 1
during the Chip Erase cycle and becomes a 0 when finished and the device is ready to accept other
commands again. After the Chip Erase cycle has finished the Write Enable Latch (WEL) bit in the Status
Register is cleared to 0. The Chip Erase command will not be executed if any page is protected by the Block
Protect (BP3,BP2, BP1, and BP0) bits (see Table 7.1 on page 13).
Figure 8.11 Chip Erase Command Sequence
CS #
M o d e3
SCK
0
1
2
3
4
5
6
7
M o d e3
M o d e0
M o d e0
Ins truc tion( C 7H )
SI/IO0
SO
8.12
H igh Im pedanc e
Deep Power-down (DP) (B9h)
The Deep Power-Down (DP) command provides the lowest power consumption mode of the device. It is
intended for periods when the device is not in active use, and ignores all commands except for the Release
from Deep Power-Down (RES) command. The lower power consumption makes the Deep Power-down
command especially useful for battery powered applications (See ICC1 and ICC2 in DC Characteristics
on page 30.) The command is initiated by driving the CS# pin low and shifting the command code “B9h” as
shown in Figure 8.12.
The CS# pin must be driven high after the eighth bit has been latched. If this is not done the Deep
Power-down command will not be executed. After CS# is driven high, the power-down state will enter within
the time duration of tDP (See AC Characteristics on page 31.) While in the power-down state only the Release
from Power-down / Device ID command, which restores the device to normal operation, will be recognized.
All other commands are ignored. This includes the Read Status Register command, which is always available
during normal operation. The Deep Power-down mode therefore provides the maximum data protection
against unintended write operations. Deep Power-down mode automatically terminates when power is
removed, and the device always powers up in the standard standby mode. The device rejects any Deep
Power-down command issued while it is executing a program, erase, or Write Registers operation, and
continues the operation uninterrupted.
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Figure 8.12 Deep Power-down Command Sequence
CS #
M ode 3
SCK
0
1
2
3
4
5
6
7
t DP
M ode 0
M ode 3
M ode 0
In stru ctio n (B 9 H)
SI/IO0
H ig h Im p e d a n ce
SO
S ta n d a rd C u rre n t
8.13
P o w e r-d o w n C u rre n t
Release Deep Power-down / Device ID (ABh)
The Release from Deep Power-down / Device ID command is a multi-purpose command. The device requires
the Release from Deep Power-down command to exit the Deep Power-down mode. When the device is in the
Deep Power-down mode, all commands except Release from Deep Power-down command are ignored. In
addition, the ABh command can also be used to read the device's 8-bit electronic Device ID.
When used only to release the device from the power-down state, the command is issued by driving the CS#
pin low, shifting the command code “ABh” and driving CS# high as shown in Figure 8.13. After the time
duration of tRES1 (See AC Characteristics on page 31.) the device will resume normal operation and other
commands will be accepted. The CS# pin must remain high during the tRES1 time duration.
When used only to obtain the Device ID while not in the Deep power-down state, the command is initiated by
driving the CS# pin low and shifting the command code “ABh” followed by 3-dummy bytes. The Device ID bits
are then shifted out on the falling edge of SCK with most significant bit (MSB) first as shown in Figure 8.14.
The Device ID value for the S25FL216K is listed in Manufacturer and Device Identification table. The Device
ID can be read continuously. The command is completed by driving CS# high.
When used to release the device from the Deep power-down state and obtain the Device ID, the command is
the same as previously described, and shown in Figure 8.14, except that after CS# is driven high it must
remain high for a time duration of tRES2 (See AC Characteristics on page 31.). After this time duration the
device will resume normal operation and other commands will be accepted. If the Release from Deep Powerdown / Device ID command is issued while an Erase, Program or Write cycle is in process (when WIP equals
1) the command is ignored and will not have any effects on the current cycle.
Figure 8.13 Release Deep Power-down Command
CS #
M ode 3
SCK
0
1
2
3
4
5
6
7
t RES 1
M ode 0
M ode 3
M ode 0
In stru ctio n (A B H)
SI/IO0
SO
H ig h Im p e d a n ce
Deep P o w e r-d o w n C u rre n t
H ig h P e rfo rm a n ce C u rre n t
24
S25FL216K
S ta n d- b y C u rre n t
S25FL216K_00_07 August 9, 2012
D a t a
S h e e t
( P r e l i m i n a r y)
Figure 8.14 Release Deep Power-down / Device ID Command Sequence
CS #
SCK
Mode3
Mode0
0
1
2
3
4
5
6
7
8
9
Instruction (ABH )
10
28
29 30
31 32
36
37
38
Mode3
Mode0
tR ES2
3 Dum m y Bytes
SI/IO0
23
SO
High Im pedance
*
22
21
3
2
1
0
Device ID **
7
*
6
5
4
3
2
Power down Current
High Perform ance M ode Current
*=M SB
8.14
33 34 35
1
0
Stand -by
Current
Read Manufacturer / Device ID (90h)
The Read Manufacturer/Device ID command is an alternative to the Release from Deep Power-down /Device
ID command that provides both the JEDEC assigned manufacturer ID and the specific device ID.
The Read Manufacturer/Device ID command is very similar to the Release from Deep Power-down / Device
ID command. The command is initiated by driving the CS# pin low and shifting the command code “90h”
followed by a 24-bit address (A23-A0) of 000000h. After which, the Manufacturer ID for Spansion (01h) and
the Device ID are shifted out on the falling edge of SCK with most significant bit (MSB) first as shown in
Figure 8.15. The Device ID values for the S25FL216K are listed in Table 8.2 on page 15. If the 24-bit address
is initially set to 000001h the Device ID will be read first, followed by the Manufacturer ID.
August 9, 2012 S25FL216K_00_07
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Figure 8.15 Read Manufacturer / Device ID Command Sequence
CS#
SCK
Mode3
Mode0
0
1
2
3
4
5
6
7
8
9
Instruction (90H)
SI/IO0
28 29 30 31
10
Address᧤000000H᧥
23 22 21
3
2
1
0
*
High Impedance
SO
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46
Mode3
Mode0
SCK
SI/IO0
Manufacturer ID
62
7
*
*=MSB
8.15
Device ID**
6
5
4
3
2
1
0
*
Read Identification (RDID) (9Fh)
For compatibility reasons, the S25FL216K provides several commands to electronically determine the identity
of the device. The Read JEDEC ID command is compatible with the JEDEC standard for SPI compatible
serial memories that was adopted in 2003.
The command is initiated by driving the CS# pin low and shifting the command code “9Fh”. The JEDEC
assigned Manufacturer ID byte for Spansion (01h) and two Device ID bytes, Memory Type (ID15-ID8) and
Capacity (ID7-ID0) are then shifted out on the falling edge of SCK with most significant bit (MSB) first as
shown in Figure 8.16. For memory type and capacity values refer to Table 8.2, Manufacturer and Device
Identification on page 15.
26
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Figure 8.16 Read JEDEC ID Command Sequence
CS #
SCK
0
Mode3
Mode0
1
2
3
4
5
7
6
8
9
10
11
12 13
14 15
Instruction (9FH )
SI/IO0
M anufacturer ID
High Im pedance
SO
7
*
6
5
4
3
2
1
0
CS #
16
17
18
19 20
21
22
23
24 25
26
27
28 29
30 31
SCK
Mode3
Mode0
SI/IO0
M e m o ry T yp e ID 1 5- ID 8
SO
*= M SB
August 9, 2012 S25FL216K_00_07
7
6
5
4
3
2
C a p a city ID 7 -ID 0
1
*
S25FL216K
0
7
*
6
5
4
3
2
1
0
27
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9. Electrical Specifications
9.1
Power-up Timing
Figure 9.1 Power-up Timing
V cc
V cc (m a x)
Program, E rase, and W rite Instruction are Ignored
C S # M ust T rack V cc
V cc (m in)
t VSL
R ead Instructions
A llow ed
D evice is F ully
A ccessible
Reset
Stast
VWI
tPUW
T im e
Table 9.1 Power-up Voltage and Timing
Type
Parameter
Symbol
Unit
Min
Max
VCC (min) to CS# Low
tVSL (1)
10
Time Delay Before Write Instruction
tPUW (1)
1
10
ms
Write Inhibit Threshold Voltage
VWI (1)
1
2
V
µs
Notes:
1. The parameters are characterized only.
2. VCC (max.) is 3.6V and VCC (min.) is 2.7V.
28
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9.2
S h e e t
( P r e l i m i n a r y)
Absolute Maximum Ratings
Stresses above the values so mentioned above may cause permanent damage to the device. These values
are for a stress rating only and do not imply that the device should be operated at conditions up to or above
these values.
Table 9.2 Absolute Maximum Ratings
Parameters
Symbol
Conditions
Range
Unit
Supply Voltage
VCC
-0.6 to +4.0
V
Voltage applied on any pin
VIO
Relative to Ground
-0.6 to VCC+0.4
V
Transient Voltage on any Pin
VIOT
<20 ns Transient Relative
to Ground
-2.0 to VCC+2.0
V
Storage Temperature
TSTG
-65 to +150
°C
Lead Temperature
TLEAD
(Note 2)
°C
Notes:
1. This device has been designed and tested for the specified operation ranges. Proper operation outside of these levels is not guaranteed.
Exposure to absolute maximum ratings may affect device reliability. Exposure beyond absolute maximum ratings may cause permanent
damage.
2. Compliant with JEDEC Standard J-STD-20C for small body Sn-Pb or Pb-free (Green) assembly and the European directive on
restrictions on hazardous substances (RoHS) 2002/95/EU.
9.3
Recommended Operating Ranges
Table 9.3 Recommended Operating Ranges
Spec
Parameter
Symbol
Conditions
Unit
Min
Max
Supply Voltage
VCC
FR = 65 MHz, fR = 44 MHz
2.7
3.6
V
Ambient Temperature, Operating
TA
Industrial
-40
+85
°C
Note:
1. Recommended Operating Ranges define those limits between which the functionality of the device is guaranteed.
August 9, 2012 S25FL216K_00_07
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29
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9.4
S h e e t
( P r e lim in a r y )
DC Characteristics
This section summarizes the DC Characteristics of the device. Designers should check that the operating
conditions in their circuit match the measurement conditions specified in the AC Measurement Conditions in
Table 9.6 on page 31, when relying on the quoted parameters.
Table 9.4 DC Characteristics
Symbol
(Notes)
Parameter
(Notes)
Spec
Conditions
(Notes)
Unit
Min
Typ
Max
CIN (1)
Input Capacitance
VIN = 0V (2)
6
pF
COUT (1)
Output Capacitance
VOUT = 0V (2)
8
pF
ILI
Input Leakage
±2
µA
ILO
I/O Leakage
±2
µA
ICC1
Standby Current
CS# = VCC, VIN = GND or
VCC
15
35
µA
ICC2
Power-down Current
CS# = VCC, VIN = GND or
VCC
15
32
µA
ICC3
Current Read Data / Dual Output Read
33 MHz (2)
C = 0.1 VCC / 0.9 VCC SO
= Open
10/12
15/18
mA
ICC3
Current Read Data / Dual Output Read
65 MHz (2)
C = 0.1 VCC / 0.9 VCC SO
= Open
25
mA
ICC4
Current Page Program
CS# = VCC
15
20
mA
ICC5
Current Write Status Register
CS# = VCC
10
18
mA
ICC6
Current Sector/Block Erase
CS# = VCC
20
25
mA
ICC7
Current Chip Erase
CS# = VCC
25
mA
VIL
Input Low Voltage
-0.5
VCC x 0.3
V
VIH
Input High Voltage
VCC x0.7
VCC +0.4
V
VOL
Output Low Voltage
IOL = 1.6 mA
VOH
Output High Voltage
IOH = -100 µA
20
0.4
V
VCC -0.2
V
Notes:
1. Tested on sample basis and specified through design and characterization data. TA=25°C, VCC 3V.
2. Checker Board Pattern.
9.5
AC Measurement Conditions
Table 9.5 AC Measurement Conditions
30
Symbol
Parameter
Max
Unit
CL
Load Capacitance
Min
30
pF
TR, TF
Input Rise and Fall Times
5
ns
VIN
Input Pulse Voltages
0.2 VCC to 0.8 VCC
V
VtIN
Input Timing Reference Voltages
0.3 VCC to 0.7 VCC
V
VtON
Output Timing Reference Voltages
0.5 VCC to 0.5 VCC
V
S25FL216K
S25FL216K_00_07 August 9, 2012
D a t a
S h e e t
( P r e l i m i n a r y)
Figure 9.2 AC Measurement I/O Waveform
Input and O utput
Tim ing Reference Levels
Input Levels
0.8 Vcc
0.7 Vcc
0.3 Vcc
0.2 Vcc
9.6
AC Characteristics
Table 9.6 AC Characteristics (Sheet 1 of 2)
Symbol
(Notes)
Alt
FR
fC
fR
tCLH, tCLL (1)
tCRLH, tCRLL (1)
Parameter
(Notes)
Spec
Unit
Min
Typ
Max
Clock frequency
For all instructions, except Read Data (03h)
D.C.
65
MHz
Clock freq. Read Data instruction (03h)
D.C.
44
MHz
Clock High, Low Time for all instructions except
Read Data (03h)
4
ns
Clock High, Low Time for Read Data (03h)
instruction
4
ns
tCLCH (2)
Clock Rise Time peak to peak
0.1
V/ns
tCHCL (2)
Clock Fall Time peak to peak
0.1
V/ns
CS# Active Setup Time relative to SCK
5
ns
CS# Not Active Hold Time relative to SCK
5
ns
tSLCH
tCSS
tCHSL
tDVCH
tDSU
Data In Setup Time
4
ns
tCHDX
tDH
Data In Hold Time
5
ns
tCHSH
CS# Active Hold Time relative to SCK
3
ns
tSHCH
CS# Not Active Setup Time relative to SCK
5
ns
tSHSL
tCSH
CS# Deselect Time (for Array Read 'Array Read /
Erase or Program ' Read Status Register)
50/100
ns
tSHQZ (2)
tDIS
Output Disable Time
tCLQV
tV
tCLQX
tHO
6
Clock Low to Output Valid
11
14
ns
ns
Output Hold Time
0
ns
ns
tHLCH
HOLD# Active Setup Time relative to SCK
5
tCHHH
HOLD# Active Hold Time relative to SCK
5
ns
tHHCH
HOLD# Not Active Setup Time relative to SCK
5
ns
HOLD# Not Active Hold Time relative to SCK
5
tCHHL
ns
tHHQX (2)
tLZ
HOLD# to Output Low-Z
7
ns
tHLQZ (2)
tHZ
HOLD# to Output High-Z
12
ns
tWHSL (3)
tSHWL (3)
tDP (2)
Write Protect Setup Time Before CS# Low
20
Write Protect Hold Time After CS# High
100
ns
ns
CS# High to Power-down Mode
3
µs
tRES1 (2)
CS# High to Standby Mode without Electronic
Signature Read
3
µs
tRES2 (2)
CS# High to Standby Mode with Electronic
Signature Read
1.8
µs
tW
Write Status Register Time
3
5
ms
tBP1
Byte Program Time (First Byte) (4)
30
50
µs
tBP2
Additional Byte Program Time (After First Byte) (4)
6
12
µs
tPP
Page Program Time
1.6
5
ms
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Table 9.6 AC Characteristics (Sheet 2 of 2)
Symbol
(Notes)
Spec
Parameter
(Notes)
Alt
Unit
Min
Typ
Max
tSE
Sector Erase Time (4 kB)
45
200
tBE (5)
Block Erase Time (64 kB)
0.45
1.5
ms
s
tCE (6)
Chip Erase Time
12
25
s
Notes:
1. Clock high + Clock low must be less than or equal to 1/fC.
2. Value guaranteed by design and/or characterization, not 100% tested in production.
3. Only applicable as a constraint for a Write Status Register instruction when Sector Protect Bit is set to 1.
4. For multiple bytes after first byte within a page, tBPN = tBP1 + tBP2 * N (typical) and tBPN = tBP1 + tBP2 * N (max), where N = number of
bytes programmed.
5. Max value shown is for less than 10k cycles. For greater than 10k cycles, max value is 4.0s.
6. Max value shown is for less than 10k cycles. For greater than 10k cycles, max value is 30s.
Figure 9.3 Serial Output Timing
CS#
tCH
SCK
t C LQ V
t C LQ V
t C LQ X
tCL
t SH QZ
t C LQ X
SO / SI(IO0)
LS B O ut
Note
t C LQ H
t C LQ L
Note: SI(IO0) is an O utput O NLY for the Fast Read Dual Output command (3Bh)
Figure 9.4 Input Timing
tSHSL
CS#
t S LC H
tCHSH
tCHSL
tSHCH
SCK
tDVCH
SI/IO0
SO
32
tCHCL
t C LC H
tCHDX
M S B IN
L S B IN
H ig h Im p e d a n ce
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Figure 9.5 Hold Timing
CS#
tCHHL
t H LC H
tHHCH
SCK
tCHHH
SI/IO0
t H LQ Z
tHHQH
SO
HO LD#
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10. Package Material
10.1
8-Pin SOIC 150-mil Package (SOA 008)
NOTES:
1.
ALL DIMENSIONS ARE IN BOTH INCHES AND MILLMETERS.
2.
DIMENSIONING AND TOLERANCING PER ASME Y14.5M - 1994.
3.
DIMENSION D DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH,
PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.15 mm
PER END. DIMENSION E1 DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 mm PER SIDE. D AND E1
DIMENSIONS ARE DETERMINED AT DATUM H.
4.
THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE
BOTTOM. DIMENSIONS D AND E1 ARE DETERMINED AT THE
OUTMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF
MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD
FLASH. BUT INCLUDING ANY MISMATCH BETWEEN THE TOP
AND BOTTOM OF THE PLASTIC BODY.
5.
DATUMS A AND B TO BE DETERMINED AT DATUM H.
6.
"N" IS THE MAXIMUM NUMBER OF TERMINAL POSITIONS FOR
THE SPECIFIED PACKAGE LENGTH.
7.
THE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD
BETWEEN 0.10 TO 0.25 mm FROM THE LEAD TIP.
8.
DIMENSION "b" DOES NOT INCLUDE DAMBAR PROTRUSION.
ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.10 mm TOTAL
IN EXCESS OF THE "b" DIMENSION AT MAXIMUM MATERIAL
CONDITION. THE DAMBAR CANNOT BE LOCATED ON THE
LOWER RADIUS OF THE LEAD FOOT.
9.
THIS CHAMFER FEATURE IS OPTIONAL. IF IT IS NOT PRESENT,
THEN A PIN 1 IDENTIFIER MUST BE LOCATED WITHIN THE INDEX
AREA INDICATED.
10.
LEAD COPLANARITY SHALL BE WITHIN 0.10 mm AS MEASURED
FROM THE SEATING PLANE.
g1019 \ 16-038.3f \ 10.06.11
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8-Pin SOIC 208-mil Package (SOC 008)
NOTES:
PACKAGE
SOC 008 (inches)
SOC 008 (mm)
JEDEC
SYMBOL
MIN
MAX
MIN
A
0.069
0.085
1.753
2.159
A1
0.002
0.0098
0.051
0.249
A2
0.067
0.075
1.70
1.91
b
0.014
0.019
0.356
0.483
b1
0.013
0.018
0.330
0.457
c
0.0075
0.0095
0.191
0.241
c1
0.006
0.008
0.152
0.203
0.208 BSC
5.283 BSC
E
0.315 BSC
8.001 BSC
0.208 BSC
e
.050 BSC
L
0.020
0.030
5.283 BSC
1.27 BSC
0.508
.049 REF
1.25 REF
L2
.010 BSC
0.25 BSC
8
3.
DIMENSION D DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH,
PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.15 mm
PER END. DIMENSION E1 DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 mm PER SIDE. D AND E1
DIMENSIONS ARE DETERMINED AT DATUM H.
4.
THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE
BOTTOM. DIMENSIONS D AND E1 ARE DETERMINED AT THE
OUTMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF
MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD
FLASH. BUT INCLUDING ANY MISMATCH BETWEEN THE TOP
AND BOTTOM OF THE PLASTIC BODY.
5.
DATUMS A AND B TO BE DETERMINED AT DATUM H.
6.
"N" IS THE MAXIMUM NUMBER OF TERMINAL POSITIONS FOR
THE SPECIFIED PACKAGE LENGTH.
7.
THE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD
BETWEEN 0.10 TO 0.25 mm FROM THE LEAD TIP.
8.
DIMENSION "b" DOES NOT INCLUDE DAMBAR PROTRUSION.
ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.10 mm TOTAL
IN EXCESS OF THE "b" DIMENSION AT MAXIMUM MATERIAL
CONDITION. THE DAMBAR CANNOT BE LOCATED ON THE
LOWER RADIUS OF THE LEAD FOOT.
9.
THIS CHAMFER FEATURE IS OPTIONAL. IF IT IS NOT PRESENT,
THEN A PIN 1 IDENTIFIER MUST BE LOCATED WITHIN THE INDEX
AREA INDICATED.
10.
LEAD COPLANARITY SHALL BE WITHIN 0.10 mm AS MEASURED
FROM THE SEATING PLANE.
8
θ
0˚
8˚
0˚
8˚
θ1
5˚
15˚
5˚
15˚
θ2
DIMENSIONING AND TOLERANCING PER ASME Y14.5M - 1994.
0.762
L1
N
ALL DIMENSIONS ARE IN BOTH INCHES AND MILLMETERS.
2.
MAX
D
E1
1.
0˚
0˚
3602 \ 16-038.03 \ 9.1.6
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11. Revision History
Section
Description
Revision 01 (October 7, 2011)
Initial release
Revision 02 (October 31, 2011)
Global
Removed USON package offering
Revision 03 (December 21, 2011)
DC Characteristics
Updated ICC2 values
Revision 04 (January 6, 2012)
Distinctive Features
Updated Standby Current value
Revision 05 (May 7, 2012)
Global
Promoted data sheet from Advance Information to Preliminary
Distinctive Features
Updated SPI clock frequencies: Fast Read and Dual Output Read
Updated Sector erase time
Recommended Operating Ranges
Updated Supply Voltage Conditions
DC Characteristics
DC Characteristics table: updated Max values for ICC1 and ICC2
AC Characteristics
AC Characteristics table: Updated Max values for FR, updated Max value for fR, updated values for
tCLQV, updated values for tW
Revision 06 (July 18, 2012)
AC Characteristics
AC Characteristics table: added note 5 and 6
Revision 07 (August 9, 2012)
Status Register
Changed status register bit R0 from ‘BUSY’ to ‘WIP’
Global
Changed ‘BUSY’ to ‘WIP’
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Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as
contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the
public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility,
aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for
any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to
you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor
devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design
measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal
operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under
the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country,
the prior authorization by the respective government entity will be required for export of those products.
Trademarks and Notice
The contents of this document are subject to change without notice. This document may contain information on a Spansion product under
development by Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this
document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose,
merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any
damages of any kind arising out of the use of the information in this document.
Copyright © 2011-2012 Spansion Inc. All rights reserved. Spansion®, the Spansion logo, MirrorBit®, MirrorBit® Eclipse™, ORNAND™ and
combinations thereof, are trademarks and registered trademarks of Spansion LLC in the United States and other countries. Other names used
are for informational purposes only and may be trademarks of their respective owners.
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