L9958
Low RDSON SPI controlled H-Bridge
Datasheet − production data
Features
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
Programmable current regulation peak
threshold by SPI up to 8.6 A typ.
Operating battery supply voltage 4.0 V to 28 V
Operating Vdd supply voltage 4.5 V to 5.5 V
All pins withstand 19 V, Vs and output pins
withstand 40 V
Full path Ron from 100 mΩ (at Tj = -40 °C) to
300 mΩ (at Tj =150 °C)
Logic inputs TTL/CMOS-compatible
Operating frequency up to 20 kHz
16-bit SPI interface for
configuration/diagnostics, daisy chain
capability
Over temperature and short circuit protection
VS undervoltage disable function
Vdd undervoltage and overvoltage protection
Vdd overvoltage detection
Open-load detection in ON condition
Full diagnostics in OFF state
Enable and disable input
Low stand by current (<10 µA)
Voltage and current slew-rate control for low
EMI, programmable through SPI
Available in three power packages
The L9958 is an SPI controlled H-Bridge,
designed for the control of DC and stepper motors
in safety critical applications and under extreme
environmental conditions.
The H-Bridge is protected against over
temperature, short circuits and has an
undervoltage lockout for all the supply voltages Vs
and Vdd, and for overvoltage on Vdd. All
malfunctions cause the output stages to go
tristate.
This is information on a product in full production.
*$3*36
*$3*36
PowerSO16
Detailed failure diagnostics on each channel is
provided via SPI: short circuit to battery, short
circuit to ground, short circuit overload, over
temperature.
Open-load can be detected in ON condition, for
the widest application ranges. Current regulation
threshold can be set by SPI from 2.5 A to 8.6 A
(Typ.), in 4 steps. Guaranteed accuracy is ±10 %
on all temp range, using an external reference
resistor with 1% accuracy over all temp range.
Current limitation threshold is linearly reduced by
temperature over 165 °C.and a thermal warning
bit is set by SPI. The H-Bridge contains integrated
free-wheel diodes. In case of free-wheeling
condition, the low side transistor is switched on in
parallel of its diode to reduce power dissipation.
A multiple wire bonding technique, as well as ST
proprietary package design is making L9958
compatible with three power packages, for
maximum flexibility:
PowerSO-20 package (medium power, JEDEC
standard MO166);
Description
September 2013
*$3*36
PowerSO-20 PowerSSO24
PowerSO16 package (medium power, lower
cost);
PowerSSO24 package (low power, very low cost
JEDEC standard MO271A).
Table 1.
Device summary
Order code
Package
Packing
L9958
PowerSO-20
Tube
L9958SB
PowerSO16
Tube
L9958XP
PowerSSO24
Tube
Doc ID 17269 Rev 5
1/38
www.st.com
1
Contents
L9958
Contents
1
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
Pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3
2.1
PowerSO-20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2
PowerSO16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3
PowerSSO24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1
Supply range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.2
Control inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.3
3.2.1
DI and EN inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.2.2
DIR and PWM inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.3.1
4
5
3.4
SPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.5
SPI communication failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.6
5 V and 3.3 V output compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Current regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.1
Temperature-dependent current regulation . . . . . . . . . . . . . . . . . . . . . . . 16
4.2
Current regulation with low-inductive loads . . . . . . . . . . . . . . . . . . . . . . . 17
4.3
Slew rate control in case of current limitation on low-side . . . . . . . . . . . . 17
Diagnostics and protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.1
5.2
2/38
Daisy chain operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Diagnosis reset strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.1.1
Reset requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.1.2
Diagnosis reset bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Protection and on state diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.2.1
Over-current on high-side - short to ground . . . . . . . . . . . . . . . . . . . . . . 20
5.2.2
Over-current on low-side - short to Vs . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.2.3
Short circuit over-load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.2.4
Open load in on state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.2.5
Over-temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Doc ID 17269 Rev 5
L9958
Contents
5.3
5.4
6
5.2.6
Vs under-voltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.2.7
Vdd over-voltage detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.2.8
Vdd under-voltage detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.2.9
Output short protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Off-state diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.3.1
Off-state detection scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.3.2
Open load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
H-Bridge functional status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.2
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.3
Range of functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.4
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.4.1
Device supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.4.2
Device supply monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.4.3
SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.4.4
Digital inputs: TTL // 3.3V / 5V CMOS compatible . . . . . . . . . . . . . . . . . 29
6.4.5
Bridge output drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.4.6
Over-temperature monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.4.7
Current limitation and over-current detection . . . . . . . . . . . . . . . . . . . . . 30
6.4.8
Diagnostic of open-load in on-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.4.9
Off-state diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.4.10
Timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7
Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
8
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
9
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Doc ID 17269 Rev 5
3/38
List of tables
L9958
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
4/38
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
PowerSO-20 pin function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
PowerSO16 pin function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
PowerSSO24 pin function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Control pins EN, DI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Control pins DIR, PWM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Configuration protocol (CFG_REG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Diagnosis protocol (DIA_REG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Current limitation programmability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Slew rate control on low side MOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Diagnosis reset strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Over-temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Vs under-voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Vdd over-voltage detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Range of functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Device supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Device supply monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Digital inputs: TTL // 3.3V / 5V CMOS compatible . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Bridge output drivers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Over-temperature monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Current limitation and over-current detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Diagnostic of open-load in on-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Off-state diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Doc ID 17269 Rev 5
L9958
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
PowerSO-20 pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
PowerSO16 pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
PowerSSO24 pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
H-Bridge configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
SPI protocol structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
FSI bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Daisy chain topology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
SPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
SPI zero clock communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Current limitation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Temperature dependent current regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Current regulation with different loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Slew rate switching strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Diagnostics for SCB / SCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Open load in on state - Low-side current recirculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Off-state detection scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Open load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Off-state diagnostic principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Thermal impedance (junction-ambient) of power packages . . . . . . . . . . . . . . . . . . . . . . . . 26
Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
PowerSO-20 mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . 34
PowerSO16 mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . 35
PowerSSO24 mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . 36
Doc ID 17269 Rev 5
5/38
Block diagram
L9958
1 Block diagram
Figure 1.
Block diagram
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6/38
Doc ID 17269 Rev 5
L9958
Pins description
2
Pins description
2.1
PowerSO-20
The exposed slug must be soldered on the PCB and connected to GND.
Table 2.
PowerSO-20 pin function
Pin N°
Name
1
GND
2
SO
3
VDDIO
4
CS
Chip select
5
CP
Charge pump
6
VS
Supply voltage
7
DIR
Direction input
8
OUT1
Output 1
9
DI
Disable
10
GND
Ground
11
GND
Ground
12
EN
Enable
13
OUT2
Output 2
14
PWM
PWM input
15
REXT
External reference resistor
16
SI
Serial in
17
SCK
SPI clock
18
VDD
Supply voltage
19
N.C.
Not connected (To be connected to GND on the PCB)
20
GND
Ground
Figure 2.
Description
Ground
Serial out
Supply voltage for SPI
PowerSO-20 pin connection (top view)
*1'
*1'
62
1&
9'',2
9''
&6
6&.
&3
6,
96
5(;7
',5
3:0
287
287
',
(1
*1'
*1'
*$3*36
Doc ID 17269 Rev 5
7/38
Pins description
2.2
L9958
PowerSO16
The exposed slug must be soldered on the PCB and connected to GND
Table 3.
PowerSO16 pin function
Pin Nº
Name
1
GND
2
SO
Serial Out
3
CS
Chip Select
4
CP
Charge pump
5
DIR
Direction Input
6
OUT1
Output 1
7
DI
Disable
8
PGND
9
EN
10
OUT2
Output 2
11
PWM
PWM Input
12
REXT
External Reference Resistor
13
VS
Supply Voltage
14
SI
Serial In
15
SCK
SPI Clock
16
VDD
Supply Voltage
Figure 3.
Description
Ground
Power Ground
Enable
PowerSO16 pin connection (top view)
*1'
9''
62
6&.
&6
6,
&3
96
',5
5(;7
287
3:0
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287
3*1'
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*$3*36
8/38
Doc ID 17269 Rev 5
L9958
2.3
Pins description
PowerSSO24
Although this package has two separate pins for the ground (pin11 = PGND = Power
Ground and pin22 = GND = Logic Ground), the device is designed to work with shortening
ground and is mandatory that the two pins have to be connected nearby the IC on the PCB.
The exposed slug must be soldered on the PCB and connected to GND.
Table 4.
PowerSSO24 pin function
Pin Nº
Name
1, 2, 12, 13,
14, 23, 24
N.C.
Not Connected
3
SO
Serial Out
4
VDDIO
5
CS
Chip Select
6
CP
Supply Voltage for SPI
7
VS
Supply Voltage
8
DIR
Direction Input
9
OUT1
Output 1
10
DI
Disable
11
PGND
15
EN
16
OUT2
Output 2
17
PWM
PWM Input
18
REXT
External Reference Resistor
19
SI
20
SCK
SPI Clock
21
VDD
Supply Voltage
22
GND
Ground
Figure 4.
Description
Supply Voltage for SPI
Power Ground
Enable
Serial In
PowerSSO24 pin connection (top view)
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Doc ID 17269 Rev 5
9/38
Device description
L9958
3
Device description
3.1
Supply range
The L9958 has an operating supply range from "Vs_uv" (battery monitoring) up to 28 V.
However, the device is tested until 16 V; the functionality of the device is guaranteed until
28 V. The absolute maximum rating is defined to 40 V DC.
3.2
Control inputs
The bridge is controlled by the Inputs PWM, DIR, EN and DI.
All the digital inputs and outputs of the L9958 are compatible with 3.3 V and 5 V CMOS. The
power stages output OUT1 and OUT2 are controlled by the direct inputs DIR and PWM as
given in Table 5. The DIR input gives the direction of output current, while the PWM input
controls whether the current is increased or reduced.
3.2.1
DI and EN inputs
The pin DI is internally pulled-up and high active. When DI is active (set to HIGH), the bridge
is set to tristate, whatever the state of the DIR and PWM inputs. All the data stored in SPI
registers are not reset and SPI communication with the MCU is still possible. When DI is
inactive (set to LOW), the bridge is controlled by the DIR and PWM inputs.
The pin EN is internally pulled down and high active. When EN is inactive (set to LOW), the
bridge is set to tri-state, whatever the state of the DIR and PWM inputs. All the data stored in
SPI registers are not reset and SPI communication with the MCU is still possible. When EN
is active (set to HIGH), the bridge is controlled by the DIR and PWM inputs. The coding is
performed as shown in the next table. The state of the bridge is transferred in the diagnostic
register in a bit called "ACT".
Table 5.
10/38
Control pins EN, DI
EN
DI
Bit “ACT”
Bridge status
0
0
0
Tri-state
0
1
0
Tri-state
1
0
1
On-state
1
1
0
Tri-state
Doc ID 17269 Rev 5
L9958
3.2.2
Device description
DIR and PWM inputs
The pins DIR and PWM are internally pulled down. The bridge is controlled by these two
inputs according to the table below.
Table 6.
Control pins DIR, PWM
DIR
PWM
OUT1
OUT2
Bridge Status
H
H
H
L
Forward
L
L
L
L
Freewheeling Low
L
H
L
H
Reverse
H
L
L
L
Freewheeling low
Figure 5.
H-Bridge configurations
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The outputs can be disabled (set to tri-state) by the Disable and Enable inputs DI and EN.
Input DI has an internal pull-up. Input EN has an internal pull-down. During freewheeling
phase, an active freewheeling on the Low-Side MOS is automatically set, switching ON the
power transistor in parallel to the internal freewheeling diode.
Doc ID 17269 Rev 5
11/38
Device description
3.3
L9958
Serial peripheral interface (SPI)
The SPI is used for bidirectional communication with a control unit, allowing IC
configuration, diagnosis and identification. L9958 can also be used in daisy-chain
configuration (number of device in the daisy chain is not limited).
The SPI interface of L9958 is a slave SPI interface: the master is the µC which provides CS
and SCK to L9958.
Transfer format uses 16 bits word in case of single device configuration and multiple of 16
bits word in case of daisy chain configuration.
The first answer after Power-ON-Reset is the IC identifier.
A command sent by the µC during transfer N is answered during transfer N+1. SO is
clocked on SCK rising edge. SI is sampled on falling edge. When CS = '1' and during powerON reset, SO is in tri-state. Otherwise, the SPI interface is always active.
Settings made by the SPI control word become active at the end of the SPI transmission
and remain valid until a different control word is transmitted or a power on reset occurs.
At each SPI transmission, the diagnosis bits as currently valid in the error logic are
transmitted. Details on diagnosis are described in Section 5.
Figure 6.
SPI protocol structure
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Between CS falling edge and SCK rising edge, an internal signal called "FSI bit" is set
asynchronously on SO output. This can be useful to have internal information on the device
without stimulating the SCK clock. The definition of the FSI bit is presented in the
diagnostics chapter.
Figure 7.
FSI bit
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Except the Enable / Disable bit (“ACT” pin), all the bits of diagnosis register are latched and
can be released by:
●
Diagnosis register read by SPI
●
Power-On-Reset condition.
The coding for the Configuration and Diagnosis Registers is reported in the table below.
12/38
Doc ID 17269 Rev 5
L9958
Device description
Table 7.
Table 8.
Configuration protocol (CFG_REG)
Bit
Name
0 - LSB
RES
1
DR
2
Config. value
after reset
Description
Reserved
—
Diagnostic Reset Bit
0
CL_1
Bit1 for Regulation Current Level
0
3
CL_2
Bit2 for Regulation Current Level
1
4
RES
Reserved
—
5
RES
Reserved
—
6
RES
Reserved
—
7
RES
Reserved
—
8
VSR
Voltage Slew Rate Control Value
0
9
ISR
Current Slew Rate Control Value
0
10
ISR_DIS
Current Slew Rate Control Disable
0
11
OL_ON
Open Load in ON state Enable
0
12
RES
Reserved
—
13
RES
Reserved
—
14
0
“0” to be written
—
15-MSB
0
“0” to be written
—
Diagnosis protocol (DIA_REG)
Bit
Name
Description
Status after
reset
Bit state
DR impact
H-bridge
status
0-LSB
OL_OFF
Open Load in OFF condition
0
Latched
–
–
1
OL_ON
Open Load in ON condition
0
Latched
–
–
2
VS_UV
Vs undervoltage
0
Not latched
–
Hi-Z if “1”
3
VDD_OV
Vdd overvoltage
0
Latched
X
Hi-Z if “1”
4
ILIM
5
TWARN
Current Limitation reached
0
Latched
–
–
Temperature warning
0
Latched
–
–
6
TSD
Over-temperature Shutdown
0
Latched
X
Hi-Z if “1”
7
ACT
Bridge enable
1
Not latched
–
Hi-Z if “0”
8
OC_LS1
Over-Current on Low Side 1
0
Latched
X
Hi-Z if “1”
9
OC_LS2
Over-Current on Low Side 2
0
Latched
X
Hi-Z if “1”
10
OC_HS1
Over-Current on High Side 1
0
Latched
X
Hi-Z if “1”
11
OC_HS2
Over-Current on High Side 2
0
Latched
X
Hi-Z if “1”
12
Null
Not Used
–
–
–
–
13
Null
Not Used
–
–
–
–
14
SGND_OFF
Short to GND in OFF condition
0
Latched
–
–
15-MSB
SBAT_OFF
Short to Battery in OFF condition
0
Latched
–
–
Doc ID 17269 Rev 5
13/38
Device description
3.3.1
L9958
Daisy chain operation
Several L9958 can be connected to one SPI connection in daisy chain operation to save µC
interface pins. The number of devices connected in daisy chain is unlimited.
Figure 8.
Daisy chain topology
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3.4
SPI timing
Figure 9.
SPI timing
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14/38
Doc ID 17269 Rev 5
L9958
3.5
Device description
SPI communication failure
In case of "no SCK edge" when CS = '0', the transfer is considered as valid: no error is
returned to the µC. The answer of last command is sent during next transfer.
When the number of SCK period is different from 0 or multiple of 16, next SPI answer is all
zero.
Figure 10. SPI zero clock communication
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3.6
5 V and 3.3 V output compatibility
In order to ensure a full compatibility with 5V and 3.3V MCU peripherals, the pin VDDIO is
dedicated to supply the output buffer of SO. The overall current consumption on Vddio is
"Ivddio". A parasitic current from the pin SO could flow through the pin VDDIO in case of
over-voltage on SO pin vs. VDDIO pin.
Doc ID 17269 Rev 5
15/38
Current regulation
4
L9958
Current regulation
To protect the actuator and limit power dissipation, a two-level chopper current limitation is
integrated as shown in figure below. The current is measured by sense cells integrated in
the low-side switches. As soon the upper current limit “IH” is reached, both low-side drivers
are switched on to allow free-wheeling recirculation, until the lower current limit “IL” is
reached. During the current regulation, all the slew rate controls are disabled in order to
minimize the power dissipation. Four current limit levels can be set by the SPI control bits 0
and 1. In order to achieve very precise current threshold and ripple, an external resistance is
required (1 % accuracy on all temp range/lifetime) to generate a current reference. Detailed
values for current thresholds and ripple are reported in Table 9.
Figure 11.
Current limitation
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Table 9.
4.1
Current limitation programmability
CL_2
CL_1
Current limit (typical values)
0
0
2.5 A
0
1
4A
1
0
6.6 A (default value)
1
1
8.6 A
Temperature-dependent current regulation
In order to reduce power dissipation and thus the junction temperature, above a
temperature Twarn = 160 °C, current regulation high limit linearly decreases with
temperature, to reach about 2.5 A at Tsd = 175 °C (shutdown temperature).
When this thermal threshold is reached during a current limitation phase, the information is
stored and latched in a coding of bits called "Twarn". This bit can be reset only if the settings
conditions (Tj > Twarn and ILIM = 0) are not present anymore. This feature is mainly used to
reduce the power dissipation and thus the junction temperature.
16/38
Doc ID 17269 Rev 5
L9958
Current regulation
Figure 12. Temperature dependent current regulation
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Current regulation with low-inductive loads
Each time output stages are turned off, an internal timing starts for duration Toff-min.
Whenever turn-on is reached in a time Toff that is shorter than Toff-min, output stages are
kept OFF, until Toff-min is reached.
In such case the ripple control could be not so precise as specified.
Figure 13. Current regulation with different loads
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4.3
Slew rate control in case of current limitation on low-side
The slew rate control can be done on voltage and current or only on voltage. This can be
selected by SPI through the bit ISR_DIS.
The slew rate of each high-side power transistor of the bridge is controlled either during
turn-on and turn-off (current AND voltage slew rate). The same setting is applied for both
switching. Moreover, this slew rate is configurable by SPI in order to get the best trade-off
between conducted/radiated EMI and power dissipation during switching. The slew rate
Doc ID 17269 Rev 5
17/38
Current regulation
L9958
selection can be done "on the fly" by SPI. The corresponding bits are called "VSR" and
"ISR". No external component is needed to select the slew rate range. Only the power
transistors not used for freewheeling can be adjusted, the two others can be controlled with
a preset slew rate.
The couples of value defined to fulfill most of the application requirements are described in
the table below. The required accuracy is ±50 % for an output current from 1A to 8A and
with output voltage up to 19 V. The overall delay implemented between high-side and lowside transistor switching must be adjusted automatically to avoid any cross-conduction
through one half-bridge in all conditions.
Table 10.
Slew rate control on low side MOS
Range
VSR
ISR
dV/dt (V/µs)
dI/dt (A/µs)
1 (default value)
0
0
4
3
2
0
1
4
0.3
3
1
0
2
3
4
1
1
2
0.3
14
14
No SR control
Not selectable
In case of current limitation and any detection that put the bridge in tri-state, the slew rate is
not related anymore to the preset bits "VSR"; "ISR" but to a dedicated faster slew rate
control named "SUPER FAST" mode. The automatic change from SPI selectable to SUPER
FAST slew rate is described hereafter.
Figure 14. Slew rate switching strategy
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18/38
Doc ID 17269 Rev 5
L9958
5
Diagnostics and protections
Diagnostics and protections
A detailed diagnostic of the H-bridge is available through SPI communication. The 16 bits
diagnostic word is sent back to the MCU in return of a command word. The diagnostic word
is used to report two kinds of information:
●
●
H-Bridge failures:
–
Over-current on each transistor in on-state,
–
Vps under-voltage,
–
Vdd over-voltage,
–
Over-temperature,
–
Open-load in on-state,
–
Off-state diagnostic.
H-bridge functional status:
–
Current limitation condition,
–
Current limitation decreasing condition,
–
Disable / Enable status.
5.1
Diagnosis reset strategy
5.1.1
Reset requests
Except "ACT" and "VS_UV" bits, all the others are latched and can only be released by:
●
Transition from "Disable" to "Enable" on DI / EN pins,
●
Diagnostic register read by SPI (see details on each failure release) depending on bit
"DR",
●
Power-On-Reset condition.
When the diagnostic register is reset, the bridge is switched back to normal mode driven by
DIR and PWM. All the settings are kept as before the failure. In case of SPI read, no
additional action on DI / EN is needed.
5.1.2
Diagnosis reset bit
In case of "DR" set to LOW (default value), all the bits of the diagnostic register can be reset
by the three possibilities described in previous section.
In case of "DR" set to HIGH, the over-current, Vdd over-voltage and over-temperature
diagnostic bits can NOT be reset by SPI read and therefore, the bridge is kept in tri-state
until a transition from "Disable" to "Enable" on DI/EN pins or Power-on-Reset condition.
Table 11.
DR
Diagnosis reset strategy
Diagnosis reset strategy
0
All diagnostic bits reset at each SPI reading (Default)
1
Over current bits (8..11) + Temp. shutdown TSD bit (6) + Vdd over voltage bit (3) NOT
reset by SPI
Doc ID 17269 Rev 5
19/38
Diagnostics and protections
5.2
L9958
Protection and on state diagnostics
L9958 is protected against short circuits, overload and invalid supply voltage by the
following measures.
5.2.1
Over-current on high-side - short to ground
The high-side switches are protected against a short of the output to ground by an overcurrent shutdown. If a high-side switch is turned on and the current rises above the short
circuit detection current Ioc all output transistors are turned off after a filter time Toc_ls and
the error bits "overcurrent on high side 1 (2)", OC_HS1 (OC_HS2) are stored in the internal
status register.
5.2.2
Over-current on low-side - short to Vs
Due to the chopper current regulation, the low-side switches are already protected against a
short to the supply voltage. To be able to distinguish a short circuit from normal current limit
operation, the current limitation is deactivated for the blanking time tb after the current has
exceeded the current limit threshold IH. If the short circuit detection current Ioc is reached
within this blanking time, a short circuit is detected. All output transistors are turned OFF
and the according error bit “Over-Current on Low Side 1 (2)”, OC_LS1 (OC_LS2) is set.
5.2.3
Short circuit over-load
If, during the Blanking time (tb) of the current regulation mode, the current reaches the Ioc
threshold; after a filtering time, the output MOS are switched OFF and the “Short circuit over
load” can be checked by the reading of the overcurrent bits of the DIA_REG (please refer to
Table 8 bit 8, 9,10 and 11).
Figure 15. Diagnostics for SCB / SCOL
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5.2.4
Open load in on state
To perform the Open Load diagnosis in ON state, the flag OL_ON has to be set high through
SPI. After every open load diagnosis in ON state, the OL_ON flag is resetted, to perform a
new open load diagnosis in ON state the OL_ON flag has to be set again.
20/38
Doc ID 17269 Rev 5
L9958
Diagnostics and protections
This disable the turning on of the low-side drivers during current recirculation. The current
flows through the body diode of the low-side MOS for a fixed time. At the end of this fixed
time the Vout voltage is sampled and the possible open load condition detected (see
Figure 16).
Figure 16. Open load in on state - Low-side current recirculation
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5.2.5
Over-temperature
When Twarn is reached, thermal current reduction is activated, and the information is stored
and latched. When Tsd is reached, the “TSD” bit is set and all output transistors are put in
tri-state conditions as long as a reset is applied.
Table 12.
Over-temperature
TSD
5.2.6
Comments
Bridge state
FSI
1
Tj > TSD
Tri-state-
1
0 (default)
Tj < TSD
-
0
Vs under-voltage shutdown
If the supply-voltage at the VS pins falls below the under-voltage detection threshold
Vs_uv_off, the outputs are set to tri-state and the error bit "Undervoltage at VS" is set.
A filtering time "Tuv_Vs" is implemented to avoid unwanted detection due to parasitic
glitches. The information is transferred into the SPI register in a bit called "VS_UV". This bit
is NOT latched. As soon as the voltage rises again above the Vs under-voltage threshold
(hysteresis implemented), the bridge is switched back to normal mode driven by DIR and
PWM. All the settings are kept as before the under-voltage event.
Doc ID 17269 Rev 5
21/38
Diagnostics and protections
L9958
Figure 17. Battery voltage monitoring
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Table 13.
5.2.7
Vs under-voltage
VS_UV
Comments
Bridge state
FSI
1
Vs < Vs_uv_off
Hi Z
1 (not latched)
0 (default)
Vs > Vs_uv_on
-
0
Vdd over-voltage detection
Although the Vdd input pin and all I/O's are able to withstand up to 19 V, an over-voltage
circuitry is implemented to ensure that the bridge is kept in tri-state when the Vdd voltage is
higher than the Vdd overvoltage threshold "Vdd_ov_off" for duration longer than
"Tov_Vdd". The information is detected and stored into the SPI register in a bit called
"VDD_OV". The bridge is kept in tri-state as long as an appropriate reset is not requested
(see Section 5.1).
Table 14.
5.2.8
Vdd over-voltage detection
VDD_OV
Comments
Bridge state
FSI
1
Vdd > Vdd_ov_off
Hi-Z
1 (latched)
0 (default)
Vdd < Vdd_ov_on
-
0
Vdd under-voltage detection
When the Vdd voltage falls below the under-voltage detection threshold "Vdd_uv_off" for
duration longer than "Tuv_vdd", the bridge is switched to tri-state. In such a condition, the
L9958 is going in sleep mode. When the voltage increases above the threshold (hysteresis
implemented), the L9958 starts with all the settings reset to their default values (Power On
Reset).
5.2.9
Output short protection
The L9958 can sustain short on the outputs. In case of short to GND, short to battery or
short between outputs the battery voltage cannot exceed 18 V. The connection of a 100 µF
decoupling capacitor as close as possible to Vs pin and the GND connection of the slug or of
the exposed pad is mandatory to improve the robustness.
22/38
Doc ID 17269 Rev 5
L9958
5.3
Diagnostics and protections
Off-state diagnosis
This diagnostic is performed in any off-state condition, just after ignition key-on or during an
off-state phase occurring after an on-state phase of the bridge.
5.3.1
Off-state detection scheme
In order to avoid any wrong diagnostic, a filtering time "Tdiag_off" is applied before
performing the detection if the bridge was in on-state before. This filtering time is not applied
in case of detection after key on.
Figure 18. Off-state detection scheme
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Open load detection
An equivalent resistor of 100 kΩ (typ.) is targeted for open-load detection.
In order to avoid any unwanted supply of the bridge through the high-side transistor body
diode during off-state measurement, the current source is connected only if Vs is higher
than the Vs under-voltage threshold.
Figure 19. Open load detection
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The diagnostic is based on a closed loop voltage control on OUT1 and associated current
measurement.
A voltage amplifier forces a constant voltage on OUT1 through two current sources (highside source and low-side current sink). The OUT2 is pulled-down through a constant current
sink. Based on the current flowing out of the amplifier (Ip – In) compared to several current
thresholds, open-load as well as short-circuit to ground and battery can be detected.
Doc ID 17269 Rev 5
23/38
Diagnostics and protections
L9958
Figure 20. Off-state diagnostic principle
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5.4
H-Bridge functional status
Three bits in the diagnosis register are used to give a feedback about the state of the HBridge. Status are Current Limitation (bit 4 "C_LIM"), Temperature Warning (bit 5 "T_WRN")
and Bridge Enable Status (bit 7 "ACT"). Those bits do not report a failure but only a
functional state of the H-bridge that could be useful to change the control strategy mainly in
term of power dissipation.
24/38
Doc ID 17269 Rev 5
L9958
Electrical specifications
6
Electrical specifications
6.1
Absolute maximum ratings
The component must withstand the overall following stimulus without any damage or latchup. Beyond these values, damage to the component may occur.
Table 15.
Symbol
Absolute maximum ratings
Parameter
Test condition
Min.
Max.
Unit
-1
-2
40
40
V
Vps
Supply voltage
Continuous
Transient (0.5 s; I ≤ 10 A)
Vdd
Logic supply voltage
0 V < Vps < 40 V
-0.3
19
V
Vddio
SDO supply voltage
0 V < Vps < 40 V
-0.3
19
V
Vi
Logic input voltage
0 V < Vps < 40 V
0 V < Vdd < 19 V
-0.3
19
V
Vo
Logic output voltage
0 V < Vps < 40 V
0 V < Vdd < 18.7V
-0.3
Vddio+0.3
V
±4
-
Output pins
(OUTx, VPS) ESD Compliance
EIA/JESD22-A114-B
Input pins
-
ISO 7637 pulses
Cf. standards
-
Latch-up immunity
Jedec standard
kV
±2
-
-
-
-
-100
+100
mA
Note:
In case of load dump condition, status of device outputs is kept unchanged.
6.2
Thermal data
Table 16.
Thermal data
Symbol
Parameter
Test condition
Min.
Max.
Failure condition
-40
OTsd
Lifetime
-40
150
Unit
Tj
Junction temperature
Tstg
Storage temperature
-
-55
150
°C
Tamb
Ambient temperature
0 V < Vps < 40 V
-40
125
°C
Package PowerSO-20
-
1
Package PowerSO16
-
1
Package PowerSSO24
-
2
Rthj-case
°C
Thermal resistance junction to
case(1)
°C/W
1. Guaranteed by design and package characterization.
Doc ID 17269 Rev 5
25/38
Electrical specifications
L9958
Figure 21. Thermal impedance (junction-ambient) of power packages
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6.3
Range of functionality
Within the range of functionality, all L9958 functionalities have to be guaranteed. All voltages
refers to GND. Currents are positive into and negative out of the specified pin.
Table 17.
Range of functionality
Pos.
Symbol
Parameter
FR1
Vps
FR2
dVps/dt
FR3
Vdd
FR4
Vi
FR5
Vddio
SDO output voltage
FR6
fspi
SPI clock frequency
Test condition
Min.
Typ.
Max.
Unit
Supply voltage
-
Vps_uv_off
14
28(1)
V
Supply voltage slew rate
-
-20
-
20
V/µs
Logic supply voltage
-
Vdd_uv_off
5
Vdd_ov_off
V
-0.3
-
Vdd_ov_off
V
-
3
-
5.5
V
-
-
-
5
MHz
Logic input voltage (SDI, See alsoTable 15:
SCLK, NCS, DI, EN, DIR, Absolute maximum
PWM)
ratings.
1. In load dump conditions Vps ranges between 28V and 40V. During load dump, status of device outputs is kept unchanged,
26/38
Doc ID 17269 Rev 5
L9958
Electrical specifications
6.4
Electrical characteristics
Tcase = -40 °C ... 125 °C unless otherwise specified,
Vdd = 4.5 V ... 5.5 V unless otherwise specified
Vps = 4 V ... 28 V unless otherwise specified
All voltages refer to Gnd. Currents are positive into and negative out of the specified pin.
6.4.1
Device supply
Table 18.
Device supply
Pos.
Symbol
1.1
Ips
1.2
Iout
1.3
Icc
Parameter
Power supply current
Leakage current on output
Logic-supply current
6.4.2
Device supply monitoring
Table 19.
Device supply monitoring
Pos.
Symbol
Test condition
Min.
Typ.
Max.
Unit
Vdd < 0.7 V; Vps = 16 V
from -40 °C to 25 °C
-
-
20
µA
Vdd < 0.7 V; Vps = 16 V
at 125 °C
-
-
35
µA
Fpwm = 0, Iout = 0
-
-
20
mA
Bridge in tri-state
-
-
100
µA
Vdd >Vdd_uv_on
FPWM = 0
-
-
5
mA
FPWM = 20 kHz
(Average value)
-
-
5
mA
Min.
Typ.
Max.
Unit
Parameter
Test condition
2.1
Vps_uv_off
Vps under-voltage threshold
Vps decreasing
-
-
4
V
2.2
Vps_uv_on
Vps under-voltage threshold
Vps increasing
-
-
4.5
V
2.3
Vps_uv_hyst
Vps under-voltage hysteresis
-
0.1
-
-
V
2.4
Tuv_vps
Vps under-voltage filtering time
Vps decreasing
1
-
3
µs
2.5
Vdd_uv_off
Vdd under-voltage threshold
Vdd decreasing
3
-
3.7
V
2.6
Vdd_uv_on
Vdd under-voltage threshold
Vdd increasing
3.3
-
4
V
2.7
Vdd_uv_hyst
Vdd under-voltage hysteresis
-
0.1
-
-
V
2.8
Tuv_Vdd
Vdd under-voltage filtering time Vdd decreasing
1
-
4
µs
2.9
Vdd_ov_off
Vdd over-voltage threshold
Vdd increasing
5.8
-
6.8
V
2.10 Vdd-ov_on
Vdd over-voltage threshold
Vdd decreasing
5.5
-
6.5
V
2.11
Vdd over-voltage hysteresis
-
0.1
-
-
V
Vdd over-voltage filtering time
Vdd increasing
60
100
140
µs
Vdd_ov_hyst
2.12 Tov_Vdd
Doc ID 17269 Rev 5
27/38
Electrical specifications
6.4.3
SPI
Table 20.
SPI
Pos.
Symbol
3.1
fspi
3.2
L9958
Parameter
Test condition
Clock frequency (50 % duty
cycle)
Tsdo_trans SDO transition speed, 20-80 %
Min.
Typ.
Max.
Unit
-
-
-
5
MHz
Vsdo = 5V, Cload = 50 pF (1)
5
-
30
ns
Vsdo = 5 V, Cload = 150 pF
5
-
50
ns
3.3
Tclh
Minimum time SCLK = HIGH
-
75
-
ns
3.4
Tcll
Minimum time SCLK = LOW
-
75
-
ns
3.5
Tpcld
Propagation delay (SCLK to
data at 10% of SDO rising edge)
-
-
40
ns
3.6
Tcsdv
NCS = LOW to data at SDO
active
-
-
-
85
ns
3.7
Tsclch
SCLK low before NCS low
(setup time SCLK to NCS
change H/L)
-
75
-
-
ns
3.8
Thclcl
SCLK change L/H after NCS =
low
-
75
-
-
ns
3.9
Tscld
SDI input setup time (SCLK
change H/L after SDI data valid)
40
-
-
ns
3.10
Thcld
SDI input hold time (SDI data
hold after SCLK change H/L)
-
40
-
-
ns
3.11
Tsclcl
SCLK low before NCS high
-
100
-
-
ns
3.12
Thclch
SCLK high after NCS high
-
100
-
-
ns
3.13
Tpchdz
NCS L/H to SDO @ high
impedance
-
-
-
75
ns
3.14
Tonncs
NCS min. high time
-
300
-
ns
-
Capacitance at SDI, SCLK; NCS -
-
-
14
pF
-
Capacitance at SDO
-
-
-
19
pF
3.15
3.16
Tfncs
NCS Filter time will be ignored)
Guaranteed by design
(Pulses = TfNCS
Guaranteed by design
10
-
40
ns
3.17
Vddio
Supply voltage for SDO output
buffer
-
3
-
5.5
V
3.18
Ivddio
Current consumption on Vddio
(2)
-
-
1
mA
3.19
sdo_H
High output level on SDO
Isdo = 1.5 mA
Vddio0.4
-
-
V
3.20
sdo_L
Low output level on SDO
Isdo = 2 mA
-
-
0.4
V
3.21
Isdo
Tri state leakage current
NCS = HIGH VDDIO = 5 V
-5
-
5
µA
1. Not tested – guaranteed by Cload = 150 pF measurement
2. Measured for PSO16 at wafer sort level only.
28/38
Doc ID 17269 Rev 5
L9958
Electrical specifications
6.4.4
Digital inputs: TTL // 3.3V / 5V CMOS compatible
Table 21.
Digital inputs: TTL // 3.3V / 5V CMOS compatible
Pos.
Symbol
4.1
Vih
Input voltage HIGH
4.2
Vil
4.3
4.4
4.5
Parameter
Test condition
Min.
Typ.
Max.
Unit
-
2
-
Vdd+0.3
V
Input voltage LOW
-
-0.3
-
0.8
V
Hysteresis of input voltage
-
200
-
-
mV
Vin = 0 V
-100
-
-30
-
-
5
30
-
100
-5
-
-
-
-
1.24
-
V
-
-
10
-
kΩ
Overall tolerance can
be taken as 3.5 %
-
1
-
%
Min.
Typ.
Max.
Unit
Tj = 150 °C, Iout = 3 A
4 V < Vps < 5 V
-
-
300
Tj = 150 °C, Iout = 3 A
Vps > 5 V
-
-
150
Tj = 150 °C, Iout = 3 A
4 V < Vps < 5 V
-
-
300
Tj = 150 °C, Iout = 3 A
Vps > 5 V
-
-
150
Iinl
Input current source for: DI /
NCS / SCLK / SDI
Iinh
Input current sink for: EN / DIR / Vin = 5 V
PWM
Vin = 0 V
Vin = 5 V No back
supply allowed
Vrext
External resistor
4.6
Rext
6.4.5
Bridge output drivers
Table 22.
Bridge output drivers
Pos.
5.1
5.2
Symbol
Rdson_h
Rdson_l
Parameter
Test condition
High-side transistor Rdson
Low-side transistor Rdson
µA
µA
mΩ
mΩ
5.3
Vbd_h
Body diode forward voltage
drop high-side transistor
Idiode = 3 A
-
1.2
2
V
5.4
Vbd_l
Body diode forward voltage
drop low-side transistor
Idiode = 3 A
-
1.2
2
V
Doc ID 17269 Rev 5
29/38
Electrical specifications
L9958
6.4.6
Over-temperature monitoring
Table 23.
Over-temperature monitoring
Pos.
Symbol
6.1
OTwarn
6.2
Parameter
Test condition
Min.
Typ.
Max.
Unit
Over-temperature warning
-
150
-
170
°C
OTsd
Over-temperature shut-down
-
170
-
200
°C
6.3
OThyst
Over-temperature hysteresis
-
10
-
-
°C
6.4
TTSD
Over-temperature filtering time
Guaranteed by clock
measurement
-
36
-
µs
Unit
6.4.7
Current limitation and over-current detection
Table 24.
Current limitation and over-current detection
Pos.
7.1
Symbol
Ilim_H
Parameter
Current limitation high
threshold
Test condition
Min.
Typ.
Max.
CL1:0 = 00; -40 °C ≤ Tj ≤ 150 °C
2
2.5
3.1
CL1:0 = 01; -40 °C ≤ Tj ≤ 150 °C
3.5
4
4.85
CL1:0 = 10; -40 °C ≤ Tj < 25 °C
5.5
6.75
8
CL1:0 = 10; 25 °C ≤ Tj ≤ 150 °C
5.5
6.6
7.7
CL1:0 = 11; -40 °C ≤ Tj < 25 °C
7.8
9.1
10.4
CL1:0 = 11; 25 °C ≤ Tj ≤ 150°C
7.6
8.6
9.6
2
2.5
3
Ilim_H0.5
Ilim_H0.8
CL1:0 = XX, Tj = OTsd
CL1:0 = 0X; -40 °C ≤ Tj ≤ 150 °C Ilim_H–0.2
7.2
Ilim_L
Current limitation low
threshold
CL1:0 = 10; -40°C ≤ Tj < 25 °C
Ilim_H–
0.35
Ilim_H- Ilim_H0.65
0.95
CL1:0 = 10; 25 °C ≤ Tj ≤ 150°C
Ilim_H–
0.35
Ilim_H- Ilim_H0.55
0.85
CL1:0 = 11; -40°C ≤ Tj < 25°C
Ilim_H–
0.4
Ilim_H- Ilim_H0.7
1
CL1:0 = 11; 25 °C ≤ Tj ≤ 150°C
Ilim_H–
0.4
Ilim_H- Ilim_H0.55
0.95
7.3
Tlimh
High current limitation
threshold filtering time
can be included in Tblanck
7.4
Tliml
Low current limitation
threshold filtering time
7.5
Toffmin
7.6
Tb
30/38
A
A
0.1
-
1
µs
-
1
-
3
µs
Current limitation delay
time
30
-
45
µs
Blanking time
4.9
-
8.7
µs
-
Doc ID 17269 Rev 5
L9958
Electrical specifications
Table 24.
Pos.
Current limitation and over-current detection (continued)
Symbol
Ioc_ls
Ioc-hs
7.7
Parameter
Low-side over-current
threshold
High-side over-current
threshold
Tracking
Test condition
Min.
Typ.
Max.
CL1:0 = 0X; -40 °C ≤ Tj ≤ 150 °C
5.5
7.7
9.9
CL1:0 = 1X; -40°C ≤ Tj < 25 °C
9.3
12
15
CL1:0 = 1X; 25 °C ≤ Tj ≤ 150°C
9.3
11.5
14
Ilim_h+2
-
-
Ilim_h+1.3
-
-
0.8
-
2.5
µs
Min.
Typ.
Max.
Unit
50
-
120
CL1:0 = 0X; CL1:0 = 10;
-40 °C ≤ Tj ≤ 150 °C
CL1:0 = 11; -40 °C ≤ Tj ≤ 150 °C
7.8
Toc_ls
Toc_hs
Low-side & high-side
over-current detection
filtering time
-
6.4.8
Diagnostic of open-load in on-state
Table 25.
Diagnostic of open-load in on-state
Pos.
Symbol
Parameter
Test condition
Tj = -40 °C (go-no-go
functional test)
8.1
8.2
Is_OL-on
Current source
Tj = 25 °C to 150 °C
(go-no-go functional
test)
Tmeas_on Detection time (settling time)
6.4.9
Off-state diagnostic
Table 26.
Off-state diagnostic
-
Pos.
Symbol
9.1
ROL
9.2
Tdiag_off
Delay time before enabling offstate diagnostic structure
Tdiag-off_1
used each time OUT
pins are released from
Off-state diag filtering time
Vps (after release of
when OUT 1 and/or 2 decrease
SCB, after Tdiag_off)
from Vps
Guaranteed through
SCAN
9.4
Tdiag_off_2
Off-state diagnostic filtering
time on failure detection
One symmetric filter for
each failure type (OL,
SCG, SCB) Guaranteed
through SCAN
9.5
Tclock
Oscillator frequency
-
9.3
Parameter
Test condition
Load detection threshold
diag after on-state
Guaranteed through
SCAN
Doc ID 17269 Rev 5
Unit
A
µA
50
-
100
-
3
5
µs
Min.
Typ.
Max.
Unit
10
60
200
kΩ
100
125
150
ms
2.4
3
3.6
ms
200
250
300
µs
4
-
6
MHz
31/38
Electrical specifications
L9958
6.4.10
Timing characteristics
Table 27.
Timing characteristics
Pos.
Symbol
10.1
fpwm
PWM frequency
Tdon
10.2
Parameter
Test condition
Min.
Typ.
Max.
Unit
-
-
-
20
kHz
Delay time for switch-on
Rload @ Iout = 3 A
PWM → 90% Vout (or
10 % Iout)
-
-
10
µs
Tdoff
Delay time for switch-off
Rload @ Iout = 3 A
PWM → 10 % Vout (or
90% Iout)
-
-
10
µs
ΔTd
Delay time: symmetry
PWM accuracy = 1% @
2kHz
-
-
5
µs
10.3
Td_dis
Disable delay time
DI / EN → 90% OUTx
@ Iout = 3 A
-
-
6
µs
10.4
Td_en
Enable delay time
DI / EN → 10 % OUT
-
-
6
µs
-
-
200
µs
1
-
3
µs
10.5
Td_pow
Power-on delay time
DIR= PWM=EN=1 /
DI=0 no load / VPS =
Vdd increasing
Vps = Vdd → 10 % Vout1
(= Vps)
10.6
Td_filter
DI / EN digital filter time
-
10.7
Trise_H
Low-side transistor rise time
Non selectable by SPI
0.04
-
0.2
µs
10.8
Tfall_H
Low-side transistor fall time
Non selectable by SPI
1
-
3
µs
7
14
24
2
4
6
1
2
3
1.5
3
4.5
0.15
0.3
0.45
35
-
55
10.9
10.10
10.11
32/38
dVout/dt
dIout/dt
Tdiag
Voltage slew rate for high-side super fast mode
transistors
VSR = 0
(Measurement is performed
between 30 % and 70 % of the
VSR = 1
slope)
Current slew rate for high-side ISR=0
transistors
(Measurement is performed
between 40 % and 60 % of the ISR=1
slope)
Timing for reliable diagnostic
Guaranteed through
SCAN pattern
Doc ID 17269 Rev 5
V/µs
A/µs
µs
L9958
7
Application circuit
Application circuit
Figure 22. Application circuit
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Package information
8
L9958
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Figure 23. PowerSO-20 mechanical data and package dimensions
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Doc ID 17269 Rev 5
L9958
Package information
Figure 24. PowerSO16 mechanical data and package dimensions
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Doc ID 17269 Rev 5
35/38
Package information
L9958
Figure 25. PowerSSO24 mechanical data and package dimensions
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Doc ID 17269 Rev 5
L9958
9
Revision history
Revision history
Table 28.
Document revision history
Date
Revision
Changes
16-Mar-2010
1
Initial release.
08-Apr-2011
2
Updated Table 27: Timing characteristics on page 32 (Pos. 10.8).
03-Aug-2011
3
Updated Table 17, Table 20, Table 24 and Table 27.
23-Mar-2012
4
Updated:
Table 17: Range of functionality;
Table 20: SPI.
19-Sep-2013
5
Updated disclaimer.
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