M93C86-125 M93C76-125 M93C66-125 M93C56-125 M93C46-125 Automotive 16-Kbit, 8-Kbit, 4-Kbit, 2-Kbit and 1-Kbit (8-bit or 16-bit wide) MICROWIRE serial EEPROM Datasheet − production data Features ■ Industry standard MICROWIRETM bus ■ Memory array: 1 Kb, 2Kb, 4Kb, 8 Kb or 16 Kb ■ Dual organization: by word (x16) or byte (x8) ■ Write – Byte within 5 ms – Word within 5 ms ■ READY/BUSY signal during programming ■ 2 MHz clock rate ■ Sequential read operation ■ Single supply voltage: 4.5 V to 5.5 V or 2.5 V to 5.5 V ■ Operating temperature range: -40°c up to 125°C ■ Enhanced ESD protection ■ More than 1 million Write cycles ■ More than 40-year data retention ■ Packages – SO8, TSSOP8 packages: RoHS-compliant and Halogen-free (ECOPACK2®) – PDIP8 package: RoHS-compliant (ECOPACK1®) March 2012 This is information on a product in full production. PDIP8 (BN) SO8 (MN) 150 mil width TSSOP8 (DW) 169 mil width Doc ID 022572 Rev 1 1/32 www.st.com 1 Contents M93C86-125 M93C76-125 M93C66-125 M93C56-125 M93C46-125 Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Connecting to the serial bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1 Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1.1 Operating supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1.2 Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1.3 Power-up and device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1.4 Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.1 Read Data from Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.2 Write Enable and Write Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.3 Erase Byte or Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.4 Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.5 Erase All . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.6 Write All . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6 READY/BUSY status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8 Common I/O operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 9 Clock pulse counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 10 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 11 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 12 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2/32 Doc ID 022572 Rev 1 M93C86-125 M93C76-125 M93C66-125 M93C56-125 M93C46-125 Contents 13 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Doc ID 022572 Rev 1 3/32 List of tables M93C86-125 M93C76-125 M93C66-125 M93C56-125 M93C46-125 List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. 4/32 Memory size versus organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Instruction set for the M93Cx6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Instruction set for the M93C46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Instruction set for the M93C56 and M93C66 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Instruction set for the M93C76 and M93C86 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Operating conditions (M93Cx6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Operating conditions (M93Cx6-W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 AC measurement conditions (M93Cx6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 AC measurement conditions (M93Cx6-W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 DC characteristics (M93Cx6, device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 DC characteristics (M93Cx6-W, device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 AC characteristics (M93Cx6, device grade 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 AC characteristics (M93Cx6-W, device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 PDIP8 – 8 lead plastic dual in-line package, 300 mils body width, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 SO8 narrow – 8 lead plastic small outline, 150 mils body width, package data . . . . . . . . . 28 TSSOP8 – 8 lead thin shrink small outline, package mechanical data. . . . . . . . . . . . . . . . 29 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Doc ID 022572 Rev 1 M93C86-125 M93C76-125 M93C66-125 M93C56-125 M93C46-125 List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 DIP, SO and TSSOP connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Bus master and memory devices on the serial bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 READ, WRITE, WEN, WDS sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 ERASE, ERAL sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 WRAL sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Write sequence with one clock glitch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 AC testing input output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Synchronous timing (start and op-code input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Synchronous timing (Read or Write). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Synchronous timing (Read or Write). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 PDIP8 – 8 lead plastic dual in-line package, 300 mils body width, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 SO8 narrow – 8 lead plastic small outline, 150 mils body width, package outline . . . . . . . 28 TSSOP8 – 8 lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . . 29 Doc ID 022572 Rev 1 5/32 Description 1 M93C86-125 M93C76-125 M93C66-125 M93C56-125 M93C46-125 Description The M93C46 (1 Kbit), M93C56 (2 Kbit), M93C66 (4 Kbit), M93C76 (8 Kbit) and M93C86 (16 Kbit) are Electrically Erasable PROgrammable Memory (EEPROM) devices accessed through the MICROWIRE bus protocol. The memory array can be configured either in bytes (x8b) or in words (x16b). The M93Cx6 devices operate within a voltage supply range from 4.5 V to 5.5 V, and the M93Cx6-W devices operate within a voltage supply range from 2.5 V to 5.5 V. The M93Cx6 devices are guaranteed over the -40°C/+125°C temperature range and are compliant with the Automotive standard AEC-Q100 Grade 1. Table 1. Memory size versus organization Device Number of bits Number of 8-bit bytes Number of 16-bit words M93C86 16384 2048 1024 M93C76 8192 1024 512 M93C66 4096 512 256 M93C56 2048 256 128 M93C46 1024 128 64 Figure 1. Logic diagram VCC D Q C M93Cx6 S ORG VSS AI01928 6/32 Doc ID 022572 Rev 1 M93C86-125 M93C76-125 M93C66-125 M93C56-125 M93C46-125 Table 2. Description Signal names Signal name Function Direction S Chip Select Input D Serial Data input Input Q Serial Data output Output C Serial Clock Input ORG Organization Select Input VCC Supply voltage VSS Ground The M93Cx6 is accessed by a set of instructions, as summarized in Table 3, and in more detail in Table 4: Instruction set for the M93C46 to Table 6: Instruction set for the M93C76 and M93C86). Table 3. Instruction set for the M93Cx6 Instruction Description Data READ Read Data from Memory Byte or Word WRITE Write Data to Memory Byte or Word WEN Write Enable WDS Write Disable ERASE Erase Byte or Word ERAL Erase All Memory WRAL Write All Memory with same Data Byte or Word A Read Data from Memory (READ) instruction loads the address of the first byte or word to be read in an internal address register. The data at this address is then clocked out serially. The address register is automatically incremented after the data is output and, if Chip Select Input (S) is held High, the M93Cx6 can output a sequential stream of data bytes or words. In this way, the memory can be read as a data stream from eight to 16384 bits long (in the case of the M93C86), or continuously (the address counter automatically rolls over to 00h when the highest address is reached). Programming is internally self-timed (the external clock signal on Serial Clock (C) may be stopped or left running after the start of a Write cycle) and does not require an Erase cycle prior to the Write instruction. The Write instruction writes 8 or 16 bits at a time into one of the byte or word locations of the M93Cx6. After the start of the programming cycle, a Busy/Ready signal is available on Serial Data Output (Q) when Chip Select Input (S) is driven High. An internal Power-on Data Protection mechanism in the M93Cx6 inhibits the device when the supply is too low. Doc ID 022572 Rev 1 7/32 Description M93C86-125 M93C76-125 M93C66-125 M93C56-125 M93C46-125 Figure 2. DIP, SO and TSSOP connections (top view) M93Cx6 S C D Q 1 2 3 4 8 7 6 5 VCC DU ORG VSS AI01929B 1. See Section 12: Package mechanical data for package dimensions, and how to identify pin-1. 2. DU = Don’t Use. The DU (do not use) pin does not contribute to the normal operation of the device. It is reserved for use by STMicroelectronics during test sequences. The pin may be left unconnected or may be connected to VCC or VSS. 8/32 Doc ID 022572 Rev 1 M93C86-125 M93C76-125 M93C66-125 M93C56-125 M93C46-125 2 Connecting to the serial bus Connecting to the serial bus Figure 3 shows an example of three memory devices connected to an MCU, on a serial bus. Only one device is selected at a time, so only one device drives the Serial Data output (Q) line at a time, the other devices are high impedance. The pull-down resistor R (represented in Figure 3) ensures that no device is selected if the bus master leaves the S line in the high impedance state. In applications where the bus master may be in a state where all inputs/outputs are high impedance at the same time (for example, if the bus master is reset during the transmission of an instruction), the clock line (C) must be connected to an external pull-down resistor so that, if all inputs/outputs become high impedance, the C line is pulled low (while the S line is pulled low): this ensures that C does not become high at the same time as S goes low, and so, that the tSLCH requirement is met. The typical value of R is 100 kΩ. Figure 3. Bus master and memory devices on the serial bus VSS VCC R SDO SDI SCK Bus master C Q D VCC C Q D VCC VSS R M93xxx memory device R C Q D VCC VSS M93xxx memory device R VSS M93xxx memory device CS3 CS2 CS1 S ORG S ORG S ORG AI14377b Doc ID 022572 Rev 1 9/32 Operating features M93C86-125 M93C76-125 M93C66-125 M93C56-125 M93C46-125 3 Operating features 3.1 Supply voltage (VCC) 3.1.1 Operating supply voltage (VCC) Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage within the specified [VCC(min), VCC(max)] range must be applied. In order to secure a stable DC supply voltage, it is recommended to decouple the VCC line with a suitable capacitor (usually of the order of 10 nF to 100 nF) close to the VCC/VSS package pins. This voltage must remain stable and valid until the end of the transmission of the instruction and, for a Write instruction, until the completion of the internal write cycle (tW). 3.1.2 Power-up conditions When the power supply is turned on, VCC rises from VSS to VCC. During this time, the Chip Select (S) line is not allowed to float and should be driven to VSS, it is therefore recommended to connect the S line to VSS via a suitable pull-down resistor. The VCC rise time must not vary faster than 1 V/µs. 3.1.3 Power-up and device reset In order to prevent inadvertent Write operations during power-up, a power on reset (POR) circuit is included. At power-up (continuous rise of VCC), the device does not respond to any instruction until VCC has reached the power on reset threshold voltage (this threshold is lower than the minimum VCC operating voltage defined in Operating conditions, in Section 11: DC and AC parameters). When VCC passes the POR threshold, the device is reset and is in the following state: 3.1.4 ● Standby Power mode ● deselected (assuming that there is a pull-down resistor on the S line) Power-down At power-down (continuous decrease in VCC), as soon as VCC drops from the normal operating voltage to below the power on reset threshold voltage, the device stops responding to any instruction sent to it. During power-down, the device must be deselected and in the Standby Power mode (that is, there should be no internal Write cycle in progress). 10/32 Doc ID 022572 Rev 1 M93C86-125 M93C76-125 M93C66-125 M93C56-125 M93C46-125 4 Memory organization Memory organization The M93Cx6 memory is organized either as bytes (x8) or as words (x16). If Organization Select (ORG) is left unconnected (or connected to VCC) the x16 organization is selected; when Organization Select (ORG) is connected to Ground (VSS) the x8 organization is selected. When the M93Cx6 is in Standby mode, Organization Select (ORG) should be set either to VSS or VCC for minimum power consumption. Any voltage between VSS and VCC applied to Organization Select (ORG) may increase the Standby current. Doc ID 022572 Rev 1 11/32 Instructions 5 M93C86-125 M93C76-125 M93C66-125 M93C56-125 M93C46-125 Instructions The instruction set of the M93Cx6 devices contains seven instructions, as summarized in Table 4 to Table 6. Each instruction consists of the following parts, as shown in Figure 4: READ, WRITE, WEN, WDS sequences: ● Each instruction is preceded by a rising edge on Chip Select Input (S) with Serial Clock (C) being held low. ● A start bit, which is the first ‘1’ read on Serial Data Input (D) during the rising edge of Serial Clock (C). ● Two op-code bits, read on Serial Data Input (D) during the rising edge of Serial Clock (C). (Some instructions also use the first two bits of the address to define the op-code). ● The address bits of the byte or word that is to be accessed. For the M93C46, the address is made up of 6 bits for the x16 organization or 7 bits for the x8 organization (see Table 4). For the M93C56 and M93C66, the address is made up of 8 bits for the x16 organization or 9 bits for the x8 organization (see Table 5). For the M93C76 and M93C86, the address is made up of 10 bits for the x16 organization or 11 bits for the x8 organization (see Table 6). The M93Cx6 devices are fabricated in CMOS technology and are therefore able to run as slow as 0 Hz (static input signals) or as fast as the maximum ratings specified in “AC characteristics” tables, in Section 11: DC and AC parameters. Table 4. Instruction set for the M93C46 x8 origination (ORG = 0) Instruction Description Start bit Opcode Address (1) Data READ Read Data from Memory 1 10 A6-A0 Q7-Q0 WRITE Write Data to Memory 1 01 A6-A0 D7-D0 WEN Write Enable 1 00 WDS Write Disable 1 ERASE Erase Byte or Word ERAL WRAL Required Address clock (1) cycles Data Required clock cycles A5-A0 Q15-Q0 18 A5-A0 D15-D0 11X XXXX 10 11 XXXX 9 00 00X XXXX 10 00 XXXX 9 1 11 A6-A0 10 A5-A0 9 Erase All Memory 1 00 10X XXXX 10 10 XXXX 9 Write All Memory with same Data 1 00 01X XXXX 18 01 XXXX D15-D0 25 D7-D0 1. X = Don't Care bit. 12/32 x16 origination (ORG = 1) Doc ID 022572 Rev 1 25 M93C86-125 M93C76-125 M93C66-125 M93C56-125 M93C46-125 Table 5. Instruction set for the M93C56 and M93C66 x8 origination (ORG = 0) Instruction Instructions Description Start Opbit code Address (1) (2) Data x16 origination (ORG = 1) Required Address (1) (3) clock cycles READ Read Data from Memory 1 10 A8-A0 Q7-Q0 WRITE Write Data to Memory 1 01 A8-A0 D7-D0 WEN Write Enable 1 00 WDS Write Disable 1 ERASE Erase Byte or Word ERAL WRAL Data Required clock cycles A7-A0 Q15-Q0 20 A7-A0 D15-D0 1 1XXX XXXX 12 11XX XXXX 11 00 0 0XXX XXXX 12 00XX XXXX 11 1 11 A8-A0 12 A7-A0 11 Erase All Memory 1 00 1 0XXX XXXX 12 10XX XXXX 11 Write All Memory with same Data 1 00 0 1XXX XXXX 20 01XX XXXX D7-D0 D15-D0 27 27 1. X = Don't Care bit. 2. Address bit A8 is not decoded by the M93C56. 3. Address bit A7 is not decoded by the M93C56. Table 6. Instruction set for the M93C76 and M93C86 x8 Origination (ORG = 0) Instruction Description Start Opbit code Address(1), (2) Data READ Read Data from Memory 1 10 A10-A0 Q7-Q0 WRITE Write Data to Memory 1 01 A10-A0 D7-D0 WEN Write Enable 1 00 WDS Write Disable 1 ERASE Erase Byte or Word ERAL WRAL x16 Origination (ORG = 1) Required Address clock (1) (3) cycles Data Required clock cycles A9-A0 Q15-Q0 22 A9-A0 D15-D0 11X XXXX XXXX 14 11 XXXX XXXX 13 00 00X XXXX XXXX 14 00 XXXX XXXX 13 1 11 A10-A0 14 A9-A0 13 Erase All Memory 1 00 10X XXXX XXXX 14 10 XXXX XXXX 13 Write All Memory with same Data 1 00 01X XXXX XXXX 22 01 XXXX D15-D0 XXXX 29 D7-D0 29 1. X = Don't Care bit. 2. Address bit A10 is not decoded by the M93C76. 3. Address bit A9 is not decoded by the M93C76. Doc ID 022572 Rev 1 13/32 Instructions 5.1 M93C86-125 M93C76-125 M93C66-125 M93C56-125 M93C46-125 Read Data from Memory The Read Data from Memory (READ) instruction outputs data on Serial Data Output (Q). When the instruction is received, the op-code and address are decoded, and the data from the memory is transferred to an output shift register. A dummy 0 bit is output first, followed by the 8-bit byte or 16-bit word, with the most significant bit first. Output data changes are triggered by the rising edge of Serial Clock (C). The M93Cx6 automatically increments the internal address register and clocks out the next byte (or word) as long as the Chip Select Input (S) is held High. In this case, the dummy 0 bit is not output between bytes (or words) and a continuous stream of data can be read. 5.2 Write Enable and Write Disable The Write Enable (WEN) instruction enables the future execution of erase or write instructions, and the Write Disable (WDS) instruction disables it. When power is first applied, the M93Cx6 initializes itself so that erase and write instructions are disabled. After an Write Enable (WEN) instruction has been executed, erasing and writing remains enabled until an Write Disable (WDS) instruction is executed, or until VCC falls below the power-on reset threshold voltage. To protect the memory contents from accidental corruption, it is advisable to issue the Write Disable (WDS) instruction after every write cycle. The Read Data from Memory (READ) instruction is not affected by the Write Enable (WEN) or Write Disable (WDS) instructions. 14/32 Doc ID 022572 Rev 1 M93C86-125 M93C76-125 M93C66-125 M93C56-125 M93C46-125 Figure 4. Read Instructions READ, WRITE, WEN, WDS sequences S D 1 1 0 An A0 Qn Q ADDR Q0 DATA OUT OP CODE Write S CHECK STATUS D 1 0 1 An A0 Dn D0 Q ADDR DATA IN BUSY READY OP CODE Write Enable S D Write Disable 1 0 0 1 1 Xn X0 S D OP CODE 1 0 0 0 0 Xn X0 OP CODE AI00878d 1. For the meanings of An, Xn, Qn and Dn, see Table 4, Table 5 and Table 6. 5.3 Erase Byte or Word The Erase Byte or Word (ERASE) instruction sets the bits of the addressed memory byte (or word) to 1. Once the address has been correctly decoded, the falling edge of the Chip Select Input (S) starts the self-timed Erase cycle. The completion of the cycle can be detected by monitoring the READY/BUSY line, as described in Section 6: READY/BUSY status. Doc ID 022572 Rev 1 15/32 Instructions 5.4 M93C86-125 M93C76-125 M93C66-125 M93C56-125 M93C46-125 Write For the Write Data to Memory (WRITE) instruction, 8 or 16 data bits follow the op-code and address bits. These form the byte or word that is to be written. As with the other bits, Serial Data Input (D) is sampled on the rising edge of Serial Clock (C). After the last data bit has been sampled, the Chip Select Input (S) must be taken low before the next rising edge of Serial Clock (C). If Chip Select Input (S) is brought low before or after this specific time frame, the self-timed programming cycle will not be started, and the addressed location will not be programmed. The completion of the cycle can be detected by monitoring the READY/BUSY line, as described later in this document. Once the Write cycle has been started, it is internally self-timed (the external clock signal on Serial Clock (C) may be stopped or left running after the start of a Write cycle). The cycle is automatically preceded by an Erase cycle, so it is unnecessary to execute an explicit erase instruction before a Write Data to Memory (WRITE) instruction. Figure 5. ERASE, ERAL sequences ERASE S CHECK STATUS D 1 1 1 An A0 Q ADDR BUSY READY OP CODE ERASE ALL S CHECK STATUS D 1 0 0 1 0 Xn X0 Q ADDR BUSY READY OP CODE AI00879B 1. For the meanings of An and Xn, please see Table 4, Table 5 and Table 6. 5.5 Erase All The Erase All Memory (ERAL) instruction erases the whole memory (all memory bits are set to 1). The format of the instruction requires that a dummy address be provided. The Erase cycle is conducted in the same way as the Erase instruction (ERASE). The completion of the cycle can be detected by monitoring the READY/BUSY line, as described in Section 6: READY/BUSY status. 16/32 Doc ID 022572 Rev 1 M93C86-125 M93C76-125 M93C66-125 M93C56-125 M93C46-125 5.6 Instructions Write All As with the Erase All Memory (ERAL) instruction, the format of the Write All Memory with same Data (WRAL) instruction requires that a dummy address be provided. As with the Write Data to Memory (WRITE) instruction, the format of the Write All Memory with same Data (WRAL) instruction requires that an 8-bit data byte, or 16-bit data word, be provided. This value is written to all the addresses of the memory device. The completion of the cycle can be detected by monitoring the READY/BUSY line, as described next. Figure 6. WRITE ALL WRAL sequence S CHECK STATUS D 1 0 0 0 1 Xn X0 Dn D0 Q ADDR DATA IN BUSY READY OP CODE AI00880C 1. For the meanings of Xn and Dn, please see Table 4, Table 5 and Table 6. Doc ID 022572 Rev 1 17/32 READY/BUSY status 6 M93C86-125 M93C76-125 M93C66-125 M93C56-125 M93C46-125 READY/BUSY status While the Write or Erase cycle is underway, for a WRITE, ERASE, WRAL or ERAL instruction, the Busy signal (Q=0) is returned whenever Chip Select input (S) is driven high. (Please note, though, that there is an initial delay, of tSLSH, before this status information becomes available). In this state, the M93Cx6 ignores any data on the bus. When the Write cycle is completed, and Chip Select Input (S) is driven high, the Ready signal (Q=1) indicates that the M93Cx6 is ready to receive the next instruction. Serial Data Output (Q) remains set to 1 until the Chip Select Input (S) is brought low or until a new start bit is decoded. 7 Initial delivery state The device is delivered with all bits in the memory array set to 1 (each byte contains FFh). 8 Common I/O operation Serial Data Output (Q) and Serial Data Input (D) can be connected together, through a current limiting resistor, to form a common, single-wire data bus. Some precautions must be taken when operating the memory in this way, mostly to prevent a short circuit current from flowing when the last address bit (A0) clashes with the first data bit on Serial Data Output (Q). Please see the application note AN394 for details. 18/32 Doc ID 022572 Rev 1 M93C86-125 M93C76-125 M93C66-125 M93C56-125 M93C46-125 9 Clock pulse counter Clock pulse counter In a noisy environment, the number of pulses received on Serial Clock (C) may be greater than the number delivered by the master (the microcontroller). This can lead to a misalignment of the instruction of one or more bits (as shown in Figure 7) and may lead to the writing of erroneous data at an erroneous address. To avoid this problem, the M93Cx6 has an on-chip counter that counts the clock pulses from the start bit until the falling edge of the Chip Select Input (S). If the number of clock pulses received is not the number expected, the WRITE, ERASE, ERAL or WRAL instruction is aborted, and the contents of the memory are not modified. The number of clock cycles expected for each instruction, and for each member of the M93Cx6 family, are summarized in Table 4: Instruction set for the M93C46 to Table 6: Instruction set for the M93C76 and M93C86. For example, a Write Data to Memory (WRITE) instruction on the M93C56 (or M93C66) expects 20 clock cycles (for the x8 organization) from the start bit to the falling edge of Chip Select Input (S). That is: 1 Start bit + 2 Op-code bits + 9 Address bits + 8 Data bits Figure 7. Write sequence with one clock glitch S C D An START "0" "1" An-1 An-2 Glitch WRITE D0 ADDRESS AND DATA ARE SHIFTED BY ONE BIT AI01395 Doc ID 022572 Rev 1 19/32 Maximum rating 10 M93C86-125 M93C76-125 M93C66-125 M93C56-125 M93C46-125 Maximum rating Stressing the device outside the ratings listed in the Absolute maximum ratings table may cause permanent damage to the device. These are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in the operating sections of this specification, is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 7. Absolute maximum ratings Symbol TSTG Parameter Min. Max. Unit Ambient operating temperature –40 130 °C Storage temperature –65 150 °C 260(1) PDIP TLEAD Lead temperature during soldering VOUT Output range (Q = VOH or Hi-Z) –0.50 VCC+0.5 V VIN Input range –0.50 VCC+1 V VCC Supply voltage –0.50 6.5 V 4000 V VESD other packages Electrostatic discharge voltage (human body model)(3) See note (2) °C 1. TLEAD max must not be applied for more than 10 s. 2. Compliant with JEDEC Std J-STD-020 (for small body, Sn-Pb or Pb assembly), the ST ECOPACK® 7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU. 3. Positive and negative pulses applied on pin pairs, according to the AEC-Q100-002 (compliant with JEDEC Std JESD22-A114, C1 = 100pF, R1 = 1500Ω, R2 = 500Ω). 20/32 Doc ID 022572 Rev 1 M93C86-125 M93C76-125 M93C66-125 M93C56-125 M93C46-125 11 DC and AC parameters DC and AC parameters This section summarizes the operating and measurement conditions, and the dc and ac characteristics of the device. The parameters in the dc and ac characteristic tables that follow are derived from tests performed under the measurement conditions summarized in the relevant tables. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. Table 8. Operating conditions (M93Cx6) Symbol VCC TA Table 9. Parameter Min. Max. Unit Supply voltage 4.5 5.5 V Ambient operating temperature –40 125 °C Min. Max. Unit Supply voltage 2.5 5.5 V Ambient operating temperature –40 125 °C Operating conditions (M93Cx6-W) Symbol VCC TA Table 10. Parameter AC measurement conditions (M93Cx6) Symbol CL Parameter Min. Load capacitance Max. 100 Input rise and fall times Input voltage levels Table 11. pF 50 ns 0.4 V to 2.4 V V Input timing reference voltages 1.0 V and 2.0 V V Output timing reference voltages 0.8 V and 2.0 V V AC measurement conditions (M93Cx6-W) Symbol CL Unit Parameter Load capacitance Min. Max. 100 Input rise and fall times Unit pF 50 ns Input voltage levels 0.2 VCC to 0.8 VCC V Input timing reference voltages 0.3 VCC to 0.7 VCC V Output timing reference voltages 0.3 VCC to 0.7 VCC V Doc ID 022572 Rev 1 21/32 DC and AC parameters Figure 8. M93C86-125 M93C76-125 M93C66-125 M93C56-125 M93C46-125 AC testing input output waveforms M93CXX 2.4V )NPUTVOLTAGELEVELS 0.4V 2V 6 1V 0.8V )NPUT /UTPUT -#887 0.8VCC 0.7VCC )NPUTVOLTAGELEVELS 0.3VCC 0.2VCC )NPUTANDOUTPUT TIMINGREFERENCELEVELS -36 Table 12. Capacitance Symbol Parameter COUT Output capacitance CIN Input capacitance Test condition(1) Min Max Unit VOUT = 0V 5 pF VIN = 0V 5 pF 1. Sampled only, not 100% tested, at TA = 25 °C and a frequency of 1 MHz. Table 13. Symbol DC characteristics (M93Cx6, device grade 3) Parameter Test condition Min. Max. Unit 0V ≤VIN ≤VCC ±2.5 µA 0V ≤VOUT ≤VCC, Q in Hi-Z ±2.5 µA ILI Input leakage current ILO Output leakage current ICC Supply current VCC = 5 V, S = VIH, f = 2 MHz, Q = open 2 mA ICC1 Supply current (Standby) VCC = 5 V, S = VSS, C = VSS, ORG = VSS or VCC, pin7 = VCC, VSS or Hi-Z 15 µA VIL(1) Input low voltage VCC = 5 V ± 10% –0.45 0.8 V VIH(1) Input high voltage VCC = 5 V ± 10% 2 VCC + 1 V VOL(1) Output low voltage VCC = 5 V, IOL = 2.1 mA 0.4 V VOH(1) Output high voltage VCC = 5 V, IOH = –400 µA 0.8 VCC 1. Please note that the input and output levels defined in this table are compatible with TTL logic levels and are NOT fully compatible with CMOS levels (as defined in Table 14). 22/32 Doc ID 022572 Rev 1 V M93C86-125 M93C76-125 M93C66-125 M93C56-125 M93C46-125 Table 14. Symbol DC characteristics (M93Cx6-W, device grade 3) Parameter Test condition ILI Input leakage current ILO Output leakage current ICC DC and AC parameters Supply current (CMOS inputs) Min. Max. Unit 0V ≤VIN ≤VCC ±2.5 µA 0V ≤VOUT ≤VCC, Q in Hi-Z ±2.5 µA VCC = 5 V, S = VIH, f = 2 MHz, Q = open 2 mA VCC = 2.5 V, S = VIH, f = 2 MHz, Q = open 1 mA VCC = 2.5 V, S = VSS, C = VSS, ORG = VSS or VCC, pin7 = VCC, VSS or Hi-Z 5 µA ICC1 Supply current (Standby) VIL Input low voltage (D, C, S) –0.45 0.2 VCC V VIH Input high voltage (D, C, S) 0.7 VCC VCC + 1 V V Output low voltage (Q) VCC = 5 V, IOL = 2.1 mA 0.4 VOL VCC = 2.5 V, IOL = 100 µA 0.2 V VOH Output high voltage (Q) VCC = 5 V, IOH = –400 µA 0.8 VCC V VCC = 2.5 V, IOH = –100 µA VCC–0.2 V Doc ID 022572 Rev 1 23/32 DC and AC parameters Table 15. M93C86-125 M93C76-125 M93C66-125 M93C56-125 M93C46-125 AC characteristics (M93Cx6, device grade 3) Test conditions specified in Table 8 and Table 10 Symbol Alt. fC fSK tSLCH tSHCH tSLSH(1) tCSS Parameter Clock frequency Min. Max. Unit D.C. 2 MHz Chip Select low to Clock high 50 ns Chip Select setup time M93C46, M93C56, M93C66 50 ns Chip Select setup time M93C76, M93C86 50 ns tCS Chip Select low to Chip Select high 200 ns tCHCL (2) tSKH Clock high time 200 ns tCLCH (2) tSKL Clock low time 200 ns tDVCH tDIS Data in setup time 50 ns tCHDX tDIH Data in hold time 50 ns tCLSH tSKS Clock setup time (relative to S) 50 ns tCLSL tCSH Chip Select hold time 0 ns tSHQV tSV Chip Select to READY/BUSY status 200 ns tSLQZ tDF Chip Select low to output Hi-Z 100 ns tCHQL tPD0 Delay to output low 200 ns tCHQV tPD1 Delay to output valid 200 ns tW tWP Erase or Write cycle time 5 ms 1. Chip Select Input (S) must be brought low for a minimum of tSLSH between consecutive instruction cycles. 2. tCHCL + tCLCH ≥ 1 / fC. 24/32 Doc ID 022572 Rev 1 M93C86-125 M93C76-125 M93C66-125 M93C56-125 M93C46-125 Table 16. DC and AC parameters AC characteristics (M93Cx6-W, device grade 3) Test conditions specified in Table 9 and Table 11 Symbol Alt. fC fSK tSLCH Parameter Clock frequency Min. Max. Unit D.C. 2 MHz Chip Select low to Clock high 50 ns tSHCH tCSS Chip Select set-up time 50 ns tSLSH(1) tCS Chip Select low to Chip Select high 200 ns tCHCL (2) tSKH Clock high time 200 ns tCLCH (2) tSKL Clock low time 200 ns tDVCH tDIS Data in set-up time 50 ns tCHDX tDIH Data in hold time 50 ns tCLSH tSKS Clock set-up time (relative to S) 50 ns tCLSL tCSH Chip Select hold time 0 ns tSHQV tSV Chip Select to READY/BUSY status 200 ns tSLQZ tDF Chip Select low to output Hi-Z 100 ns tCHQL tPD0 Delay to output low 200 ns tCHQV tPD1 Delay to output valid 200 ns tW tWP Erase or Write cycle time 5 ms 1. Chip Select Input (S) must be brought low for a minimum of tSLSH between consecutive instruction cycles. 2. tCHCL + tCLCH ≥ 1 / fC. Doc ID 022572 Rev 1 25/32 DC and AC parameters Figure 9. M93C86-125 M93C76-125 M93C66-125 M93C56-125 M93C46-125 Synchronous timing (start and op-code input) tCLSH tCHCL C tSHCH tCLCH S tDVCH D START tCHDX OP CODE START OP CODE OP CODE INPUT AI01428 Figure 10. Synchronous timing (Read or Write) C tCLSL S tDVCH tCHDX A0 An D tSLSH tCHQV tSLQZ tCHQL Hi-Z Q Q15/Q7 ADDRESS INPUT Q0 DATA OUTPUT AI00820C Figure 11. Synchronous timing (Read or Write) tSLCH C tCLSL S tDVCH An D tCHDX tSLSH A0/D0 tSHQV tSLQZ Hi-Z Q BUSY READY tW ADDRESS/DATA INPUT WRITE CYCLE AI01429 26/32 Doc ID 022572 Rev 1 M93C86-125 M93C76-125 M93C66-125 M93C56-125 M93C46-125 12 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers the M93Cxx devices in ECOPACK® packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at www.st.com. Figure 12. PDIP8 – 8 lead plastic dual in-line package, 300 mils body width, package outline E b2 A2 A1 b A L c e eA eB D 8 E1 1 PDIP-B 1. Drawing is not to scale. Table 17. PDIP8 – 8 lead plastic dual in-line package, 300 mils body width, package mechanical data inches(1) millimeters Symbol Typ. Min. A Max. Typ. Min. 5.33 A1 Max. 0.2098 0.38 0.015 A2 3.3 2.92 4.95 0.1299 0.115 0.1949 b 0.46 0.36 0.56 0.0181 0.0142 0.022 b2 1.52 1.14 1.78 0.0598 0.0449 0.0701 c 0.25 0.2 0.36 0.0098 0.0079 0.0142 D 9.27 9.02 10.16 0.365 0.3551 0.4 E 7.87 7.62 8.26 0.3098 0.3 0.3252 E1 6.35 6.1 7.11 0.25 0.2402 0.2799 e 2.54 - - 0.1 - - eA 7.62 - - 0.3 - - eB L 10.92 3.3 2.92 3.81 0.4299 0.1299 0.115 0.15 1. Values in inches are converted from mm and rounded to 4 decimal digits. Doc ID 022572 Rev 1 27/32 Package mechanical data M93C86-125 M93C76-125 M93C66-125 M93C56-125 M93C46-125 Figure 13. SO8 narrow – 8 lead plastic small outline, 150 mils body width, package outline h x 45˚ A2 A c ccc b e 0.25 mm GAUGE PLANE D k 8 E1 E 1 L A1 L1 SO-A 1. Drawing is not to scale. Table 18. SO8 narrow – 8 lead plastic small outline, 150 mils body width, package data inches(1) millimeters Symbol Typ Min A Max Typ 1.75 Max 0.0689 A1 0.1 A2 1.25 b 0.28 0.48 0.011 0.0189 c 0.17 0.23 0.0067 0.0091 ccc 0.25 0.0039 0.0098 0.0492 0.1 0.0039 D 4.9 4.8 5 0.1929 0.189 0.1969 E 6 5.8 6.2 0.2362 0.2283 0.2441 E1 3.9 3.8 4 0.1535 0.1496 0.1575 e 1.27 - - 0.05 - - h 0.25 0.5 0.0098 0.0197 k 0° 8° 0° 8° L 0.4 1.27 0.0157 0.05 L1 1.04 0.0409 1. Values in inches are converted from mm and rounded to 4 decimal digits. 28/32 Min Doc ID 022572 Rev 1 M93C86-125 M93C76-125 M93C66-125 M93C56-125 M93C46-125 Package mechanical data Figure 14. TSSOP8 – 8 lead thin shrink small outline, package outline D 8 5 c E1 1 E 4 α A1 A L A2 L1 CP b e TSSOP8AM 1. Drawing is not to scale. Table 19. TSSOP8 – 8 lead thin shrink small outline, package mechanical data inches(1) millimeters Symbol Typ. Min. A Max. Min. 1.2 A1 0.05 0.15 0.8 1.05 b 0.19 c 0.09 A2 Typ. 1 CP Max. 0.0472 0.002 0.0059 0.0315 0.0413 0.3 0.0075 0.0118 0.2 0.0035 0.0079 0.0394 0.1 0.0039 D 3 2.9 3.1 0.1181 0.1142 0.122 e 0.65 - - 0.0256 - - E 6.4 6.2 6.6 0.252 0.2441 0.2598 E1 4.4 4.3 4.5 0.1732 0.1693 0.1772 L 0.6 0.45 0.75 0.0236 0.0177 0.0295 L1 1 0° 8° 0.0394 α 0° N (pin number) 8 8° 8 1. Values in inches are converted from mm and rounded to 4 decimal digits. Doc ID 022572 Rev 1 29/32 Part numbering 13 M93C86-125 M93C76-125 M93C66-125 M93C56-125 M93C46-125 Part numbering Table 20. Ordering information scheme Example: M93C86 – W MN 3 T P /S Device type M93 = MICROWIRE serial EEPROM Device function 86 = 16 Kbit (2048 x 8) 76 = 8 Kbit (1024 x 8) 66 = 4 Kbit (512 x 8) 56 = 2 Kbit (256 x 8) 46 = 1 Kbit (128 x 8) Operating voltage blank = VCC = 4.5 to 5.5 V W = VCC = 2.5 to 5.5 V Package BN = PDIP8 MN = SO8 (150 mils width) DW = TSSOP8 (169 mils width) Device grade 3 = Device tested with high reliability certified flow. Automotive temperature range (–40 to 125 °C) Packing blank = standard packing T = tape and reel packing Plating technology P or G = ECOPACK® (RoHS compliant) Process /S = Manufacturing technology code For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST sales office. 30/32 Doc ID 022572 Rev 1 M93C86-125 M93C76-125 M93C66-125 M93C56-125 M93C46-125 14 Revision history Revision history Table 21. Document revision history Date Revision 14-Mar-2012 1 Changes Initial release. Doc ID 022572 Rev 1 31/32 M93C86-125 M93C76-125 M93C66-125 M93C56-125 M93C46-125 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. 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