Data Sheet - STMicroelectronics

M24C32-125
Automotive 32-Kbit serial I²C bus EEPROM
Features
■
Compatible with all I2C bus modes:
– 400 kHz Fast mode
– 100 kHz Standard mode
■
Memory array:
– 32 Kbit (4 Kbytes) of EEPROM
– Page size: 32 bytes
TSSOP8 (DW)
169 mil width
■
Write
– Byte Write within 5 ms
– Page Write within 5 ms
■
Single supply voltage: 2.5 V to 5.5 V
■
Operating temperature range: from -40 °C up
to +125 °C
■
Random and sequential Read modes
■
Write protect of the whole memory array
■
Enhanced ESD/Latch-Up protection
■
More than 1 million Write cycles
■
More than 40-year data retention
■
Packages
– RoHS compliant and halogen-free
(ECOPACK®)
February 2012
Doc ID 022638 Rev 1
SO8 (MN)
150 mil width
1/29
www.st.com
1
Contents
M24C32-125
Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1
Serial Clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2
Serial Data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.3
Chip Enable (E2, E1, E0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.4
Write Control (WC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.5
VSS (ground) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.6
Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.6.1
2.6.2
Operating supply voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.6.3
Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.6.4
Power-down conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3
Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4
Device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5
4.1
Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.2
Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.3
Acknowledge bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.4
Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.5
Memory addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.1
5.2
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Write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.1.1
Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.1.2
Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.1.3
Minimizing Write delays by polling on ACK . . . . . . . . . . . . . . . . . . . . . . 16
Read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.2.1
Random Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.2.2
Current Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.2.3
Sequential Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.2.4
Acknowledge in Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
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M24C32-125
Contents
6
Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
8
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
9
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
10
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
11
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
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List of tables
M24C32-125
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
4/29
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Most significant address byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Least significant address byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Operating conditions (voltage range W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Input parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Memory cell characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
DC characteristics (M24C32-W, device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
400 kHz AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
TSSOP8 – 8-lead thin shrink small outline, package mechanical data. . . . . . . . . . . . . . . . 25
SO8N – 8 lead plastic small outline, 150 mils body width, package data . . . . . . . . . . . . . . 26
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Doc ID 022638 Rev 1
M24C32-125
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
8-pin package connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Write mode sequences with WC = 0 (data write enabled) . . . . . . . . . . . . . . . . . . . . . . . . . 14
Write mode sequences with WC = 1 (data write inhibited) . . . . . . . . . . . . . . . . . . . . . . . . . 15
Write cycle polling flowchart using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Read mode sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Maximum Rbus value versus bus parasitic capacitance (Cbus) for
an I2C bus at maximum frequency fC = 400 kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
TSSOP8 – 8-lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . . 25
SO8N – 8 lead plastic small outline, 150 mils body width, package outline . . . . . . . . . . . . 26
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Description
1
M24C32-125
Description
The M24C32 is a 32-Kbit I2C-compatible EEPROM (Electrically Erasable PROgrammable
Memory) organized as 4 K × 8 bits.
This I2C EEPROM can operate with a supply voltage from 2.5 V up to 5.5 V over an ambient
temperature range of -40 °C / 125 °C.
The device is compliant with the Automotive standard AEC-Q100 grade 1.
Figure 1.
Logic diagram
6##
%%
3$!
-XXX
3#,
7#
633
Table 1.
!)F
Signal names
Signal name
Function
Direction
E2, E1, E0
Chip Enable
Input
SDA
Serial Data
I/O
SCL
Serial Clock
Input
WC
Write Control
Input
VCC
Supply voltage
VSS
Ground
Figure 2.
8-pin package connections
%
%
%
633
6##
7#
3#,
3$!
!)F
1. See Section 9: Package mechanical data for package dimensions, and how to identify pin 1.
6/29
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M24C32-125
Signal description
2
Signal description
2.1
Serial Clock (SCL)
This input signal is used to strobe all data in and out of the device. In applications where this
signal is used by slave devices to synchronize the bus to a slower clock, the bus master
must have an open drain output, and a pull-up resistor must be connected from Serial Clock
(SCL) to VCC. (Figure 11 indicates how to calculate the value of the pull-up resistor). In most
applications, though, this method of synchronization is not employed, and so the pull-up
resistor is not necessary, provided that the bus master has a push-pull (rather than open
drain) output.
2.2
Serial Data (SDA)
This bidirectional signal is used to transfer data in or out of the device. It is an open drain
output that may be wire-OR’ed with other open drain or open collector signals on the bus. A
pull up resistor must be connected from Serial Data (SDA) to VCC. (Figure 11 indicates how
to calculate the value of the pull-up resistor).
2.3
Chip Enable (E2, E1, E0)
(E2,E1,E0) input signals are used to set the value that is to be looked for on the three least
significant bits (b3, b2, b1) of the 7-bit device select code (see Table 2). These inputs must
be tied to VCC or VSS, as shown in Figure 3. When not connected (left floating), these inputs
are read as low (0).
Figure 3.
Device select code
VCC
VCC
M24xxx
M24xxx
Ei
Ei
VSS
VSS
Ai12806
2.4
Write Control (WC)
This input signal is useful for protecting the entire contents of the memory from inadvertent
write operations. Write operations are disabled to the entire memory array when Write
Control (WC) is driven high. Write operations are enabled when Write Control (WC) is either
driven low or left floating.
When Write Control (WC) is driven high, device select and address bytes are
acknowledged, Data bytes are not acknowledged.
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Signal description
2.5
M24C32-125
VSS (ground)
VSS is the reference for the VCC supply voltage.
2.6
Supply voltage (VCC)
2.6.1
Operating supply voltage VCC
Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage
within the specified [VCC(min), VCC(max)] range must be applied (see Operating conditions
in Section 8: DC and AC parameters). In order to secure a stable DC supply voltage, it is
recommended to decouple the VCC line with a suitable capacitor (usually of the order of 10
nF to 100 nF) close to the VCC/VSS package pins.
This voltage must remain stable and valid until the end of the transmission of the instruction
and, for a write instruction, until the completion of the internal write cycle (tW).
2.6.2
Power-up conditions
The VCC voltage has to rise continuously from 0 V up to the minimum VCC operating voltage
(see Operating conditions in Section 8: DC and AC parameters) and the rise time must not
vary faster than 1 V/µs.
2.6.3
Device reset
In order to prevent inadvertent write operations during power-up, a power-on-reset (POR)
circuit is included.
At power-up, the device does not respond to any instruction until VCC has reached the
internal reset threshold voltage. This threshold is lower than the minimum VCC operating
voltage (see Operating conditions in Section 8: DC and AC parameters). When VCC passes
over the POR threshold, the device is reset and enters the Standby Power mode; however,
the device must not be accessed until VCC reaches a valid and stable DC voltage within the
specified [VCC(min), VCC(max)] range (see Operating conditions in Section 8: DC and AC
parameters).
In a similar way, during power-down (continuous decrease in VCC), the device must not be
accessed when VCC drops below VCC(min). When VCC drops below the power-on-reset
threshold voltage, the device stops responding to any instruction sent to it.
2.6.4
Power-down conditions
During power-down (continuous decrease in VCC), the device must be in the Standby Power
mode (mode reached after decoding a Stop condition, assuming that is there is no internal
write cycle in progress).
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Doc ID 022638 Rev 1
M24C32-125
Memory organization
The memory is organized as shown in Figure 4.
Figure 4.
Block diagram
WC
E0
E1
High Voltage
Generator
Control Logic
E2
SCL
SDA
I/O Shift Register
Address Register
and Counter
Data
Register
Y Decoder
3
Memory organization
1 Page
X Decoder
AI06899
Doc ID 022638 Rev 1
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Device operation
4
M24C32-125
Device operation
The device supports the I2C protocol. This is summarized in Figure 5. Any device that sends
data on to the bus is defined to be a transmitter, and any device that reads the data to be a
receiver. The device that controls the data transfer is known as the bus master, and the
other as the slave device. A data transfer can only be initiated by the bus master, which will
also provide the serial clock for synchronization. The device is always a slave in all
communications.
Figure 5.
I2C bus protocol
SCL
SDA
SDA
Input
START
Condition
SCL
1
SDA
MSB
2
SDA
Change
STOP
Condition
3
7
8
9
ACK
START
Condition
SCL
1
SDA
MSB
2
3
7
8
9
ACK
STOP
Condition
AI00792B
10/29
Doc ID 022638 Rev 1
M24C32-125
4.1
Device operation
Start condition
Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in
the high state. A Start condition must precede any data transfer instruction. The device
continuously monitors (except during a Write cycle) Serial Data (SDA) and Serial Clock
(SCL) for a Start condition.
4.2
Stop condition
Stop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable
and driven high. A Stop condition terminates communication between the device and the
bus master. A Read instruction that is followed by NoAck can be followed by a Stop
condition to force the device into the Standby mode.
A Stop condition at the end of a Write instruction triggers the internal Write cycle.
4.3
Acknowledge bit (ACK)
The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter,
whether it be bus master or slave device, releases Serial Data (SDA) after sending eight bits
of data. During the 9th clock pulse period, the receiver pulls Serial Data (SDA) low to
acknowledge the receipt of the eight data bits.
4.4
Data input
During data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock
(SCL). For correct device operation, Serial Data (SDA) must be stable during the rising edge
of Serial Clock (SCL), and the Serial Data (SDA) signal must change only when Serial Clock
(SCL) is driven low.
4.5
Memory addressing
To start communication between the bus master and the slave device, the bus master must
initiate a Start condition. Following this, the bus master sends the device select code, shown
in Table 2 (on Serial Data (SDA), most significant bit first).
Table 2.
Device select code
Device type identifier(1)
Chip Enable address(2)
RW
b7
b6
b5
b4
b3
b2
b1
b0
1
0
1
0
E2
E1
E0
RW
1. The most significant bit, b7, is sent first.
2. E0, E1 and E2 are compared against the respective external pins on the memory device.
The device select code consists of a 4-bit device type identifier 1010b, and a 3-bit Chip
Enable address (E2, E1, E0). A device select code handling a value other than 1010b is not
acknowledged by the device.
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Device operation
M24C32-125
Up to eight memory devices can be connected on a single I2C bus. Each one is given a
unique 3-bit code on the Chip Enable (E2, E1, E0) inputs. When the device select code is
received, the device only responds if the Chip Enable Address is the same as the value on
the Chip Enable (E2, E1, E0) inputs.
The 8th bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations.
If a match occurs on the device select code, the corresponding device gives an
acknowledgment on Serial Data (SDA) during the 9th bit time. If the device does not match
the device select code, it deselects itself from the bus, and goes into Standby mode.
Table 3.
Operating modes
Mode
Current Address
Read
RW bit WC(1)
1
X
0
X
Bytes
1
Start, device select, RW = 1
Start, device select, RW = 0, Address
Random Address
Read
1
X
Sequential Read
1
X
≥1
Byte Write
0
VIL
1
Start, device select, RW = 0
Page Write
0
VIL
≤ 32
Start, device select, RW = 0
1
reStart, device select, RW = 1
1. X = VIH or VIL.
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Initial sequence
Doc ID 022638 Rev 1
Similar to Current or Random Address
Read
M24C32-125
Instructions
5
Instructions
5.1
Write operations
Following a Start condition the bus master sends a device select code with the R/W bit (RW)
reset to 0. The device acknowledges this, as shown in Figure 6, and waits for two address
bytes. The device responds to each address byte with an acknowledge bit, and then waits
for the data byte.
Each byte location is defined by several address bits inside two address bytes. If the
address bits are less than 16, the most significant bits (A15 and lower) are Don't Care. The
most significant address byte (Table 4) is sent first, followed by the least significant address
byte (Table 5).
When the bus master generates a Stop condition immediately after a data byte Ack bit (in
the “10th bit” time slot), either at the end of a Byte Write or a Page Write, the internal Write
cycle tW is triggered. A Stop condition at any other time slot does not trigger the internal
Write cycle.
After the Stop condition and the successful completion of an internal Write cycle (tW), the
device internal address counter is automatically incremented to point to the next byte after
the last modified byte.
During the internal Write cycle, Serial Data (SDA) is disabled internally, and the device does
not respond to any requests.
If the Write Control input (WC) is driven High, the Write instruction is not executed and the
accompanying data bytes are not acknowledged, as shown in Figure 7.
Table 4.
A15
Table 5.
A7
Most significant address byte
A14
A13
A12
A11
A10
A9
A8
A3
A2
A1
A0
Least significant address byte
A6
A5
A4
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Instructions
5.1.1
M24C32-125
Byte Write
After the device select code and the address bytes, the bus master sends one data byte. If
the addressed location is Write-protected, by Write Control (WC) being driven high, the
device replies with NoAck, and the location is not modified. If, instead, the addressed
location is not Write-protected, the device replies with Ack. The bus master terminates the
transfer by generating a Stop condition, as shown in Figure 6.
Figure 6.
Write mode sequences with WC = 0 (data write enabled)
WC
ACK
ACK
Byte addr
Byte addr
ACK
Data in
Stop
Dev sel
Start
Byte Write
ACK
R/W
WC
ACK
Dev sel
Start
Page Write
ACK
Byte addr
ACK
Byte addr
ACK
Data in 1
Data in 2
R/W
WC (cont'd)
ACK
Data in N
Stop
Page Write (cont'd)
ACK
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Doc ID 022638 Rev 1
AI01106d
M24C32-125
Page Write
The Page Write mode allows up to 32 bytes to be written in a single Write cycle, provided
that they are all located in the same page in the memory: that is, the most significant
memory address bits, b11-b5, are the same. If more bytes are sent than will fit up to the end
of the page, a condition known as “roll-over” occurs. In case of roll-over, the first bytes of the
page are overwritten.
The bus master sends from 1 to 32 bytes of data, each of which is acknowledged by the
device if Write Control (WC) is low. If Write Control (WC) is high, the contents of the
addressed memory location are not modified, and each data byte is followed by a NoAck, as
shown in Figure 7. After each byte is transferred, the internal byte address counter is
incremented. The transfer is terminated by the bus master generating a Stop condition.
Figure 7.
Write mode sequences with WC = 1 (data write inhibited)
WC
ACK
ACK
Byte addr
ACK
Byte addr
NO ACK
Data in
Stop
Dev sel
Start
Byte Write
R/W
WC
ACK
Page Write
Dev sel
Start
ACK
Byte addr
ACK
Byte addr
NO ACK
Data in 1
Data in 2
R/W
WC (cont'd)
NO ACK
Page Write (cont'd)
NO ACK
Data in N
Stop
5.1.2
Instructions
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AI01120d
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Instructions
5.1.3
M24C32-125
Minimizing Write delays by polling on ACK
During the internal Write cycle, the device disconnects itself from the bus, and writes a copy
of the data from its internal latches to the memory cells. The maximum Write time (tw) is
shown in AC characteristics tables in Section 8: DC and AC parameters, but the typical time
is shorter. To make use of this, a polling sequence can be used by the bus master.
The sequence, as shown in Figure 8, is:
●
Initial condition: a Write cycle is in progress.
●
Step 1: the bus master issues a Start condition followed by a device select code (the
first byte of the new instruction).
●
Step 2: if the device is busy with the internal Write cycle, no Ack will be returned and
the bus master goes back to Step 1. If the device has terminated the internal Write
cycle, it responds with an Ack, indicating that the device is ready to receive the second
part of the instruction (the first byte of this instruction having been sent during Step 1).
Figure 8.
Write cycle polling flowchart using ACK
Write cycle
in progress
Start condition
Device select
with RW = 0
NO
First byte of instruction
with RW = 0 already
decoded by the device
ACK
returned
YES
NO
Next
Operation is
addressing the
memory
YES
Send Address
and Receive ACK
ReStart
Stop
NO
StartCondition
YES
Data for the
Write cperation
Device select
with RW = 1
Continue the
Write operation
Continue the
Random Read operation
AI01847e
AI01847d
16/29
Doc ID 022638 Rev 1
M24C32-125
5.2
Instructions
Read operations
Read operations are performed independently of the state of the Write Control (WC) signal.
After the successful completion of a Read operation, the device’s internal address counter is
incremented by one, to point to the next byte address.
Read mode sequences
ACK
Current
Address
Read
Data out
Stop
Start
Dev sel
NO ACK
R/W
ACK
Random
Address
Read
Byte addr
Dev sel *
ACK
ACK
Data out 1
ACK
NO ACK
Data out N
ACK
Byte addr
ACK
Byte addr
R/W
ACK
Dev sel *
Start
Dev sel *
Start
Data out
R/W
R/W
ACK
NO ACK
Stop
Start
Dev sel
Sequention
Random
Read
ACK
Byte addr
R/W
ACK
Sequential
Current
Read
ACK
Start
Start
Dev sel *
ACK
Stop
Figure 9.
ACK
Data out1
R/W
NO ACK
Stop
Data out N
5.2.1
AI01105d
Random Address Read
A dummy Write is first performed to load the address into this address counter (as shown in
Figure 9) but without sending a Stop condition. Then, the bus master sends another Start
condition, and repeats the device select code, with the RW bit set to 1. The device
acknowledges this, and outputs the contents of the addressed byte. The bus master must
not acknowledge the byte, and terminates the transfer with a Stop condition.
Doc ID 022638 Rev 1
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Initial delivery state
5.2.2
M24C32-125
Current Address Read
For the Current Address Read operation, following a Start condition, the bus master only
sends a device select code with the R/W bit set to 1. The device acknowledges this, and
outputs the byte addressed by the internal address counter. The counter is then
incremented. The bus master terminates the transfer with a Stop condition, as shown in
Figure 9, without acknowledging the byte.
5.2.3
Sequential Read
This operation can be used after a Current Address Read or a Random Address Read. The
bus master does acknowledge the data byte output, and sends additional clock pulses so
that the device continues to output the next byte in sequence. To terminate the stream of
bytes, the bus master must not acknowledge the last byte, and must generate a Stop
condition, as shown in Figure 9.
The output data comes from consecutive addresses, with the internal address counter
automatically incremented after each byte output. After the last memory address, the
address counter ‘rolls-over’, and the device continues to output data from memory address
00h.
5.2.4
Acknowledge in Read mode
For all Read instructions, the device waits, after each byte read, for an acknowledgment
during the 9th bit time. If the bus master does not drive Serial Data (SDA) low during this
time, the device terminates the data transfer and switches to its Standby mode.
6
Initial delivery state
The device is delivered with all the memory array bits set to 1 (each byte contains FFh).
18/29
Doc ID 022638 Rev 1
M24C32-125
7
Maximum rating
Maximum rating
Stressing the device outside the ratings listed in Table 6 may cause permanent damage to
the device. These are stress ratings only, and operation of the device at these, or any other
conditions outside those indicated in the operating sections of this specification, is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Table 6.
Absolute maximum ratings
Symbol
TSTG
TLEAD
Parameter
Min.
Max.
Unit
Ambient operating temperature
–40
130
°C
Storage temperature
–65
150
°C
(1)
°C
–0.50
6.5
V
-
5
mA
–0.50
6.5
V
-
4000
V
Lead temperature during soldering
VIO
Input or output range
IOL
DC output current (SDA = 0)
VCC
Supply voltage
VESD
Electrostatic pulse (Human Body
model)(2)
see note
1. Compliant with JEDEC Std J-STD-020D (for small body, Sn-Pb or Pb assembly), the ST ECOPACK®
7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS)
2002/95/EU.
2. Positive and negative pulses applied on pin pairs, according to AEC-Q100-002 (compliant with JEDEC Std
JESD22-A114, C1=100 pF, R1=1500 Ω, R2=500 Ω)
Doc ID 022638 Rev 1
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DC and AC parameters
8
M24C32-125
DC and AC parameters
This section summarizes the operating and measurement conditions, and the DC and AC
characteristics of the device.
Table 7.
Operating conditions (voltage range W)
Symbol
VCC
TA
Table 8.
Parameter
Min.
Max.
Unit
Supply voltage
2.5
5.5
V
Ambient operating temperature
–40
125
°C
Min.
Max.
Unit
AC measurement conditions
Symbol
Cbus
Parameter
Load capacitance
100
SCL input rise/fall time, SDA input fall time
pF
50
ns
Input levels
0.2 VCC to 0.8 VCC
V
Input and output timing reference levels
0.3 VCC to 0.7 VCC
V
Figure 10. AC measurement I/O waveform
)NPUTVOLTAGELEVELS
6##
)NPUTANDOUTPUT
4IMINGREFERENCELEVELS
6##
6##
6##
-36
20/29
Doc ID 022638 Rev 1
M24C32-125
DC and AC parameters
Table 9.
Input parameters
Parameter(1)
Symbol
Test condition
Min.
Max.
Unit
CIN
Input capacitance (SDA)
8
pF
CIN
Input capacitance (other pins)
6
pF
ZL
ZH
Input impedance (E2, E1, E0, WC)(2)
VIN < 0.3 VCC
30
kΩ
VIN > 0.7 VCC
500
kΩ
1. Characterized only, not tested in production.
2. E2, E1, E0 input impedance when the memory is selected (after a Start condition).
Table 10.
Memory cell characteristics
Symbol Parameter
Ncycle
Note:
Test condition
Endurance TA = 25 °C, 2.5 V < Vcc < 5.5 V
Min.
Max.
Unit
1,000,000
-
Write cycle
This parameter is not tested but established by characterization and qualification. For
endurance estimates in a specific application, please refer to AN2014.
Doc ID 022638 Rev 1
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DC and AC parameters
Table 11.
M24C32-125
DC characteristics (M24C32-W, device grade 3)
Test conditions (in addition to those
in Table 7 and Table 8)
Symbol
Parameter
ILI
Input leakage current
(SCL, SDA, E2, E1,
E0)
ILO
Output leakage
current
ICC
Supply current (Read) fc = 400 kHz
ICC0
Supply current (Write) During tW
ICC1
Standby supply
current
VIL
Input low voltage
(SCL, SDA, WC)
VIH
VOL
Max.
Unit
VIN = VSS or VCC
device in Standby mode
±2
µA
SDA in Hi-Z, external voltage applied
on SDA: VSS or VCC
±2
µA
2
mA
5(1)
mA
10
µA
–0.45
0.3 VCC
V
Input high voltage
(SCL, SDA)
0.7 VCC
6.5
V
Input high voltage
(WC, E2, E1, E0)
0.7 VCC VCC+0.6
Output low voltage
Min.
Device not selected(2),
VIN = VSS or VCC
IOL = 2.1 mA, VCC = 2.5 V or
IOL = 3 mA, VCC = 5.5 V
0.4
1. Characterized only, not tested in production.
2. The device is not selected after power-up, after a Read instruction (after the Stop condition), or after the
completion of the internal write cycle tW (tW is triggered by the correct decoding of a Write instruction).
22/29
Doc ID 022638 Rev 1
V
V
M24C32-125
DC and AC parameters
Table 12.
400 kHz AC characteristics
Parameter(1)
Symbol
Alt.
fC
fSCL
Clock frequency
tCHCL
tHIGH
tCLCH
tLOW
tQL1QL2(2)
tF
tXH1XH2
tR
Min.
Max.
Unit
-
400
kHz
Clock pulse width high
600
-
ns
Clock pulse width low
1300
SDA (out) fall time
20(3)
120
ns
Input signal rise time
(4)
(4)
ns
(4)
ns
ns
tXL1XL2
tF
Input signal fall time
(4)
tDXCX
tSU:DAT
Data in set up time
100
-
ns
tCLDX
tHD:DAT
Data in hold time
0
-
ns
tCLQX
(5)
tDH
Data out hold time
200
-
ns
tCLQV
(6)
tAA
Clock low to next data valid (access time)
200
900
ns
tCHDL
tSU:STA
Start condition setup time
600
-
ns
tDLCL
tHD:STA
Start condition hold time
600
-
ns
tCHDH
tSU:STO
Stop condition set up time
600
-
ns
tDHDL
tBUF
Time between Stop condition and next Start
condition
1300
-
ns
tW
tWR
Write time
-
5
ms
Pulse width ignored (input filter on SCL and
SDA) - single glitch
-
100
ns
tNS(2)
1. Test conditions (in addition to those specified under Operating conditions and AC test measurement
conditions in Section 8: DC and AC parameters).
2. Characterized only, not tested in production.
3. With CL = 10 pF.
4. There is no min. or max. values for the input signal rise and fall times. It is however recommended by the
I²C specification that the input signal rise and fall times be more than 20 ns and less than 300 ns when
fC < 400 kHz.
5. The min value for tCLQX (Data out hold time) of the M24xxx devices offers a safe timing to bridge the
undefined region of the falling edge SCL.
6. tCLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach either 0.3 VCC or
0.7 VCC, assuming that Rbus × Cbus time constant is within the values specified in Figure 11.
Doc ID 022638 Rev 1
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DC and AC parameters
M24C32-125
"USLINEPULLUPRESISTOR
K Figure 11. Maximum Rbus value versus bus parasitic capacitance (Cbus) for
an I2C bus at maximum frequency fC = 400 kHz
2
BU
S §
(ERE2BUS §#BUSNS
4HE2X#TIMECONSTANT
BUS
BUS
MUSTBEBELOWTHENS
TIMECONSTANTLINEREPRESENTED
ONTHELEFT
6##
#
BU
S 2BUS
N
K½
S
)£#BUS
MASTER
3#,
-XXX
3$!
P&
"USLINECAPACITORP&
#BUS
AIB
Figure 12. AC waveforms
T8,8,
T8(8(
T#(#,
T#,#(
3#,
T$,#,
T8,8,
3$!)N
T#($,
T#,$8
T8(8(
3TART
CONDITION
3$!
)NPUT
3$! T$8#(
#HANGE
T#($( T$($,
3TART
3TOP
CONDITION CONDITION
3#,
3$!)N
T7
T#($(
T#($,
3TOP
CONDITION
7RITECYCLE
3TART
CONDITION
T#(#,
3#,
T#,16
3$!/UT
T#,18
$ATAVALID
T1,1,
$ATAVALID
!)F
24/29
Doc ID 022638 Rev 1
M24C32-125
9
Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Figure 13. TSSOP8 – 8-lead thin shrink small outline, package outline
1. Drawing is not to scale.
Table 13.
TSSOP8 – 8-lead thin shrink small outline, package mechanical data
inches(1)
millimeters
Symbol
Typ.
Min.
A
Max.
Min.
1.200
A1
0.050
0.150
0.800
1.050
b
0.190
c
0.090
A2
Typ.
1.000
CP
Max.
0.0472
0.0020
0.0059
0.0315
0.0413
0.300
0.0075
0.0118
0.200
0.0035
0.0079
0.0394
0.100
0.0039
D
3.000
2.900
3.100
0.1181
0.1142
0.1220
e
0.650
–
–
0.0256
–
–
E
6.400
6.200
6.600
0.2520
0.2441
0.2598
E1
4.400
4.300
4.500
0.1732
0.1693
0.1772
L
0.600
0.450
0.750
0.0236
0.0177
0.0295
L1
1.000
0°
8°
α
0.0394
0°
8°
1. Values in inches are converted from mm and rounded to four decimal digits.
Doc ID 022638 Rev 1
25/29
Package mechanical data
M24C32-125
Figure 14. SO8N – 8 lead plastic small outline, 150 mils body width, package outline
h x 45˚
A2
A
c
ccc
b
e
0.25 mm
GAUGE PLANE
D
k
8
E1
E
1
L
A1
L1
SO-A
1. Drawing is not to scale.
Table 14.
SO8N – 8 lead plastic small outline, 150 mils body width, package data
inches (1)
millimeters
Symbol
Typ
Min
A
Max
Typ
1.750
Max
0.0689
A1
0.100
A2
1.250
b
0.280
0.480
0.0110
0.0189
c
0.170
0.230
0.0067
0.0091
ccc
0.250
0.0039
0.0098
0.0492
0.100
0.0039
D
4.900
4.800
5.000
0.1929
0.1890
0.1969
E
6.000
5.800
6.200
0.2362
0.2283
0.2441
E1
3.900
3.800
4.000
0.1535
0.1496
0.1575
e
1.270
0.0500
h
0.250
0.500
0.0098
0.0197
k
0°
8°
0°
8°
L
0.400
1.270
0.0157
0.0500
L1
1.040
0.0409
1. Values in inches are converted from mm and rounded to four decimal digits.
26/29
Min
Doc ID 022638 Rev 1
M24C32-125
10
Part numbering
Part numbering
Table 15.
Ordering information scheme
Example:
M24C32
W MN 3
T
P /P
Device type
M24 = I2C serial access EEPROM
Device function
C32 = 32 Kbit (4096 X 8)
Operating voltage
W = VCC = 2.5 V to 5.5 V
Package
MN = SO8 (150 mil width)(1)
DW = TSSOP8 (169 mil width)(1)
Device grade
3 = Device tested with high-reliability certified flow over -40 to 125 °C
Option
blank = standard packing
T = Tape and reel packing
Plating technology
P = ECOPACK® (RoHS compliant)
Process
/P = Manufacturing technology code
1. RoHS-compliant and halogen-free (ECOPACK2®)
For a list of available options (speed, package, etc.) or for further information on any aspect
of the devices, please contact your nearest ST sales office.
Doc ID 022638 Rev 1
27/29
Revision history
11
M24C32-125
Revision history
Table 16.
28/29
Document revision history
Date
Revision
22-Feb-2012
1
Changes
Initial release.
Doc ID 022638 Rev 1
M24C32-125
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