STEVAL-TDR005V1 RF power amplifier using 2 x SD2943 N-channel enhancement-mode lateral MOSFETs Features ■ Excellent thermal stability ■ Frequency: 1.8 - 54 MHz ■ Supply voltage: 48 V ■ Output power: 450 W typ. ■ Input power 10 W max. ■ Efficiency: 55 % - 76 % ■ IMD at 300 WPEP < -24 dBc ■ Load mismatch: 3:1 all phases Description The STEVAL-TDR005V1 is a RF broadband power amplifier intended for linear or nonlinear operation over the band 1.8 to 54 MHz using 2x SD2943 gold metallized N-channel MOS fieldeffect transistors. The temperature compensating biasing circuit supports class B and class AB operation. Table 1. Device summary Order code STEVAL-TDR005V1 STEVAL-TDR005V1 is designed in cooperation with Specific RF Devices (Germany). March 2010 Doc ID 14845 Rev 2 1/11 www.st.com 11 Contents STEVAL-TDR005V1 Contents 1 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Typical performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 Photos of STEVAL-TDR005V1 amplifier . . . . . . . . . . . . . . . . . . . . . . . . . 6 5 STEVAL-TDR005V1 class of operation . . . . . . . . . . . . . . . . . . . . . . . . . . 7 6 SD2943 mounting recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 7 2/11 6.1 Mounting recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6.2 Mounting sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Doc ID 14845 Rev 2 STEVAL-TDR005V1 Electrical data 1 Electrical data 1.1 Maximum ratings Table 2. Absolute maximum ratings Symbol Value Unit Input power 16 W Output power 500 W Drain supply voltage 50 V VGG Gate biasing voltage 15 V IDD Drain current 20 A Power dissipation 400 W PIN POUT VDD (1) PDISS Parameter 1. VGG from 9 to 15 V and PIN < 16 W Doc ID 14845 Rev 2 3/11 Electrical characteristics 2 STEVAL-TDR005V1 Electrical characteristics TA = +25 oC, VDD = 48 V, IDQ = 2 x 900 mA Table 3. Electrical specification Symbol Min Freq. Frequency range 1.8 POUT PIN = 10 W 350 Gain ND Typ Max Unit 54 MHz 450 W PIN = 10 W 16.6 ± 0.6 dB dB PIN = 10 W 55 - 76 % ND H2 2 Harmonic @ POUT = 300 W -24 / -49 dBc H3 3RD Harmonic @ POUT = 300 W -15 / -58 dBc VSWR 4/11 Test Conditions Load mismatch all phases @ POUT = 300 W Doc ID 14845 Rev 2 3:1 STEVAL-TDR005V1 Typical performance 3 Typical performance Figure 1. Output power vs frequency Figure 2. Doc ID 14845 Rev 2 Output power vs frequency 5/11 Photos of STEVAL-TDR005V1 amplifier 4 6/11 STEVAL-TDR005V1 Photos of STEVAL-TDR005V1 amplifier Figure 3. Top view Figure 4. Side view Doc ID 14845 Rev 2 STEVAL-TDR005V1 5 STEVAL-TDR005V1 class of operation STEVAL-TDR005V1 class of operation ● Class B: a low bias point with ~100 mA per transistor ● Class AB: a higher bias point with ~ 900 mA per transistor To select a bias point, STEVAL-TDR005V1 has a control port “BIAS”. ● The bias point is 2x 100 mA if “BIAS” is left open and in this case a DC voltage of ~5 V is present ● The bias point is 2 x 900 mA if “BIAS” is connected to ground. "PA_ON" control port / ON-OFF bias current ● To switch-on biasing circuit, connect “PA_ON” to ground. ● To switch-off biasing circuit, left open “PA_ON” Doc ID 14845 Rev 2 7/11 SD2943 mounting recommendations STEVAL-TDR005V1 6 SD2943 mounting recommendations 6.1 Mounting recommendations 6.2 8/11 ● Ensure holes in heatsinks are free from burrs; ● Minimum depth of tapped holes in heatsinks is 6 mm; ● Use 4-40 UNC-2A cheese-head screws with a flat washer to spread the joint pressure; ● The minimum flatness of the mounting area is 0.02 mm; ● Mounting area roughness should be less than 0.5 µm (micro); ● Avoid, as much as possible, use of flux or flux solutions because flux can penetrate even when hermetically sealed ceramic-capped transistors. Tin and wash the printedcircuit board BEFORE mounting the power transistors, then solder the transistor leads without using flux; ● Transistor leads may be tinned by dipping them full-length into a solder bath at a temperature of about 230 °C. No flux should be used during tinning; ● Recommended heatsink compounds: WPSII (silicon free) from austerlitz electronics, 340 from down corning etc. Mounting sequence ● Apply a thin layer of evenly distributed heatsink compound to the flange; ● Position the device with flat washers in place; ● Tighten the screws until finger tight (0.05 Nm); ● Further tighten the screws until the specified torque is reached; ● For M174, M177 and M244 type of packages, torque should be minimum 0.6 Nm and 0.75 Nm max. Doc ID 14845 Rev 2 STEVAL-TDR005V1 Table 4. SD2943 mounting recommendations DMOS packages - list of materials Package Description Flange Leadframe Type M174 0.500 DIA 4L NON HERM W/FLANGE Ceramic insulator Plating Leads Torque (Nm) Flange Min Max ALLOY 42 (Fe58 / Ni42) BeO (99.5% min) Au (100µ min) over Ni(100µ min) + Pd Ni (100µ min / (10µ min) 350µ max) 0.6 0.75 M174 (Moly disk) 0.500 DIA 4L NON HERM Cu-MoW/FLANGE Cu (MOLY DISK) ALLOY 42 (Fe58 / Ni42) BeO (99.5% min) Au (100µ min) over Ni(100µ min) + Pd Ni (100µ min / (10µ min) 350µ max) 0.6 0.75 M177 0.550 DIA 4L NON Cu-MoHERM Cu W/FLANGE ALLOY 42 (Fe58 / Ni42) BeO (99.5% min) Au (60µ min) over Ni (100µ min / 350µ max) Au (100µ min) over Ni (100µ min / 350µ max) 0.6 0.75 M244 2x W 0.400x0.425 (85%) WIDE 2L Cu LAP N/H (15%) FLANGE ALLOY 42 (Fe58 / Ni42) BeO (99.5% min) Au (60µ min) over Ni (100µ min / 350µ max) Au (60µ min) over Ni (100µ min / 350µ max) 0.6 0.75 Cu Doc ID 14845 Rev 2 9/11 Revision history 7 STEVAL-TDR005V1 Revision history Table 5. 10/11 Document revision history Date Revision Changes 01-Jul-2008 1 Initial release. 18-Mar-2010 2 Updated description on cover page. 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