TI TSB12LV21APGF

TSB12LV21A
(PCILynx) IEEE 1394-1995 BUS TO PCI BUS INTERFACE
SLLS273 – APRIL 1997
D
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Supports Provisions of IEEE 1394-1995
(1394) Standard for High-Performance
Serial Bus†
Performs the Function of a 1394 Cycle
Master
Supports 1394 Transfer Rates of 100, 200
and 400 Mbit/s
Provides Three Sizes of Programmable
FIFOs
Provides PCI Bus Master Function for
Supporting DMA Operations
Compliant With PCI Specification 2.1
D
D
D
D
D
Provides PCI Slave Function for Read/Write
Access of Internal Registers
Supports the Plug-and-Play (PnP)
Specification
Provides an 8-/16-bit Zoom Video (ZV) Port
for the Transferring of Video Data Directly
to an External Motion Video Memory Area
Operates from a 3.3-V Power Supply While
Maintaining 5-V Tolerant Inputs
High-Performance 176-Pin PQFP (PGF)
Package
description
The TSB12LV21A (PCILynx) provides a high-performance IEEE 1394-1995 interface with the capability to
transfer data between the 1394 phy-link interface, the PCI bus interface, and external devices connected to the
local bus interface. The 1394 phy-link interface provides the connection to the 1394 physical layer device and
is supported by the on-board link layer controller (LLC). The LLC provides the control for transmitting and
receiving 1394 packet data between the FIFO and phy-link interface at rates of 100 Mbit/s, 200 Mbit/s, and 400
Mbit/s. The link layer also provides the capability to receive status from the physical layer device and to access
the physical layer control and status registers by the application software.
An internal 1K-byte memory is provided that can be configured as multiple variable-size FIFOs and eliminates
the need for external FIFOs. Separate FIFOs can be user configured to support 1394 receive, asynchronous
transmit, and isochronous transmit transfer operations.
The PCI interface supports 32-bit burst transfers up to 33 MHz and is capable of operating as both master and
target devices. Configuration registers can be loaded from an external serial EEPROM, allowing board and
system designers to assign their own unique identification codes. An autoboot mode allows data-moving
systems (such as docking stations) to be designed to operate on the PCI bus without the need for a host CPU.
The DMA controller uses packet control list (PCL) data structures to control the transfer of data and allow the
DMA to operate without host CPU intervention. These PCLs can reside in PCI memory or in memory that is
connected to the local bus port. The PCLs implement an instruction set that allows linking, conditional
branching, 1394 data transfer control, auxiliary support commands, and status reporting. Five DMA channels
are provided to accommodate programmable data types. PCLs can be chained together to form a channel
control program that can be developed to support each DMA channel. Data can be stored in either big endian
or little endian format eliminating the need for the host CPU to perform byte swapping. Data can be transferred
to either 4-byte aligned locations to provide the highest performance or to nonaligned locations to provide the
best memory use.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
† This serial bus implements technology covered by one or more patents of Apple Computer, Incorporated and SGS Thomson, Limited.
Copyright  1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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1
TSB12LV21A
(PCILynx) IEEE 1394-1995 BUS TO PCI BUS INTERFACE
SLLS273 – APRIL 1997
description (continued)
The RAM, ROM, AUX, ZV, and general purpose I/O (GPIO) ports collectively implement the local bus interface.
These ports are mapped into the PCI address can be accessed either through the PCI bus or internal DMA
transactions. Internal transactions do not appear on the external PCI bus, thereby conserving PCI bandwidth.
DMA packet control lists or other data that may be stored in external RAM or ROM attached to the local bus
interface. This further reduces PCI use and generally improves performance. The ZV local bus port is designed
to transfer data from 1394 video devices to an external device connected to the PCILynx ZV port. This interface
provides a method of receiving 1394 digital camera packets directly to a ZV-compliant device attached to the
local bus interface.
Built-in test registers, a dedicated test output terminal, and four GPIO terminals allow observation of internal
states and provides a convenient software debug capability. Programmable interrupts are available to inform
driver software of important events such as 1394 bus resets and DMA-to-PCL transfer completion.
The 3.3-V internal operation provides reduced power consumption while maintaining compatibility with 5-V
signaling environments. The PCI interface is compatible with both 3-V and 5-V PCI systems.
2
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TSB12LV21A
(PCILynx) IEEE 1394-1995 BUS TO PCI BUS INTERFACE
SLLS273 – APRIL 1997
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zv_data_valid
zv_hsync
GND
zv_ext_clk
3.3V VCC
zv_vsync
zv_pix_clk
gpio_data0
gpio_data1
gpio_data2
gpio_data3
GND
NC
aux_adr0
aux_adr1
aux_adr2
3.3V VCC
aux_adr3
GND
aux_adr4
aux_adr5
aux_adr6
aux_adr7
5V VCC
aux_adr8
3.3V VCC
aux_adr9
aux_adr10
aux_adr11
aux_adr12
GND
aux_adr13
3.3V VCC
aux_adr14
aux_adr15
aux_data0
aux_data1
GND
aux_data2
3.3V VCC
aux_data3
aux_data4
aux_data5
GND
GND
NC
pci_ad8
pci_cbez0
3.3V VCC
pci_ad7
GND
pci_ad6
pci_ad5
pci_ad4
pci_ad3
3.3V VCC
pci_ad2
pci_ad1
pci_ad0
5V VCC
aux_intz
aux_rdy
5V VCC
aux_clk
GND
aux_rstz
ram_csz
rom_csz
aux_csz
3.3V VCC
aux_wez1
GND
aux_wez0
aux_oez
3.3V VCC
aux_data15
aux_data14
aux_data13
GND
aux_data12
aux_data11
aux_data10
aux_data9
5V VCC
aux_data8
3.3V VCC
aux_data7
aux_data6
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46
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3.3V VCC
NC
pci_ad25
pci_ad24
pci_cbez3
GND
pci_idselz
3.3V VCC
pci_ad23
pci_ad22
pci_ad21
5V VCC
pci_ad20
GND
pci_ad19
pci_ad18
pci_ad17
pci_ad16
3.3V VCC
pci_cbez2
GND
pci_framez
pci_irdyz
pci_trdyz
pci_devselz
3.3V VCC
pci_stopz
GND
NC
pci_perrz
pci_serrz
pci_par
3.3V VCC
pci_cbez1
GND
pci_ad15
pci_ad14
pci_ad13
pci_ad12
5V VCC
pci_ad11
3.3V VCC
pci_ad10
pci_ad9
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140
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138
137
136
135
134
133
pci_ad26
GND
pci_ad27
pci_ad28
3.3V VCC
pci_ad29
pci_ad30
pci_ad31
GND
pci_reqz
pci_intaz
3.3V VCC
pci_gntz
pci_resetz
5V VCC
pci_clk
GND
autoboot
GND
3.3V VCC
phy_clk50
GND
phy_data7
phy_data6
phy_data5
phy_data4
GND
phy_data3
phy_data2
phy_data1
phy_data0
3.3V VCC
phy_lreq
phy_ctl1
phy_ctl0
GND
test_out
link_cycleout
3.3V VCC
link_cyclein
3.3V VCC
5V VCC
seeprom_data
seeprom_clk
PGF PACKAGE
(TOP VIEW)
NC – No internal connection
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3
TSB12LV21A
(PCILynx) IEEE 1394-1995 BUS TO PCI BUS INTERFACE
SLLS273 – APRIL 1997
Terminal Functions
Terminal
Name
No.
I/O
Description
3.3V VCC
1,8,19,26,33,42,49
56,70,75,86,93,100
107,116,128,136,138,
145,157,165,172
I
3.3-V power input
5V VCC
12,40,60,63
84,109,135,162
I
5-V tolerant power input. When interfacing with a 3.3-V parts, these terminals should be connected to 3.3-V power.
autoboot
159
I
Autoboot to select autoboot mode
aux_adr15–0
98,99,101,103–106
108,110–113,115
117–119
O
Auxiliary port address lines
aux_clk
64
O
Auxiliary port clock out (output at frequency of PCI clock)
aux_csz
69
O
Auxiliary port chip select
aux_data15–0
76–78,80–83,85,87
88,90–92,94,96,97
I/O
Auxiliary port bidirectional data bus to external logic
aux_intz
61
I
Auxiliary port interrupt
aux_oez
74
O
Auxiliary port output enable
aux_rdy
62
I
Auxiliary port ready indication (from external logic)
aux_rstz
66
O
Auxiliary port reset out
aux_wez1–0
71,73
O
Auxiliary port write strobes (to external logic)
GND
6,14,21,28,35,45
51,65,72,79,89,95
102,114,121,130,141
150,155,158,160,168
175
I
Ground
gpio_data3–0
122–125
link_cyclein
137
I
Optional external 8-kHz clock
link_cycleout
139
O
Cycle timer 8-kHz cycle clock out
N/C
2,29,46,120
pci_ad31–0
169–171,173,174,176
3,4,9–11,13,15–18
36–39,41,43,44,47,50
52–55,57–59
I/O
PCI multiplexed address/data bus signals
pci_cbez3–0
5,20,34,48
I/O
PCI multiplexed command/byte enable signals
pci_clk
161
I
PCI system clock
pci_devselz
25
I/O
PCI device select
pci_framez
22
I/O
PCI frame signal
4
I/O
Auxiliary port general purpose programmable I/O signals
Not connected
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TSB12LV21A
(PCILynx) IEEE 1394-1995 BUS TO PCI BUS INTERFACE
SLLS273 – APRIL 1997
Terminal Functions (continued)
Terminal
Name
No.
I/O
I
Description
pci_gntz
164
PCI bus grant signal (from PCI bus arbiter)
pci_idselz
7
I/O
PCI initialization device select
pci_intaz
166
OD
PCI system interrupt A. This is an open drain signal.
pci_irdyz
23
I/O
PCI initiator-ready signal
pci_par
32
I/O
PCI parity signal
pci_perrz
30
I/O
PCI data-parity-error signal
pci_reqz
167
O
PCI master bus request (to PCI bus arbiter)
pci_resetz
163
I
PCI system reset
pci_serrz
31
OD
PCI system-error signal. This is an open drain signal.
pci_stopz
27
I/O
PCI stop signal
pci_trdyz
24
I/O
PCI target-ready signal
phy_clk50
156
I
phy_ctl0 –1
142,143
I/O
Phy-link bidirectional control lines
phy_data0–7
146–149,151–154
I/O
Phy-link bidirectional data lines
phy_lreq
144
O
Phy-link request signal
ram_csz
67
O
External RAM chip select
rom_csz
68
O
External ROM chip select
seeprom_clk
133
I/O
External serial EEPROM data clock
seeprom_data
134
I/O
External serial EEPROM read/write data line
test_out
140
O
Test MUX out
zv_data_valid
132
O
Zoom port data-valid signal
zv_ext_clk
129
I
Zoom port external clock input
zv_hsync
131
O
Zoom port horizontal-sync output
zv_pix_clk
126
O
Zoom port pixel clock
zv_vsync
127
O
Zoom port vertical-sync output
50-MHz system clock (from PHY chip)
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5
TSB12LV21A
(PCILynx) IEEE 1394-1995 BUS TO PCI BUS INTERFACE
SLLS273 – APRIL 1997
system block diagram
1394 Peripheral Devices
Personal Computer
1394
CD ROM
PCI Data Bus
Serial EEPROM
1394
Laser
Printer
PCILynx-to-Phy
Interface
1394
3 Port
Physical
Layer
Interface
PCILynx
(TSB12LV21A)
1394
Digital
VCR
AUX Port Local Bus
Flash
PROM
(RPL ROM)
PCI Host
Bridge
DMA
Channel
Control
(SRAM)
User
Defined
Function
(AUX)
ZV
Port
(Video)
Host Local Bus
Host
CPU
Local
Memory
PCI
Agent
PCI
Agent
6
1394
Desktop
Camera
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1394
Video
Cable
Set-Top
Box
TSB12LV21A
(PCILynx) IEEE 1394-1995 BUS TO PCI BUS INTERFACE
SLLS273 – APRIL 1997
functional block diagram
seeprom_data
seeprom_clk
32
pci_ad31 – pci_ad0
aux_clk
aux_rstz
Serial EPROM
Interface
aux_intz
/
4
4
pci_cbez3 – pci_cbez0
pci_par
pci_framez
pci_irdyz
pci_trdyz
pci_devselz
pci_stopz
pci_idselz
pci_perrz
pci_serrz
pci_reqz
pci_gntz
pci_clk
pci_resetz
pci_intaz
/
/
gpio_data3 – gpio_data0
16
/
PCI Master
Local Bus
Interface
Logic
/
RAM
ROM
AUX
ZV
PCI Slave
aux_adr15 – aux_adr0
16
aux_data15 – aux_data0
aux_oez
2
/
aux_wez1 – aux_wez0
aux_rdy
3
/
zv_hsync, zv_vsync, zv_pix_clk
zv_data_valid
3
PCI Configuration Control
and Status Registers
/
aux_csz, rom_csz, ram_csz
zv_ext_clk
PCI Bus Logic
DMA Engine
DMA Control
and
Status Registers
DMA Logic
General
Receiver
FIFO
Asynchronous
Transmit
FIFO
Isosynchronous
Transmit
FIFO
Pointer
Address
Mapping Logic
FIFO Control
and Status
Registers
FIFO Logic
2
1394 Link Layer Control (LLC) Logic
1394 LLC
Control and
Status Registers
Cycle
Timer
1394 Packet
Transmit
Control Logic
/
Phy-Link
Interface
Logic
Parallel-to-Serial
1394 Packet
Receive
Control Logic
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/
phy_data0 – phy_data7
phy_clk50
phy_lreq
link_cyclein
CRC Logic
Cycle
Monitor
phy_ctl0 – phy_ctl1
8
link_cycleout
Serial-to-Parallel
• DALLAS, TEXAS 75265
7
TSB12LV21A
(PCILynx) IEEE 1394-1995 BUS TO PCI BUS INTERFACE
SLLS273 – APRIL 1997
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC(3V) (VCC = 3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 4.0 V
Supply voltage range, VCC(5V) (VCC = 5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 5.5 V
Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC(5v) +0.5 V
Output voltage range at any output, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC(5v) + 0.5 V
Input clamp current, IIK (VI < 0 or VI > VCC5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
MIN
NOM
MAX
UNIT
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Supply voltage
voltage, VCC
VCC = 3 V
VCC = 5 V
Input voltage, VI
PCI terminals
Low-level input voltage,
g ,
VIL
PCI terminals
5.5
0.475 ×
VCC(3V)
All other terminals
2
All other terminals
VCC(5v)
VCC(3V)
VCC(5V)
VCC(5V)
0.325 VCC(3V)
0.8
PCI terminals
6
All other terminals
6
PCI terminals
6
All other terminals
6
Junction temperature, TJ
8
3.6
5
0
High-level input voltage,
VIH
Fall time,
time input,t
input tf
3.3
0
Output voltage, VO
Rise time,
time input,t
input tr
3
4.5
0
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115
V
V
V
V
V
ns
ns
°C
TSB12LV21A
(PCILynx) IEEE 1394-1995 BUS TO PCI BUS INTERFACE
SLLS273 – APRIL 1997
PCI interface switching characteristics, see Figure 1
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PARAMETER
tsu1
th1
td1
tsu2
MEASURED
TEST
CONDITION
MIN
TYP
MAX
UNIT
Setup time, pci_xx low or high to pci_clk high†
Hold time, pci_clk high to pci_xx low or high†, pci_gntz low or
high
40% to 40%
7
ns
40% to 40%
0
ns
Delay time, pci_clk high to pci_xx low or high†
40% to 40%
2
Setup time, pci_gntz low or high to pci_clk high
40% to 40%
10
11
ns
ns
td2
Delay time, pci_clk high to pci_intaz low or high
40% to 40%
2
13
ns
† In this case, pci_xx refers to the following signals; pci_ad31–0, pci_cbez3–0, pci_par, pci_framez, pci_irdyz, pci_trdyz, pci_devselz, pci_stopz,
pci_idselz, pci_perrz, pci_serrz, pci_reqz.
phy-link interface switching characteristics, see Figure 2
PARAMETER
tsu3
th2
td3
tsu4
MEASURED
TEST
CONDITION
MIN
TYP
MAX
UNIT
Setup time, phy_xx low or high to phy_clk high†
1.3 V to 1.3 V
4
ns
Hold time, phy_clk high to phy_xx, link_cyclein low or high
Delay time, phy_clk high to phy_xx, phy_lreq low or high†
1.3 V to 1.3 V
1
ns
1.3 V to 1.3 V
3
Setup time, phy_clk high to link_cyclein low or high
1.3 V to 1.3 V
5
td4
Delay time, phy_clk high to lynk_cycleout low or high
1.3 V to 1.3 V
† In this case, phy_xx refers to the following bidirectional signals; phy_ctl1–0, phy_data7–0.
11
ns
ns
3
13
ns
local bus switching characteristics, see Figure 3
PARAMETER
MEASURED
TEST
CONDITION
MIN
TYP
MAX
UNIT
td5
Delay time, aux_clk high to aux_adr, aux_data15–0 (write),
aux_oez valid†
1.3 V to 1.3 V
0
15
ns
td6
Delay time, aux_clk high to rom_csz, ram_csz, aux_csz valid
1.3 V to 1.3 V
0
20
ns
td7
Delay time, aux_wez0, aux_wez1 high (deasserted) to
aux_adr, aux_data15–0 (write), aux_oez, rom_csz, ram_csz,
aux_csz valid
1.3 V to 1.3 V
0.5
td8
Delay time, aux_clk low to aux_wez0, aux_wez1 low
(asserted)
1.3 V to 1.3 V
0
10
ns
td9
Delay time, aux_clk high to aux_wez0, aux_wez1 high
(deasserted)
1.3 V to 1.3 V
0
10
ns
td10
Delay time, aux_clk high to gpio_data3–0 valid
1.3 V to 1.3 V
2
15
ns
tsu5
Setup time, aux_adr, adr_data15–0 (write), auxoez, rom_csz,
ram_csz, aux_csz valid before aux_wez0, aux_wez1 low
(asserted)
1.3 V to 1.3 V
5
ns
tsu6
Setup time, aux_data15–0 (read), aux_rdyz, gpio_data3–0
valid before aux_clk high
1.3 V to 1.3 V
10
ns
th3
Hold time, aux_data15–0 (read), auxrdyz, gpio_data3–1
invalid after aux_clk high
1.3 V to 1.3 V
0
ns
ns
† These signals are asserted asynchronously when a ZOOM port transfer imediately preceeds the local bus transfer. In all cases, the setup time
to aux_wez and the number of waitstates remain the same.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
9
TSB12LV21A
(PCILynx) IEEE 1394-1995 BUS TO PCI BUS INTERFACE
SLLS273 – APRIL 1997
zoom video port switching characteristics, source clock = 30 ns with a 50% duty cycle
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PARAMETER
MEASURED
TEST
CONDITION
MIN
TYP
MAX
UNIT
tsu7
Setup time, zv_hsync low, zv_vsync, zv_data_valid high before
zv_pix_clk high
1.3 V to 1.3 V
See Figure 4
12
ns
th4
Hold time, zv_hsync high, zv_vsync, zv_data_valid low after
zv_pix_clk low
1.3 V to 1.3 V
See Figure 4
14
ns
Setup time, aux_data7–0 valid before zv_pix_clk high or low
1.3 V to 1.3 V
See Figure 4
10
ns
Hold time, aux_data7–0 valid after zv_pix_clk high or low
1.3 V to 1.3 V
See Figure 4
14
ns
Delay time, zv_hsync low, zv_vsync, zv_data_valid high after
zv_pix_clk low
1.3 V to 1.3 V
See Figure 5
–1
3
ns
td12
tsu9
Delay time, aux_data7–0 invalid after zv_pix_clk low
1.3 V to 1.3 V
See Figure 5
–1
5
ns
Setup time, zv_hsync low before zv_pix_clk high
1.3 V to 1.3 V
See Figure 6
25
ns
th6
Hold time, zv_hsync high after zv_pix_clk high
1.3 V to 1.3 V
See Figure 6
14
ns
tsu10
Setup time, zv_vsync high before zv_pix_clk high
1.3 V to 1.3 V
See Figure 6
10
ns
tsu11
Setup time, aux_data7–0 valid, zv_data_valid high before
zv_pix_clk high
1.3 V to 1.3 V
See Figure 6
25
ns
th7
Hold time, aux_data7–0 valid, zv_data-valid low after
zv_pix_clk high
1.3 V to 1.3 V
See Figure 6
14
ns
tsu8
th5
td11
10
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TSB12LV21A
(PCILynx) IEEE 1394-1995 BUS TO PCI BUS INTERFACE
SLLS273 – APRIL 1997
PARAMETER MEASUREMENT INFORMATION
pci_clk
td1
tsu1
th1
pci_xx
(Bidirectional
(see Note A)
td2
pci_intaz
tsu2
th1
pci_gntz
NOTE A: In this case, pci_xx refers to the following bidirectional signals; pci_ad31–0, pci_cbez3–0, pci_par, pci_framez,
pci_irdyz, pci_trdyz, pci_devselz, pci_stopz, pci_idselz, pci_perrz, pci_serrz, pci_reqz.
Figure 1. PCI Interface Timing Waveforms
phy_clk
td3
tsu3
th2
phy_xx
(Bidirectional
(see Note A)
td3
phy_lreq
td4
link_cycleout
tsu4
th2
link_cyclein
NOTE A: In this case, phy_xx refers to the following bidirectional signals; phy_ctl1–0, phy_data7–0.
Figure 2. Phy-Link Interface Timing Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
11
TSB12LV21A
(PCILynx) IEEE 1394-1995 BUS TO PCI BUS INTERFACE
SLLS273 – APRIL 1997
PARAMETER MEASUREMENT INFORMATION
OUTPUTS
aux_clk
ÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏ
td5
aux_adr15 – 0
aux_data15 – 0 (write)
aux_oez
(see Note A)
DATA VALID
td6
rom_csz
ram_csz
aux_csz
td7
DATA VALID
tsu5
td8
td9
td9
aux_wez0
aux_wez1
ÏÏÏÏÏÏ
ÏÏÏÏÏÏ
ÏÏÏÏÏÏ
td10
gpio_data7 – 0
INPUTS
Wait States = 0
Wait States > 0
DATA VALID
tsu6
ÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏ
th3
aux_data
DATA
VALID
aux_rdyz
DATA
VALID
gpio_data7 – 0
DATA
VALID
NOTE A: These signals are asserted asynchronlusly when a ZOOM port transfer immediately preceeds the local bus transfer. In all cases,
the setup time to aux_wez and the number of waitstates reamins valid.
Figure 3. Local Bus Timing Waveforms
12
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TSB12LV21A
(PCILynx) IEEE 1394-1995 BUS TO PCI BUS INTERFACE
SLLS273 – APRIL 1997
PARAMETER MEASUREMENT INFORMATION
15 ns
15 ns
Internal
Clock Source
internal
zv_pix_clk
zv_pix_clk
(gated, 8 bit)
tsu7
th4
zv_hsync
zv_vsync
zv_data_valid
aux_data15–0
(Write)
ÏÏÏÏÏÏ
ÏÏÏÏÏÏ
tsu8
th5
8-BIT DATA VALID
tsu8
th5
8-BIT DATA VALID
ÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏ
NOTES: A. The data is in 8-bit mode and zv_pix_clk is in divide-by-2 mode.
B. The timing for these waveforms is for write access to zoom address space.
C. The aux_datax signal meets timing while the zv_data_valid signal is asserted. The aux_datax signal can be asynchronous to
zv_pix_clk at other times.
D. The polarity of zv_pix_clk depends on the setting of the invert_zv_clk register bit. The polarity shown in this figure is with
invert_zv_clk = 0.
E. The timing of these waveforms is with a 30-ns source clock and a 50/50 duty cycle.
Figure 4. Zoom Video IF Timing Waveforms (8 Bit, Divide-By-2 Mode)
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
13
TSB12LV21A
(PCILynx) IEEE 1394-1995 BUS TO PCI BUS INTERFACE
SLLS273 – APRIL 1997
PARAMETER MEASUREMENT INFORMATION
Internal
zv_pix_clk
zv_pix_clk
(gated, 16 bit)
td11
td11
zv_hsync
zv_vsync
zv_data_valid
aux_data15–0
(16 bit only)
ÏÏÏÏ
ÏÏÏÏ
td12
td12
16-BIT DATA VALID
ÏÏÏÏÏÏ
ÏÏÏÏÏÏ
NOTES: A. The data is in 16-bit mode and zv_pix_clk is in divide-by-1 mode.
B. The timing for these waveforms is for write access to zoom address space.
C. The aux_datax signal meets timing while the zv_data_valid signal is asserted. The aux_datax signal can be asynchronous to
zv_pix_clk at other times.
D. The polarity of zv_pix_clk depends on the setting of the invert_zv_clk register bit. The polarity shown in this figure is with
invert_zv_clk = 0.
Figure 5. Zoom Video IF Timing Waveforms (16 Bit, Divide-By-1 Mode)
14
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TSB12LV21A
(PCILynx) IEEE 1394-1995 BUS TO PCI BUS INTERFACE
SLLS273 – APRIL 1997
PARAMETER MEASUREMENT INFORMATION
15 ns
15 ns
Internal
Clock Source
Internal
zv_pix_clk
(see Note A)
zv_pix_clk
(gated, 16 bit)
tsu9
th6
zv_hsync
tsu10
zv_vsync
zv_data_valid
aux_data15–0
(Write)
ÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏ
tsu9
th7
16-BIT DATA VALID
ÏÏÏÏÏ
ÏÏÏÏÏ
NOTES: A. The data is in 16-bit mode and zv_pix_clk is in divide-by-2 mode.
B. The timing for these waveforms is for write access to zoom address space.
C. The aux_datax signal meets timing while the zv_data_valid signal is asserted. The aux_datax signal can be asynchronous to
zv_pix_clk at other times.
D. The polarity of zv_pix_clk depends on the setting of the invert_zv_clk terminal. The polarity shown in this figure is with
invert_zv_clk = 0.
E. The timing of these waveforms is with a 30-ns source clock and a 50/50 duty cycle.
Figure 6. Zoom Video IF Timing Waveforms (16 Bit, Divide-By-2 Mode)
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
15
TSB12LV21A
(PCILynx) IEEE 1394-1995 BUS TO PCI BUS INTERFACE
SLLS273 – APRIL 1997
APPLICATION INFORMATION
power supply sequencing
Turning power supplies on and off within a mixed 5-V/3.3-V system is an important consideration. A few basic
rules need to be observed to avoid damaging PCILynx devices. Check with the manufacturers of all components
used in the 3.3-V to 5-V interface to ensure that no unique device characteristics exist that would lead to more
restrictive rules.
D
D
D
D
D
When the 3.3-V supply is turned on before turning on the 5-V supply. PCILynx output buffers in a logic 1
state can supply large amounts of current through their clamp diodes to the 5-V supply terminals (5V VCC ).
This can lead to excessive power dissipation and violation of current density limits. However, if the 5-V
supply is turned on before the 3.3-V supply, the maximum drain-to-gate voltage of the n-channel transistors
in the 5-V tolerant buffers exceeds the recommended value and the effects of channel-hot carries can be
accelerated.
When turning on the power supply, all 3.3-V and 5-V supplies should start ramping up from 0 V and reach
95% of their end-point values within a 25-ms time window. All bus contention between the PCILynx and
external devices is eliminated by the end of the 25-ms time window. The preferred order of supply ramping
is to ramp the 3.3-V supply followed by the 5-V supply. This order is not mandatory, but it allows a larger
cumulative number of power-supply events than the reverse order.
When turning off the power supply, all 3.3-V and 5-V supplies should start ramping down from steady state
values and reach 5% of these values within a 25-ms window. All bus contention between the PCILynx and
external devices is eliminated by the end of the 25-ms time window. The preferred order of supply ramping
is to ramp down the 5-V supply followed by the 3.3-V supply. This order is not mandatory, but it allows a
larger cumulative number of power-supply off events than the reverse order.
A cumulative total of 250 seconds of power supply turn-on and turn-off events is allowed during the
operating lifetime of the PCILynx under worst-case conditions. Worst-case conditions are where the 5-V
supply is ramped up before the 3.3-V supply and the 3.3-V supply is ramped down before the 5-V supply.
If the maximum time window of the 25 ms is used, a total of 10,000 power supply on or off events can occur
as long as the 25-ms time window is observed.
An additional precaution must be observed when the PCILynx is connected to a 5-V IEEE 1394
physical-layer device that is powered from the 1394 cable. In this case, it is possible for the physical-layer
device to have power while the PCILynx does not. It is essential that the physical-layer device must not
supply a high signal on any terminal that connects to the PCILynx while the PCILynx power is off. This is
normally achieved through the use of the link-power status terminal on the physical-layer device.
If any of these precautions and guidelines are not followed, the PCILynx device can experience possible failures
related to overheating, accumulation of channel-hot carriers, and/or metal migration due to excessive current
density.
16
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TSB12LV21A
(PCILynx) IEEE 1394-1995 BUS TO PCI BUS INTERFACE
SLLS273 – APRIL 1997
MECHANICAL INFORMATION
PGF (S-PQFP-G176)
PLASTIC QUAD FLATPACK
132
89
88
133
0,27
0,17
0,08 M
0,50
0,13 NOM
176
45
1
44
Gage Plane
21,50 SQ
24,20
SQ
23,80
26,20
SQ
25,80
0,25
0,05 MIN
0°– 7°
0,75
0,45
1,45
1,35
Seating Plane
0,08
1,60 MAX
4040134 / B 03/95
NOTES: F. All linear dimensions are in millimeters.
G. This drawing is subject to change without notice.
H. Falls within JEDEC MO-136
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
17
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