TI SN74HCT377DWR

SN54HCT377, SN74HCT377
OCTAL D-TYPE FLIP-FLOPS
WITH CLOCK ENABLE
SCLS067D – NOVEMBER 1988 – REVISED MARCH 2003
D
D
D
D
D
D
D
D
Operating Voltage Range of 4.5 V to 5.5 V
Outputs Can Drive Up To 10 LSTTL Loads
Low Power Consumption, 80-µA Max ICC
Typical tpd = 12 ns
±4-mA Output Drive at 5 V
Low Input Current of 1 µA Max
Inputs Are TTL-Voltage Compatible
D
D
Contain Eight Flip-Flops With Single-Rail
Outputs
Clock Enable Latched to Avoid False
Clocking
Applications Include:
– Buffer/Storage Registers
– Shift Registers
– Pattern Generators
SN54HCT377 . . . FK PACKAGE
(TOP VIEW)
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
VCC
8Q
8D
7D
7Q
6Q
6D
5D
5Q
CLK
2D
2Q
3Q
3D
4D
4
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
8D
7D
7Q
6Q
6D
4Q
GND
CLK
5Q
5D
CLKEN
1Q
1D
2D
2Q
3Q
3D
4D
4Q
GND
1D
1Q
CLKEN
VCC
8Q
SN54HCT377 . . . J OR W PACKAGE
SN74HCT377 . . . DW OR N PACKAGE
(TOP VIEW)
description/ordering information
These devices are positive-edge-triggered D-type flip-flops. The ’HCT377 devices are similar to the ’HCT273
devices, but feature a latched clock-enable (CLKEN) input instead of a common clear.
Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the
positive-going edge of the clock (CLK) pulse if CLKEN is low. Clock triggering occurs at a particular voltage level
and is not directly related to the transition time of the positive-going pulse. When CLK is at either the high or
low level, the D input has no effect at the output. These devices are designed to prevent false clocking by
transitions at CLKEN.
ORDERING INFORMATION
PDIP – N
–40°C to 85°C
–55°C to 125°C
ORDERABLE
PART NUMBER
PACKAGE†
TA
TOP-SIDE
MARKING
Tube
SN74HCT377N
Tube
SN74HCT377DW
Tape and reel
SN74HCT377DWR
CDIP – J
Tube
SNJ54HCT377J
SNJ54HCT377J
CFP – W
Tube
SNJ54HCT377W
SNJ54HCT377W
LCCC – FK
Tube
SNJ54HCT377FK
SOIC – DW
SN74HCT377N
HCT377
SNJ54HCT377FK
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2003, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN54HCT377, SN74HCT377
OCTAL D-TYPE FLIP-FLOPS
WITH CLOCK ENABLE
SCLS067D – NOVEMBER 1988 – REVISED MARCH 2003
FUNCTION TABLE
(each flip-flop)
INPUTS
D
OUTPUT
Q
X
X
Q0
↑
H
H
CLKEN
CLK
H
L
L
↑
L
L
X
L
X
Q0
logic diagram (positive logic)
CLKEN
CLK
1
11
C1
1D
3
C1
2D
4
3D
4D
13
6D
7D
2
18
16
1D
C1
8D
15
1D
C1
17
12
1D
C1
14
9
1D
C1
5D
6
1D
C1
8
5
1D
C1
7
2
1D
1D
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
19
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
SN54HCT377, SN74HCT377
OCTAL D-TYPE FLIP-FLOPS
WITH CLOCK ENABLE
SCLS067D – NOVEMBER 1988 – REVISED MARCH 2003
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Package thermal impedance, θJA (see Note 2): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
SN54HCT377
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.5
5
5.5
VCC
VIH
Supply voltage
VIL
VI
Low-level input voltage
Input voltage
0
VO
tt
Output voltage
0
High-level input voltage
VCC = 4.5 V to 5.5 V
VCC = 4.5 V to 5.5 V
SN74HCT377
2
2
Input transition (rise and fall) times
V
V
0.8
VCC
VCC
UNIT
0
0
500
0.8
V
VCC
VCC
V
500
ns
V
TA
Operating free-air temperature
–55
125
–40
85
°C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TA = 25°C
TYP
MAX
SN54HCT377
MIN
MAX
SN74HCT377
MIN
MAX
UNIT
VOH
VI = VIH or VIL
IOH = –20 µA
IOH = –4 mA
4.5 V
4.4
4.499
4.4
4.4
4.5 V
3.98
4.30
3.7
3.84
VOL
VI = VIH or VIL
IOL = 20 µA
IOL = 4 mA
4.5 V
0.001
0.1
0.1
0.1
4.5 V
0.17
0.26
0.4
0.33
II
ICC
VI = VCC or 0
VI = VCC or 0,
5.5 V
±0.1
±100
±1000
±1000
nA
8
160
80
µA
1.4
2.4
3
2.9
mA
3
10
10*
10
pF
∆ICC‡
IO = 0
One input at 0.5 V or 2.4 V,
Other inputs at GND or VCC
Ci
5.5 V
5.5 V
4.5 V to
5.5 V
V
V
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
‡ This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or VCC.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
SN54HCT377, SN74HCT377
OCTAL D-TYPE FLIP-FLOPS
WITH CLOCK ENABLE
SCLS067D – NOVEMBER 1988 – REVISED MARCH 2003
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
fclock
l k
Clock frequency
tw
Pulse duration
CLK high or low
Data
tsu
Setup time before CLK↑
↑
CLKEN high or low
Data
th
Hold time data after CLK↑
↑
CLKEN inactive or active
VCC
TA = 25°C
MIN
MAX
SN54HCT377
4.5 V
25
17
20
5.5 V
30
19
22
MIN
SN74HCT377
MAX
MIN
4.5 V
20
30
25
5.5 V
18
28
23
4.5 V
12
18
15
5.5 V
10
17
14
4.5 V
12
18
15
5.5 V
10
17
14
4.5 V
3
3
3
5.5 V
3
3
3
4.5 V
5
5
5
5.5 V
5
5
5
MAX
UNIT
MHz
ns
ns
ns
switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless
otherwise noted) (see Figure 1)
SN54HCT377
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
fmax
tpd
d
Any
CLK
tt
Any
VCC
TA = 25°C
MIN
TYP
MAX
MIN
4.5 V
25
31
17
5.5 V
30
37
19
MAX
UNIT
MHz
4.5 V
15
30
45
5.5 V
12
28
40
4.5 V
8
15
22
5.5 V
6
14
21
ns
ns
switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless
otherwise noted) (see Figure 1)
SN74HCT377
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC
MIN
fmax
tpd
d
Any
CLK
tt
Any
TA = 25°C
TYP
MAX
MIN
4.5 V
25
31
20
5.5 V
30
37
22
MAX
UNIT
MHz
4.5 V
15
30
38
5.5 V
12
28
35
4.5 V
8
15
19
5.5 V
6
14
17
ns
ns
operating characteristics, TA = 25°C
PARAMETER
Cpd
TEST CONDITIONS
Power dissipation capacitance
No load
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TYP
30
UNIT
pF
SN54HCT377, SN74HCT377
OCTAL D-TYPE FLIP-FLOPS
WITH CLOCK ENABLE
SCLS067D – NOVEMBER 1988 – REVISED MARCH 2003
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
Test
Point
3V
High-Level
Pulse
1.3 V
0V
CL = 50 pF
(see Note A)
tw
1.3 V
1.3 V
0V
VOLTAGE WAVEFORMS
PULSE DURATIONS
3V
1.3 V
3V
Low-Level
Pulse
LOAD CIRCUIT
Input
1.3 V
1.3 V
0V
tPLH
In-Phase
Output
1.3 V
10%
tPHL
90%
90%
tr
Out-ofPhase
Output
tPHL
90%
VOH Reference
1.3 V
Input
10% V
OL
tf
tPLH
1.3 V
10%
tf
1.3 V
10%
90%
VOH
Data
Input 1.3 V
0.3 V
3V
1.3 V
0V
tsu
2.7 V
VOL
tr
tr
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT RISE AND FALL TIMES
th
2.7 V
3V
1.3 V
0.3 V 0 V
tf
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
NOTES: A. CL includes probe and test-fixture capacitance.
B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
C. The outputs are measured one at a time with one input transition per measurement.
D. For clock inputs, fmax is measured when the input duty cycle is 50%.
E. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
PACKAGE OPTION ADDENDUM
www.ti.com
10-May-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
SN74HCT377DW
ACTIVE
SOIC
DW
20
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74HCT377DWE4
ACTIVE
SOIC
DW
20
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74HCT377DWG4
ACTIVE
SOIC
DW
20
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74HCT377DWR
ACTIVE
SOIC
DW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74HCT377DWRE4
ACTIVE
SOIC
DW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74HCT377DWRG4
ACTIVE
SOIC
DW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74HCT377N
ACTIVE
PDIP
N
20
20
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
SN74HCT377NE4
ACTIVE
PDIP
N
20
20
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
SN74HCT377DWR
Package Package Pins
Type Drawing
SOIC
DW
20
SPQ
Reel
Reel
Diameter Width
(mm) W1 (mm)
2000
330.0
24.4
Pack Materials-Page 1
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
10.8
13.0
2.7
12.0
24.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2008
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74HCT377DWR
SOIC
DW
20
2000
346.0
346.0
41.0
Pack Materials-Page 2
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