[ /Title (CD74H C4040, CD74HC T4040) /Subject (High Speed CMOS Logic 12-Stage Binary CD54HC4040, CD74HC4040, CD54HCT4040, CD74HCT4040 Data sheet acquired from Harris Semiconductor SCHS203D High-Speed CMOS Logic 12-Stage Binary Counter February 1998 - Revised October 2003 Features Description • Fully Static Operation The ’HC4040 and ’HCT4040 are 14-stage ripple-carry binary counters. All counter stages are master-slave flipflops. The state of the stage advances one count on the negative clock transition of each input pulse; a high voltage level on the MR line resets all counters to their zero state. All inputs and outputs are buffered. • Buffered Inputs • Common Reset • Negative Edge Pulsing • Fanout (Over Temperature Range) Ordering Information - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads PART NUMBER • Wide Operating Temperature Range . . . -55oC to 125oC TEMP. RANGE (oC) PACKAGE • Balanced Propagation Delay and Transition Times CD54HC4040F3A -55 to 125 16 Ld CERDIP • Significant Power Reduction Compared to LSTTL Logic ICs CD54HCT4040F3A -55 to 125 16 Ld CERDIP CD74HC4040E -55 to 125 16 Ld PDIP CD74HC4040M -55 to 125 16 Ld SOIC CD74HC4040MT -55 to 125 16 Ld SOIC CD74HC4040M96 -55 to 125 16 Ld SOIC CD74HC4040NSR -55 to 125 16 Ld SOP CD74HCT4040E -55 to 125 16 Ld PDIP CD74HCT4040M -55 to 125 16 Ld SOIC CD74HCT4040MT -55 to 125 16 Ld SOIC CD74HCT4040M96 -55 to 125 16 Ld SOIC • HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V • HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH NOTE: When ordering, use the entire part number. The suffixes 96 and R denote tape and reel. The suffix T denotes a small-quantity reel of 250. Pinout CD54HC4040, CD54HCT4040 (CERDIP) CD74HC4040 (PDIP, SOIC, SOP) CD74HCT4040 (PDIP, SOIC) TOP VIEW Q12 1 16 VCC Q6 2 15 Q11 Q5 3 14 Q10 Q7 4 13 Q8 Q4 5 12 Q9 Q3 6 11 MR Q2 7 10 CP GND 8 9 Q1‘ CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, Texas Instruments Incorporated 1 CD54HC4040, CD74HC4040, CD54HCT4040, CD74HCT4040 Functional Diagram VCC 16 10 9 INPUT PULSES 7 6 5 3 12-STAGE RIPPLE COUNTER 2 4 13 12 14 15 1 11 MASTER RESET Q1’ Q2 Q3 Q4 Q5 Q6 BUFFERED OUTPUTS Q7 Q8 Q9 Q10 Q11 Q12 8 GND TRUTH TABLE CP COUNT MR OUTPUT STATE ↑ L No Change ↓ L Advance to Next State X H All Outputs Are Low H = High Voltage Level, L = Low Voltage Level, X = Don’t Care, ↑ = Transition from Low to High Level, ↓ = Transition from High to Low. 2 MR CP 11 10 Q1’ R R 9 CP Q 2 CP Q CP Q I Q’ CP Q Q2 7 R CP Q 3 CP Q Q3 6 R CP Q 4 CP Q Q4 5 R CP Q 5 CP Q Q5 3 R CP Q 6 CP Q Q6 2 R CP Q 7 CP Q Q7 4 R CP Q 8 CP Q Q8 13 R CP Q 9 CP Q Q9 12 R CP Q 10 CP Q Q10 14 R CP Q 11 CP Q Q11 15 R CP Q 12 CP Q Q12 1 CD54/74HC4040, CD54/74HCT4040 Logic Diagram 3 CD54HC4040, CD74HC4040, CD54HCT4040, CD74HCT4040 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA Package Thermal Impedance, θJA (see Note 1): E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67oC/W M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73oC/W NS (SOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64oC/W Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. The package thermal impedance is calculated in accordance with JESD 51-7. DC Electrical Specifications TEST CONDITIONS PARAMETER 25oC -40oC TO 85oC -55oC TO 125oC SYMBOL VI (V) IO (mA) VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS VIH - - 2 1.5 - - 1.5 - 1.5 - V 4.5 3.15 - - 3.15 - 3.15 - V 6 4.2 - - 4.2 - 4.2 - V HC TYPES High Level Input Voltage Low Level Input Voltage High Level Output Voltage CMOS Loads VIL VOH - VIH or VIL High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads VOL VIH or VIL Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current - 2 - - 0.5 - 0.5 - 0.5 V 4.5 - - 1.35 - 1.35 - 1.35 V 6 - - 1.8 - 1.8 - 1.8 V -0.02 2 1.9 - - 1.9 - 1.9 - V -0.02 4.5 4.4 - - 4.4 - 4.4 - V -0.02 6 5.9 - - 5.9 - 5.9 - V - - - - - - - - - V -4 4.5 3.98 - - 3.84 - 3.7 - V -5.2 6 5.48 - - 5.34 - 5.2 - V 0.02 2 - - 0.1 - 0.1 - 0.1 V 0.02 4.5 - - 0.1 - 0.1 - 0.1 V 0.02 6 - - 0.1 - 0.1 - 0.1 V - - - - - - - - - V 4 4.5 - - 0.26 - 0.33 - 0.4 V 5.2 6 - - 0.26 - 0.33 - 0.4 V II VCC or GND - 6 - - ±0.1 - ±1 - ±1 µA ICC VCC or GND 0 6 - - 8 - 80 - 160 µA 4 CD54HC4040, CD74HC4040, CD54HCT4040, CD74HCT4040 DC Electrical Specifications (Continued) TEST CONDITIONS 25oC -40oC TO 85oC -55oC TO 125oC SYMBOL VI (V) IO (mA) VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS High Level Input Voltage VIH - - 4.5 to 5.5 2 - - 2 - 2 - V Low Level Input Voltage VIL - - 4.5 to 5.5 - - 0.8 - 0.8 - 0.8 V High Level Output Voltage CMOS Loads VOH VIH or VIL -0.02 4.5 4.4 - - 4.4 - 4.4 - V -4 4.5 3.98 - - 3.84 - 3.7 - V 0.02 4.5 - - 0.1 - 0.1 - 0.1 V 4 4.5 - - 0.26 - 0.33 - 0.4 V PARAMETER HCT TYPES High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads VOL VIH or VIL Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current Additional Quiescent Device Current Per Input Pin: 1 Unit Load II VCC and GND 0 5.5 - - ±0.1 - ±1 - ±1 µA ICC VCC or GND 0 5.5 - - 8 - 80 - 160 µA ∆ICC (Note 2) VCC -2.1 - 4.5 to 5.5 - 100 360 - 450 - 490 µA NOTE: 2. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA. HCT Input Loading Table INPUT UNIT LOADS MR 0.65 CP 0.5 NOTE: Unit Load is ∆ICC limit specified in DC Electrical Table, e.g., 360µA max at 25oC. Prerequisite for Switching Specifications 25oC PARAMETER SYMBOL VCC (V) MIN -40oC TO 85oC MAX MIN MAX -55oC TO 125oC MIN MAX UNITS HC TYPES Maximum Input Pulse Frequency Input Pulse Width fMAX tW 2 6 - 5 - 4 - MHz 4.5 30 - 25 - 20 - MHz 6 35 - 29 - 24 - MHz 2 80 - 100 - 120 - ns 4.5 16 - 20 - 24 - ns 6 14 - 17 - 20 - ns 5 CD54HC4040, CD74HC4040, CD54HCT4040, CD74HCT4040 Prerequisite for Switching Specifications (Continued) 25oC PARAMETER Reset Removal Time Reset Pulse Width -40oC TO 85oC -55oC TO 125oC SYMBOL VCC (V) MIN MAX MIN MAX MIN MAX UNITS tREM 2 50 - 65 - 75 - ns 4.5 10 - 13 - 15 - ns 6 9 - 11 - 13 - ns 2 80 - 100 - 120 - ns 4.5 16 - 20 - 24 - ns 6 14 - 17 - 20 - ns fMAX 4.5 25 - 20 - 16 - MHz tW 4.5 20 - 25 - 30 - ns tREM 4.5 10 - 13 - 15 - ns tW 4.5 20 - 25 - 30 - ns tW HCT TYPES Maximum Input Pulse Frequency Input Pulse Width Reset Recovery Time Reset Pulse Width Switching Specifications Input tr, tf = 6ns PARAMETER SYMBOL TEST CONDITIONS -40oC TO 85oC 25oC -55oC TO 125oC VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS 2 - - 140 - 175 - 210 ns 4.5 - - 28 - 35 - 42 ns CL =15pF 5 - 11 - - - - - ns CL = 50pF 6 - - 24 - 30 - 36 ns tPLH, tPHL CL = 50pF 2 - - 75 - 95 - 110 ns 4.5 - - 15 - 19 - 22 ns CL =15pF 5 - 4 - - - - - ns CL = 50pF 6 - - 13 - 16 - 19 ns tPLH, tPHL CL = 50pF 2 - - 170 - 215 - 255 ns 4.5 - - 34 - 43 - 51 ns 5 - 14 - - - - - ns 6 - - 29 - 37 - 43 ns 2 - - 75 - 95 - 110 ns 4.5 - - 15 - 19 - 22 ns 6 - - 13 - 16 - 19 ns HC TYPES Propagation Delay (Figure 1) tPLH, tPHL CL = 50pF CP to Q1’ Output Qn to Qn + 1 MR to Qn Output Transition Time (Figure 1) tTLH, tTHL CL = 50pF Input Capacitance CIN CL = 50pF - - - 10 - 10 - 10 pF Power Dissipation Capacitance (Notes 3, 4) CPD CL =15pF 5 - 40 - - - - - pF 4.5 - - 40 - 50 - 60 ns 5 - 17 - - - - - ns HCT TYPES Propagation Delay (Figure 1) CP to Q1’ Output tPLH, tPHL CL = 50pF CL =15pF 6 CD54HC4040, CD74HC4040, CD54HCT4040, CD74HCT4040 Switching Specifications Input tr, tf = 6ns PARAMETER SYMBOL Qn to Qn + 1 (Continued) TEST CONDITIONS tPLH, tPHL CL = 50pF tPLH, tPHL CL = 50pF MIN TYP MAX MIN MAX MIN MAX UNITS 4.5 - - 15 - 19 - 22 ns 5 - 4 - - - - - ns 4.5 - - 40 - 50 - 60 ns 5 - 17 - - - - - ns 4.5 - - 15 - 19 - 22 ns CL =15pF Output Transition tTLH, tTHL CL = 50pF -55oC TO 125oC VCC (V) CL =15pF MR to Qn -40oC TO 85oC 25oC Input Capacitance CIN CL =15pF - - - 10 - 10 - 10 pF Power Dissipation Capacitance (Notes 3, 4) CPD CL =15pF 5 - 45 - - - - - pF NOTES: 3. CPD is used to determine the dynamic power consumption, per package. 4. PD = VCC2 fi + ∑ (CLVCC2 fi/M) where: M = 21, 22, 23, ...212, fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage. Test Circuits and Waveforms tfCL trCL CLOCK tWL + tWH = 90% 10% I fCL CLOCK 50% 50% 1.3V 0.3V tf = 6ns tr = 6ns VCC 90% 50% 10% GND tTLH 3V 2.7V 1.3V 0.3V INPUT GND tTHL 90% 50% 10% INVERTING OUTPUT tWH FIGURE 2. HCT CLOCK PULSE RISE AND FALL TIMES AND PULSE WIDTH tf = 6ns tTHL GND NOTE: Outputs should be switching from 10% VCC to 90% VCC in accordance with device truth table. For fMAX, input duty cycle = 50%. FIGURE 1. HC CLOCK PULSE RISE AND FALL TIMES AND PULSE WIDTH tr = 6ns I fCL 1.3V 1.3V tWL tWH NOTE: Outputs should be switching from 10% VCC to 90% VCC in accordance with device truth table. For fMAX, input duty cycle = 50%. tPHL 2.7V 0.3V GND tWL INPUT tfCL = 6ns 3V VCC 50% 10% tWL + tWH = trCL = 6ns tTLH 90% 1.3V 10% INVERTING OUTPUT tPHL tPLH FIGURE 3. HC TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC tPLH FIGURE 4. HCT TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC 7 CD54HC4040, CD74HC4040, CD54HCT4040, CD74HCT4040 Test Circuits and Waveforms trCL tfCL trCL CLOCK INPUT (Continued) VCC 90% GND tH(H) GND tH(H) VCC DATA INPUT 50% tH(L) 3V 1.3V 1.3V 1.3V GND tSU(H) tSU(H) tSU(L) tTLH 90% OUTPUT tTHL 90% 50% 10% tTLH 90% 1.3V OUTPUT tREM 3V SET, RESET OR PRESET GND tTHL 1.3V 10% FIGURE 5. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME, AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED SEQUENTIAL LOGIC CIRCUITS tPHL 1.3V GND IC CL 50pF GND 90% tPLH 50% IC tSU(L) tPHL tPLH tREM VCC SET, RESET OR PRESET 1.3V 0.3V tH(L) DATA INPUT 3V 2.7V CLOCK INPUT 50% 10% tfCL CL 50pF FIGURE 6. HCT SETUP TIMES, HOLD TIMES, REMOVAL TIME, AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED SEQUENTIAL LOGIC CIRCUITS 8 PACKAGE OPTION ADDENDUM www.ti.com 4-Jun-2007 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty 5962-8994701MEA ACTIVE CDIP J 16 1 TBD A42 SNPB N / A for Pkg Type CD54HC4040F ACTIVE CDIP J 16 1 TBD A42 SNPB N / A for Pkg Type Lead/Ball Finish MSL Peak Temp (3) CD54HC4040F3A ACTIVE CDIP J 16 1 TBD A42 SNPB N / A for Pkg Type CD54HCT4040F3A ACTIVE CDIP J 16 1 TBD A42 SNPB N / A for Pkg Type CD74HC4040E ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type CD74HC4040EE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type CD74HC4040M ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC4040M96 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC4040M96E4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC4040M96G4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC4040ME4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC4040MG4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC4040MT ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC4040MTE4 ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC4040MTG4 ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC4040NSR ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC4040NSRE4 ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC4040NSRG4 ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT4040E ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type CD74HCT4040EE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type CD74HCT4040M ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT4040M96 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT4040M96E4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT4040M96G4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT4040ME4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT4040MG4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT4040MT ACTIVE SOIC D 16 250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 4-Jun-2007 Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty CD74HCT4040MTE4 ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT4040MTG4 ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Lead/Ball Finish MSL Peak Temp (3) no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 16-Jul-2007 TAPE AND REEL INFORMATION Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com Device 16-Jul-2007 Package Pins Site Reel Diameter (mm) Reel Width (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant CD74HC4040M96 D 16 FMX 330 16 6.5 10.3 2.1 8 16 Q1 CD74HC4040NSR NS 16 MLA 330 16 8.2 10.5 2.5 12 16 Q1 CD74HCT4040M96 D 16 FMX 330 16 6.5 10.3 2.1 8 16 Q1 TAPE AND REEL BOX INFORMATION Device Package Pins Site Length (mm) Width (mm) Height (mm) CD74HC4040M96 D 16 FMX 342.9 336.6 28.58 CD74HC4040NSR NS 16 MLA 346.0 346.0 33.0 CD74HCT4040M96 D 16 FMX 342.9 336.6 28.58 Pack Materials-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 16-Jul-2007 Pack Materials-Page 3 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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