TI CD74HC4024M

[ /Title
(CD74
HC402
4,
CD74
HCT40
24)
/Subject
(High
Speed
CMOS
CD54HC4024, CD74HC4024,
CD54HCT4024, CD74HCT4024
Data sheet acquired from Harris Semiconductor
SCHS202C
High-Speed CMOS Logic
7-Stage Binary Ripple Counter
November 1997 - Revised October 2003
Features
Description
• Fully Static Operation
The ’HC4024 and ’HCT4024 are 7-stage ripple-carry binary
counters. All counter stages are master-slave flip-flops. The
state of the stage advances one count on the negative
transition of each input pulse; a high voltage level on the MR
line resets all counters to their zero state. All inputs and
outputs are buffered.
• Buffered Inputs
• Common Reset
• Negative Edge Clocking
• Fanout (Over Temperature Range)
Ordering Information
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
PART NUMBER
• Wide Operating Temperature Range . . . -55oC to 125oC
TEMP. RANGE
(oC)
PACKAGE
• Balanced Propagation Delay and Transition Times
CD54HC4024F3A
-55 to 125
14 Ld CERDIP
• Significant Power Reduction Compared to LSTTL
Logic ICs
CD54HCT4024F3A
-55 to 125
14 Ld CERDIP
CD74HC4024E
-55 to 125
14 Ld PDIP
CD74HC4024M
-55 to 125
14 Ld SOIC
CD74HC4024MT
-55 to 125
14 Ld SOIC
CD74HC4024M96
-55 to 125
14 Ld SOIC
CD74HC4024PW
-55 to 125
14 Ld TSSOP
CD74HC4024PWR
-55 to 125
14 Ld TSSOP
CD74HC4024PWT
-55 to 125
14 Ld TSSOP
CD74HCT4024E
-55 to 125
14 Ld PDIP
CD74HCT4024M
-55 to 125
14 Ld SOIC
• HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC
at VCC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH
NOTE: When ordering, use the entire part number. The suffixes 96
and R denote tape and reel. The suffix T denotes a small-quantity
reel of 250.
Pinout
CD54HC4024, CD54HCT4024
(CERDIP)
CD74HC4024
(PDIP, SOIC, TSSOP)
CD74HCT4024
(PDIP, SOIC)
TOP VIEW
CP 1
14 VCC
MR 2
13 NC
Q7 3
12 Q1’
Q6 4
11 Q2
Q5 5
10 NC
Q4 6
9 Q3
GND 7
8 NC
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
© 2003, Texas Instruments Incorporated
1
CD54HC4024, CD74HC4024, CD54HCT4024, CD74HCT4024
Functional Diagram
12
CP
Q1’
11
1
Q2
9
Q3
6
Q4
5
Q5
4
2
MR
Q6
3
Q7
TRUTH TABLE
CP COUNT
MR
OUTPUT STATE
↑
L
No Change
↓
L
Advance to Next State
X
H
All Outputs Are Low
H = High Voltage Level, L = Low Voltage Level, X = Don’t Care,
↑ = Transition from Low to High Level, ↓ = Transition from High to Low.
Logic Diagram
1
CP Q
CP
CP Q
CP Q
CP Q
CP Q
CP Q
CP Q
2
3
4
5
6
7
CP Q
CP Q
CP Q
CP Q
CP Q
CP Q
CP Q
R
R
R
R
R
R
R
1 Q1
2
MR
7
GND
14
VCC
12
Q1’
11
Q2
9
Q3
2
6
Q4
5
Q5
4
Q6
3
Q7
CD54HC4024, CD74HC4024, CD54HCT4024, CD74HCT4024
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, IIK
For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, IOK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Source or Sink Current per Output Pin, IO
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA
Thermal Resistance (Typical, Note 1)
θJA (oC/W)
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . .
80
M (SOIC) Package . . . . . . . . . . . . . . . . . . . . . . . .
86
PW (TSSOP) Package. . . . . . . . . . . . . . . . . . . . . .
113
(Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
Operating Conditions
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, VCC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
TEST
CONDITIONS
PARAMETER
25oC
-40oC TO 85oC -55oC TO 125oC
SYMBOL
VI (V)
IO (mA)
VCC
(V)
VIH
-
-
2
1.5
-
-
1.5
4.5
3.15
-
-
3.15
-
3.15
-
V
6
4.2
-
-
4.2
-
4.2
-
V
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
-
1.5
-
V
HC TYPES
High Level Input
Voltage
Low Level Input
Voltage
High Level Output
Voltage
CMOS Loads
VIL
VOH
-
VIH or VIL
High Level Output
Voltage
TTL Loads
Low Level Output
Voltage
CMOS Loads
VOL
VIH or VIL
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
Quiescent Device
Current
-
2
-
-
0.5
-
0.5
-
0.5
V
4.5
-
-
1.35
-
1.35
-
1.35
V
6
-
-
1.8
-
1.8
-
1.8
V
-0.02
2
1.9
-
-
1.9
-
1.9
-
V
-0.02
4.5
4.4
-
-
4.4
-
4.4
-
V
-0.02
6
5.9
-
-
5.9
-
5.9
-
V
-
-
-
-
-
-
-
-
-
V
-4
4.5
3.98
-
-
3.84
-
3.7
-
V
-5.2
6
5.48
-
-
5.34
-
5.2
-
V
0.02
2
-
-
0.1
-
0.1
-
0.1
V
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
0.02
6
-
-
0.1
-
0.1
-
0.1
V
-
-
-
-
-
-
-
-
-
V
4
4.5
-
-
0.26
-
0.33
-
0.4
V
5.2
6
-
-
0.26
-
0.33
-
0.4
V
II
VCC or
GND
-
6
-
-
±0.1
-
±1
-
±1
µA
ICC
VCC or
GND
0
6
-
-
8
-
80
-
160
µA
3
CD54HC4024, CD74HC4024, CD54HCT4024, CD74HCT4024
DC Electrical Specifications
(Continued)
TEST
CONDITIONS
SYMBOL
VI (V)
IO (mA)
High Level Input
Voltage
VIH
-
-
Low Level Input
Voltage
VIL
-
High Level Output
Voltage
CMOS Loads
VOH
VIH or VIL
PARAMETER
25oC
VCC
(V)
-40oC TO 85oC -55oC TO 125oC
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
4.5 to
5.5
2
-
-
2
-
2
-
V
-
4.5 to
5.5
-
-
0.8
-
0.8
-
0.8
V
-0.02
4.5
4.4
-
-
4.4
-
4.4
-
V
-4
4.5
3.98
-
-
3.84
-
3.7
-
V
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
4
4.5
-
-
0.26
-
0.33
-
0.4
V
HCT TYPES
High Level Output
Voltage
TTL Loads
Low Level Output
Voltage
CMOS Loads
VOL
VIH or VIL
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
Quiescent Device
Current
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
II
VCC and
GND
0
5.5
-
-
±0.1
-
±1
-
±1
µA
ICC
VCC or
GND
0
5.5
-
-
8
-
80
-
160
µA
∆ICC
(Note 2)
VCC
-2.1
-
4.5 to
5.5
-
100
360
-
450
-
490
µA
NOTE:
2. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.
HCT Input Loading Table
INPUT
UNIT LOADS
CP, MR
0.5
NOTE: Unit Load is ∆ICC limit specified in DC Electrical Table, e.g.,
360µA max at 25oC.
Prerequisite for Switching Specifications
25oC
PARAMETER
SYMBOL
VCC (V)
MIN
-40oC TO 85oC
MAX
MIN
MAX
-55oC TO 125oC
MIN
MAX
UNITS
HC TYPES
Maximum Input Pulse
Frequency
Input Pulse Width
Reset Removal Time
fMAX
tW
tREM
2
6
-
5
-
4
-
MHz
4.5
30
-
24
-
20
-
MHz
6
35
-
29
-
24
-
MHz
2
80
-
100
-
120
-
ns
4.5
16
-
20
-
24
-
ns
6
14
-
17
-
20
-
ns
2
50
-
65
-
75
-
ns
4.5
10
-
13
-
15
-
ns
6
9
-
11
-
13
-
ns
4
CD54HC4024, CD74HC4024, CD54HCT4024, CD74HCT4024
Prerequisite for Switching Specifications
(Continued)
25oC
PARAMETER
Reset Pulse Width
-40oC TO 85oC
-55oC TO 125oC
SYMBOL
VCC (V)
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
tW
2
80
-
100
-
120
-
ns
4.5
16
-
20
-
24
-
ns
6
14
-
17
-
20
-
ns
fMAX
4.5
25
-
20
-
16
-
MHz
tW
4.5
20
-
25
-
30
-
ns
tREC
4.5
10
-
13
-
15
-
ns
tW
4.5
20
-
25
-
30
-
ns
HCT TYPES
Maximum Input Pulse
Frequency
Input Pulse Width
Reset Recovery Time
Reset Pulse Width
Switching Specifications Input tr, tf = 6ns
PARAMETER
TEST
SYMBOL CONDITIONS
25oC
-40oC TO 85oC -55oC TO 125oC
VCC
(V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
2
-
-
140
-
175
-
210
ns
4.5
-
-
28
-
35
-
42
ns
CL =15pF
5
-
11
-
-
-
-
-
ns
CL = 50pF
6
-
-
24
-
30
-
36
ns
CL = 50pF
2
-
-
75
-
95
-
110
ns
4.5
-
-
15
-
19
-
22
ns
CL =15pF
5
-
6
-
-
-
-
-
ns
CL = 50pF
6
-
-
13
-
13
-
19
ns
CL = 50pF
2
-
-
170
-
215
-
255
ns
4.5
-
-
34
-
43
-
51
ns
5
-
14
-
-
-
-
-
ns
6
-
-
29
-
27
-
43
ns
2
-
-
75
-
95
-
110
ns
4.5
-
-
15
-
19
-
22
ns
6
-
-
13
-
16
-
19
ns
HC TYPES
Propagation Delay Time
(Figure 1)
tPLH,
tPHL
CL = 50pF
CP to Q1’ Output
Qn to Qn + 1
MR to Qn
Output Transition Time
(Figure 1)
tPLH,
tPHL
tPLH,
tPHL
tTLH, tTHL CL = 50pF
Input Capacitance
CIN
CL = 50pF
-
-
-
10
-
10
-
10
pF
Power Dissipation Capacitance
(Notes 3, 4)
CPD
CL =15pF
5
-
30
-
-
-
-
-
pF
tPLH,
tPHL
CL = 50pF
4.5
-
-
40
-
50
-
60
ns
CL =15pF
5
-
17
-
-
-
-
-
ns
tPLH,
tPHL
CL = 50pF
4.5
-
-
15
-
19
-
22
ns
CL =15pF
5
-
6
-
-
-
-
-
ns
tPLH,
tPHL
CL = 50pF
4.5
-
-
40
-
50
-
60
ns
CL =15pF
5
-
17
-
-
-
-
-
ns
HCT TYPES
Propagation Delay Time
(Figure 2)
CP to Q1’ Output
Qn to Qn + 1
MR to Qn
5
CD54/74HC4024, CD54/74HCT4024
Switching Specifications Input tr, tf = 6ns
PARAMETER
Output Transition
(Continued)
25oC
-40oC TO 85oC -55oC TO 125oC
TEST
SYMBOL CONDITIONS
VCC
(V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
tTLH, tTHL CL = 50pF
4.5
-
-
15
-
19
-
22
ns
Input Capacitance
CIN
CL =15pF
-
-
-
10
-
10
-
10
pF
Power Dissipation Capacitance
(Notes 3, 4)
CPD
CL =15pF
5
-
30
-
-
-
-
-
pF
NOTES:
3. CPD is used to determine the dynamic power consumption, per package.
4. PD = VCC2 fi + ∑ (CLVCC2 fi/M) where: M = 21, 22, 23, 24,25, 26, 27 fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply
Voltage.
Test Circuits and Waveforms
tfCL
trCL
CLOCK
tWL + tWH =
90%
10%
I
fCL
CLOCK
50%
50%
1.3V
0.3V
tf = 6ns
tr = 6ns
VCC
90%
50%
10%
GND
tTLH
3V
2.7V
1.3V
0.3V
INPUT
GND
tTHL
90%
50%
10%
INVERTING
OUTPUT
tWH
FIGURE 2. HCT CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
tf = 6ns
tTHL
GND
NOTE: Outputs should be switching from 10% VCC to 90% VCC in
accordance with device truth table. For fMAX, input duty cycle = 50%.
FIGURE 1. HC CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
tr = 6ns
I
fCL
1.3V
1.3V
tWL
tWH
NOTE: Outputs should be switching from 10% VCC to 90% VCC in
accordance with device truth table. For fMAX, input duty cycle = 50%.
tPHL
2.7V
0.3V
GND
tWL
INPUT
tfCL = 6ns
3V
VCC
50%
10%
tWL + tWH =
trCL = 6ns
tTLH
90%
1.3V
10%
INVERTING
OUTPUT
tPHL
tPLH
FIGURE 3. HC AND HCU TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC
tPLH
FIGURE 4. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
6
PACKAGE OPTION ADDENDUM
www.ti.com
9-Oct-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
Lead/Ball Finish
MSL Peak Temp (3)
CD54HC4024F
ACTIVE
CDIP
J
14
1
TBD
A42 SNPB
N / A for Pkg Type
CD54HC4024F3A
ACTIVE
CDIP
J
14
1
TBD
A42 SNPB
N / A for Pkg Type
CD54HCT4024F3A
ACTIVE
CDIP
J
14
1
TBD
A42 SNPB
N / A for Pkg Type
CD74HC4024E
ACTIVE
PDIP
N
14
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
CD74HC4024EE4
ACTIVE
PDIP
N
14
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
CD74HC4024M
ACTIVE
SOIC
D
14
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HC4024M96
ACTIVE
SOIC
D
14
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HC4024M96E4
ACTIVE
SOIC
D
14
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HC4024M96G4
ACTIVE
SOIC
D
14
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HC4024ME4
ACTIVE
SOIC
D
14
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HC4024MG4
ACTIVE
SOIC
D
14
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HC4024MT
ACTIVE
SOIC
D
14
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HC4024MTE4
ACTIVE
SOIC
D
14
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HC4024MTG4
ACTIVE
SOIC
D
14
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HC4024PW
ACTIVE
TSSOP
PW
14
90
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HC4024PWE4
ACTIVE
TSSOP
PW
14
90
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HC4024PWG4
ACTIVE
TSSOP
PW
14
90
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HC4024PWR
ACTIVE
TSSOP
PW
14
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HC4024PWRE4
ACTIVE
TSSOP
PW
14
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HC4024PWRG4
ACTIVE
TSSOP
PW
14
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HC4024PWT
ACTIVE
TSSOP
PW
14
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HC4024PWTE4
ACTIVE
TSSOP
PW
14
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HC4024PWTG4
ACTIVE
TSSOP
PW
14
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HCT4024E
ACTIVE
PDIP
N
14
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
CD74HCT4024EE4
ACTIVE
PDIP
N
14
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
CD74HCT4024M
ACTIVE
SOIC
D
14
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
9-Oct-2007
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
CD74HCT4024ME4
ACTIVE
SOIC
D
14
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HCT4024MG4
ACTIVE
SOIC
D
14
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Oct-2007
TAPE AND REEL BOX INFORMATION
Device
Package Pins
Site
Reel
Diameter
(mm)
Reel
Width
(mm)
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
CD74HC4024M96
D
14
SITE 41
330
16
6.5
9.0
2.1
8
16
Q1
CD74HC4024PWR
PW
14
SITE 41
330
12
7.0
5.6
1.6
8
12
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
Device
4-Oct-2007
Package
Pins
Site
Length (mm)
Width (mm)
Height (mm)
CD74HC4024M96
D
14
SITE 41
346.0
346.0
33.0
CD74HC4024PWR
PW
14
SITE 41
346.0
346.0
29.0
Pack Materials-Page 2
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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