UNISONIC TECHNOLOGIES CO., LTD U74AC74 CMOS IC DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET DESCRIPTION The U74AC74 is a dual positive-edge-triggered D-type flip-flop. The preset ( PRE ) and clear ( CLR ) input can set or reset the output at a low level ,regardless of the level of others inputs .when the PRE and CLR are inactive(high), data at the data D input meeting the set-up time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Following the hold-time interval, data D can be changed without affecting the levels at the outputs. FEATURES * Operating voltage rauge: VCC(OPR)=2V to 6V. * Inputs accept voltages to 6V * Max tpd at 10ns of 5V ORDERING INFORMATION Ordering Number Lead Free Halogen Free U74AC74L-S14-R U74AC74G-S14-R www.unisonic.com.tw Copyright © 2012 Unisonic Technologies Co., Ltd Package Packing SOP-14 Tape Reel 1 of 6 QW-R502-800.A U74AC74 CMOS IC PIN CONFIGURATION FUNCTION TABLE (each gate) INPUT OUTPUT PRE CLR CLK D Q Q L H X X H L H L X X L H L L X X H H H H ↑ H H L H H ↑ L L H H H L X Q0 Q0 LOGIC DIAGRAM (positive logic) UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw 2 of 6 QW-R502-800.A U74AC74 CMOS IC ABSOLUTE MAXIMUM RATING (TA=25°C, unless otherwise specified)(Note 1) PARAMETER Supply Voltage Input Voltage Output Voltage(active mode) SYMBOL RATINGS UNIT VCC -0.5~7 V VIN -0.5~ VCC+0.5 V -0.5~VCC+0.5 V VOUT Input Clamp Current(VIN<0) IIK -20(MIN) mA Output Clamp Current(VOUT<0) IOK ±20 mA Output Current IOUT ±50 mA VCC or GND Current ICC ±200 mA Storage Temperature TSTG -65 ~ +150 °C Note 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied. RECOMMENDED OPERATING COMDITIONS PARAMETER Supply Voltage Input Voltage Output Voltage High-level input voltage SYMBOL VCC VIN VOUT VIH Low-level input voltage VIL High-level Output Current IOH Low-level Output Current IOL Input Transition Rise or Fall Rate Operating Temperature TEST CONDITIONS VCC =3V VCC=4.5V VCC =5.5V VCC=3V VCC =4.5V VCC=5.5V VCC =3V VCC=4.5V VCC =5.5V VCC=3V VCC =4.5V VCC=5.5V Δt/Δv TA MIN 2 0 0 2.1 3.15 3.85 TYP MAX 6 5.5 VCC UNIT V V V V -40 0.9 1.35 1.65 -12 -24 -24 12 24 24 8 +85 ns/V °C MAX UNIT V mA mA STATIC CHARACTERISTICS (TA=25°C, unless otherwise specified) PARAMETER High-Level Output Voltage Low-Level Output Voltage Input Leakage Current SYMBOL VOH VOL II(LEAK) Quiescent Supply Current ICC Input Capacitance CIN TEST CONDITIONS VCC=3V IOH=-50uA VCC=4.5V VCC=5.5V IOH=-12mA VCC=3V VCC=4.5V IOH=-24mA VCC=5.5V VCC=3V IOL=-50uA VCC=4.5V VCC=5.5V IOL=12mA VCC=3V VCC=4.5V IOL=24mA VCC=5.5V VCC =0V ~ 5.5V, VIN=VCC or GND VCC = 5.5V, VIN=5.5V or GND IOUT=0 VCC =3.3V, VIN=VCC or GND UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw MIN 2.9 4.4 5.4 2.56 3.86 4.86 TYP V 0.1 0.1 0.1 0.36 0.36 0.36 ±0.1 2 3 V μA pF 3 of 6 QW-R502-800.A U74AC74 CMOS IC DYNAMIC CHARACTERISTICS TA=25°C, unless otherwise specified, Input: tR, tF≤2.5ns; PRR≤1MHz PARAMETER SYMBOL TEST CONDITIONS Clock frequency Pulse duration Setup time before CLK↑ Hold time ,data after CLK↑ Clock frequency Pulse duration Setup time before CLK↑ Hold time ,data after CLK↑ FCLOCK VCC=3V±0.3V VCC=3V±0.3V， PRE tw VCC=3V±0.3V, CLK VCC=3V±0.3V, PRE tsu Data th VCC=3V±0.3V FCLOCK VCC=5V±0.5V VCC=5V±0.5V， PRE tw VCC=3V±0.3V, CLK VCC=5V±0.5V, PRE tsu Data th VCC=5V±0.5V or CLR in Low or CLR inactive MIN TYP MAX UNIT 100 MHZ 5.5 5.5 0 4 0.5 ns ns 140 or CLR in Low or CLR inactive 4.5 4.5 0 3 0.5 ns MHz ns ns ns DYNAMIC CHARACTERISTICS (See Fig. 1 and Fig. 2 for test circuit and waveforms.) PARAMETER SYMBOL TEST CONDITIONS Maximum clock FMAX VCC=3V±0.3V, CL=50pF, RL=500Ω tPLH Propagation delay from input VCC=3V±0.3V, CL=50pF, RL=500Ω ( PRE or CLR ) to output(Q or Q) tPHL tPLH Propagation delay from input VCC=3V±0.3V, CL=50pF, RL=500Ω (CLK) to output(Q or Q) tPHL Maximum clock FMAX VCC=5V±0.5V tPLH Propagation delay from input VCC=5V±0.5V, CL=50pF, RL=500Ω ( PRE or CLR ) to output(Q or Q) tPHL Propagation delay from input tPLH VCC=5V±0.5V, CL=50pF, RL=500Ω (CLK) to output(Q or Q) tPHL MIN 100 3.5 4 4.5 3.5 140 2.5 3 3.5 2.5 TYP 125 8 10.5 8 8 160 6 8 6 6 MAX MIN TYP 45 MAX 12 12 13.5 14 UNIT MHz ns ns MHz 9 9.5 10 10 ns ns OPERATING CHARACTERISTICS PARAMETER Power Dissipation Capacitance SYMBOL TEST CONDITIONS Cpd CL=50p, f=1MHz, VCC=3.3V UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw UNIT pF 4 of 6 QW-R502-800.A U74AC74 CMOS IC TEST CIRCUIT AND WAVEFORMS From Output CL RL TEST CIRCUIT Note: CL includes probe and jig capacitance. Fig. 1 Load circuitry for switching times. Fig. 2 Propagation delay from input to output and input voltage waveforms. UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw 5 of 6 QW-R502-800.A U74AC74 CMOS IC UTC assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all UTC products described or contained herein. UTC products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw 6 of 6 QW-R502-800.A