[ /Title (CD74 HC401 05, CD74 HCT40 105) /Subject (High Speed CMOS CD54HC40105, CD74HC40105, CD54HCT40105, CD74HCT40105 Data sheet acquired from Harris Semiconductor SCHS222C High-Speed CMOS Logic 4-Bit x 16-Word FIFO Register February 1998 - Revised October 2003 Features Description • Independent Asynchronous Inputs and Outputs The ’HC40105 and ’HCT40105 are high-speed silicon-gate CMOS devices that are compatible, except for “shift-out” circuitry, with the CD40105B. They are low-power first-in-out (FIFO) “elastic” storage registers that can store 16 four-bit words. The 40105 is capable of handling input and output data at different shifting rates. This feature makes it particularly useful as a buffer between asynchronous systems. • Expandable in Either Direction • Reset Capability • Status Indicators on Inputs and Outputs • Three-State Outputs • Shift-Out Independent of Three-State Control Each work position in the register is clocked by a control flipflop, which stores a marker bit. A “1” signifies that the position’s data is filled and a “0” denotes a vacancy in that position. The control flip-flop detects the state of the preceding flip-flop and communicates its own status to the succeeding flip-flop. When a control flip-flop is in the “0” state and sees a “1” in the preceeding flip-flop, it generates a clock pulse that transfers data from the preceding four data latches into its own four data latches and resets the preceding flip-flop to “0”. The first and last control flip-flops have buffered outputs. Since all empty locations “bubble” automatically to the input end, and all valid data ripple through to the output end, the status of the first control flip-flop (DATA-IN READY) indicates if the FIFO is full, and the status of the last flip-flop (DATAOUT READY) indicates if the FIFO contains data. As the earliest data are removed from the bottom of the data stack (the output end), all data entered later will automatically propagate (ripple) toward the output. • Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads • Wide Operating Temperature Range . . . -55oC to 125oC • Balanced Propagation Delay and Transition Times • Significant Power Reduction Compared to LSTTL Logic ICs • HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V • HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH Ordering Information PART NUMBER TEMP. RANGE (oC) PACKAGE Applications CD54HC40105F3A -55 to 125 16 Ld CERDIP • Bit-Rate Smoothing CD54HCT40105F3A -55 to 125 16 Ld CERDIP • CPU/Terminal Buffering CD74HC40105E -55 to 125 16 Ld PDIP • Data Communications CD74HC40105M -55 to 125 16 Ld SOIC • Peripheral Buffering CD74HC40105MT -55 to 125 16 Ld SOIC • Line Printer Input Buffers CD74HC40105M96 -55 to 125 16 Ld SOIC • Auto-Dialers CD74HCT40105E -55 to 125 16 Ld PDIP • CRT Buffer Memories CD74HCT40105M -55 to 125 16 Ld SOIC • Radar Data Acquisition CD74HCT40105MT -55 to 125 16 Ld SOIC CD74HCT40105M96 -55 to 125 16 Ld SOIC NOTE: When ordering, use the entire part number. The suffix 96 denotes tape and reel. The suffix T denotes a small-quantity reel of 250. CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, Texas Instruments Incorporated 1 CD54HC40105, CD74HC40105, CD54HCT40105, CD74HCT40105 Pinout Three-State Outputs In order to facilitate data busing, three-state outputs (Q0 to Q3) are provided on the data output lines, while the load condition of the register can be detected by the state of the DOR output. A HIGH on the three-state control flag (output enable input OE) forces the outputs into the high-impedance OFF-state mode. Note that the shift-out signal, unlike that in the CD40105B, is independent of the three-state output control. In the CD40105B, the three-state control must not be shifted from High to Low when the shift-out signal is Low (data loss would occur). In the high-speed CMOS version this restriction has been eliminated. CD54HC40105, CD54HCT40105 (CERDIP) CD74HC40105, CD74HCT40105 (PDIP, SOIC) TOP VIEW THREE-STATE 1 CONTROL DIR 2 SI 3 16 VCC 15 SO 14 DOR D0 4 13 Q0 D1 5 12 Q1 D2 6 11 Q2 D3 7 10 Q3 GND 8 9 MR Cascading The 40105 can be cascaded to form longer registers simply by connecting the DIR to SO and DOR to SI. In the cascaded mode, a MASTER RESET pulse must be applied after the supply voltage is turned on. For words wider than four bits, the DIR and the DOR outputs must be gated together with AND gates. Their outputs drive the SI and SO inputs in parallel, if expanding is done in both directions (see Figures 12 and 13). Loading Data Data can be entered whenever the DATA-IN READY (DIR) flag is high, by a low to high transition on the SHIFT-IN (SI) input. This input must go low momentarily before the next word is accepted by the FIFO. The DIR flag will go low momentarily, until the data have been transferred to the second location. The flag will remain low when all 16-word locations are filled with valid data, and further pulses on the SI input will be ignored until DIR goes high. Functional Diagram THREESTATE CONTROL 1 4 13 5 12 6 11 7 10 D0 D1 Unloading Data D2 As soon as the first word has rippled to the output, the dataout ready output (DOR) goes HIGH and data of the first word is available on the outputs. Data of other words can be removed by a negative-going transition on the shift-out input (SO). This negative-going transition causes the DOR signal to go LOW while the next word moves to the output. As long as valid data is available in the FIFO, the DOR signal will go high again, signifying that the next word is ready at the output. When the FIFO is empty, DOR will remain LOW, and any further commands will be ignored until a “1” marker ripples down to the last control register and DOR goes HIGH. If during unloading SI is HIGH, (FIFO is full) data on the data input of the FIFO is entered in the first location. D3 SHIFT IN SHIFT OUT MASTER RESET Master Reset A high on the MASTER RESET (MR) sets all the control logic marker bits to “0”. DOR goes low and DIR goes high. The contents of the data register are not changed, only declared invalid, and will be superseded when the first word is loaded. Thus, MR does not clear data within the register but only the control logic. If the shift-in flag (SI) is HIGH during the master reset pulse, data present at the input (D0 to D3) are immediately moved into the first location upon completion of the reset process. 2 Q0 Q1 Q2 Q3 3 15 9 14 DATA-OUT READY 2 DATA-IN READY GND = 8 VCC = 16 CD54HC40105, CD74HC40105, CD54HCT40105, CD74HCT40105 INPUT BUFFERS D0 4 D1 5 D2 6 D3 7 OUTPUT BUFFERS 13 Q0 12 Q1 4 x 16 DATA REGISTER 11 Q2 10 Q3 1 THREE-STATE CONTROL DATA-OUT READY (DOR) DATA-IN READY (DIR) 2 CONTROL LOGIC 14 SHIFT OUT (SO) 3 SHIFT IN (SI) 15 9 MASTER RESET (MR) FIGURE 1. FUNCTIONAL BLOCK DIAGRAM 3 CD54HC40105, CD74HC40105, CD54HCT40105, CD74HCT40105 9 MR 14 DOR SI 3 15 R Q † S Q F/F1 F/Fs 2-15 F/F16 R Q R Q R Q †† †† †† S Q S Q S Q S0 R † 14 x 2 S Q DIR 14 x 13 4 D0 CL CL CL CL CL Q0 CL 5 12 D1 6 4 LATCHES 4 x 14 LATCHES 4 LATCHES D2 7 D3 L1 14 x L1 L16 POSITION 1 POSITION 2-15 POSITIONS 16 1 OE † “S” overrides “R”. †† “R” overrides “S”. FIGURE 2. LOGIC DIAGRAM 4 THREESTATE OUTPUT BUFFERS E E Q1 11 Q2 10 Q3 CD54HC40105, CD74HC40105, CD54HCT40105, CD74HCT40105 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA Thermal Resistance (Typical, Note 1) θJA (oC/W) E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . 67 M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . 73 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. The package thermal impedance is calculated in accordance with JESD 51-7. DC Electrical Specifications TEST CONDITIONS PARAMETER 25oC -40oC TO 85oC -55oC TO 125oC SYMBOL VI (V) IO (mA) VCC (V) VIH - - 2 1.5 - - 1.5 4.5 3.15 - - 3.15 - 3.15 - V 6 4.2 - - 4.2 - 4.2 - V MIN TYP MAX MIN MAX MIN MAX UNITS - 1.5 - V HC TYPES High Level Input Voltage Low Level Input Voltage High Level Output Voltage CMOS Loads VIL VOH - VIH or VIL High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads VOL VIH or VIL Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current - 2 - - 0.5 - 0.5 - 0.5 V 4.5 - - 1.35 - 1.35 - 1.35 V 6 - - 1.8 - 1.8 - 1.8 V -0.02 2 1.9 - - 1.9 - 1.9 - V -0.02 4.5 4.4 - - 4.4 - 4.4 - V -0.02 6 5.9 - - 5.9 - 5.9 - V - - - - - - - - - V -4 4.5 3.98 - - 3.84 - 3.7 - V -5.2 6 5.48 - - 5.34 - 5.2 - V 0.02 2 - - 0.1 - 0.1 - 0.1 V 0.02 4.5 - - 0.1 - 0.1 - 0.1 V 0.02 6 - - 0.1 - 0.1 - 0.1 V - - - - - - - - - V 4 4.5 - - 0.26 - 0.33 - 0.4 V 5.2 6 - - 0.26 - 0.33 - 0.4 V II VCC or GND - 6 - - ±0.1 - ±1 - ±1 µA ICC VCC or GND 0 6 - - 8 - 80 - 160 µA 5 CD54HC40105, CD74HC40105, CD54HCT40105, CD74HCT40105 DC Electrical Specifications (Continued) TEST CONDITIONS 25oC -40oC TO 85oC -55oC TO 125oC VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS PARAMETER SYMBOL VI (V) IO (mA) Three-State Leakage Current IOZ VIL or VIH VO = VCC or GND 6 - - ±0.5 - ±5 - ±10 µA High Level Input Voltage VIH - - 4.5 to 5.5 2 - - 2 - 2 - V Low Level Input Voltage VIL - - 4.5 to 5.5 - - 0.8 - 0.8 - 0.8 V High Level Output Voltage CMOS Loads VOH VIH or VIL -0.02 4.5 4.4 - - 4.4 - 4.4 - V -4 4.5 3.98 - - 3.84 - 3.7 - V 0.02 4.5 - - 0.1 - 0.1 - 0.1 V 4 4.5 - - 0.26 - 0.33 - 0.4 V HCT TYPES High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads VOL VIH or VIL Low Level Output Voltage TTL Loads II VCC and GND 0 5.5 - - ±0.1 - ±1 - ±1 µA Quiescent Device Current ICC VCC or GND 0 5.5 - - 8 - 80 - 160 µA Three-State Leakage Current IOZ VIL or VIH VO = VCC or GND 5.5 - - ±0.5 - ±5 - ±10 µA Additional Quiescent Device Current Per Input Pin: 1 Unit Load ∆ICC (Note 2) VCC -2.1 - 4.5 to 5.5 - 100 360 - 450 - 490 µA Input Leakage Current NOTE: 2. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA. HCT Input Loading Table INPUT UNIT LOADS OE 0.75 SI, SO 0.4 Dn 0.3 MR 1.5 NOTE: Unit Load is ∆ICC limit specified in DC Electrical Table, e.g., 360µA max at 25oC. 6 CD54HC40105, CD74HC40105, CD54HCT40105, CD74HCT40105 Prerequisite for Switching Specifications 25oC PARAMETER -40oC TO 85oC -55oC TO 125oC SYMBOL VCC (V) MIN MAX MIN MAX MIN MAX UNITS SI Pulse Width HIGH or LOW tW 2 80 - 100 - 120 - ns 4.5 16 - 20 - 24 - ns 6 14 - 17 - 20 - ns SO Pulse Width HIGH or LOW tW 2 120 - 150 - 180 - ns 4.5 24 - 30 - 36 - ns 6 20 - 26 - 31 - ns HC TYPES DIR Pulse Width HIGH or LOW DOR Pulse Width HIGH or LOW MR Pulse Width HIGH Removal Time MR to SI Set-Up Time Dn to SI Hold Time Dn to SI Maximum Pulse Frequency SI, SO tW tW tW tREM tSU tH fMAX 2 200 - 250 - 300 - ns 4.5 40 - 50 - 60 - ns 6 34 - 43 - 51 - ns 2 200 - 250 - 300 - ns 4.5 40 - 50 - 60 - ns 6 34 - 43 - 51 - ns 2 120 - 150 - 180 - ns 4.5 24 - 30 - 36 - ns 6 20 - 26 - 31 - ns 2 50 - 65 - 75 - ns 4.5 10 - 13 - 15 - ns 6 9 - 11 - 13 - ns 2 5 - 5 - 5 - ns 4.5 5 - 5 - 5 - ns 6 5 - 5 - 5 - ns 2 125 - 155 - 190 - ns 4.5 25 - 31 - 38 - ns 6 21 - 26 - 32 - ns 2 3 - 2 - 2 - MHz 4.5 15 - 12 - 10 - MHz 6 18 - 14 - 12 - MHz HCT TYPES SI Pulse Width HIGH or LOW tW 4.5 16 - 20 - 24 - ns SO Pulse Width HIGH or LOW tW 4.5 16 - 20 - 24 - ns DIR Pulse Width HIGH or LOW tW 4.5 40 - 50 - 60 - ns DOR Pulse Width HIGH or LOW tW 4.5 40 - 50 - 60 - ns MR Pulse Width HIGH Removal Time MR to SI Set-Up Time Dn to SI Hold Time Dn to SI Maximum Pulse Frequency SI, SO tW 4.5 24 - 30 - 36 - ns tREM 4.5 15 - 19 - 22 - ns tSU 4.5 0 - 0 - 0 - ns tH 4.5 25 - 31 - 38 - ns fMAX 4.5 15 - 12 - 10 - MHz 7 CD54HC40105, CD74HC40105, CD54HCT40105, CD74HCT40105 Switching Specifications Input tr, tf = 6ns PARAMETER TEST SYMBOL CONDITIONS 25oC -40oC TO 85oC -55oC TO 125oC VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS CL = 50pF 2 - - 175 - 220 - 265 ns CL = 50pF 4.5 - - 35 - 44 - 53 ns CL = 15pF 5 - 15 - - - - - ns CL = 50pF 6 - - 30 - 37 - 45 ns CL = 50pF 2 - - 210 - 265 - 315 ns CL = 50pF 4.5 - - 42 - 53 - 63 ns CL = 15pF 5 - 18 - - - - - ns CL = 50pF 6 - - 36 - 45 - 54 ns CL = 50pF 2 - - 210 - 265 - 315 ns CL = 50pF 4.5 - - 42 - 53 - 63 ns CL = 15pF 5 - 18 - - - - - ns CL = 50pF 6 - - 36 - 45 - 54 ns CL = 50pF 2 - - 400 - 500 - 600 ns CL = 50pF 4.5 - - 80 - 100 - 120 ns CL = 15pF 5 - 35 - - - - - ns CL = 50pF 6 - - 68 - 85 - 102 ns CL = 50pF 2 - - 2000 - 2500 - 3000 ns 4.5 - - 400 - 500 - 600 ns 6 - - 340 - 425 - 510 ns 2 - - 2500 - 3125 - 3750 ns 4.5 - - 500 - 625 - 750 ns 6 - - 425 - 532 - 638 ns 2 - - 1500 - 1900 - 2250 ns 4.5 - - 300 - 380 - 450 ns 6 - - 260 - 330 - 380 ns 2 - - 150 - 190 - 225 ns 4.5 - - 30 - 38 - 45 ns 6 - - 26 - 33 - 38 ns 2 - - 140 - 175 - 210 ns CL = 50pF 4.5 - - 28 - 35 - 42 ns CL = 50pF 6 - - 24 - 30 - 36 ns tTLH, tTHL CL = 50pF 2 - - 75 - 95 - 110 ns 4.5 - - 15 - 19 - 22 ns 6 - - 13 - 16 - 19 ns HC TYPES Propagation Delay MR to DIR, DOR SI to DIR SO to DOR SO to Qn Propagation Delay/Ripple thru Delay SI to DOR Propagation Delay/Ripple thru Delay SO to DIR Propagation Delay/Ripple thru Delay SI to Qn Three-State Output Enable OE to Qn Three-State Output Disable OE to Qn Output Transition Time Maximum SI, SO Frequency tPHL, tPLH tPHL, tPLH tPHL, tPLH tPHL, tPLH tPLH tPLH tPLH CL = 50pF CL = 50pF tPZH, tPZL CL = 50pF tPHZ, tPLZ CL = 50pF fMAX CL = 15pF 5 - 32 - - - - - MHz Input Capacitance CIN CL = 50pF - - - 10 - 10 - 10 pF Power Dissipation Capacitance (Notes 3, 4) CPD CL = 15pF 5 - 83 - - - - - pF 8 CD54HC40105, CD74HC40105, CD54HCT40105, CD74HCT40105 Switching Specifications Input tr, tf = 6ns PARAMETER Three-State Output Capacitance (Continued) TEST SYMBOL CONDITIONS 25oC -40oC TO 85oC -55oC TO 125oC VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS CO CL = 50pF - - - 15 - 15 - 15 pF tPLH, tPHL CL = 50pF 4.5 - - 36 - 45 - 54 ns CL = 15pF 5 - 15 - - - - - ns tPLH, tPHL CL = 50pF 4.5 - - 42 - 53 - 63 ns CL =15pF 5 - 18 - - - - - ns tPLH, tPHL CL = 50pF 4.5 - - 42 - 53 - 63 ns CL =15pF 5 - 18 - - - - - ns tPLH, tPHL CL = 50pF 4.5 - - 80 - 100 - 120 ns CL =15pF 5 - 35 - - - - - ns Propagation Delay/Ripple thru Delay SI to DOR tPLH CL = 50pF 4.5 - - 400 - 500 - 600 ns Propagation Delay/Ripple thru Delay SO to DIR tPLH CL = 50pF 4.5 - - 500 - 625 - 750 ns Propagation Delay/Ripple thru Delay SI to Qn tPLH CL = 50pF 4.5 - - 300 - 380 - 450 ns Three-State Output Enable OE to Qn tPZH, tPZL CL = 50pF 4.5 - - 35 - 44 - 53 ns Three-State Output Disable OE to Qn tPHZ, tPLZ CL = 50pF 4.5 - - 30 - 38 - 45 ns Output Transition Time tTLH, tTHL CL = 50pF 4.5 - - 15 - 19 - 22 ns HCT TYPES Propagation Delay Time MR to DIR, DOR SI to DIR SO to DOR SO to Qn Maximum CP Frequency fMAX CL =15pF 5 - 32 - - - - - MHz Input Capacitance CIN CL = 50pF - - - 10 - 10 - 10 pF Power Dissipation Capacitance (Notes 3, 4) CPD CL =15pF 5 - 83 - - - - - pF Three-State Output Capacitance CO CL = 50pF - - - 15 - 15 - 15 pF NOTES: 3. CPD is used to determine the dynamic power consumption, per package. 4. PD = CPD VCC2 fi + Σ (CL VCC2 fo) where fi = Input Frequency, fo = Output Frequency, CL = Output Load Capacitance, VCC = Supply Voltage. 9 CD54HC40105, CD74HC40105, CD54HCT40105, CD74HCT40105 Test Circuits and Waveforms tfCL trCL CLOCK tWL + tWH = 90% 10% I fCL CLOCK 50% 50% 1.3V 0.3V tf = 6ns tr = 6ns VCC 90% 50% 10% GND tTLH 3V 2.7V 1.3V 0.3V INPUT GND tTHL 90% 50% 10% INVERTING OUTPUT tWH FIGURE 4. HCT CLOCK PULSE RISE AND FALL TIMES AND PULSE WIDTH tf = 6ns tTHL GND NOTE: Outputs should be switching from 10% VCC to 90% VCC in accordance with device truth table. For fMAX, input duty cycle = 50%. FIGURE 3. HC CLOCK PULSE RISE AND FALL TIMES AND PULSE WIDTH tr = 6ns 1.3V 1.3V tWL tWH NOTE: Outputs should be switching from 10% VCC to 90% VCC in accordance with device truth table. For fMAX, input duty cycle = 50%. tPHL 2.7V 0.3V GND tWL INPUT tfCL = 6ns I fCL 3V VCC 50% 10% tWL + tWH = trCL = 6ns tTLH 90% 1.3V 10% INVERTING OUTPUT tPHL tPLH FIGURE 5. HC TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC tPLH FIGURE 6. HCT TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC 10 CD54HC40105, CD74HC40105, CD54HCT40105, CD74HCT40105 Test Circuits and Waveforms (Continued) trCL tfCL trCL VCC 90% CLOCK INPUT GND tH(H) 3V 2.7V CLOCK INPUT 50% 10% tfCL 1.3V 0.3V GND tH(H) tH(L) VCC DATA INPUT 3V DATA INPUT 50% tH(L) 1.3V 1.3V 1.3V GND tSU(H) tSU(H) tSU(L) tTLH tTHL 90% 50% 10% 90% OUTPUT tREM VCC SET, RESET OR PRESET tTLH OUTPUT tREM 3V SET, RESET OR PRESET GND 6ns OUTPUT LOW TO OFF OUTPUT HIGH TO OFF 50% OUTPUTS DISABLED FIGURE 9. HC THREE-STATE PROPAGATION DELAY WAVEFORM OTHER INPUTS TIED HIGH OR LOW OUTPUT DISABLE IC WITH THREESTATE OUTPUT GND 1.3V tPZH 90% OUTPUTS ENABLED OUTPUTS ENABLED 0.3 10% tPHZ tPZH 90% 3V tPZL tPLZ 10% OUTPUTS ENABLED 6ns 2.7 1.3 GND 50% tPHZ tf OUTPUT DISABLE tPZL tPLZ OUTPUT HIGH TO OFF 6ns tr VCC 10% CL 50pF FIGURE 8. HCT SETUP TIMES, HOLD TIMES, REMOVAL TIME, AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED SEQUENTIAL LOGIC CIRCUITS 6ns OUTPUT LOW TO OFF GND IC 90% 50% tPHL 1.3V CL 50pF FIGURE 7. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME, AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED SEQUENTIAL LOGIC CIRCUITS OUTPUT DISABLE 1.3V 10% tPLH 50% IC tTHL 90% 90% 1.3V tPHL tPLH GND tSU(L) 1.3V OUTPUTS DISABLED OUTPUTS ENABLED FIGURE 10. HCT THREE-STATE PROPAGATION DELAY WAVEFORM OUTPUT RL = 1kΩ CL 50pF VCC FOR tPLZ AND tPZL GND FOR tPHZ AND tPZH NOTE: Open drain waveforms tPLZ and tPZL are the same as those for three-state shown on the left. The test circuit is Output RL = 1kΩ to VCC, CL = 50pF. FIGURE 11. HC AND HCT THREE-STATE PROPAGATION DELAY TEST CIRCUIT 11 CD54HC40105, CD74HC40105, CD54HCT40105, CD74HCT40105 DATA OUT READY SHIFT IN SI DOR Q0 D0 SI DOR Q0 D0 D1 Q1 D1 Q1 D2 Q2 D2 Q2 D3 MR Q3 DIR SO D3 MR Q3 DIR SO 8-BIT DATA 8-BIT DATA SI DOR Q0 D0 SI DOR Q0 D0 D1 Q1 D1 Q1 D2 Q2 D2 Q2 D3 MR Q3 DIR SO D3 MR Q3 DIR SO SHIFT OUT DATA IN READY MASTER RESET (NOTE) NOTE: Pulse must be applied for cascading by 16 N bits. FIGURE 12. EXPANSION, 8-BITS WIDE BY 16 N-BITS LONG USING HC/HCT40105 12 CD54HC40105, CD74HC40105, CD54HCT40105, CD74HCT40105 MASTER RESET SHIFT IN (DATA VALID) INPUTS SHIFT-IN PULSES HAVE NO EFFECT ≈180ns (NOTE 6) SHIFT OUT SHIFT-OUT PULSES HAVE NO EFFECT OUTPUTS ≈180ns (NOTE 7) INPUT READY (CLEAR OUT) (NOTE 5) OUTPUT READY (DATA VALID) INPUTS DATA IN (Db) THREE-STATE (OUTPUT ENABLE) DATA OUT (NOTE 5) 1 0 1 1 1 0 0 1 1 0 10 1 0 1 0 (UNKNOWN) HIGH Z 1 0 1 1 1 0 INVALID NOTES: 5. Data valid goes to high level in advance of the data out by a maximum of 38ns at VCC = 4.5V for CL = 50pF and TA = 25oC. 6. At VCC = 4.5V, ripple time from position 1 to position 16. 7. At VCC = 4.5V, ripple time from position 16 to position 1. FIGURE 13. TIMING DIAGRAM FOR THE CD74HC/HCT40105 13 PACKAGE OPTION ADDENDUM www.ti.com 26-Sep-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) CD54HC40105F3A ACTIVE CDIP J 16 1 TBD Call TI Level-NC-NC-NC CD54HCT40105F3A ACTIVE CDIP J 16 1 TBD Call TI Level-NC-NC-NC CD74HC40105E ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC CD74HC40105EE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC CD74HC40105M ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC40105M96 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC40105M96E4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC40105ME4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC40105MT ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC40105MTE4 ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT40105E ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC CD74HCT40105EE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC CD74HCT40105M ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT40105M96 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT40105M96E4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT40105ME4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT40105MT ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT40105MTE4 ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 26-Sep-2005 (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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