FREESCALE M68HC05_13

Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc.
MC68HC705C8A
MC68HSC705C8A
Technical Data
M68HC05
Microcontrollers
MC68HC705C8A/D
Rev. 3, 3/2002
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Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc.
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Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
MC68HC705C8A
MC68HSC705C8A
Technical Data
To provide the most up-to-date information, the revision of our
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The following revision history table summarizes changes contained in
this document. For your convenience, the page number designators
have been linked to the appropriate location.
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Revision History
Date
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May, 2001
March, 2002
Revision
Level
2.1
3
Description
Page
Number(s)
1.7 Pin Functions — Added description of programming voltage
(VPP) pin 1.7.2 VPP
29
Removed note following 1.7.11 Port D I/O Pins (PD7 and
PD5–PD0)
33
14.2 Introduction — Updated Motorola contact information
192
14.7 44-Pin Quad Flat Pack (QFP) — Corrected case outline
drawing from Case #824E to Case #824A
195
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Technical Data — MC68HC705C8A
List of Sections
Section 1. General Description . . . . . . . . . . . . . . . . . . . . 21
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Section 2. Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Section 3. Central Processor Unit (CPU) . . . . . . . . . . . . 43
Section 4. Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Section 5. Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Section 6. Low-Power Modes. . . . . . . . . . . . . . . . . . . . . . 69
Section 7. Parallel Input/Output (I/O). . . . . . . . . . . . . . . . 77
Section 8. Capture/Compare Timer . . . . . . . . . . . . . . . . . 89
Section 9. EPROM/OTPROM (PROM) . . . . . . . . . . . . . . 103
Section 10. Serial Communications Interface (SCI). . . 121
Section 11. Serial Peripheral Interface (SPI). . . . . . . . . 139
Section 12. Instruction Set . . . . . . . . . . . . . . . . . . . . . . . 153
Section 13. Electrical Specifications . . . . . . . . . . . . . . 171
Section 14. Mechanical Specifications . . . . . . . . . . . . . 191
Section 15. Ordering Information . . . . . . . . . . . . . . . . . 199
Appendix A. MC68HSC705C8A . . . . . . . . . . . . . . . . . . . 201
Index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
MC68HC705C8A — Rev. 3
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Technical Data
List of Sections
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List of Sections
Technical Data
6
MC68HC705C8A — Rev. 3
List of Sections
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Technical Data — MC68HC705C8A
Table of Contents
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Section 1. General Description
1.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
1.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
1.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
1.4
Programmable Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
1.5
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
1.6
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
1.7
Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
1.7.1
VDD and VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
1.7.2
VPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
1.7.3
OSC1 and OSC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
1.7.4
External Reset Pin (RESET) . . . . . . . . . . . . . . . . . . . . . . . .32
1.7.5
External Interrupt Request Pin (IRQ) . . . . . . . . . . . . . . . . . . 32
1.7.6
Input Capture Pin (TCAP) . . . . . . . . . . . . . . . . . . . . . . . . . . 32
1.7.7
Output Compare Pin (TCMP) . . . . . . . . . . . . . . . . . . . . . . . .33
1.7.8
Port A I/O Pins (PA7–PA0). . . . . . . . . . . . . . . . . . . . . . . . . . 33
1.7.9
Port B I/O Pins (PB7–PB0). . . . . . . . . . . . . . . . . . . . . . . . . . 33
1.7.10 Port C I/O Pins (PC7–PC0) . . . . . . . . . . . . . . . . . . . . . . . . . 33
1.7.11 Port D I/O Pins (PD7 and PD5–PD0) . . . . . . . . . . . . . . . . . . 33
Section 2. Memory
2.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2.3
Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2.4
Input/Output (I/O) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
MC68HC705C8A — Rev. 3
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2.5
RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2.6
EPROM/OTPROM (PROM) . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2.7
Bootloader ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
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Section 3. Central Processor Unit (CPU)
3.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.3
CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.3.1
Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.3.2
Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.3.3
Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.3.4
Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.3.5
Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.4
Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Section 4. Interrupts
4.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
4.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
4.3
Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.3.1
Software Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.3.2
External Interrupt (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
4.3.3
Port B Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
4.3.4
Capture/Compare Timer Interrupts . . . . . . . . . . . . . . . . . . .55
4.3.5
SCI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
4.3.6
SPI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
4.4
Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Section 5. Resets
5.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
5.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Technical Data
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5.3
Reset Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
5.3.1
Power-On Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
5.3.2
External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
5.3.3
Programmable and Non-Programmable
COP Watchdog Resets . . . . . . . . . . . . . . . . . . . . . . . . . . 62
5.3.4
Clock Monitor Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
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Section 6. Low-Power Modes
6.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
6.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
6.3
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
6.3.1
SCI During Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
6.3.2
SPI During Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
6.3.3
Programmable COP Watchdog in Stop Mode . . . . . . . . . . . 71
6.3.4
Non-Programmable COP Watchdog in Stop Mode . . . . . . . 73
6.4
Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
6.4.1
Programmable COP Watchdog in Wait Mode . . . . . . . . . . . 75
6.4.2
Non-Programmable COP Watchdog in Wait Mode . . . . . . . 75
6.5
Data-Retention Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Section 7. Parallel Input/Output (I/O)
7.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
7.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
7.3
Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
7.3.1
Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
7.3.2
Data Direction Register A. . . . . . . . . . . . . . . . . . . . . . . . . . . 79
7.3.3
Port A Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
7.4
Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
7.4.1
Port B Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
7.4.2
Data Direction Register B. . . . . . . . . . . . . . . . . . . . . . . . . . . 82
7.4.3
Port B Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
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7.5
Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
7.5.1
Port C Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
7.5.2
Data Direction Register C. . . . . . . . . . . . . . . . . . . . . . . . . . . 86
7.5.3
Port C Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
7.6
Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
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Section 8. Capture/Compare Timer
8.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
8.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
8.3
Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
8.3.1
Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
8.3.2
Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
8.4
Timer I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
8.4.1
Timer Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
8.4.2
Timer Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
8.4.3
Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
8.4.4
Alternate Timer Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . 98
8.4.5
Input Capture Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 100
8.4.6
Output Compare Registers. . . . . . . . . . . . . . . . . . . . . . . . . 101
Section 9. EPROM/OTPROM (PROM)
9.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
9.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
9.3
EPROM/OTPROM (PROM) Programming . . . . . . . . . . . . . . . 104
9.3.1
Program Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
9.3.2
Preprogramming Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
9.4
PROM Programming Routines . . . . . . . . . . . . . . . . . . . . . . . . 111
9.4.1
Program and Verify PROM. . . . . . . . . . . . . . . . . . . . . . . . . 111
9.4.2
Verify PROM Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
9.4.3
Secure PROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
9.4.4
Secure PROM and Verify . . . . . . . . . . . . . . . . . . . . . . . . . . 113
9.4.5
Secure PROM and Dump. . . . . . . . . . . . . . . . . . . . . . . . . . 113
9.4.6
Load Program into RAM and Execute . . . . . . . . . . . . . . . . 114
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9.4.7
9.4.8
Execute Program in RAM. . . . . . . . . . . . . . . . . . . . . . . . . . 115
Dump PROM Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . .115
9.5
Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
9.5.1
Option Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
9.5.2
Mask Option Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
9.5.3
Mask Option Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
9.6
EPROM Erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
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Section 10. Serial Communications Interface (SCI)
10.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
10.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
10.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
10.4
SCI Data Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
10.5 SCI Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
10.5.1 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
10.5.2 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
10.6 SCI I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
10.6.1 SCI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
10.6.2 SCI Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
10.6.3 SCI Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
10.6.4 SCI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
10.6.5 Baud Rate Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Section 11. Serial Peripheral Interface (SPI)
11.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
11.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
11.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
11.4 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
11.4.1 Pin Functions in Master Mode . . . . . . . . . . . . . . . . . . . . . . 143
11.4.2 Pin Functions in Slave Mode . . . . . . . . . . . . . . . . . . . . . . .144
11.5
Multiple-SPI Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
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11.6
Serial Clock Polarity and Phase . . . . . . . . . . . . . . . . . . . . . . .146
11.7 SPI Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
11.7.1 Mode Fault Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147
11.7.2 Write Collision Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
11.7.3 Overrun Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
11.8
SPI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148
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11.9 SPI I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
11.9.1 SPI Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
11.9.2 SPI Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
11.9.3 SPI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Section 12. Instruction Set
12.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
12.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
12.3 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
12.3.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
12.3.2 Immediate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
12.3.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
12.3.4 Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
12.3.5 Indexed, No Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
12.3.6 Indexed, 8-Bit Offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
12.3.7 Indexed, 16-Bit Offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
12.3.8 Relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
12.4 Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
12.4.1 Register/Memory Instructions. . . . . . . . . . . . . . . . . . . . . . .158
12.4.2 Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . . 159
12.4.3 Jump/Branch Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . 160
12.4.4 Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . .162
12.4.5 Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
12.5
Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
12.6
Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Technical Data
12
MC68HC705C8A — Rev. 3
Table of Contents
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Table of Contents
Freescale Semiconductor, Inc...
Section 13. Electrical Specifications
13.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
13.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
13.3
Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
13.4
Operating Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . 173
13.5
Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
13.6
Power Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
13.7
5.0-Volt DC Electrical Characteristics. . . . . . . . . . . . . . . . . . .175
13.8
3.3-Volt DC Electrical Characteristics . . . . . . . . . . . . . . . . . .176
13.9
5.0-Volt Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
13.10 3.3-Volt Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
13.11 5.0-Volt Serial Peripheral Interface (SPI) Timing . . . . . . . . . . 185
13.12 3.3-Volt Serial Peripheral Interface (SPI) Timing . . . . . . . . . . 187
Section 14. Mechanical Specifications
14.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
14.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
14.3
40-Pin Plastic Dual In-Line Package (PDIP). . . . . . . . . . . . . .192
14.4
40-Pin Ceramic Dual In-Line Package (Cerdip) . . . . . . . . . . . 193
14.5
44-Lead Plastic-Leaded Chip Carrier (PLCC) . . . . . . . . . . . . 194
14.6
44-Lead Ceramic-Leaded Chip Carrier (CLCC) . . . . . . . . . . . 195
14.7
44-Pin Quad Flat Pack (QFP). . . . . . . . . . . . . . . . . . . . . . . . . 196
14.8
42-Pin Shrink Dual In-Line Package (SDIP) . . . . . . . . . . . . . .197
MC68HC705C8A — Rev. 3
MOTOROLA
Technical Data
Table of Contents
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Table of Contents
Section 15. Ordering Information
15.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
15.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
15.3
MCU Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Freescale Semiconductor, Inc...
Appendix A. MC68HSC705C8A
A.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
A.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
A.3
5.0-Volt High-Speed DC Electrical Characteristics. . . . . . . . .202
A.4
3.3-Volt High-Speed DC Electrical Characteristics . . . . . . . . 203
A.5
5.0-Volt High-Speed Control Timing . . . . . . . . . . . . . . . . . . . . 204
A.6
3.3-Volt High-Speed Control Timing . . . . . . . . . . . . . . . . . . . . 204
A.7
5.0-Volt High-Speed SPI Timing . . . . . . . . . . . . . . . . . . . . . . 205
A.8
3.3-Volt High-Speed SPI Timing. . . . . . . . . . . . . . . . . . . . . . .207
A.9
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Index
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Technical Data
14
MC68HC705C8A — Rev. 3
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Technical Data — MC68HC705C8A
List of Figures
Freescale Semiconductor, Inc...
Figure
Title
1-1
1-2
1-3
1-4
1-5
1-6
1-7
1-8
1-9
1-10
1-11
Option Register (Option) . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
MC68HC705C8A Block Diagram . . . . . . . . . . . . . . . . . . . . . 25
40-Pin PDIP/Cerdip Pin Assignments . . . . . . . . . . . . . . . . . 26
44-Lead PLCC/CLCC Pin Assignments . . . . . . . . . . . . . . . . 27
44-Pin QFP Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . .27
42-Pin SDIP Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . 28
Bypassing Layout Recommendation . . . . . . . . . . . . . . . . . . 29
Crystal Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2-Pin Ceramic Resonator Connections . . . . . . . . . . . . . . . . 31
3-Pin Ceramic Resonator Connections . . . . . . . . . . . . . . . . 31
External Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2-1
2-2
Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3-1
3-2
3-3
3-4
3-5
3-6
Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 044
Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 045
Index Register (X) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 045
Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 046
Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . .046
Condition Code Register (CCR) . . . . . . . . . . . . . . . . . . . . . 047
4-1
4-2
4-3
4-4
4-5
External Interrupt Internal Function Diagram . . . . . . . . . . . . 52
External Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Port B I/O Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Interrupt Stacking Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Reset and Interrupt Processing Flowchart . . . . . . . . . . . . . . 59
MC68HC705C8A — Rev. 3
MOTOROLA
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List of Figures
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List of Figures
Figure
5-1
5-2
5-3
5-4
6-1
6-2
Freescale Semiconductor, Inc...
6-3
Title
Programmable COP Watchdog Diagram . . . . . . . . . . . . . . .63
Programmable COP Reset Register (COPRST) . . . . . . . . . 64
Programmable COP Control Register (COPCR) . . . . . . . . . 64
Non-Programmable COP Watchdog Diagram . . . . . . . . . . . 67
Stop/Wait Mode Function Flowchart . . . . . . . . . . . . . . . . . . 70
Programmable COP Watchdog
in Stop Mode (PCOPE = 1) Flowchart. . . . . . . . . . . . . . .72
Non-Programmable COP Watchdog
in Stop Mode (NCOPE = 1) Flowchart . . . . . . . . . . . . . . 74
7-1
7-2
7-3
7-4
7-5
7-6
7-7
7-8
7-9
7-10
Port A Data Register (PORTA). . . . . . . . . . . . . . . . . . . . . . . 78
Data Direction Register A (DDRA) . . . . . . . . . . . . . . . . . . . .79
Port A I/O Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Port B Data Register (PORTB). . . . . . . . . . . . . . . . . . . . . . . 81
Data Direction Register B (DDRB) . . . . . . . . . . . . . . . . . . . .82
Port B I/O Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Port C Data Register (PORTC) . . . . . . . . . . . . . . . . . . . . . . 85
Data Direction Register C (DDRC) . . . . . . . . . . . . . . . . . . . .86
Port C I/O Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Port D Fixed Input Register (PORTD) . . . . . . . . . . . . . . . . . 88
8-1
8-2
8-3
8-4
8-5
8-6
8-7
8-8
8-10
8-9
8-11
8-12
Timer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Timer I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . .91
Input Capture Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Output Compare Operation . . . . . . . . . . . . . . . . . . . . . . . . . 93
Timer Control Register (TCR) . . . . . . . . . . . . . . . . . . . . . . . 94
Timer Status Register (TSR) . . . . . . . . . . . . . . . . . . . . . . . .96
Timer Registers (TRH and TRL) . . . . . . . . . . . . . . . . . . . . . 97
Timer Register Reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Alternate Timer Register Reads . . . . . . . . . . . . . . . . . . . . . . 99
Alternate Timer Registers (ATRH and ATRL) . . . . . . . . . . . 99
Input Capture Registers (ICRH and ICRL) . . . . . . . . . . . . . 100
Output Compare Registers (OCRH and OCRL). . . . . . . . .101
9-1
9-2
EPROM/OTPROM Programming Flowchart . . . . . . . . . . . 105
PROM Programming Circuit . . . . . . . . . . . . . . . . . . . . . . . . 106
Technical Data
16
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List of Figures
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Figure
Title
9-3
9-4
9-5
9-6
Program Register (PROG) . . . . . . . . . . . . . . . . . . . . . . . . . 109
Option Register (Option) . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Mask Option Register 1 (MOR1) . . . . . . . . . . . . . . . . . . . . 117
Mask Option Register 2 (MOR2) . . . . . . . . . . . . . . . . . . . . 118
10-1
10-2
10-3
10-4
10-5
10-6
10-7
10-8
10-9
SCI Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
SCI Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
SCI Transmitter I/O Register Summary . . . . . . . . . . . . . . . 125
SCI Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
SCI Data Register (SCDR). . . . . . . . . . . . . . . . . . . . . . . . . 129
SCI Control Register 1 (SCCR1) . . . . . . . . . . . . . . . . . . . . 130
SCI Control Register 2 (SCCR2) . . . . . . . . . . . . . . . . . . . . 131
SCI Status Register (SCSR) . . . . . . . . . . . . . . . . . . . . . . .133
Baud Rate Register (Baud) . . . . . . . . . . . . . . . . . . . . . . . . 136
11-1
11-2
11-3
11-4
11-5
11-6
11-7
11-8
11-9
SPI Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
SPI I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . 142
Master/Slave Connections . . . . . . . . . . . . . . . . . . . . . . . . . 143
One Master and Three Slaves Block Diagram . . . . . . . . . . 145
Two Master/Slaves and Three Slaves Block Diagram . . . . 146
SPI Clock/Data Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . .146
SPI Data Register (SPDR) . . . . . . . . . . . . . . . . . . . . . . . . . 149
SPI Control Register (SPCR) . . . . . . . . . . . . . . . . . . . . . . .149
SPI Status Register (SPSR) . . . . . . . . . . . . . . . . . . . . . . . . 151
13-1
13-2
13-3
Equivalent Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Typical Voltage Compared to Current . . . . . . . . . . . . . . . . 177
Typical Current versus Internal
Frequency for Run and Wait Modes . . . . . . . . . . . . . . . 179
Total Current Drain versus Frequency . . . . . . . . . . . . . . . . 180
Timer Relationships . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Stop Recovery Timing Diagram . . . . . . . . . . . . . . . . . . . . . 183
Power-On Reset and External Reset Timing Diagram. . . . 184
SPI Master Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
SPI Slave Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190
13-4
13-5
13-6
13-7
13-8
13-9
MC68HC705C8A — Rev. 3
MOTOROLA
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Figure
14-1
14-2
14-3
Freescale Semiconductor, Inc...
14-4
14-5
14-6
Title
MC68HC705C8AP Package Dimensions
(Case #711). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
MC68HC705C8AS Package Dimensions
(Case #734A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193
MC68HC705C8AFN Package Dimensions
(Case #777). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
MC68HC705C8AFS Package Dimensions
(Case #777B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .195
MC68HC705C8AFB Package Dimensions
(Case #824A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196
MC68HC705C8AB Package Dimensions
(Case #858). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Technical Data
18
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MC68HC705C8A — Rev. 3
List of Figures
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Technical Data — MC68HC705C8A
List of Tables
Freescale Semiconductor, Inc...
Table
Title
2-1
Memory Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4-1
Reset/Interrupt Vector Addresses . . . . . . . . . . . . . . . . . . . . . 57
5-1
Programmable COP Timeout Period Selection . . . . . . . . . . . 66
7-1
7-2
7-3
Port A Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Port B Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Port C Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
9-1
9-2
MC68HC05PGMR PCB Reference Designators . . . . . . . . .104
PROM Programming Routines . . . . . . . . . . . . . . . . . . . . . . .108
10-1
10-2
10-3
Baud Rate Generator Clock Prescaling . . . . . . . . . . . . . . . . 136
Baud Rate Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Baud Rate Selection Examples . . . . . . . . . . . . . . . . . . . . . . 138
11-1
SPI Clock Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
12-1
12-2
12-3
12-4
12-5
12-6
12-7
Register/Memory Instructions. . . . . . . . . . . . . . . . . . . . . . . . 158
Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . . . 159
Jump and Branch Instructions . . . . . . . . . . . . . . . . . . . . . . .161
Bit Manipulation Instructions. . . . . . . . . . . . . . . . . . . . . . . . . 162
Control Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170
15-1
MC68HC705C8A Order Numbers . . . . . . . . . . . . . . . . . . . . 199
MC68HC705C8A — Rev. 3
MOTOROLA
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List of Tables
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List of Tables
Table
Page
Programmable COP Timeout Period Selection . . . . . . . . . . . 202
MC68HSC705C8A Order Numbers . . . . . . . . . . . . . . . . . . . . 209
Freescale Semiconductor, Inc...
A-1
A-2
Title
Technical Data
20
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List of Tables
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Technical Data — MC68HC705C8A
Section 1. General Description
Freescale Semiconductor, Inc...
1.1 Contents
1.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
1.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
1.4
Programmable Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
1.5
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
1.6
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
1.7
Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
1.7.1
VDD and VSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
1.7.2
VPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
1.7.3
OSC1 and OSC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
1.7.3.1
Crystal Resonator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
1.7.3.2
Ceramic Resonator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
1.7.3.3
External Clock Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
1.7.4
External Reset Pin (RESET) . . . . . . . . . . . . . . . . . . . . . . . .32
1.7.5
External Interrupt Request Pin (IRQ) . . . . . . . . . . . . . . . . . . 32
1.7.6
Input Capture Pin (TCAP) . . . . . . . . . . . . . . . . . . . . . . . . . . 32
1.7.7
Output Compare Pin (TCMP) . . . . . . . . . . . . . . . . . . . . . . . .33
1.7.8
Port A I/O Pins (PA7–PA0). . . . . . . . . . . . . . . . . . . . . . . . . . 33
1.7.9
Port B I/O Pins (PB7–PB0). . . . . . . . . . . . . . . . . . . . . . . . . . 33
1.7.10 Port C I/O Pins (PC7–PC0) . . . . . . . . . . . . . . . . . . . . . . . . . 33
1.7.11 Port D I/O Pins (PD7 and PD5–PD0) . . . . . . . . . . . . . . . . . . 33
MC68HC705C8A — Rev. 3
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General Description
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1.2 Introduction
The MC68HC705C8A, an enhanced version of the MC68HC705C8, is a
member of the low-cost, high-performance M68HC05 Family of 8-bit
microcontroller units (MCU). The MC68HSC705C8A, introduced in
Appendix A. MC68HSC705C8A, is an enhanced, high-speed version of
the MC68HC705C8A. The M68HC05 Family is based on the
customer-specified integrated circuit (CSIC) design strategy. All MCUs
in the family use the M68HC05 central processor unit (CPU) and are
available with a variety of subsystems, memory sizes and types, and
package types.
1.3 Features
Features of the MC68HC705C8A include:
•
M68HC05 central processor unit (CPU)
•
On-chip oscillator with crystal/ceramic resonator
•
Memory-mapped input/output (I/O)
•
Selectable memory configurations
•
Selectable programmable and/or non-programmable computer
operating properly (COP) watchdog timers
•
Selectable port B external interrupt capability
•
Clock monitor
•
High current drive on pin C7 (PC7)
•
24 bidirectional I/O lines and 7 input-only lines
•
Serial communications interface (SCI) system
•
Serial peripheral interface (SPI) system
•
Bootstrap capability
•
Power-saving stop, wait, and data-retention modes
•
Single 3.0-volt to 5.5-volt supply (2-volt data-retention mode)
•
Fully static operation
Technical Data
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MC68HC705C8A — Rev. 3
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General Description
Programmable Options
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NOTE:
•
Software-programmable external interrupt sensitivity
•
Bidirectional RESET pin
A line over a signal name indicates an active low signal. For example,
RESET is active high and RESET is active low. Any reference to voltage,
current, or frequency specified in this document will refer to the nominal
values. The exact values and their tolerance or limits are specified in
Section 13. Electrical Specifications.
1.4 Programmable Options
These options are programmable in the mask option registers:
•
Enabling of port B pullup devices (see 9.5.2 Mask Option
Register 1)
•
Enabling of non-programmable COP watchdog (see 9.5.3 Mask
Option Register 2)
These options are programmable in the option register (see Figure 1-1):
•
One of four selectable memory configurations
•
Programmable read-only memory (PROM) security1
•
External interrupt sensitivity
Address:
$1FDF
Bit 7
6
5
4
3
RAM0
RAM1
0
0
SEC*
0
0
0
0
*
Read:
2
1
Bit 0
IRQ
0
1
0
Write:
Reset:
U
*Implemented as an EPROM cell
= Unimplemented
U = Unaffected
Figure 1-1. Option Register (Option)
1. No security feature is absolutely secure. However, Motorola’s strategy is to make reading or
copying the PROM difficult for unauthorized users.
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RAM0 — Random-Access Memory Control Bit 0
1 = Maps 32 bytes of RAM into page zero starting at address
$0030. Addresses from $0020 to $002F are reserved. This bit
can be read or written at any time, allowing memory
configuration to be changed during program execution.
0 = Provides 48 bytes of PROM at location $0020–$005F.
RAM1 — Random-Access Memory Control Bit 1
1 = Maps 96 bytes of RAM into page one starting at address $0100.
This bit can be read or written at any time, allowing memory
configuration to be changed during program execution.
0 = Provides 96 bytes of PROM at location $0100.
SEC — Security Bit
This bit is implemented as an erasable, programmable read-only
memory (EPROM) cell and is not affected by reset.
1 = Bootloader disabled; MCU operates only in single-chip mode
0 = Security off; bootloader can be enabled
IRQ — Interrupt Request Pin Sensitivity Bit
IRQ is set only by reset, but can be cleared by software. This bit can
be written only once.
1 = IRQ pin is both negative edge- and level-sensitive.
0 = IRQ pin is negative edge-sensitive only.
Bits 5, 4, and 0 — Not used; always read 0
Bit 2 — Unaffected by reset; reads either 1 or 0
1.5 Block Diagram
Figure 1-2 shows the structure of the MC68HC705C8A.
Technical Data
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MC68HC705C8A — Rev. 3
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General Description
Block Diagram
PA0
EPROM/OTPROM — 7744 BYTES
(144 BYTES CONFIGURABLE)
PA1
PA2
PORT A
PROGRAM REGISTER
DATA DIRECTION A
VPP
EPROM PROGRAMMING
CONTROL
PA3
PA4
PA5
PA6
PA7
OPTION
REGISTER
BOOT ROM — 240 BYTES
PB1*
PB2*
PORT B
DATA DIRECTION B
RAM — 176 BYTES
(304 BYTES MAXIMUM)
PB3*
PB4*
PB5*
PB6*
PB7*
RESET
ARITHMETIC
LOGIC UNIT
CPU
CONTROL
PC0
M68HC05 CPU
CPU REGISTERS
ACCUMULATOR
INDEX REGISTER
0
0
0
0
0
1
1
PC1
PC2
PORT C
IRQ
DATA DIRECTION C
PC3
PC4
PC5
PC6
STACK POINTER
PC7†
PROGRAM COUNTER
CONDITION CODE REGISTER
1
1
1
H
I
N
Z
PD7
C
RDI (PD0)
SCI
OSC2
OSC1
÷2
OSCILLATOR
TDO (PD1)
PORT D
Freescale Semiconductor, Inc...
PB0*
INTERNAL
PROCESSOR
CLOCK
MISO (PD2)
MOSI (PD3)
SPI
SCK (PD4)
COP WATCHDOG
AND
CLOCK MONITOR
VDD
VSS
POWER
SS (PD5)
BAUD RATE
GENERATOR
16-BIT
CAPTURE/COMPARE
TIMER SYSTEM
TCMP
TCAP
* Port B pins also function as external interrupts.
† PC7 has a high current sink and source capability.
Figure 1-2. MC68HC705C8A Block Diagram
MC68HC705C8A — Rev. 3
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General Description
1.6 Pin Assignments
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The MC68HC705C8A is available in six packages:
•
40-pin plastic dual in-line package (PDIP)
•
40-pin ceramic dual in-line package (cerdip)
•
44-lead plastic-leaded chip carrier (PLCC)
•
44-lead ceramic-leaded chip carrier (CLCC)
•
44-pin quad flat pack (QFP)
•
42-pin shrink dual in-line package (SDIP)
The pin assignments for these packages are shown in Figure 1-3,
Figure 1-4, Figure 1-5, and Figure 1-6.
RESET
1
40
VDD
IRQ
2
39
OSC1
VPP
3
38
OSC2
PA7
4
37
TCAP
PA6
5
36
PD7
PA5
6
35
TCMP
PA4
7
34
PD5/SS
PA3
8
33
PD4/SCK
PA2
9
32
PD3/MOSI
PA1
10
31
PD2/MISO
PA0
11
30
PD1/TDO
PB0
12
29
PD0/RDI
PB1
13
28
PC0
PB2
14
27
PC1
PB3
15
26
PC2
PB4
16
25
PC3
PB5
17
24
PC4
PB6
18
23
PC5
PB7
19
22
PC6
VSS
20
21
PC7
Figure 1-3. 40-Pin PDIP/Cerdip Pin Assignments
Technical Data
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MC68HC705C8A — Rev. 3
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PA6
PA7
VPP
NC
IRQ
RESET
VDD
OSC1
OSC2
TCAP
NC
5
4
3
2
1
44
43
42
41
40
28
PD7
TCMP
PD5/SS
PD4/SCK
PD3/MOSI
PD2/MISO
PD1/TDO
PD0/RDI
PC0
PC1
PC2
PC3
25
PC6
27
24
PC7
PC4
23
NC
26
22
VSS
PC5
21
PB7
20
PB6
NC
18
Freescale Semiconductor, Inc...
PA1
PA0
PB0
PB1
PB2
PB3
PB4
37
36
35
34
33
32
31
30
29
10
11
12
13
14
15
16
17
19
PA3
PA2
39
38
7
8
9
PB5
PA5
PA4
6
General Description
Pin Assignments
PC3
PC2
PC1
PC0
PD0/RDI
PD1/TDO
PD2/MISO
PD3/MOSI
PD4/SCK
PD5/SS
TCMP
Figure 1-4. 44-Lead PLCC/CLCC Pin Assignments
PC6
VDD
38
18
PC7
NC
39
17
VSS
NC
40
16
NC
RESET
41
15
PB7
IRQ
42
14
PB6
VPP
43
13
PB5
PB4
2
3
4
5
6
7
8
9
12
10 11
PB3
PA6
PA7
44
1
PB2
PC5
19
PB1
20
37
PB0
36
OSC1
PA0
OSC2
PA1
PC4
PA2
21
PA3
35
PA4
NC
TCAP
PA5
33 32 31 30 29 28 27 26 25 24 23
34
22
PD7
Figure 1-5. 44-Pin QFP Pin Assignments
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General Description
RESET
1
42
VDD
IRQ
2
41
OSC1
VPP
3
40
OSC2
PA7
4
39
TCAP
PA6
5
38
PD7
PA5
6
37
TCMP
PA4
7
36
PD5/SS
PA3
8
35
PD4/SCK
PA2
9
34
PD3/MOSI
PA1
10
33
PD2/MISO
PA0
11
32
PD1/TDO
PB0
12
31
PD0/RDI
PB1
13
30
PC0
PB2
14
29
PC1
PB3
15
28
PC2
NC
16
27
NC
PB4
17
26
PC3
PB5
18
25
PC4
PB6
19
24
PC5
PB7
20
23
PC6
VSS
21
22
PC7
Figure 1-6. 42-Pin SDIP Pin Assignments
Technical Data
28
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General Description
Pin Functions
1.7 Pin Functions
This subsection describes the MC68HC705C8A signals. Reference is
made, where applicable, to other sections that contain more detail about
the function being performed.
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1.7.1 VDD and VSS
VDD and VSS are the power supply and ground pins. The MCU operates
from a single power supply.
Very fast signal transitions occur
on the MCU pins, placing high
short-duration current demands
on the power supply. To prevent
noise problems, take special care
to provide good power supply
bypassing at the MCU. Place
bypass capacitors as close to the
MCU as possible, as shown in
Figure 1-7.
V+
VDD
+
MCU
C1
C2
VSS
Figure 1-7. Bypassing Layout
Recommendation
1.7.2 VPP
This pin provides the programming voltage to the EPROM array. For
normal operation, VPP shuld be tied to VDD.
NOTE:
Connecting the VPP pin (programming voltage) to VSS (ground) could
result in damage to the MCU.
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1.7.3 OSC1 and OSC2
The OSC1 and OSC2 pins are the control connections for the 2-pin
on-chip oscillator. The oscillator can be driven by:
Freescale Semiconductor, Inc...
NOTE:
•
Crystal resonator
•
Ceramic resonator
•
External clock signal
The frequency of the internal oscillator is fOSC. The MCU divides the
internal oscillator output by two to produce the internal clock with a
frequency of fOP.
1.7.3.1 Crystal Resonator
The circuit in Figure 1-8 shows a
crystal oscillator circuit for an AT-cut,
parallel resonant crystal. Follow the
crystal supplier’s recommendations,
because the crystal parameters
determine the external component
values required to provide reliable
startup and maximum stability. The
load capacitance values used in the
oscillator circuit design should
account for all stray layout
capacitances. To minimize output
distortion, mount the crystal and
capacitors as close as possible to the
pins.
NOTE:
MCU
OSC1
∗
10 MΩ
∗
XTAL
2 MHz
22 pF
∗
∗
22 pF
Starting value only. Follow crystal supplier’s
recommendations regarding component
values that will provide reliable startup and
maximum stability.
Figure 1-8. Crystal
Connections
Use an AT-cut crystal and not a strip or tuning fork crystal. The MCU
might overdrive or have the incorrect characteristic impedance for a strip
or tuning fork crystal.
Technical Data
30
OSC2
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General Description
Pin Functions
1.7.3.2 Ceramic Resonator
To reduce cost, use a ceramic
resonator instead of a crystal. Use the
circuit shown in Figure 1-9 for a 2-pin
ceramic resonator or the circuit shown
in Figure 1-10 for a 3-pin ceramic
resonator, and follow the resonator
manufacturer’s recommendations.
MCU
OSC1
Freescale Semiconductor, Inc...
C
R
CERAMIC
RESONATOR
OSC2
C
The external component values
required for maximum stability and
Figure 1-9. 2-Pin Ceramic
reliable starting depend upon the
Resonator Connections
resonator parameters. The load
.
capacitance values used in the oscillator circuit design should include all
stray layout capacitances. To minimize output distortion, mount the
resonator and capacitors as close as possible to the pins.
MCU
OSC1
OSC2
CERAMIC
RESONATOR
Figure 1-10. 3-Pin
Ceramic Resonator
Connections
NOTE:
The bus frequency (fOP) is one-half the external or crystal frequency
(fOSC), while the processor clock cycle (tCYC) is two times the fOSC
period.
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General Description
1.7.3.3 External Clock Signal
OSC2
MCU
OSC1
An external clock from another
CMOS-compatible device can drive the
OSC1 input, with the OSC2 pin
unconnected, as Figure 1-11 shows.
Freescale Semiconductor, Inc...
EXTERNAL
CMOS CLOCK
Figure 1-11. External
Clock
NOTE:
The bus frequency (fOP) is one-half the external frequency (fOSC) while
the processor clock cycle is two times the fOSC period.
1.7.4 External Reset Pin (RESET)
A logic 0 on the bidirectional RESET pin forces the MCU to a known
startup state. The RESET pin contains an internal Schmitt trigger as part
of its input to improve noise immunity. See Section 5. Resets.
1.7.5 External Interrupt Request Pin (IRQ)
The IRQ pin is an asynchronous external interrupt pin. The IRQ pin
contains an internal Schmitt trigger as part of its input to improve noise
immunity. See 4.3.2 External Interrupt (IRQ).
1.7.6 Input Capture Pin (TCAP)
The TCAP pin is the input capture pin for the on-chip capture/compare
timer. The TCAP pin contains an internal Schmitt trigger as part of its
input to improve noise immunity. See Section 8. Capture/Compare
Timer.
Technical Data
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General Description
Pin Functions
1.7.7 Output Compare Pin (TCMP)
The TCMP pin is the output compare pin for the on-chip
capture/compare timer. See Section 8. Capture/Compare Timer.
Freescale Semiconductor, Inc...
1.7.8 Port A I/O Pins (PA7–PA0)
These eight I/O lines comprise port A, a general-purpose, bidirectional
I/O port. The pins are programmable as either inputs or outputs under
software control of the data direction registers. See 7.3 Port A.
1.7.9 Port B I/O Pins (PB7–PB0)
These eight I/O pins comprise port B, a general-purpose, bidirectional
I/O port. The pins are programmable as either inputs or outputs under
software control of the data direction registers. Port B pins also can be
configured to function as external interrupts. See 7.4 Port B.
1.7.10 Port C I/O Pins (PC7–PC0)
These eight I/O pins comprise port C, a general-purpose, bidirectional
I/O port. The pins are programmable as either inputs or outputs under
software control of the data direction registers. PC7 has a high current
sink and source capability. See 7.5 Port C.
1.7.11 Port D I/O Pins (PD7 and PD5–PD0)
These seven lines comprise port D, a fixed input port. All special
functions that are enabled (SPI and SCI) affect this port. See 7.6 Port D.
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General Description
Technical Data
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MC68HC705C8A — Rev. 3
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Technical Data — MC68HC705C8A
Section 2. Memory
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2.1 Contents
2.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2.3
Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2.4
Input/Output (I/O) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2.5
RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2.6
EPROM/OTPROM (PROM) . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2.7
Bootloader ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2.2 Introduction
This section describes the organization of the on-chip memory.
2.3 Memory Map
The central processor unit (CPU) can address eight Kbytes of memory
and input/output (I/O) registers. The program counter typically advances
one address at a time through memory, reading the program instructions
and data. The programmable read-only memory (PROM) portion of
memory — either one-time programmable read-only memory
(OTPROM) or erasable, programmable read-only memory
(EPROM) — holds the program instructions, fixed data, user-defined
vectors, and interrupt service routines. The random-access memory
(RAM) portion of memory holds variable data.
I/O registers are memory-mapped so that the CPU can access their
locations in the same way that it accesses all other memory locations.
The shared stack area is used during processing of an interrupt or
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Memory
subroutine call to save the CPU state. The stack pointer decrements
during pushes and increments during pulls.
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Figure 2-1 is a memory map of the MCU. Addresses $0000–$001F,
shown in Figure 2-2, contain most of the control, status, and data
registers. Additional I/O registers have these addresses:
•
$1FDF, option register
•
$1FF0, mask option register 1 (MOR1)
•
$1FF1, mask option register 2 (MOR2)
2.4 Input/Output (I/O)
The first 32 addresses of memory space, from $0000 to $001F, are the
I/O section. These are the addresses of the I/O control registers, status
registers, and data registers. See Figure 2-2 for more information.
2.5 RAM
One of four selectable memory configurations is selected by the state of
the RAM1 and RAM0 bits in the option register located at $1FDF. Reset
or power-on reset (POR) clears these bits, automatically selecting the
first memory configuration as shown in Table 2-1. See 9.5.1 Option
Register.
Table 2-1. Memory Configurations
NOTE:
RAM0
RAM1
RAM Bytes
PROM Bytes
0
0
176
7744
1
0
208
7696
0
1
272
7648
1
1
304
7600
Be careful when using nested subroutines or multiple interrupt levels.
The CPU can overwrite data in the stack RAM during a subroutine or
during the interrupt stacking operation.
Technical Data
36
MC68HC705C8A — Rev. 3
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Memory
EPROM/OTPROM (PROM)
2.6 EPROM/OTPROM (PROM)
An MCU with a quartz window has a maximum of 7744 bytes of EPROM.
The quartz window allows the EPROM erasure with ultraviolet light. In
an MCU without a quartz window, the EPROM cannot be erased and
serves a maximum 7744 bytes of OTPROM (see Table 2-1). See
Section 9. EPROM/OTPROM (PROM).
Freescale Semiconductor, Inc...
2.7 Bootloader ROM
The 240 bytes at addresses $1F00–$1FEF are reserved ROM
addresses that contain the instructions for the bootloader functions. See
Section 9. EPROM/OTPROM (PROM).
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Memory
$0000
$001F
$0020
$002F
$0030
$004F
$0050
I/O REGISTERS
32 BYTES
UNUSED
16 BYTES
USER PROM
48 BYTES
RAM
32 BYTES
RAM0 = 1(1)
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$00BF
$00C0
RAM0 = 0(1)
RAM
176 BYTES
STACK
64 BYTES
$00FF
$0100
$015F
$0160
$1EFF
$1F00
$1FDE
$1FDF
$1FE0
USER PROM
96 BYTES
RAM
96 BYTES
RAM1 = 0(1)
RAM1 = 1(1)
USER PROM
7584 BYTES
BOOTLOADER ROM
240 BYTES
OPTION REGISTER
PORT A DATA REGISTER
PORT B DATA REGISTER
PORT C DATA REGISTER
PORT D FIXED INPUT PORT
PORT A DATA DIRECTION REGISTER
PORT B DATA DIRECTION REGISTER
PORT C DATA DIRECTION REGISTER
UNUSED
UNUSED
UNUSED
SPI CONTROL REGISTER
SPI STATUS REGISTER
SPI DATA REGISTER
SCI BAUD RATE REGISTER
SCI CONTROL REGISTER 1
SCI CONTROL REGISTER 2
SCI STATUS REGISTER
SCI DATA REGISTER
TIMER CONTROL REGISTER
TIMER STATUS REGISTER
INPUT CAPTURE REGISTER (HIGH)
INPUT CAPTURE REGISTER (LOW)
OUTPUT COMPARE REGISTER (HIGH)
OUTPUT COMPARE REGISTER (LOW)
TIMER REGISTER (HIGH)
TIMER REGISTER (LOW)
ALTERNATE TIMER REGISTER (HIGH)
ALTERNATE TIMER REGISTER (LOW)
EPROM PROGRAM REGISTER
COP RESET REGISTER
COP CONTROL REGISTER
UNUSED
$0000
$0001
$0002
$0003
$0004
$0005
$0006
$0007
$0008
$0009
$000A
$000B
$000C
$000D
$000E
$000F
$0010
$0011
$0012
$0013
$0014
$0015
$0016
$0017
$0018
$0019
$001A
$001B
$001C
$001D
$001E
$001F
RESERVED
RESERVED
SPI INTERRUPT VECTOR (HIGH)
SPI INTERRUPT VECTOR (LOW)
SCI INTERRUPT VECTOR (HIGH)
SCI INTERRUPT VECTOR (LOW)
TIMER INTERRUPT VECTOR (HIGH)
TIMER INTERRUPT VECTOR (LOW)
EXTERNAL INTERRUPT VECTOR (HIGH)
EXTERNAL INTERRUPT VECTOR (LOW)
SOFTWARE INTERRUPT VECTOR (HIGH)
SOFTWARE INTERRUPT VECTOR (LOW)
RESET VECTOR (HIGH)
RESET VECTOR (LOW)
$1FF2
$1FF3
$1FF4
$1FF5
$1FF6
$1FF7
$1FF8
$1FF9
$1FFA
$1FFB
$1FFC
$1FFD
$1FFE
$1FFF
BOOT ROM VECTORS
16 BYTES
$1FEF
$1FF0
MASK OPTION REGISTER 1
$1FF1
MASK OPTION REGISTER 2
$1FF2
$1FFF
(1)
USER PROM VECTORS
12 BYTES
See 9.5.1 Option Register for information.
Figure 2-1. Memory Map
Technical Data
38
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Memory
Bootloader ROM
Addr.
Register Name
Read:
Port A Data Register
(PORTA) Write:
See page 78.
Reset:
$0000
Read:
Port B Data Register
(PORTB) Write:
See page 81.
Reset:
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$0001
Read:
Port C Data Register
(PORTC) Write:
See page 85.
Reset:
$0002
$0003
Read:
Port D Fixed Input Register
(PORTD) Write:
See page 88.
Reset:
$0004
$0005
$0006
Bit 7
6
5
4
3
2
1
Bit 0
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
PB2
PB1
PB0
PC2
PC1
PC0
MISO
TDO
RDI
Unaffected by reset
PB7
PB6
PC7
PC6
Unimplemented
$0009
Unimplemented
PC5
SS
PD7
PC4
PC3
SCK
MOSI
Unaffected by reset
DDRA6
DDRA5
DDRA4
DDRA3
DDRA2
DDRA1
DDRA0
0
0
0
0
0
0
0
DDRB6
DDRB5
DDRB4
DDRB3
DDRB2
DDRB1
DDRB0
0
0
0
0
0
0
0
DDRC5
DDRC4
DDRC3
DDRC2
DDRC1
DDRC0
0
0
0
0
0
0
Read:
Port C Data Direction
DDRC7 DDRC6
(DDRC) Write:
See page 86.
Reset:
0
0
$0008
PB3
Unaffected by reset
Read:
Port B Data Direction
DDRB7
Register (DDRB) Write:
See page 82.
Reset:
0
Unimplemented
PB4
Unaffected by reset
Read:
Port A Data Direction
DDRA7
Register (DDRA) Write:
See page 79.
Reset:
0
$0007
PB5
= Unimplemented
U = Unaffected
Figure 2-2. I/O Register Summary (Sheet 1 of 4)
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Memory
Addr.
Register Name
Read:
SPI Control Register
(SPCR) Write:
See page 149.
Reset:
$000A
Read:
SPI Status Register
(SPSR) Write:
See page 151.
Reset:
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$000B
Read:
SPI Data Register
(SPDR) Write:
See page 149.
Reset:
$000C
Read:
Baud Rate Register
(Baud) Write:
See page 136.
Reset:
$000D
$000E
$000F
Read:
SCI Control Register 1
(SCCR1) Write:
See page 130.
Reset:
Read:
SCI Control Register 2
(SCCR2) Write:
See page 131.
Reset:
6
4
3
2
1
Bit 0
SPIE
SPE
MSTR
CPOL
CPHA
SPR1
SPR0
0
0
0
U
U
U
U
SPIF
WCOL
MODF
0
0
0
Bit 7
Bit 6
Bit 3
BIt 2
Bit 1
Bit 0
Read:
SCI Data Register
(SCDR) Write:
See page 129.
Reset:
$0011
Read:
Timer Control Register
(TCR) Write:
See page 94.
Reset:
5
SCR2
SCR1
SCR0
U
U
U
Bit 5
Bit 4
Unaffected by reset
SCP1
SCP0
0
0
U
U
U
R8
T8
M
WAKE
U
U
U
U
TIE
TCIE
RIE
ILIE
TE
RE
RWU
SBK
0
0
0
0
0
0
0
0
TC
RDRF
IDLE
OR
NF
FE
1
0
0
0
0
0
U
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Read: TDRE
SCI Status Register
(SCSR) Write:
See page 133.
Reset:
1
$0010
$0012
Bit 7
Bit 7
Unaffected by reset
ICIE
OCIE
TOIE
0
0
0
IEDG
OLVL
0
0
0
0
0
0
U
0
= Unimplemented
U = Unaffected
Figure 2-2. I/O Register Summary (Sheet 2 of 4)
Technical Data
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Memory
Bootloader ROM
Addr.
Register Name
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$0014
$0015
$0017
6
5
4
3
2
1
Bit 0
ICF
OCF
TOF
0
0
0
0
0
U
U
U
0
0
0
0
0
Read: Bit 15
Input Capture Register
High (ICRH) Write:
See page 100.
Reset:
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Read:
Input Capture Register
Low (ICRL) Write:
See page 100.
Reset:
Bit 6
Bit 2
Bit 1
Bit 0
Bit 10
Bit 9
Bit 8
Bit 2
Bit 1
Bit 0
Bit 10
Bit 9
Bit 8
Bit 2
Bit 1
Bit 0
Bit 10
Bit 9
Bit 8
Bit 2
Bit 1
Bit 0
Read:
Timer Status Register
(TSR) Write:
See page 96.
Reset:
$0013
$0016
Bit 7
Bit 7
$0018
$0019
$001A
$001B
Bit 5
Bit 4
Bit 3
Unaffected by reset
Output Compare Register Read:
Bit 15
High (OCRH)
Write:
See page 101.
Reset:
Read:
Output Compare Register
Low (OCRL) Write:
See page 101.
Reset:
Unaffected by reset
Bit 7
Bit 14
Bit 13
Bit 12
Bit 11
Unaffected by reset
Bit 6
Bit 5
Bit 4
Bit 3
Unaffected by reset
Read: Bit 15
Timer Register High
(TRH) Write:
See page 97.
Reset:
Bit 14
Read:
Timer Register Low
(TRL) Write:
See page 97.
Reset:
Bit 6
Bit 7
Bit 13
Bit 12
Bit 11
Reset initializes TRH to $FF
Bit 5
Bit 4
Bit 3
Reset initializes TRL to $FC
Read: Bit 15
Alternate Timer Register
High (ATRH) Write:
See page 99.
Reset:
Bit 14
Read:
Alternate Timer Register
Low (ATRL) Write:
See page 99.
Reset:
Bit 6
Bit 7
Bit 13
Bit 12
Bit 11
Reset initializes ATRH to $FF
Bit 5
Bit 4
Bit 3
Reset initializes ATRL to $FC
= Unimplemented
U = Unaffected
Figure 2-2. I/O Register Summary (Sheet 3 of 4)
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Memory
Addr.
$001C
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$001D
$001E
Register Name
Read:
EPROM Programming
Register (PROG) Write:
See page 109.
Reset:
Read:
Programmable COP Reset
Register (COPRST) Write:
See page 64.
Reset:
Read:
Programmable COP Control
Register (COPCR) Write:
See page 64.
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
LAT
0
PGM
0
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
U
U
U
U
U
U
U
U
0
0
0
COPF
CME
PCOPE
CM1
CM0
0
0
0
IRQ
0
0
$001F
Unimplemented
$1FDF
Read:
Option Register
RAM0
(Option) Write:
See page 116.
Reset:
0
0
0
U
0
RAM1
0
0
SEC*
0
0
0
*
U
1
0
PBPU6
PBPU5
PBPU4
PBPU3
PBPU2
PBPU1
PBPU0/
COPC
*Implemented as an EPROM cell
$1FF0
$1FF1
Read:
Mask Option Register 1
PBPU7
(MOR1) Write:
See page 117.
Reset:
Unaffected by reset
Read:
Mask Option Register 2
(MOR2) Write:
See page 118.
Reset:
NCOPE
Unaffected by reset
= Unimplemented
U = Unaffected
Figure 2-2. I/O Register Summary (Sheet 4 of 4)
Technical Data
42
MC68HC705C8A — Rev. 3
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Technical Data — MC68HC705C8A
Section 3. Central Processor Unit (CPU)
3.1 Contents
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3.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.3
CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.3.1
Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.3.2
Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.3.3
Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.3.4
Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.3.5
Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.4
Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.2 Introduction
This section describes the central processor unit (CPU) registers.
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Central Processor Unit (CPU)
3.3 CPU Registers
Figure 3-1 shows the five CPU registers. These are hard-wired registers
within the CPU and are not part of the memory map.
Bit 7
6
5
4
3
2
1
Bit 0
ACCUMULATOR (A)
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Bit 7
6
5
4
3
2
1
Bit 0
INDEX REGISTER (X)
Bit 12 11
10
9
8
7
6
0
0
0
0
1
1
Bit 12 11
10
9
8
7
6
0
5
4
3
2
1
Bit 0
STACK POINTER (SP)
5
4
3
2
1
Bit 0
PROGRAM COUNTER (PC)
Bit 7
6
5
4
3
2
1
Bit 0
1
1
1
H
I
N
Z
C
CONDITION CODE REGISTER (CCR)
HALF-CARRY FLAG
INTERRUPT MASK
NEGATIVE FLAG
ZERO FLAG
CARRY/BORROW FLAG
Figure 3-1. Programming Model
Technical Data
44
MC68HC705C8A — Rev. 3
Central Processor Unit (CPU)
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Central Processor Unit (CPU)
CPU Registers
3.3.1 Accumulator
The accumulator (A) shown in Figure 3-2 is a general-purpose 8-bit
register. The CPU uses the accumulator to hold operands and results of
arithmetic and non-arithmetic operations.
Bit 7
6
5
4
3
2
1
Bit 0
Read:
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Write:
Reset:
Unaffected by reset
Figure 3-2. Accumulator (A)
3.3.2 Index Register
In the indexed addressing modes, the CPU uses the byte in the index
register (X) shown in Figure 3-3 to determine the conditional address of
the operand. See 12.3.5 Indexed, No Offset, 12.3.6 Indexed, 8-Bit
Offset, and 12.3.7 Indexed, 16-Bit Offset for more information on
indexed addressing.
The 8-bit index register also can serve as a temporary data storage
location.
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
Unaffected by reset
Figure 3-3. Index Register (X)
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Central Processor Unit (CPU)
3.3.3 Stack Pointer
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The stack pointer (SP) shown in Figure 3-4 is a 13-bit register that
contains the address of the next free location on the stack. During a reset
or after the reset stack pointer (RSP) instruction, the stack pointer
initializes to $00FF. The address in the stack pointer decrements as data
is pushed onto the stack and increments as data is pulled from the stack.
The seven most significant bits of the stack pointer are fixed
permanently at 0000011, so the stack pointer produces addresses from
$00C0 to $00FF. If subroutines and interrupts use more than 64 stack
locations, the stack pointer wraps around to address $00FF and begins
writing over the previously stored data. A subroutine uses two stack
locations. An interrupt uses five locations.
Read:
Bit 12
11
10
9
8
7
6
0
0
0
0
0
1
1
0
0
0
0
0
1
1
5
4
3
2
1
Bit 0
1
1
1
1
1
1
Write:
Reset:
= Unimplemented
Figure 3-4. Stack Pointer (SP)
3.3.4 Program Counter
The program counter (PC) shown in Figure 3-5 is a 13-bit register that
contains the address of the next instruction or operand to be fetched.
Normally, the address in the program counter automatically increments
to the next sequential memory location every time an instruction or
operand is fetched. Jump, branch, and interrupt operations load the
program counter with an address other than that of the next sequential
location.
Bit 12
11
10
9
8
7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
Loaded with reset vector from $1FFE and $1FFF
Figure 3-5. Program Counter (PC)
Technical Data
46
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Central Processor Unit (CPU)
CPU Registers
3.3.5 Condition Code Register
The condition code register (CCR) shown in Figure 3-6 is an 8-bit
register whose three most significant bits are permanently fixed at 111.
The condition code register contains the interrupt mask and four bits that
indicate the results of prior instructions.
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Read:
Bit 7
6
5
1
1
1
4
3
2
1
Bit 0
H
I
N
Z
C
U
1
U
U
U
Write:
Reset:
1
1
1
= Unimplemented
U = Unaffected
Figure 3-6. Condition Code Register (CCR)
H — Half-Carry Bit
The CPU sets the half-carry flag when a carry occurs between bits 3
and 4 of the accumulator during an add without carry (ADD) or add
with carry (ADC) operation. The half-carry bit is required for
binary-coded decimal (BCD) arithmetic operations. Reset has no
affect on the half-carry flag.
I — Interrupt Mask Bit
Setting the interrupt mask (I) disables interrupts. If an interrupt
request occurs while the interrupt mask is a logic 0, the CPU saves
the CPU registers on the stack, sets the interrupt mask, and then
fetches the interrupt vector. If an interrupt request occurs while the
interrupt mask is set, the interrupt request is latched. The CPU
processes the latched interrupt as soon as the interrupt mask is
cleared again.
A return-from-interrupt (RTI) instruction pulls the CPU registers from
the stack, restoring the interrupt mask to its cleared state. After a
reset, the interrupt mask is set and can be cleared only by a CLI,
STOP, or WAIT instruction.
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Central Processor Unit (CPU)
N — Negative Flag
The CPU sets the negative flag when an arithmetic operation, logical
operation, or data manipulation produces a negative result (bit 7 in the
results is a logic 1). Reset has no effect on the negative flag.
Z — Zero Flag
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The CPU sets the zero flag when an arithmetic operation, logical
operation, or data manipulation produces a result of $00. Reset has
no effect on the zero flag.
C — Carry/Borrow Flag
The CPU sets the carry/borrow flag when an addition operation
produces a carry out of bit 7 of the accumulator or when a subtraction
operation requires a borrow. Some logical operations and data
manipulation instructions also clear or set the carry/borrow bit. Reset
has no effect on the carry/borrow flag.
3.4 Arithmetic/Logic Unit (ALU)
The arithmetic/logic unit (ALU) performs the arithmetic and logical
operations defined by the instruction set. The binary arithmetic circuits
decode instructions and set up the ALU for the selected operation. Most
binary arithmetic is based on the addition algorithm, carrying out
subtraction as negative addition. Multiplication is not performed as a
discrete operation but as a chain of addition and shift operations within
the ALU. The multiply instruction requires 11 internal clock cycles to
complete this chain of operations.
Technical Data
48
MC68HC705C8A — Rev. 3
Central Processor Unit (CPU)
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Technical Data — MC68HC705C8A
Section 4. Interrupts
4.1 Contents
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4.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
4.3
Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.3.1
Software Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.3.2
External Interrupt (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
4.3.3
Port B Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
4.3.4
Capture/Compare Timer Interrupts . . . . . . . . . . . . . . . . . . .55
4.3.5
SCI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
4.3.6
SPI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
4.4
Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
4.2 Introduction
This section describes how interrupts temporarily change the normal
processing sequence.
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Interrupts
4.3 Interrupt Sources
These sources can generate interrupts:
•
Software instructions (SWI)
•
External interrupt pin (IRQ)
•
Port B pins
•
Serial communications interface (SCI):
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– SCI transmit data register empty
– SCI transmission complete
– SCI receive data register full
– SCI receiver overrun
– SCI receiver input idle
•
Serial peripheral interface (SPI):
– SPI transmission complete
– SPI mode fault
– SPI overrun
The IRQ pin, port B pins, SCI, and SPI can be masked (disabled) by
setting the I bit of the condition code register (CCR). The software
interrupt (SWI) instruction is non-maskable.
An interrupt temporarily changes the program sequence to process a
particular event. An interrupt does not stop the execution of the
instruction in progress but takes effect when the current instruction
completes its execution. Interrupt processing automatically saves the
central processor unit (CPU) registers on the stack and loads the
program counter with a user-defined vector address.
4.3.1 Software Interrupt
The software interrupt instruction (SWI) causes a non-maskable
interrupt.
Technical Data
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MC68HC705C8A — Rev. 3
Interrupts
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Interrupts
Interrupt Sources
4.3.2 External Interrupt (IRQ)
An interrupt signal on the IRQ pin latches an external interrupt request.
After completing the current instruction, the CPU tests these bits:
•
IRQ latch
•
I bit in the CCR
Setting the I bit in the CCR disables external interrupts.
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If the IRQ latch is set and the I bit is clear, the CPU then begins the
interrupt sequence. The CPU clears the IRQ latch while it fetches the
interrupt vector, so that another external interrupt request can be latched
during the interrupt service routine. As soon as the I bit is cleared during
the return-from-interrupt (RTI) instruction, the CPU can recognize the
new interrupt request. Figure 4-1 shows the logic for external interrupts.
Figure 4-1 shows an external interrupt functional diagram. Figure 4-2
shows an external interrupt timing diagram for the interrupt line. The
timing diagram illustrates two treatments of the interrupt line to the
processor.
1. Two single pulses on the interrupt line are spaced far enough
apart to be serviced. The minimum time between pulses is a
function of the length of the interrupt service.
Once a pulse occurs, the next pulse normally should not occur
until an RTI occurs. This time (tILIL) is obtained by adding 19
instruction cycles to the total number of cycles needed to complete
the service routine (not including the RTI instruction).
2. Many interrupt lines are “wire-ORed” to the IRQ line. If the interrupt
line remains low after servicing an interrupt, then the CPU
continues to recognize an interrupt.
NOTE:
The internal interrupt latch is cleared in the first part of the interrupt
service routine. Therefore, a new external interrupt pulse could be
latched and serviced as soon as the I bit is cleared.
If the IRQ pin is not in use, connect it to the VDD pin.
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Interrupts
EDGE- AND LEVEL-SENSITIVE TRIGGER
OPTION REGISTER
VDD
D
EXTERNAL
INTERRUPT
REQUEST
Q
I BIT (CCR)
IRQ LATCH
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INTERRUPT PIN
C
Q
POR
R
INTERNAL RESET (COP)
EXTERNAL RESET
EXTERNAL INTERRUPT BEING SERVICED
(VECTOR FETCH)
Figure 4-1. External Interrupt Internal Function Diagram
tILIL
tILIH
IRQ PIN
a. Edge-Sensitive Trigger Condition. The minimum pulse width (tILIH) is either 125 ns (fOP = 2.1 MHz)
or 250 ns (fOP = 1 MHz). The period tILIL should not be less than the number of tCYC cycles it takes to
execute the interrupt service routine plus 19 tCYC cycles.
IRQ1
NORMALLY
USED WITH
WIRED-OR
CONNECTION
tILIH
.
.
.
IRQn
IRQ
(INTERNAL)
b. Level-Sensitive Trigger Condition. If the interrupt line remains low after servicing an interrupt, then the
CPU continues to recognize an interrupt.
Figure 4-2. External Interrupt Timing
Technical Data
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Interrupts
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Interrupts
Interrupt Sources
4.3.3 Port B Interrupts
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When these three conditions are true, a port B pin (PBx) acts as an
external interrupt pin:
•
The corresponding port B pullup bit (PBPUx) in mask option
register 1 (MOR1) is programmed to a logic 1.
•
The corresponding port B data direction bit (DDRBx) in data
direction register B (DDRB) is a logic 0.
•
The clear interrupt mask (CLI) instruction has cleared the I bit in
the CCR.
MOR1 is an erasable, programmable read-only memory (EPROM)
register that enables the port B pullup device. Data from MOR1 is
latched on the rising edge of the voltage on the RESET pin. See 9.5.2
Mask Option Register 1.
Port B external interrupt pins can be falling-edge sensitive only or both
falling-edge and low-level sensitive, depending on the state of the IRQ
bit in the option register at location $1FDF.
When the IRQ bit is a logic 1, a falling edge or a low level on a port B
external interrupt pin latches an external interrupt request. As long as
any port B external interrupt pin is low, an external interrupt request is
present, and the CPU continues to execute the interrupt service routine.
When the IRQ bit is a logic 0, a falling-edge only on a port B external
interrupt pin latches an external interrupt request. A subsequent port B
external interrupt request can be latched only after the voltage level of
the previous port B external interrupt signal returns to a logic 1 and then
falls again to a logic 0.
Figure 4-3 shows the port B input/output (I/O) logic.
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Interrupts
VDD
PBPU7
FROM MOR1
READ $0005
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INTERNAL DATA BUS
WRITE $0005
DATA DIRECTION
REGISTER B
BIT DDRB7
RESET
PORT B DATA
REGISTER
BIT PB7
WRITE $0001
PB7
READ $0001
IRQ
FROM OPTION
REGISTER
VDD
D
FROM OTHER
PORT B PINS
C
EXTERNAL
INTERRUPT
REQUEST
Q
R
Q
I BIT
FROM CCR
IRQ
RESET
EXTERNAL INTERRUPT VECTOR FETCH
Figure 4-3. Port B I/O Logic
Technical Data
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Interrupts
Interrupt Sources
4.3.4 Capture/Compare Timer Interrupts
Setting the I bit in the CCR disables all interrupts except for SWI.
4.3.5 SCI Interrupts
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The serial communications interface (SCI) can generate these
interrupts:
•
Transmit data register empty interrupt
•
Transmission complete interrupt
•
Receive data register full interrupt
•
Receiver overrun interrupt
•
Receiver input idle interrupt
Setting the I bit in the CCR disables all SCI interrupts.
•
SCI Transmit Data Register Empty Interrupt — The transmit
data register empty bit (TDRE) indicates that the SCI data register
is ready to receive a byte for transmission. TDRE becomes set
when data in the SCI data register transfers to the transmit shift
register. TDRE generates an interrupt request if the transmit
interrupt enable bit (TIE) is set also.
•
SCI Transmission Complete Interrupt — The transmission
complete bit (TC) indicates the completion of an SCI transmission.
TC becomes set when the TDRE bit becomes set and no data,
preamble, or break character is being transmitted. TC generates
an interrupt request if the transmission complete interrupt enable
bit (TCIE) is set also.
•
SCI Receive Data Register Full Interrupt — The receive data
register full bit (RDRF) indicates that a byte is ready to be read in
the SCI data register. RDRF becomes set when the data in the
receive shift register transfers to the SCI data register. RDRF
generates an interrupt request if the receive interrupt enable bit
(RIE) is set also.
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Interrupts
•
SCI Receiver Overrun Interrupt — The overrun bit (OR)
indicates that a received byte is lost because software has not
read the previously received byte. OR becomes set when a byte
shifts into the receive shift register before software reads the word
already in the SCI data register. OR generates an interrupt
request if the receive interrupt enable bit (RIE) is set also.
•
SCI Receiver Input Idle Interrupt — The receiver input idle bit
(IDLE) indicates that the SCI receiver input is not receiving data.
IDLE becomes set when 10 or 11 consecutive logic 1s appear on
the receiver input. IDLE generates an interrupt request if the idle
line interrupt enable bit (ILIE) is set also.
4.3.6 SPI Interrupts
The serial peripheral interrupt (SPI) can generate these interrupts:
•
SPI transmission complete interrupt
•
SPI mode fault interrupt
Setting the I bit in the CCR disables all SPI interrupts.
•
SPI Transmission Complete Interrupt — The SPI flag bit (SPIF)
in the SPI status register indicates the completion of an SPI
transmission. SPIF becomes set when a byte shifts into or out of
the SPI data register. SPIF generates an interrupt request if the
SPIE bit is set also.
•
SPI Mode Fault Interrupt — The mode fault bit (MODF) in the SPI
status register indicates an SPI mode error. MODF becomes set
when a logic 0 occurs on the PD5/SS pin while the master bit
(MSTR) in the SPI control register is set. MODF generates an
interrupt request if the SPIE bit is set also.
Technical Data
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Interrupt Processing
4.4 Interrupt Processing
The CPU takes these actions to begin servicing an interrupt:
1. Stores the CPU registers on the stack in the order shown in
Figure 4-4
2. Sets the I bit in the CCR to prevent further interrupts
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3. Loads the program counter with the contents of the appropriate
interrupt vector locations as shown in Table 4-1.
Table 4-1. Reset/Interrupt Vector Addresses
Function
Source
Reset
Power-on
logic
Local
Mask
Global
Mask
Priority
(1 = Highest)
Vector Address
None
None
1
$1FFE–$1FFF
None
None
Same priority
as any
instruction
$1FFC–$1FFD
None
I bit
2
$1FFA–$1FFB
I bit
3
$1FF8–$1FF9
I bit
4
$1FF6–$1FF7
I bit
5
$1FF4–$1FF5
RESET pin
Software
interrupt
(SWI)
External
interrupt
Timer
interrupts
User code
IRQ pin
Port B pins
ICF bit
ICIE bit
OCF bit
OCIE bit
TOF bit
TOIE bit
TDRE bit
TCIE bit
TC bit
SCI
interrupts
RDRF bit
RIE bit
OR bit
IDLE bit
SPI
interrupts
ILIE bit
SPIF bit
SPIE
MODF bit
The return-from-interrupt (RTI) instruction causes the CPU to recover
the CPU registers from the stack as shown in Figure 4-4.
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$00C0 (BOTTOM OF STACK)
$00C1
$00C2
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UNSTACKING
ORDER
•
•
•
•
•
•
5
1
CONDITION CODE REGISTER
4
2
ACCUMULATOR
3
3
INDEX REGISTER
2
4
PROGRAM COUNTER (HIGH BYTE)
1
5
PROGRAM COUNTER (LOW BYTE)
STACKING
ORDER
•
•
•
•
•
•
$00FD
$00FE
$00FF (TOP OF STACK)
Figure 4-4. Interrupt Stacking Order
NOTE:
If more than one interrupt request is pending, the CPU fetches the vector
of the higher priority interrupt first. A higher priority interrupt does not
interrupt a lower priority interrupt service routine unless the lower priority
interrupt service routine clears the I bit. See Table 4-1 for a priority
listing.
Figure 4-5 shows the sequence of events caused by an interrupt.
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Interrupts
Interrupt Processing
FROM
RESET
YES
I BIT IN
CCR REGISTER
SET?
NO
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EXTERNAL
IRQ
INTERRUPT?
YES
CLEAR IRQ REQUEST LATCH
NO
TIMER
INTERRUPT?
YES
NO
SCI
INTERRUPT?
YES
NO
SPI
INTERRUPT?
YES
NO
1. STACK PC, X, A, CCR
2. SET I BIT
3. LOAD PC WITH VECTOR
SWI: $1FFC–$1FFD
IRQ: $1FFA–$1FFB
TIMER: $1FF8–$1FF9
SCI: $1FF6–$1FF7
SPI: $1FF4–$1FF5
FETCH NEXT
INSTRUCTION
SWI
INSTRUCTION?
YES
NO
RTI
INSTRUCTION?
YES
RESTORE REGISTERS FROM STACK:
CCR, A, X, PC
NO
EXECUTE INSTRUCTION
Figure 4-5. Reset and Interrupt Processing Flowchart
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Interrupts
Technical Data
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Technical Data — MC68HC705C8A
Section 5. Resets
5.1 Contents
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5.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
5.3
Reset Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
5.3.1
Power-On Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
5.3.2
External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
5.3.3
Programmable and Non-Programmable
COP Watchdog Resets . . . . . . . . . . . . . . . . . . . . . . . . . . 62
5.3.3.1
Programmable COP Watchdog Reset . . . . . . . . . . . . . . .63
5.3.3.2
Non-Programmable COP Watchdog . . . . . . . . . . . . . . . . 66
5.3.4
Clock Monitor Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
5.2 Introduction
This section describes how resets initialize the microcontroller unit
(MCU).
5.3 Reset Sources
A reset immediately stops the operation of the instruction being
executed, initializes certain control bits, and loads the program counter
with a user-defined reset vector address. These conditions produce a
reset:
•
Power-on reset (POR) — Initial power-up
•
External reset — A logic 0 applied to the RESET pin
•
Internal programmable computer operating properly (COP)
watchdog timer reset
•
Internal non-programmable COP watchdog timer reset
•
Internal clock monitor reset
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5.3.1 Power-On Reset (POR)
A positive transition on the VDD pin generates a power-on reset (POR).
The POR is strictly for the power-up condition and cannot be used to
detect drops in power supply voltage.
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A 4064 tCYC (internal clock cycle) delay after the oscillator becomes
active allows the clock generator to stabilize. If the RESET pin is at
logic 0 at the end of 4064 tCYC, the MCU remains in the reset condition
until the signal on the RESET pin goes to logic 1.
5.3.2 External Reset
The minimum time required for the MCU to recognize a reset is 1 1/2
tCYC. However, to guarantee that the MCU recognizes an external reset
as an external reset and not as a COP or clock monitor reset, the RESET
pin must be low for eight tCYC. After six tCYC, the input on the RESET pin
is sampled. If the pin is still low, an external reset has occurred. If the
input is high, then the MCU assumes that the reset was initiated
internally by either the COP watchdog timer or by the clock monitor. This
method of differentiating between external and internal reset conditions
assumes that the RESET pin will rise to a logic 1 less than two tCYC after
its release and that an externally generated reset should stay active for
at least eight tCYC.
5.3.3 Programmable and Non-Programmable COP Watchdog Resets
A timeout of a COP watchdog generates a COP reset. A COP watchdog,
once enabled, is part of a software error detection system and must be
cleared periodically to start a new timeout period.
The MC68HC705C8A has two different COP watchdogs for compatibility
with devices such as the MC68HC705C8 and the MC68HC05C4A:
1. Programmable COP watchdog reset
2. Non-programmable COP watchdog
One COP has four programmable timeout periods and the other has a
fixed non-programmable timeout period.
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Reset Sources
5.3.3.1 Programmable COP Watchdog Reset
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A timeout of the 18-stage ripple counter in the programmable COP
watchdog generates a reset. Figure 5-1 is a diagram of the
programmable COP watchdog. Two registers control and monitor
operation of the programmable COP watchdog:
•
COP reset register (COPRST), $001D
•
COP control register (COPCR), $001E
To clear the programmable COP watchdog and begin a new timeout
period, write these values to the COP reset register (COPRST).
See Figure 5-2.
1. $55
2. $AA
The $55 write must precede the $AA write. Instructions may be executed
between the write operations provided that the COP watchdog does not
time out before the second write.
INTERNAL
CLOCK
(fOP)
PROGRAMMABLE COP WATCHDOG (MC68HC705C8 TYPE)
÷4
÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2
÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2
213
CM0
CM1
215
217
RESET
219
÷4
÷2 ÷2
÷2 ÷2
÷2 ÷2
221
PCOPE
COPRST
Figure 5-1. Programmable COP Watchdog Diagram
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Address:
$001D
Bit 7
6
5
4
3
2
1
Bit 0
Write:
Bit 7
6
5
4
3
2
1
Bit 0
Reset:
U
U
U
U
U
U
U
U
Read:
= Unimplemented
U = Unaffected
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Figure 5-2. Programmable COP Reset Register (COPRST)
The programmable COP control register (COPCR) shown in Figure 5-3
does these functions:
•
Flags programmable COP watchdog resets
•
Enables the clock monitor
•
Enables the programmable COP watchdog
•
Controls the timeout period of the programmable COP watchdog
Address:
Read:
$001E
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
COPF
CME
PCOPE
CM1
CM0
0
0
0
U
0
0
0
0
Write:
Reset:
= Unimplemented
U = Unaffected
Figure 5-3. Programmable COP Control Register (COPCR)
COPF — COP Flag
This read-only bit is set when a timeout of the programmable COP
watchdog occurs or when the clock monitor detects a slow or absent
internal clock. Clear the COPF bit by reading the COP control register.
Reset has no effect on the COPF bit.
1 = COP timeout or internal clock failure
0 = No COP timeout and no internal clock failure
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Reset Sources
CME — Clock Monitor Enable Bit
This read/write bit enables the clock monitor. The clock monitor sets
the COPF bit and generates a reset if it detects an absent internal
clock for a period of from 5 µs to 100 µs. CME is readable and writable
at any time. Reset clears the CME bit.
1 = Clock monitor enabled
0 = Clock monitor disabled
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NOTE:
Do not enable the clock monitor in applications with an internal clock
frequency of 200 kHz or less.
If the clock monitor detects a slow clock, it drives the bidirectional
RESET pin low for four clock cycles. If the clock monitor detects an
absent clock, it drives the RESET pin low until the clock recovers.
PCOPE — Programmable COP Enable Bit
This read/write bit enables the programmable COP watchdog.
PCOPE is readable at any time but can be written only once after
reset. Reset clears the PCOPE bit.
1 = Programmable COP watchdog enabled
0 = Programmable COP watchdog disabled
NOTE:
Programming the non-programmable COP enable bit (NCOPE) in mask
option register 2 (MOR2) to logic 1 enables the non-programmable COP
watchdog. Setting the PCOPE bit while the NCOPE bit is programmed
to logic 1 enables both COP watchdogs to operate at the same time.
(See 9.5.3 Mask Option Register 2.)
CM1 and CM0 — COP Mode Bits
These read/write bits select the timeout period of the programmable
COP watchdog. (See Table 5-1.) CM1 and CM0 can be read anytime
but can be written only once. They can be cleared only by reset.
Bits 7–5 — Unused
Bits 7–5 always read as logic 0s. Reset clears bits 7–5.
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Table 5-1. Programmable COP Timeout Period Selection
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Programmable COP Timeout Period
CM1:CM0
COP
Timeout Rate
00
fOSC = 4.0 MHz
fOP = 2.0 MHz
fOSC = 3.5795 MHz
fOP = 1.7897 MHz
fOSC = 2.0 MHz
fOP = 1.0 MHz
fOSC = 1.0 MHz
fOP = 0.5 MHz
fOP ÷ 215
16.38 ms
18.31 ms
32.77 ms
65.54 ms
01
fOP ÷ 217
65.54 ms
73.24 ms
131.07 ms
262.14 ms
10
fOP ÷ 219
262.14 ms
292.95 ms
524.29 ms
1.048 s
11
fOP ÷ 221
1.048 s
1.172 s
2.097 s
4.194 s
5.3.3.2 Non-Programmable COP Watchdog
A timeout of the 18-stage ripple counter in the non-programmable COP
watchdog generates a reset. The timeout period is 65.536 ms when
fOSC = 4 MHz. The timeout period for the non-programmable COP timer
is a direct function of the crystal frequency. The equation is:
Timeout period =
262,144
fOSC
Two memory locations control operation of the non-programmable COP
watchdog:
1. Non-programmable COP enable bit (NCOPE) in mask option
register 2 (MOR2)
Programming the NCOPE bit in MOR2 to a logic 1 enables the
non-programmable COP watchdog. See 9.5.3 Mask Option
Register 2.
NOTE:
Writing a logic 1 to the programmable COP enable bit (PCOPE) in the
COP control register enables the programmable COP watchdog. Setting
the PCOPE bit while the NCOPE bit is programmed to logic 1 enables
both COP watchdogs to operate at the same time.
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Reset Sources
2. COP clear bit (COPC) at address $1FF0
To clear the non-programmable COP watchdog and start a new
COP timeout period, write a logic 0 to bit 0 of address $1FF0.
Reading address $1FF0 returns the mask option register 1
(MOR1) data at that location. See 9.5.2 Mask Option Register 1.
NOTE:
The non-programmable watchdog COP is disabled in bootloader mode,
even if the NCOPE bit is programmed.
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Figure 5-4 is a diagram of the non-programmable COP.
NON-PROGRAMMABLE COP WATCHDOG (MC68HC05C4A TYPE)
÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2
NCOPE
÷2 ÷2 ÷2 ÷2 ÷2
Figure 5-4. Non-Programmable COP Watchdog Diagram
5.3.4 Clock Monitor Reset
When the CME bit in the COP control register is set, the clock monitor
detects the absence of the internal bus clock for a certain period of time.
The timeout period depends on processing parameters and varies from
5 µs to 100 µs, which implies that systems using a bus clock rate of
200 kHz or less should not use the clock monitor function.
If a slow or absent clock is detected, the clock monitor causes a system
reset. The reset is issued to the external system for four bus cycles using
the bidirectional RESET pin.
Special consideration is required when using the STOP instruction with
the clock monitor. Since STOP causes the system clocks to halt, the
clock monitor issues a system reset when STOP is executed.
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The clock monitor is a useful backup to the COP watchdog system.
Because the watchdog timer requires a clock to function, it cannot
indicate a system clock failure. The clock monitor would detect such a
condition and force the MCU to a reset state. Clocks are not required for
the MCU to reach a reset condition. They are, however, required to bring
the MCU through the reset sequence and back to run condition.
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Technical Data — MC68HC705C8A
Section 6. Low-Power Modes
6.1 Contents
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6.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
6.3
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
6.3.1
SCI During Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
6.3.2
SPI During Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
6.3.3
Programmable COP Watchdog in Stop Mode . . . . . . . . . . . 71
6.3.4
Non-Programmable COP Watchdog in Stop Mode . . . . . . . 73
6.4
Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
6.4.1
Programmable COP Watchdog in Wait Mode . . . . . . . . . . . 75
6.4.2
Non-Programmable COP Watchdog in Wait Mode . . . . . . . 75
6.5
Data-Retention Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
6.2 Introduction
This section describes the three low-power modes:
•
Stop mode
•
Wait mode
•
Data-retention mode
6.3 Stop Mode
The STOP instruction places the microcontroller unit (MCU) in its lowest
power consumption mode. In stop mode, the internal oscillator is turned
off, halting all internal processing including timer, serial communications
interface (SCI), and master mode serial peripheral interface (SPI)
operation. See Figure 6-1.
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Low-Power Modes
STOP
WAIT
STOP OSCILLATOR
AND ALL CLOCKS
CLEAR I BIT
OSCILLATOR ACTIVE
TIMER, SCI, AND SPI
CLOCKS ACTIVE
CPU CLOCKS STOPPED
CLEAR I BIT
RESET
RESET
NO
NO
EXTERNAL
INTERRUPT
(IRQ)
NO
YES
YES
YES
EXTERNAL
INTERRUPT
(IRQ)
NO
YES
INTERNAL TIMER
INTERRUPT
YES
TURN ON OSCILLATOR
WAIT FOR TIME
DELAY TO STABILIZE
1. FETCH RESET VECTOR
OR
2. SERVICE INTERRUPT:
a. STACK
b. SET I BIT
c. VECTOR TO
INTERRUPT ROUTINE
NO
RESTART CPU CLOCK
YES
1. FETCH RESET VECTOR
OR
2. SERVICE INTERRUPT:
a. STACK
b. SET I BIT
c. VECTOR TO
INTERRUPT ROUTINE
INTERNAL SCI
INTERRUPT
NO
YES
INTERNAL SPI
INTERRUPT
NO
Figure 6-1. Stop/Wait Mode Function Flowchart
During stop mode, the I bit in the condition code register (CCR) is
cleared to enable external interrupts. All other registers and memory
remain unaltered. All input/output (I/O) lines remain unchanged. The
processor can be brought out of stop mode only by an external interrupt
or reset.
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Low-Power Modes
Stop Mode
6.3.1 SCI During Stop Mode
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When the MCU enters stop mode, the baud rate generator stops, halting
all SCI activity. If the STOP instruction is executed during a transmitter
transfer, that transfer is halted. If a low input to the IRQ pin is used to exit
stop mode, the transfer resumes.
If the SCI receiver is receiving data and stop mode is entered, received
data sampling stops because the baud rate generator stops, and all
subsequent data is lost. Therefore, all SCI transfers should be in the idle
state when the STOP instruction is executed.
6.3.2 SPI During Stop Mode
When the MCU enters stop mode, the baud rate generator stops,
terminating all master mode SPI operations. If the STOP instruction is
executed during an SPI transfer, that transfer halts until the MCU exits
stop mode by a low signal on the IRQ pin. If reset is used to exit stop
mode, the SPI control and status bits are cleared, and the SPI is
disabled.
If the MCU is in slave mode when the STOP instruction is executed, the
slave SPI continues to operate and can still accept data and clock
information in addition to transmitting its own data back to a master
device. At the end of a possible transmission with a slave SPI in stop
mode, no flags are set until a low on the IRQ pin wakes up the MCU.
NOTE:
Although a slave SPI in stop mode can exchange data with a master SPI,
the status bits of a slave SPI are inactive in stop mode.
6.3.3 Programmable COP Watchdog in Stop Mode
The STOP instruction turns off the internal oscillator and suspends the
computer operating properly (COP) watchdog counter. If the RESET pin
brings the MCU out of stop mode, the reset function clears and disables
the COP watchdog.
If the IRQ pin brings the MCU out of stop mode, the COP counter
resumes counting from its suspended value after the 4064-tCYC clock
stabilization delay. See Figure 6-2.
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NOTE:
If the clock monitor is enabled (CME = 1), the STOP instruction causes
the clock monitor to time out and reset the MCU.
STOP
Freescale Semiconductor, Inc...
CLEAR I BIT IN CCR
TURN OFF INTERNAL OSCILLATOR
SUSPEND COP COUNTER
EXTERNAL
RESET?
YES
NO
NO
EXTERNAL
INTERRUPT?
TURN ON INTERNAL OSCILLATOR
CLEAR COP COUNTER
CLEAR PCOPE BIT IN COPCR
YES
TURN ON INTERNAL OSCILLATOR
END OF
STABILIZATION
DELAY?
YES
NO
END OF
STABILIZATION
DELAY?
YES
NO
TURN ON INTERNAL CLOCK
TURN ON INTERNAL CLOCK
RESUME COP WATCHDOG COUNT
1. LOAD PC WITH RESET VECTOR
OR
2. SERVICE INTERRUPT:
a. SAVE CPU REGISTERS ON STACK
b. SET I BIT IN CCR
c. LOAD PC WITH INTERRUPT VECTOR
1. LOAD PC WITH RESET VECTOR
OR
2. SERVICE INTERRUPT:
a. SAVE CPU REGISTERS ON STACK
b. SET I BIT IN CCR
c. LOAD PC WITH INTERRUPT VECTOR
Figure 6-2. Programmable COP Watchdog
in Stop Mode (PCOPE = 1) Flowchart
Technical Data
72
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Wait Mode
6.3.4 Non-Programmable COP Watchdog in Stop Mode
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The STOP instruction has these effects on the non-programmable COP
watchdog:
•
Turns off the oscillator and the COP watchdog counter
•
Clears the COP watchdog counter
If the RESET pin brings the MCU out of stop mode, the COP watchdog
begins counting immediately. The reset function clears the COP counter
again after the 4064-tCYC clock stabilization delay.
If the IRQ pin brings the MCU out of stop mode, the COP watchdog
begins counting immediately. The IRQ function does not clear the
COP counter again after the 4064-tCYC clock stabilization delay. See
Figure 6-3.
NOTE:
If the clock monitor is enabled (CME = 1), the STOP instruction causes
it to time out and reset the MCU.
6.4 Wait Mode
The WAIT instruction places the MCU in an intermediate power
consumption mode. All central processor unit (CPU) activity is
suspended, but the oscillator, capture/compare timer, SCI, and SPI
remain active. Any interrupt or reset brings the MCU out of wait mode.
See Figure 6-1.
The WAIT instruction has these effects on the CPU:
•
Clears the I bit in the condition code register, enabling interrupts
•
Stops the CPU clock, but allows the internal clock to drive the
capture/compare timer, SCI, and SPI
The WAIT instruction does not affect any other registers or I/O lines. The
capture/compare timer, SCI, and SPI can be enabled to allow a periodic
exit from wait mode.
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STOP
CLEAR I BIT IN CCR
CLEAR COP COUNTER
TURN OFF INTERNAL OSCILLATOR
TURN OFF COP COUNTER
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EXTERNAL
RESET?
YES
NO
NO
EXTERNAL
INTERRUPT?
TURN ON INTERNAL OSCILLATOR
TURN ON COP WATCHDOG
YES
TURN ON INTERNAL OSCILLATOR
TURN ON COP WATCHDOG
END OF
STABILIZATION
DELAY?
YES
NO
END OF
STABILIZATION
DELAY?
YES
NO
CLEAR COP COUNTER
TURN ON INTERNAL CLOCK
TURN ON INTERNAL CLOCK
1. LOAD PC WITH RESET VECTOR
OR
2. SERVICE INTERRUPT:
a. SAVE CPU REGISTERS ON STACK
b. SET I BIT IN CCR
c. LOAD PC WITH INTERRUPT VECTOR
1. LOAD PC WITH RESET VECTOR
OR
2. SERVICE INTERRUPT:
a. SAVE CPU REGISTERS ON STACK
b. SET I BIT IN CCR
c. LOAD PC WITH INTERRUPT VECTOR
Figure 6-3. Non-Programmable COP Watchdog
in Stop Mode (NCOPE = 1) Flowchart
Technical Data
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Data-Retention Mode
6.4.1 Programmable COP Watchdog in Wait Mode
The programmable COP watchdog is active during wait mode. Software
must periodically bring the MCU out of wait mode to clear the
programmable COP watchdog.
Freescale Semiconductor, Inc...
6.4.2 Non-Programmable COP Watchdog in Wait Mode
The non-programmable COP watchdog is active during wait mode.
Software must periodically bring the MCU out of wait mode to clear the
non-programmable COP watchdog.
6.5 Data-Retention Mode
In data-retention mode, the MCU retains random-access memory (RAM)
contents and CPU register contents at VDD voltages as low as 2.0 Vdc.
The data-retention feature allows the MCU to remain in a low
power-consumption state during which it retains data, but the CPU
cannot execute instructions.
To put the MCU in data-retention mode:
1. Drive the RESET pin to logic 0.
2. Lower VDD voltage. The RESET pin must remain low continuously
during data-retention mode.
To take the MCU out of data-retention mode:
1. Return VDD to normal operating voltage.
2. Return the RESET pin to logic 1.
MC68HC705C8A — Rev. 3
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Low-Power Modes
Technical Data
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MC68HC705C8A — Rev. 3
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Technical Data — MC68HC705C8A
Section 7. Parallel Input/Output (I/O)
7.1 Contents
Freescale Semiconductor, Inc...
7.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
7.3
Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
7.3.1
Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
7.3.2
Data Direction Register A. . . . . . . . . . . . . . . . . . . . . . . . . . . 79
7.3.3
Port A Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
7.4
Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
7.4.1
Port B Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
7.4.2
Data Direction Register B. . . . . . . . . . . . . . . . . . . . . . . . . . . 82
7.4.3
Port B Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
7.5
Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
7.5.1
Port C Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
7.5.2
Data Direction Register C. . . . . . . . . . . . . . . . . . . . . . . . . . . 86
7.5.3
Port C Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
7.6
Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
7.2 Introduction
This section describes the programming of ports A, B, C, and D.
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Parallel Input/Output (I/O)
7.3 Port A
Port A is an 8-bit, general-purpose, bidirectional input/output (I/O) port.
7.3.1 Port A Data Register
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The port A data register (PORTA) shown in Figure 7-1 contains a data
latch for each of the eight port A pins. When a port A pin is programmed
to be an output, the state of its data register bit determines the state of
the output pin. When a port A pin is programmed to be an input, reading
the port A data register returns the logic state of the pin.
Address:
$0000
Bit 7
6
5
4
3
2
1
Bit 0
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
Read:
Write:
Reset:
Unaffected by reset
Figure 7-1. Port A Data Register (PORTA)
PA7–PA0 — Port A Data Bits
These read/write bits are software programmable. Data direction of
each bit is under the control of the corresponding bit in data direction
register A. Reset has no effect on port A data.
Technical Data
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Parallel Input/Output (I/O)
Port A
7.3.2 Data Direction Register A
The contents of data direction register A (DDRA) shown in Figure 7-2
determine whether each port A pin is an input or an output. Writing a
logic 1 to a DDRA bit enables the output buffer for the associated port A
pin; a logic 0 disables the output buffer. A reset clears all DDRA bits,
configuring all port A pins as inputs.
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Address:
$0004
Bit 7
6
5
4
3
2
1
Bit 0
DDRA7
DDRA6
DDRA5
DDRA4
DDRA3
DDRA2
DDRA1
DDRA0
0
0
0
0
0
0
0
0
Read:
Write:
Reset:
Figure 7-2. Data Direction Register A (DDRA)
DDRA7–DDRA0 — Port A Data Direction Bits
These read/write bits control port A data direction. Reset clears bits
DDRA7–DDRA0.
1 = Corresponding port A pin configured as output
0 = Corresponding port A pin configured as input
NOTE:
Avoid glitches on port A pins by writing to the port A data register before
changing DDRA bits from logic 0 to logic 1.
MC68HC705C8A — Rev. 3
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Parallel Input/Output (I/O)
7.3.3 Port A Logic
Figure 7-3 is a diagram of the port A I/O logic.
READ $0004
WRITE $0004
DATA DIRECTION
REGISTER A
BIT DDRAx
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INTERNAL DATA BUS
RESET
PORT A DATA
REGISTER
BIT PAx
WRITE $0000
PAx
READ $0000
Figure 7-3. Port A I/O Logic
When a port A pin is programmed to be an output, the state of its data
register bit determines the state of the output pin. When a port A pin is
programmed to be an input, reading the port A data register returns the
logic state of the pin.
The data latch can always be written, regardless of the state of its DDRA
bit. Table 7-1 summarizes the operation of the port A pins.
Table 7-1. Port A Pin Functions
Accesses to DDRA
DDRA Bit
Accesses to PORTA
I/O Pin Mode
Read/Write
Read
Write
0
Input, Hi-Z(1)
DDRA7–DDRA0
Pin
PA7–PA0(2)
1
Output
DDRA7–DDRA0
PA7–PA0
PA7–PA0
1. Hi-Z = high impedance
2. Writing affects data register but does not affect input.
NOTE:
To avoid excessive current draw, tie all unused input pins to VDD or VSS,
or change I/O pins to outputs by writing to DDRA in user code as early
as possible.
Technical Data
80
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Parallel Input/Output (I/O)
Port B
7.4 Port B
Port B is an 8-bit, general-purpose, bidirectional I/O port. Port B pins can
also be configured to function as external interrupts. The port B pullup
devices are enabled in mask option register 1 (MOR1). See 9.5.2 Mask
Option Register 1 and 4.3.3 Port B Interrupts.
7.4.1 Port B Data Register
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The port B data register (PORTB) shown in Figure 7-4 contains a data
latch for each of the eight port B pins.
Address:
$0001
Bit 7
6
5
4
3
2
1
Bit 0
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
Read:
Write:
Reset:
Unaffected by reset
Figure 7-4. Port B Data Register (PORTB)
PB7–PB0 — Port B Data Bits
These read/write bits are software programmable. Data direction of
each bit is under the control of the corresponding bit in data direction
register B. Reset has no effect on port B data.
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7.4.2 Data Direction Register B
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The contents of data direction register B (DDRB) shown in Figure 7-5
determine whether each port B pin is an input or an output. Writing a
logic 1 to a DDRB bit enables the output buffer for the associated port B
pin; a logic 0 disables the output buffer. A reset clears all DDRB bits,
configuring all port B pins as inputs. If the pullup devices are enabled by
mask option, setting a DDRB bit to a logic 1 turns off the pullup device
for that pin.
Address:
$0005
Bit 7
6
5
4
3
2
1
Bit 0
DDRB7
DDRB6
DDRB5
DDRB4
DDRB3
DDRB2
DDRB1
DDRB0
0
0
0
0
0
0
0
0
Read:
Write:
Reset:
Figure 7-5. Data Direction Register B (DDRB)
DDRB7–DDRB0 — Port B Data Direction Bits
These read/write bits control port B data direction. Reset clears bits
DDRB7–DDRB0.
1 = Corresponding port B pin configured as output
0 = Corresponding port B pin configured as input
NOTE:
Avoid glitches on port B pins by writing to the port B data register before
changing DDRB bits from logic 0 to logic 1.
Technical Data
82
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Parallel Input/Output (I/O)
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Parallel Input/Output (I/O)
Port B
7.4.3 Port B Logic
Figure 7-6 shows the port B I/O logic.
VDD
PBPU7
FROM MOR1
READ $0005
INTERNAL DATA BUS
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WRITE $0005
DATA DIRECTION
REGISTER B
BIT DDRB7
RESET
PORT B DATA
REGISTER
BIT PB7
WRITE $0001
PB7
READ $0001
IRQ
FROM OPTION
REGISTER
VDD
D
EXTERNAL
INTERRUPT
REQUEST
Q
IRQ
LATCH
C
Q
R
FROM OTHER
PORT B PINS
I BIT
FROM CCR
IRQ
RESET
EXTERNAL INTERRUPT VECTOR FETCH
Figure 7-6. Port B I/O Logic
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Parallel Input/Output (I/O)
When a port B pin is programmed as an output, reading the port bit reads
the value of the data latch and not the voltage on the pin itself. When a
port B pin is programmed as an input, reading the port bit reads the
voltage level on the pin. The data latch can always be written, regardless
of the state of its DDRB bit.
Table 7-2. Port B Pin Functions
Accesses to DDRB
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DDRB Bit
Accesses to PORTB
I/O Pin Mode
Read/Write
Read
Write
0
Input, Hi-Z(1)
DDRB7–DDRB0
Pin
PB7–PB0(2)
1
Output
DDRB7–DDRB0
PB7–PB0
PB7–PB0
1. Hi-Z = high impedance
2. Writing affects data register but does not affect input.
NOTE:
To avoid excessive current draw, tie all unused input pins to VDD or VSS,
or for I/O pins change to outputs by writing to DDRB in user code as early
as possible.
Technical Data
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MC68HC705C8A — Rev. 3
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Parallel Input/Output (I/O)
Port C
7.5 Port C
Port C is an 8-bit, general-purpose, bidirectional I/O port. PC7 has a high
current sink and source capability.
7.5.1 Port C Data Register
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The port C data register (PORTC) shown in Figure 7-7 contains a data
latch for each of the eight port C pins. When a port C pin is programmed
to be an output, the state of its data register bit determines the state of
the output pin. When a port C pin is programmed to be an input, reading
the port C data register returns the logic state of the pin.
Address:
$0002
Bit 7
6
5
4
3
2
1
Bit 0
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
Read:
Write:
Reset:
Unaffected by reset
Figure 7-7. Port C Data Register (PORTC)
PC7–PC0 — Port C Data Bits
These read/write bits are software programmable. Data direction of
each bit is under the control of the corresponding bit in data direction
register C. PC7 has a high current sink and source capability. Reset
has no effect on port C data.
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7.5.2 Data Direction Register C
The contents of data direction register C (DDRC) shown in Figure 7-8
determine whether each port C pin is an input or an output. Writing a
logic 1 to a DDRC bit enables the output buffer for the associated port C
pin; a logic 0 disables the output buffer. A reset clears all DDRC bits,
configuring all port C pins as inputs.
Freescale Semiconductor, Inc...
Address:
$0006
Bit 7
6
5
4
3
2
1
Bit 0
DDRC7
DDRC6
DDRC5
DDRC4
DDRC3
DDRC2
DDRC1
DDRC0
0
0
0
0
0
0
0
0
Read:
Write:
Reset:
Figure 7-8. Data Direction Register C (DDRC)
DDRC7–DDRC0 — Port C Data Direction Bits
These read/write bits control port C data direction. Reset clears bits
DDRC7–DDRC0.
1 = Corresponding port C pin configured as output
0 = Corresponding port C pin configured as input
NOTE:
Avoid glitches on port C pins by writing to the port C data register before
changing DDRC bits from logic 0 to logic 1.
Technical Data
86
MC68HC705C8A — Rev. 3
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Port C
7.5.3 Port C Logic
Figure 7-9 shows port C I/O logic.
READ $0006
WRITE $0006
DATA DIRECTION
REGISTER C
BIT DDRCx
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INTERNAL DATA BUS
RESET
PORT C DATA
REGISTER
BIT PCx
WRITE $0002
PCx
READ $0002
Figure 7-9. Port C I/O Logic
When a port C pin is programmed as an output, reading the port bit reads
the value of the data latch and not the voltage on the pin. When a port C
pin is programmed as an input, reading the port bit reads the voltage
level on the pin. The data latch can always be written, regardless of the
state of its DDRC bit. Table 7-3 summarizes the operation of the port C
pins.
Table 7-3. Port C Pin Functions
Accesses to DDRC
DDRC Bit
Accesses to PORTC
I/O Pin Mode
Read/Write
Read
Write
0
Input, Hi-Z(1)
DDRC7–DDRC0
Pin
PC7–PC0(2)
1
Output
DDRC7–DDRC0
PC7–PC0
PC7–PC0
1. Hi-Z = high impedance
2. Writing affects data register but does not affect input.
NOTE:
To avoid excessive current draw, tie all unused input pins to VDD or VSS
or change I/O pins to outputs by writing to DDRC in user code as early
as possible.
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Parallel Input/Output (I/O)
7.6 Port D
Port D is a 7-bit, special-purpose, input-only port that has no data
register. Reading address $0003 returns the logic states of the port D
pins.
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Port D shares pins PD5–PD2 with the serial peripheral interface module
(SPI). When the SPI is enabled, PD5–PD2 read as logic 0s. When the
SPI is disabled, reading address $0003 returns the logic states of the
PD5–PD2 pins.
Port D shares pins PD1 and PD0 with the SCI module. When the SCI is
enabled, PD1 and PD0 read as logic 0s. When the SCI is disabled,
reading address $0003 returns the logic states of the PD1 and PD0 pins.
Address:
$0003
Bit 7
Read:
PD7
6
5
4
3
2
1
Bit 0
SS
SCK
MOSI
MISO
TDO
RDI
Write:
Reset:
Unaffected by reset
= Unimplemented
Figure 7-10. Port D Fixed Input Register (PORTD)
Technical Data
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MC68HC705C8A — Rev. 3
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Technical Data — MC68HC705C8A
Section 8. Capture/Compare Timer
8.1 Contents
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8.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
8.3
Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
8.3.1
Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
8.3.2
Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
8.4
Timer I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
8.4.1
Timer Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
8.4.2
Timer Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
8.4.3
Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
8.4.4
Alternate Timer Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . 98
8.4.5
Input Capture Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 100
8.4.6
Output Compare Registers. . . . . . . . . . . . . . . . . . . . . . . . . 101
8.2 Introduction
This section describes the operation of the 16-bit capture/compare timer.
Figure 8-1 shows the structure of the timer module. Figure 8-2 is a
summary of the timer input/output (I/O) registers.
8.3 Timer Operation
The core of the capture/compare timer is a 16-bit free-running counter.
The counter is the timing reference for the input capture and output
compare functions. The input capture and output compare functions can
latch the times at which external events occur, measure input
waveforms, and generate output waveforms and timing delays. Software
can read the value in the counter at any time without affecting the
counter sequence.
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Capture/Compare Timer
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TCAP
EDGE
SELECT/
DETECT
LOGIC
ICRH ($0014)
ICRL ($0015)
TRH ($0018)
TRL ($0019)
÷4
16-BIT COUNTER
OVERFLOW
ATRH ($001A)
INTERNAL CLOCK (XTAL ÷ 2)
PIN
CONTROL
LOGIC
16-BIT COMPARATOR
OCRH ($0016)
ATRL ($001B)
TCMP
OCRL ($0017)
$0012
TIMER CONTROL REGISTER
TOF
OCF
ICF
OLVL
IEDG
TOIE
OCIE
ICIE
TIMER
INTERRUPT
REQUEST
TIMER STATUS REGISTER
$0013
INTERNAL DATA BUS
Figure 8-1. Timer Block Diagram
Technical Data
90
MC68HC705C8A — Rev. 3
Capture/Compare Timer
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Capture/Compare Timer
Timer Operation
Addr.
Register Name
$0012
Read:
Timer Control Register
(TCR) Write:
See page 94.
Reset:
Freescale Semiconductor, Inc...
$0014
$0015
$0017
6
5
4
3
2
1
Bit 0
ICIE
OCIE
TOIE
0
0
0
IEDG
OLVL
0
0
0
0
0
0
U
0
ICF
OCF
TOF
0
0
0
0
0
U
U
U
0
0
0
0
0
Read: Bit 15
Input Capture Register
High (ICRH) Write:
See page 100.
Reset:
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Read:
Input Capture Register
Low (ICRL) Write:
See page 100.
Reset:
Bit 6
Bit 2
Bit 1
Bit 0
Bit 10
Bit 9
Bit 8
Bit 2
Bit 1
Bit 0
Bit 10
Bit 9
Bit 8
Bit 2
Bit 1
Bit 0
Bit 10
Bit 9
Bit 8
Bit 2
Bit 1
Bit 0
Read:
Timer Status Register
(TSR) Write:
See page 96.
Reset:
$0013
$0016
Bit 7
Bit 7
$0018
$0019
$001A
$001B
Bit 5
Bit 4
Bit 3
Unaffected by reset
Output Compare Register Read:
Bit 15
High (OCRH)
Write:
See page 101.
Reset:
Read:
Output Compare Register
Low (OCRL) Write:
See page 101.
Reset:
Unaffected by reset
Bit 7
Bit 14
Bit 13
Bit 12
Bit 11
Unaffected by reset
Bit 6
Bit 5
Bit 4
Bit 3
Unaffected by reset
Read: Bit 15
Timer Register High
(TRH) Write:
See page 97.
Reset:
Bit 14
Read:
Timer Register Low
(TRL) Write:
See page 97.
Reset:
Bit 6
Bit 7
Bit 13
Bit 12
Bit 11
Reset initializes TRH to $FF
Bit 5
Bit 4
Bit 3
Reset initializes TRL to $FC
Read: Bit 15
Alternate Timer Register
High (ATRH) Write:
See page 99.
Reset:
Bit 14
Read:
Alternate Timer Register
Low (ATRL) Write:
See page 99.
Reset:
Bit 6
Bit 7
Bit 13
Bit 12
Bit 11
Reset initializes ATRH to $FF
Bit 5
Bit 4
Bit 3
Reset initializes ATRL to $FC
= Unimplemented
U = Unaffected
Figure 8-2. Timer I/O Register Summary
MC68HC705C8A — Rev. 3
MOTOROLA
Technical Data
Capture/Compare Timer
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Capture/Compare Timer
Because of the 16-bit timer architecture, the I/O registers for the input
capture and output compare functions are pairs of 8-bit registers.
Because the counter is 16 bits long and preceded by a fixed
divide-by-four prescaler, the counter rolls over every 262,144 internal
clock cycles. Timer resolution with a 4-MHz crystal is 2 µs.
8.3.1 Input Capture
Freescale Semiconductor, Inc...
The input capture function can record the time at which an external event
occurs. When the input capture circuitry detects an active edge on the
input capture pin (TCAP), it latches the contents of the timer registers
into the input capture registers. The polarity of the active edge is
programmable.
Latching values into the input capture registers at successive edges of
the same polarity measures the period of the input signal on the TCAP
pin. Latching the counter values at successive edges of opposite polarity
measures the pulse width of the signal. Figure 8-3 shows the logic of the
input capture function.
15
$0018
8
TIMER REGISTER HIGH
TCAP
EDGE
SELECT/DETECT
LOGIC
0
TIMER REGISTER LOW
8
15
LATCH
$0019
7
7
0
INPUT CAPTURE REGISTER HIGH
INPUT CAPTURE REGISTER LOW
$0014
$0015
TOF
OCF
ICF
OLVL
TOIE
OCIE
TIMER CONTROL REGISTER
TIMER STATUS REGISTER
$0012
$0013
IEDG
ICIE
TIMER
INTERRUPT
REQUEST
Figure 8-3. Input Capture Operation
Technical Data
92
MC68HC705C8A — Rev. 3
Capture/Compare Timer
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Capture/Compare Timer
Timer Operation
8.3.2 Output Compare
Software can use the output compare register to measure time periods,
to generate timing delays, or to generate a pulse of specific duration or
a pulse train of specific frequency and duty cycle on the TCMP pin.
Figure 8-4 shows the logic of the output compare function.
15
0
COUNTER LOW BYTE
COUNTER HIGH BYTE
PIN
CONTROL
LOGIC
16-BIT COMPARATOR
8
15
TCMP
0
7
OUTPUT COMPARE REGISTER HIGH
OUTPUT COMPARE REGISTER LOW
$0016
$0017
TOF
OCF
ICF
TOIE
OCIE
TIMER
INTERRUPT
REQUEST
ICIE
Freescale Semiconductor, Inc...
The output compare function can generate an output signal when the
16-bit counter reaches a selected value. Software writes the selected
value into the output compare registers. On every fourth internal clock
cycle the output compare circuitry compares the value of the counter to
the value written in the output compare registers. When a match occurs,
the timer transfers the programmable output level bit (OLVL) from the
timer control register to the output compare pin (TCMP).
TIMER STATUS REGISTER
TIMER STATUS REGISTER
$0012
$0013
Figure 8-4. Output Compare Operation
MC68HC705C8A — Rev. 3
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Capture/Compare Timer
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Capture/Compare Timer
8.4 Timer I/O Registers
Freescale Semiconductor, Inc...
These registers control and monitor the timer operation:
•
Timer control register (TCR)
•
Timer status register (TSR)
•
Timer registers (TRH and TRL)
•
Alternate timer registers (ATRH and ATRL)
•
Input capture registers (ICRH and ICRL)
•
Output compare registers (OCRH and OCRL)
8.4.1 Timer Control Register
The timer control register (TCR) as shown in Figure 8-5 performs these
functions:
•
Enables input capture interrupts
•
Enables output compare interrupts
•
Enables timer overflow interrupts
•
Controls the active edge polarity of the TCAP signal
•
Controls the active level of the TCMP output
Address:
$0012
Bit 7
6
5
4
3
2
1
Bit 0
ICIE
OCIE
TOIE
0
0
0
IEDG
OLVL
0
0
0
0
0
0
U
0
Read:
Write:
Reset:
U = Unaffected
Figure 8-5. Timer Control Register (TCR)
Technical Data
94
MC68HC705C8A — Rev. 3
Capture/Compare Timer
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Capture/Compare Timer
Timer I/O Registers
ICIE — Input Capture Interrupt Enable Bit
This read/write bit enables interrupts caused by an active signal on
the TCAP pin. Reset clears the ICIE bit.
1 = Input capture interrupts enabled
0 = Input capture interrupts disabled
OCIE — Output Compare Interrupt Enable Bit
Freescale Semiconductor, Inc...
This read/write bit enables interrupts caused by an active signal on
the TCMP pin. Reset clears the OCIE bit.
1 = Output compare interrupts enabled
0 = Output compare interrupts disabled
TOIE — Timer Overflow Interrupt Enable Bit
This read/write bit enables interrupts caused by a timer overflow.
Reset clears the TOIE bit.
1 = Timer overflow interrupts enabled
0 = Timer overflow interrupts disabled
IEDG — Input Edge Bit
The state of this read/write bit determines whether a positive or
negative transition on the TCAP pin triggers a transfer of the contents
of the timer register to the input capture registers. Reset has no effect
on the IEDG bit.
1 = Positive edge (low-to-high transition) triggers input capture
0 = Negative edge (high-to-low transition) triggers input capture
OLVL — Output Level Bit
The state of this read/write bit determines whether a logic 1 or a
logic 0 appears on the TCMP pin when a successful output compare
occurs. Reset clears the OLVL bit.
1 = TCMP goes high on output compare
0 = TCMP goes low on output compare
Bits 4–2 — Not used; these bits always read 0
MC68HC705C8A — Rev. 3
MOTOROLA
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Capture/Compare Timer
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Capture/Compare Timer
8.4.2 Timer Status Register
Freescale Semiconductor, Inc...
The timer status register (TSR) is a read-only register shown in
Figure 8-6 contains flags for these events:
•
An active signal on the TCAP pin, transferring the contents of the
timer registers to the input capture registers
•
A match between the 16-bit counter and the output compare
registers, transferring the OLVL bit to the TCMP pin
•
A timer rollover from $FFFF to $0000
Address:
Read:
$0013
Bit 7
6
5
4
3
2
1
Bit 0
ICF
OCF
TOF
0
0
0
0
0
U
U
U
0
0
0
0
0
Write:
Reset:
= Unimplemented
U = Unaffected
Figure 8-6. Timer Status Register (TSR)
ICF — Input Capture Flag
The ICF bit is set automatically when an edge of the selected polarity
occurs on the TCAP pin. Clear the ICF bit by reading the timer status
register with ICF set and then reading the low byte ($0015) of the
input capture registers. Reset has no effect on ICF.
1 = Input capture
0 = No input capture
OCF — Output Compare Flag
The OCF bit is set automatically when the value of the timer registers
matches the contents of the output compare registers. Clear the OCF
bit by reading the timer status register with OCF set and then reading
the low byte ($0017) of the output compare registers. Reset has no
effect on OCF.
1 = Output compare
0 = No output compare
Technical Data
96
MC68HC705C8A — Rev. 3
Capture/Compare Timer
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Capture/Compare Timer
Timer I/O Registers
TOF — Timer Overflow Flag
The TOF bit is automatically set when the 16-bit counter rolls over
from $FFFF to $0000. Clear the TOF bit by reading the timer status
register with TOF set and then reading the low byte ($0019) of the
timer registers. Reset has no effect on TOF.
1 = Timer overflow
0 = No timer overflow
Freescale Semiconductor, Inc...
Bits 4–0 — Not used; these bits always read 0
8.4.3 Timer Registers
The read-only timer registers (TRH and TRL) shown in Figure 8-7
contain the current high and low bytes of the 16-bit counter. Reading
TRH before reading TRL causes TRL to be latched until TRL is read.
Reading TRL after reading the timer status register clears the timer
overflow flag bit (TOF). Writing to the timer registers has no effect.
Bit 7
6
5
4
3
2
1
Bit 0
Bit 11
Bit 10
Bit 9
Bit 8
Bit 2
Bit 1
Bit 0
Register Name and Address: Timer Register High — $0018
Read:
Bit 15
Bit 14
Bit 13
Bit 12
Write:
Reset:
Reset initializes TRH to $FF
Register Name and Address: Timer Register Low — $0019
Read:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Write:
Reset:
Reset initializes TRL to $FC
= Unimplemented
Figure 8-7. Timer Registers (TRH and TRL)
MC68HC705C8A — Rev. 3
MOTOROLA
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Capture/Compare Timer
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Capture/Compare Timer
Reading TRH returns the current value of the high byte of the counter
and causes the low byte to be latched into a buffer, as shown in
Figure 8-8. The buffer value remains fixed even if the high byte is read
more than once. Reading TRL reads the transparent low byte buffer and
completes the read sequence of the timer registers.
Freescale Semiconductor, Inc...
INTERNAL DATA BUS
7
LATCH
15
$0018
8
TIMER REGISTER HIGH
0
LOW BYTE BUFFER
7
0
TIMER REGISTER LOW
$0019
READ TRH
Figure 8-8. Timer Register Reads
NOTE:
To prevent interrupts from occurring between readings of TRH and TRL,
set the interrupt mask (I bit) in the condition code register before reading
TRH, and clear the mask after reading TRL.
8.4.4 Alternate Timer Registers
The alternate timer registers (ATRH and ATRL) shown in Figure 8-9
contain the current high and low bytes of the 16-bit counter. Reading
ATRH before reading ATRL causes ATRL to be latched until ATRL is
read. Reading does not affect the timer overflow flag (TOF). Writing to
the alternate timer registers has no effect.
Technical Data
98
MC68HC705C8A — Rev. 3
Capture/Compare Timer
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Capture/Compare Timer
Timer I/O Registers
Bit 7
6
5
4
3
2
1
Bit 0
Bit 10
Bit 9
Bit 8
Bit 2
Bit 1
Bit 0
Register Name and Address: Alternate Timer Register High — $001A
Read:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Write:
Reset:
Reset initializes ATRH to $FF
Register Name and Address: Alternate Timer Register Low — $001B
Read:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Freescale Semiconductor, Inc...
Write:
Reset:
Reset initializes ATRL to $FC
= Unimplemented
Figure 8-9. Alternate Timer Registers (ATRH and ATRL)
Reading ATRH returns the current value of the high byte of the counter
and causes the low byte to be latched into a buffer, as shown in
Figure 8-10.
INTERNAL DATA BUS
7
LATCH
15
$001A
8
ALTERNATE TIMER REGISTER HIGH
0
LOW BYTE BUFFER
7
0
ALTERNATE TIMER REGISTER LOW
$001B
READ ATRH
Figure 8-10. Alternate Timer Register Reads
NOTE:
To prevent interrupts from occurring between readings of ATRH and
ATRL, set the interrupt mask (I bit) in the condition code register before
reading ATRH, and clear the mask after reading ATRL.
MC68HC705C8A — Rev. 3
MOTOROLA
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Capture/Compare Timer
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Capture/Compare Timer
8.4.5 Input Capture Registers
When a selected edge occurs on the TCAP pin, the current high and low
bytes of the 16-bit counter are latched into the read-only input capture
registers (ICRH and ICRL) shown in Figure 8-11. Reading ICRH before
reading ICRL inhibits further captures until ICRL is read. Reading ICRL
after reading the timer status register clears the input capture flag (ICF).
Writing to the input capture registers has no effect.
Freescale Semiconductor, Inc...
Bit 7
6
5
4
3
2
1
Bit 0
Bit 10
Bit 9
Bit 8
Bit 2
Bit 1
Bit 0
Register Name and Address: Input Capture Register High — $0014
Read:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Write:
Reset:
Unaffected by reset
Register Name and Address: Input Capture Register Low — $0015
Read:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Write:
Reset:
Unaffected by reset
= Unimplemented
Figure 8-11. Input Capture Registers (ICRH and ICRL)
NOTE:
To prevent interrupts from occurring between readings of ICRH and
ICRL, set the interrupt mask (I bit) in the condition code register before
reading ICRH and clear the mask after reading ICRL.
Technical Data
100
MC68HC705C8A — Rev. 3
Capture/Compare Timer
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Capture/Compare Timer
Timer I/O Registers
8.4.6 Output Compare Registers
When the value of the 16-bit counter matches the value in the read/write
output compare registers (OCRH and OCRL) shown in Figure 8-12, the
planned TCMP pin action takes place. Writing to OCRH before writing to
OCRL inhibits timer compares until OCRL is written. Reading or writing
to OCRL after reading the timer status register clears the output
compare flag (OCF).
Freescale Semiconductor, Inc...
Bit 7
6
5
4
3
2
1
Bit 0
Bit 10
Bit 9
Bit 8
Bit 2
Bit 1
Bit 0
Register Name and Address: Output Compare Register High — $0016
Read:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Write:
Reset:
Unaffected by reset
Register Name and Address: Output Compare Register Low — $0017
Read:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Write:
Reset:
Unaffected by reset
Figure 8-12. Output Compare Registers (OCRH and OCRL)
To prevent OCF from being set between the time it is read and the time
the output compare registers are updated, use this procedure:
1. Disable interrupts by setting the I bit in the condition code register.
2. Write to OCRH. Compares are now inhibited until OCRL is written.
3. Clear bit OCF by reading the timer status register (TSR).
4. Enable the output compare function by writing to OCRL.
5. Enable interrupts by clearing the I bit in the condition code register.
MC68HC705C8A — Rev. 3
MOTOROLA
Technical Data
Capture/Compare Timer
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Freescale Semiconductor, Inc...
Capture/Compare Timer
Technical Data
102
MC68HC705C8A — Rev. 3
Capture/Compare Timer
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Technical Data — MC68HC705C8A
Section 9. EPROM/OTPROM (PROM)
9.1 Contents
Freescale Semiconductor, Inc...
9.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
9.3
EPROM/OTPROM (PROM) Programming . . . . . . . . . . . . . . . 104
9.3.1
Program Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
9.3.2
Preprogramming Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
9.4
PROM Programming Routines . . . . . . . . . . . . . . . . . . . . . . . . 111
9.4.1
Program and Verify PROM. . . . . . . . . . . . . . . . . . . . . . . . . 111
9.4.2
Verify PROM Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
9.4.3
Secure PROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
9.4.4
Secure PROM and Verify . . . . . . . . . . . . . . . . . . . . . . . . . . 113
9.4.5
Secure PROM and Dump. . . . . . . . . . . . . . . . . . . . . . . . . . 113
9.4.6
Load Program into RAM and Execute . . . . . . . . . . . . . . . . 114
9.4.7
Execute Program in RAM. . . . . . . . . . . . . . . . . . . . . . . . . . 115
9.4.8
Dump PROM Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . .115
9.5
Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
9.5.1
Option Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
9.5.2
Mask Option Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
9.5.3
Mask Option Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
9.6
EPROM Erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
9.2 Introduction
This section describes erasable, programmable read-only
memory/one-time programmable read-only memory (EPROM/OTPROM
(PROM)) programming.
MC68HC705C8A — Rev. 3
MOTOROLA
Technical Data
EPROM/OTPROM (PROM)
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EPROM/OTPROM (PROM)
9.3 EPROM/OTPROM (PROM) Programming
Freescale Semiconductor, Inc...
The internal PROM can be programmed efficiently using the Motorola
MC68HC05PGMR-2 programmer board, which can be purchased from
a Motorola-authorized distributor. The user can program the
microcontroller unit (MCU) using this printed circuit board (PCB) in
conjunction with an EPROM device already programmed with user code.
Only standalone programming is discussed in this section. For more
information concerning the MC68HC05PGMR and its usages, contact a
local Motorola representative for a copy of the MC68HC05PGMR
Programmer Board User’s Manual #2, Motorola document number
MC68HC05PGMR2/D1.
Refer to Figure 9-1 for an EPROM programming flowchart. Figure 9-2
provides a schematic of the MC68HC05PGMR PCB with the reference
designators defined in Table 9-1.
Table 9-1. MC68HC05PGMR PCB Reference Designators
Reference
Designators
Device
Type
Ground
+5 V
+12 V
–12 V
VPP
U1
2764
14, 20
1, 26, 27, 28
—
—
—
8 K x 8-bit EPROM
U2
MCU
20
40
—
—
3
40-pin DIP socket
U3
MCU
22
44
—
—
4
44-lead PLCC socket
U4
MC145406
9
16
1
8
—
Driver/receiver
VR1
NMA0512S
2.5
1
6
4
—
DC-DC converter
Technical Data
104
Notes
MC68HC705C8A — Rev. 3
EPROM/OTPROM (PROM)
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EPROM/OTPROM (PROM)
EPROM/OTPROM (PROM) Programming
START
APPLY VPP
NTRYS = 0
Freescale Semiconductor, Inc...
START AT BEGINNING
OF MEMORY
LAT = 1
WRITE PROM DATA
PGM = 1
WAIT 1 ms
PGM = 0
LAT = 0
YES
WRITE
ADDITIONAL
BYTE
NO
NTRYS = NTRYS + 1
NO
NTRYS = 2
YES
VPP OFF
END
Figure 9-1. EPROM/OTPROM Programming Flowchart
MC68HC705C8A — Rev. 3
MOTOROLA
Technical Data
EPROM/OTPROM (PROM)
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EPROM/OTPROM (PROM)
VR1 NMA0512S
DC-DC CONVERTER
(OPTIONAL)
S1
OFF
A
+5 V
ON
P1
+5 V
4
+12 V
2
–12 V
3
+V
6
OFF
1
VCC
5
0V
–V
4
GND
2
5
GND
1
+ C1
100 µF
40
VDD
+12 V
ON
VPP
R15
10 K
39
B
OSC1
–12 V
3
D1
1N4001
38
C
OSC2
VPP
VPP
1
Freescale Semiconductor, Inc...
RESET
+5 V
16
RXD
37
14
3
E
IRQ
9
P3
3
D
2
F
TCAP
30
PD1
36
PD1
G
PD7
35
2
TXD
15
2
29
PD0
+12 V
U1
2764
A0
A1
+5 V
–12 V
VPP
A3
NC
A4
27
PGM
A5
VCC
A6
28
CTS
5
C5
0.1 µF
DSR
6
(A0)
PA0
PD5
11
9
(A1)
PA1
PD4
10
(A2)
PA2
9
PD3
PA2
7
(A3)
PA3
8
6
(A4)
PA4
7
5
(A5)
PA5
6
4
(A6)
PA6
5
3
(A7)
PA7
4
PD2
PA6
PC5
20
GND
1
(A8)
25
(A9)
24
(A10)
21
(A11)
23
(A12)
2
PB0
12
(D1)
PB1
D3
A9
A10
13
(D2)
PB2
14
15
(D3)
PB3
15
16
(D4)
PB4
16
17
(D5)
PB5
17
A12
D6
OE
D7
18
(D6)
PB6
18
PC1
PB2
PC2
19
(D7)
PB7
19
28
(A8)
27
(A9)
26
(A10)
25
(A11)
24
(A12)
PC3
PC4
PB5
PB6
GND
Notes:
1. The asterisk (*) denotes option T
command only.
2. Unless otherwise specified, resistors are in ohms,
±5% 1/4 W; capacitors are in µF; voltages are dc.
PB1
PB4
D5
22
PC0
PB3
D4
A11
PB0
13
D2
M
N
PC6
12
D1
A8
GND
7
(D0)
D0
CE
23
22
PA7
11
20
DTR
L
U2
PA4 40-PIN DIP
SOCKET
PA5
DCD
8
K
31
PA3
A7
J
32
PA1
8
I
33
PA0
A2
1
26
34
PD0
10
U4
MC145406
8
1
H
TCMP
14
21
PC7
PB7
O
VSS
20
P
Q
(ENABLE)
3. Device type numbers shown in circuit are for
reference only. Device type number varies
with manufacturer.
R
S
Figure 9-2. PROM Programming Circuit
Technical Data
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EPROM/OTPROM (PROM)
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EPROM/OTPROM (PROM)
EPROM/OTPROM (PROM) Programming
R3 10 K
R2
J1
3 2 1
+5 V
A
NC
B
+12 V
NC
NC
NC
NC
2.7 K
C
R5
C2
1.0 µF
+5 V
10 M
Y1
C4
22 pF
1
NC
10 K
R1
S2
3
38
39
40
OUT
RESET
R13
10 K
R4
10 K
+5 V
C3
22 pF
2.0 MHz
IRQ
+5 V
D
P2
2
E
Freescale Semiconductor, Inc...
F
S3
G
S4
S5
S6
H
PD5
I
34
PD4
J
33
PD3
K
+5 V
+5 V
R10*
470
1 2
VERF
R9
10 K
DS2*
31
36
R12
10 K
J2
TCAP
+5 V
TCMP
PB0
(VERF)
(PROG)
NC
PROG
DS1*
(A5)
(A4)
(A3)
(A2)
(A1)
(A0)
R11*
470
+5 V
14
15
16
17
PA5
PA4
PA3
PA2
PA1
PA0
PB0
PB1
PB2
PB3
PB4
PD7
TCMP
PD5
PD4
PD3
PD2
PD1
PD0
PC0
PC1
PC2
U3
44-LEAD PLCC
SOCKET
PB1
PB2
PB3
PB4
PB5
C6
0.1 µF
39
38
37
36
35
34
33
32
31
30
29
PD5
PD4
PD3
PD2
PD1
PD0
(A8)
(A9)
(A10)
(D5)
(D6)
(D7)
18
19
20
21
22
23
24
(PROG) 25
(VERF) 26
(A12) 27
(A11) 28
NC
PB5
PB6
PB7
VSS
NC
PC7
PC6
PC5
(D0)
(D1)
(D2)
(D3)
(D4)
7
8
9
10
11
12
13
NC
PC4
PC3
N
R6
10 K
6 (A6)
PA6
5 (A7)
PA7
VPP 4
3
NC
2
IRQ
1
RESET
VDD 44
43
OSC1
42
OSC2
41
TCAP
40
NC
M
R7
10 K
R8
10 K
32
PD2
PD7
L
O
NC
NC
P
PB6
PB7
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PC0
PC1
PC2
PC3
PC4
PD1
PD0
PC5
Q
R
PC6
PC7
S
VSS
37
35
12
13
14
15
16
17
18
19
11
10
9
8
7
6
5
4
28
27
26
25
24
30
29
23
22
21
20
Figure 9-2. PROM Programming Circuit (Continued)
MC68HC705C8A — Rev. 3
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EPROM/OTPROM (PROM)
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To program the PROM MCU, the MCU is installed in the PCB, along with
an EPROM device programmed with user code; the MCU is then
subjected to a series of routines. The routines necessary to program,
verify, and secure the PROM MCU are:
•
Program and verify PROM
•
Verify PROM contents only
•
Secure PROM and verify
•
Secure PROM and dump through the serial communications
interface (SCI)
Other board routines available to the user are:
•
Load program into random-access memory (RAM) and execute
•
Execute program in RAM
•
Dump PROM contents (binary upload)
The user first configures the MCU for the bootstrap mode of operations
by installing a fabricated jumper across pins 1 and 2 of the board’s mode
select header, J1. Next, the board’s mode switches (S3, S4, S5, and S6)
are set to determine the routine to be executed after the next reset, as
shown in Table 9-2.
Table 9-2. PROM Programming Routines
Routine
S3
S4
S5
S6
Program and verify PROM
Off
Off
Off
Off
Verify PROM contents only
Off
Off
On
Off
Secure PROM contents and verify
On
Off
On
Off
Secure PROM contents and dump
On
On
On
Off
Load program into RAM and execute
Off
On
Off
Off
Execute program in RAM
Off
Off
Off
On
Dump PROM contents
Off
On
On
Off
Technical Data
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EPROM/OTPROM (PROM)
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EPROM/OTPROM (PROM)
EPROM/OTPROM (PROM) Programming
9.3.1 Program Register
The program register (PROG) shown in Figure 9-3 is used for PROM
programming.
Address:
$001C
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
LAT
0
PGM
0
0
0
0
0
0
0
0
Read:
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Write:
Reset:
Figure 9-3. Program Register (PROG)
LAT — Latch Enable Bit
This bit is both readable and writable.
1 = Enables PROM data and address bus latches for programming
on the next byte write cycle
0 = Latch disabled. PROM data and address buses are unlatched
for normal CPU operations.
PGM — Program Bit
If LAT is cleared, PGM cannot be set.
1 = Enables VPP power to the PROM for programming
0 = VPP is disabled.
Bits 1 and 3−7 — Not used; always read 0
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EPROM/OTPROM (PROM)
9.3.2 Preprogramming Steps
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Before programming the PROM using an MC68HC05PGMR PCB in
standalone mode, the user should ensure that:
NOTE:
•
A jumper is installed on pins 1 and 2 of mode select header J1.
•
An EPROM is programmed with the necessary user code.
•
The erasure window (if any) of the device to be programmed is
covered.
•
VDD of +5 Vdc is available on the board.
•
VPP is available on the board.
If the VPP level at the MCU exceeds +16 Vdc, then the MC68HC705C8A
MCU device will suffer permanent damage.
Once those conditions are met, the user should take these steps before
beginning programming:
1. Remove the VPP power source.
2. Set switch 1 in the OFF position (removes VDD).
3. Place the programmed EPROM in socket U1.
4. Insert the erased PROM MCU device to be programmed in the
proper socket:
– MC68HC705C8S or MC68HC705C8P in socket U2 (40-pin
dual in-line package (DIP)) or
– MC68HC705C8FN in socket U3 (44-pin plastic leaded chip
carrier (PLCC)) with the device notch at the upper right corner
of the socket.
5. Set switch S2 in the RESET position.
NOTE:
No PROM MCU should be inserted in or removed from its board socket
(U2 or U3) while VPP (P1, slot 5) or VDD (switch 1) is active on the board.
Technical Data
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EPROM/OTPROM (PROM)
PROM Programming Routines
9.4 PROM Programming Routines
This subsection describes the routines necessary to program, verify, and
secure the PROM device, and other routines available to the user.
9.4.1 Program and Verify PROM
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The program and verify PROM routine copies the contents of the
external EPROM into the MCU PROM with direct correspondence
between the addresses. Memory addresses in the MCU that are not
implemented in PROM are skipped. Unprogrammed addresses in the
EPROM being copied should contain $00 bytes to speed up the
programming process.
To run the program and verify the PROM routine on the PROM MCU,
take these steps:
1. Set switch 1 in the ON position (restores VDD).
2. Restore the VPP power source.
3. Set switches S3, S4, S5, and S6 in the OFF position (selects
proper routine).
4. Set switch 2 in the OUT position (routine is activated).
The red light-emitting diode (LED) is illuminated, showing that the
programming part of the routine is running. The LED goes out
when programming is finished. The verification part of the routine
now begins. When the green LED is illuminated, verification is
successfully completed and the routine is finished.
5. Set switch 2 in the RESET position.
At this point, if no other MCU is to be programmed or secured, remove
VPP power from the board. If another routine is to be performed on the
MCU being programmed, the user can then set switches S3, S4, S5, and
S6 to the positions necessary to select the next routine, and begin the
routine by setting switch 2 to the OUT position. If no other routine is to
be performed, remove VDD from the board and remove the MCU from
the programming socket.
MC68HC705C8A — Rev. 3
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EPROM/OTPROM (PROM)
9.4.2 Verify PROM Contents
The verify PROM contents routine is normally run automatically after the
PROM is programmed. Direct entry to this routine causes the PROM
contents of the MCU to be compared to the contents of the external
memory locations of the EPROM at the same addresses.
To invoke the verify PROM contents routine of the MCU, take these
steps:
Freescale Semiconductor, Inc...
1. Set switch 1 in the ON position (restores VDD).
2. Connect VPP to VDD.
3. Set switches S3, S4, and S6 in the OFF position.
4. Set S5 in the ON position.
5. Set switch 2 in the OUT position (routine is activated).
The red LED is not illuminated during this routine, since no
programming takes place. If verification fails, the routine halts with
the failing address in the external memory bus. When the green
LED is illuminated, verification is completed successfully and the
routine is finished.
6. Set switch 2 in the RESET position.
At this point, if another routine is to be performed on the MCU being
programmed, the user can set switches S3, S4, S5, and S6 to the
positions necessary to select the next routine and move switch S2 to the
OUT position to start the routine. If no other routine is to be performed,
remove VDD from the board and remove the MCU from the programming
socket.
9.4.3 Secure PROM
The secure PROM routines are used after the PROM is successfully
programmed and verified. Only the SEC bit of the option register
($1FDF) is programmed, but VPP is necessary. Once this bit is
programmed, PROM is secure and can be neither verified nor dumped.
Technical Data
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EPROM/OTPROM (PROM)
PROM Programming Routines
9.4.4 Secure PROM and Verify
This routine is used after the PROM is programmed successfully to
verify the contents of the MCU PROM against the contents of the
EPROM and then to secure the PROM. To accomplish this routine, take
these steps:
1. Set switch 1 in the ON position (restores VDD).
Freescale Semiconductor, Inc...
2. Restore VPP power to the programming board.
3. Set switches S4 and S6 in the OFF position.
4. Set switches S3 and S5 in the ON position.
5. Set switch 2 in the OUT position (routine is activated).
Execution time for this routine is about one second.
6. Set switch 2 in the RESET position when the routine is completed.
No LED is illuminated during this routine. Further, the end of the routine
does not mean that the SEC bit was verified. To ensure that security is
properly enabled, attempt to perform another verify routine. If the green
LED does not light, the PROM has been secured properly.
9.4.5 Secure PROM and Dump
This routine is used after the PROM is successfully programmed to
dump the contents of the MCU PROM through the SCI (binary upload)
and then to secure the PROM. To accomplish this routine, take these
steps:
1. Set switch 1 in the ON position (restores VDD).
2. Restore VPP power to the programming board.
3. Set switch S6 in the OFF position.
4. Set switches S3, S4, and S5 in the ON position.
5. Set switch 2 in the OUT position (routine is activated).
Execution time for this routine is about one second.
6. Set switch 2 in the RESET position when the routine is completed.
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EPROM/OTPROM (PROM)
No LED is illuminated during this routine. Further, the end of the routine
does not mean that the SEC bit was verified. To ensure that security is
properly enabled, attempt to perform another verify routine. If the green
LED does not light, the PROM has been secured properly.
9.4.6 Load Program into RAM and Execute
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In the load program in RAM and execute routine, user programs are
loaded via the SCI port and then executed. Data is loaded sequentially
starting at address $0050. After the last byte is loaded, control is
transferred to the RAM program starting at $0051. The first byte loaded
is the count of the total number of bytes in the program plus the count
byte. The program starts at location $0051 in RAM. During initialization,
the SCI is configured for eight data bits and one stop bit. The baud rate
is 4800 with a 2-MHz crystal or 9600 with a 4-MHz crystal.
To load a program into RAM and execute it, take these steps:
1. Set switch 1 in the ON position (restores VDD).
2. Connect VPP to VDD.
3. Set switches S3, S5, and S6 in the OFF position.
4. Set switch S4 in the ON position.
5. Set switch 2 in the OUT position (routine is activated).
The downloaded program starts executing as soon as the last byte is
received by the SCI.
Execution of the routine can be held off by setting the byte count in the
count byte (the first byte loaded) to a value greater than the number of
bytes to be loaded. After loading the last byte, the firmware waits for
more data. Program execution does not begin. At this point, placing
switch 2 in the RESET position resets the MCU with the RAM data intact.
Any other routine can be entered, including the one to execute the
program in RAM, simply by setting switches S3–S6 as necessary to
select the desired routine, then setting switch 2 in the OUT position.
Technical Data
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EPROM/OTPROM (PROM)
PROM Programming Routines
9.4.7 Execute Program in RAM
This routine allows the MCU to transfer control to a program previously
loaded in RAM. This program is executed once bootstrap mode is
entered, if switch S6 is in the ON position and switch 2 is in the OUT
position, without any firmware initialization. The program must start at
location $0051 to be compatible with the load program in RAM routine.
To run the execute program in RAM routine, take these steps:
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1. Set switch 1 in the ON position (restores VDD).
2. Connect VPP to VDD.
3. Set switch S6 in the OFF position.
4. Switches S3, S4, and S5 can be in either position.
5. Set switch 2 in the OUT position (routine is activated).
NOTE:
The non-programmable watchdog COP is disabled in bootloader mode,
even if the NCOPE bit is programmed.
9.4.8 Dump PROM Contents
In the dump PROM contents routine, the PROM contents are dumped
sequentially to the SCI output, provided the PROM has not been
secured. The first location sent is $0020 and the last location sent is
$1FFF. Unused locations are skipped so that no gaps exist in the data
stream. The external memory address lines indicate the current location
being sent. Data is sent with eight data bits and one stop bit at 4800 baud
with a 2-MHz crystal or 9600 baud with a 4-MHz crystal.
To run the dump PROM contents routine, take these steps:
1. Set switch 1 in the ON position (restores VDD).
2. Connect VPP to VDD.
3. Set switches S3 and S6 in the OFF position.
4. Set switches S4 and S5 in the ON position.
5. Set switch 2 in the OUT position (routine is activated).
6. Once PROM dumping is complete, set switch 2 in the RESET
position.
MC68HC705C8A — Rev. 3
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EPROM/OTPROM (PROM)
9.5 Control Registers
This subsection describes the three registers that control memory
configuration, PROM security, and IRQ edge or level sensitivity; port B
pullups; and non-programmable COP enable/disable.
9.5.1 Option Register
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The option register shown in Figure 9-4 is used to select the IRQ
sensitivity, enable the PROM security, and select the memory
configuration.
Address:
$1FDF
Bit 7
6
5
4
3
RAM0
RAM1
0
0
SEC*
0
0
0
0
*
Read:
2
1
Bit 0
IRQ
0
1
0
Write:
Reset:
U
*Implemented as an EPROM cell
= Unimplemented
U = Unaffected
Figure 9-4. Option Register (Option)
RAM0 — Random-Access Memory Control Bit 0
1 = Maps 32 bytes of RAM into page zero starting at address
$0030. Addresses from $0020 to $002F are reserved. This bit
can be read or written at any time, allowing memory
configuration to be changed during program execution.
0 = Provides 48 bytes of PROM at location $0020–$005F.
RAM1 — Random-Access Memory Control Bit 1
1 = Maps 96 bytes of RAM into page one starting at address $0100.
This bit can be read or written at any time, allowing memory
configuration to be changed during program execution.
0 = Provides 96 bytes of PROM at location $0100.
Technical Data
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EPROM/OTPROM (PROM)
Control Registers
SEC — Security Bit
This bit is implemented as an EPROM cell and is not affected by
reset.
1 = Security enabled
0 = Security off; bootloader able to be enabled
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IRQ — Interrupt Request Pin Sensitivity Bit
IRQ is set only by reset, but can be cleared by software. This bit can
only be written once.
1 = IRQ pin is both negative edge- and level-sensitive.
0 = IRQ pin is negative edge-sensitive only.
Bits 5, 4, and 0 — Not used; always read 0
Bit 2 — Unaffected by reset; reads either 1 or 0
9.5.2 Mask Option Register 1
Mask option register 1 (MOR1) shown in Figure 9-5 is an EPROM
register that enables the port B pullup devices. Data from MOR1 is
latched on the rising edge of the voltage on the RESET pin.
See 4.3.3 Port B Interrupts.
Address:
$1FF0
Bit 7
6
5
4
3
2
1
Bit 0
PBPU7
PBPU6
PBPU5
PBPU4
PBPU3
PBPU2
PBPU1
PBPU0/
COPC
0
0
0
Read:
Write:
Reset:
Erased:
Unaffected by reset
0
0
0
0
0
Figure 9-5. Mask Option Register 1 (MOR1)
PBPU7–PBPU0/COPC — Port B Pullup Enable Bits 7–0
These EPROM bits enable the port B pullup devices.
1 = Port B pullups enabled
0 = Port B pullups disabled
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EPROM/OTPROM (PROM)
NOTE:
PBPU0/COPC programmed to a 1 enables the port B pullup bit. This bit
is also used to clear the non-programmable COP (MC68HC05C4A
type). Writing to this bit to clear the COP will not affect the state of the
port B pull-up (bit 0). See 5.3.3 Programmable and
Non-Programmable COP Watchdog Resets.
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When using the MC68HC705C8A in an MC68HC705C8 or
MC68HSC705C8 application, program locations $1FF0 and $1FF1 to
$00.
9.5.3 Mask Option Register 2
Mask option register 2 (MOR2) shown in Figure 9-6 is an EPROM
register that enables the non-programmable COP watchdog. Data from
MOR2 is latched on the rising edge of the voltage on the RESET pin.
See 5.3.3 Programmable and Non-Programmable COP Watchdog
Resets.
Address:
$1FF1
Bit 7
6
5
4
3
2
1
Bit 0
Read:
NCOPE
Write:
Reset:
Erased:
Unaffected by reset
0
0
0
0
0
0
0
0
= Unimplemented
Figure 9-6. Mask Option Register 2 (MOR2)
NCOPE — Non-Programmable COP Watchdog Enable Bit
This EPROM bit enables the non-programmable COP watchdog.
1 = Non-programmable COP watchdog enabled
0 = Non-programmable COP watchdog disabled
Technical Data
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MC68HC705C8A — Rev. 3
EPROM/OTPROM (PROM)
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EPROM/OTPROM (PROM)
EPROM Erasing
9.6 EPROM Erasing
The erased state of an EPROM or OTPROM byte is $00. EPROM
devices can be erased by exposure to a high intensity ultraviolet (UV)
light with a wave length of 2537 Å. The recommended erasure dosage
(UV intensity on a given surface area x exposure time) is 15 Ws/cm2. UV
lamps should be used without short-wave filters, and the EPROM device
should be positioned about one inch from the UV source.
Freescale Semiconductor, Inc...
OTPROM devices are shipped in an erased state. Once programmed,
they cannot be erased. Electrical erasing procedures cannot be
performed on either EPROM or OTPROM devices.
MC68HC705C8A — Rev. 3
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EPROM/OTPROM (PROM)
Technical Data
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MC68HC705C8A — Rev. 3
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Technical Data — MC68HC705C8A
Section 10. Serial Communications Interface (SCI)
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10.1 Contents
10.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
10.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
10.4
SCI Data Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
10.5 SCI Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
10.5.1 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
10.5.2 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
10.6 SCI I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
10.6.1 SCI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
10.6.2 SCI Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
10.6.3 SCI Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
10.6.4 SCI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
10.6.5 Baud Rate Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
10.2 Introduction
The serial communications interface (SCI) module allows high-speed
asynchronous communication with peripheral devices and other
microcontroller units (MCUs).
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Serial Communications Interface (SCI)
10.3 Features
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Features of the SCI module include:
•
Standard mark/space non-return-to-zero format
•
Full-duplex operation
•
32 programmable baud rates
•
Programmable 8-bit or 9-bit character length
•
Separately enabled transmitter and receiver
•
Two receiver wakeup methods:
– Idle line wakeup
– Address mark wakeup
•
Interrupt-driven operation capability with five interrupt flags:
– Transmitter data register empty
– Transmission complete
– Receiver data register full
– Receiver overrun
– Idle receiver input
•
Receiver framing error detection
•
1/16 bit-time noise detection
10.4 SCI Data Format
The SCI uses the standard non-return-to-zero mark/space data format
illustrated in Figure 10-1.
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Serial Communications Interface (SCI)
SCI Operation
8-BIT DATA FORMAT
(BIT M IN SCCR1 CLEAR)
START
BIT
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
STOP
BIT
BIT 6
BIT 7
BIT 8
NEXT
START
BIT
9-BIT DATA FORMAT
(BIT M IN SCCR1 SET)
START
BIT
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
STOP
BIT
NEXT
START
BIT
Freescale Semiconductor, Inc...
Figure 10-1. SCI Data Format
10.5 SCI Operation
The SCI allows full-duplex, asynchronous, RS232 or RS422 serial
communication between the MCU and remote devices, including other
MCUs. The transmitter and receiver of the SCI operate independently,
although they use the same baud-rate generator. This subsection
describes the operation of the SCI transmitter and receiver.
10.5.1 Transmitter
Figure 10-2 shows the structure of the SCI transmitter. Figure 10-3 is a
summary of the SCI transmitter input/output (I/O) registers.
•
Character Length — The transmitter can accommodate either
8-bit or 9-bit data. The state of the M bit in SCI control register 1
(SCCR1) determines character length. When transmitting 9-bit
data, bit T8 in SCCR1 is the ninth bit (bit 8).
•
Character Transmission — During transmission, the transmit shift
register shifts a character out to the PD1/TDO pin. The SCI data
register (SCDR) is the write-only buffer between the internal data
bus and the transmit shift register.
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Serial Communications Interface (SCI)
SCDR ($0011)
1X
BAUD RATE
CLOCK
TRANSMIT SHIFT REGISTER
PIN BUFFER
AND CONTROL
SCSR ($0010)
INTERNAL DATA BUS
TDRE
TC
RDRF
IDLE
OR
NF
FE
M
WAKE
R8
T8
TRANSMITTER
CONTROL LOGIC
SCCR1 ($000E)
PD1/
TDO
BREAK (ALL LOGIC 0s)
PREAMBLE (ALL LOGIC 1s)
SHIFT ENABLE
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LOAD FROM SCDR
H 8 7 6 5 4 3 2 1 0 L
TDRE
TIE
TC
TCIE
TIE
TCIE
RIE
ILIE
TE
RE
RWU
SBK
SCI RECEIVE
REQUESTS
SCCR2 ($000F)
SCI INTERRUPT
REQUEST
Figure 10-2. SCI Transmitter
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Serial Communications Interface (SCI)
SCI Operation
Addr.
$000D
Freescale Semiconductor, Inc...
$000E
$000F
$0010
$0011
Register Name
Bit 7
Read:
Baud Rate Register
(Baud) Write:
See page 136.
Reset:
Read:
SCI Control Register 1
(SCCR1) Write:
See page 130.
Reset:
Read:
SCI Control Register 2
(SCCR2) Write:
See page 131.
Reset:
5
4
3
SCP1
SCP0
0
0
U
2
1
Bit 0
SCR2
SCR1
SCR0
U
U
U
U
U
R8
T8
M
WAKE
U
U
U
U
TIE
TCIE
RIE
ILIE
TE
RE
RWU
SBK
0
0
0
0
0
0
0
0
TC
RDRF
IDLE
OR
NF
FE
1
0
0
0
0
0
U
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Read: TDRE
SCI Status Register
(SCSR) Write:
See page 133.
Reset:
1
Read:
SCI Data Register
(SCDR) Write:
See page 129.
Reset:
6
Bit 7
Unaffected by reset
= Unimplemented
U = Unaffected
Figure 10-3. SCI Transmitter I/O Register Summary
Writing a logic 1 to the TE bit in SCI control register 2 (SCCR2) and
then writing data to the SCDR begins the transmission. At the start
of a transmission, transmitter control logic automatically loads the
transmit shift register with a preamble of logic 1s. After the
preamble shifts out, the control logic transfers the SCDR data into
the shift register. A logic 0 start bit automatically goes into the least
significant bit (LSB) position of the shift register, and a logic 1 stop
bit goes into the most significant bit (MSB) position.
When the data in the SCDR transfers to the transmit shift register,
the transmit data register empty (TDRE) flag in the SCI status
register (SCSR) becomes set. The TDRE flag indicates that the
SCDR can accept new data from the internal data bus.
When the shift register is not transmitting a character, the
PD1/TDO pin goes to the idle condition, logic 1. If software clears
the TE bit during the idle condition, and while TDRE is set, the
transmitter relinquishes control of the PD1/TDO pin.
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Serial Communications Interface (SCI)
•
Break Characters — Writing a logic 1 to the SBK bit in SCCR2
loads the shift register with a break character. A break character
contains all logic 0s and has no start and stop bits. Break
character length depends on the M bit in SCCR1. As long as SBK
is at logic 1, transmitter logic continuously loads break characters
into the shift register. After software clears the SBK bit, the shift
register finishes transmitting the last break character and then
transmits at least one logic 1. The automatic logic 1 at the end of
a break character is to guarantee the recognition of the start bit of
the next character.
•
Idle Characters — An idle character contains all logic 1s and has
no start or stop bits. Idle character length depends on the M bit in
SCCR1. The preamble is a synchronizing idle character that
begins every transmission.
Clearing the TE bit during a transmission relinquishes the
PD1/TDO pin after the last character to be transmitted is shifted
out. The last character may already be in the shift register, or
waiting in the SCDR, or it may be a break character generated by
writing to the SBK bit. Toggling TE from logic 0 to logic 1 while the
last character is in transmission generates an idle character (a
preamble) that allows the receiver to maintain control of the
PD1/TDO pin.
•
Transmitter Interrupts — These sources can generate SCI
transmitter interrupt requests:
– Transmit Data Register Empty (TDRE) — The TDRE bit in the
SCSR indicates that the SCDR has transferred a character to
the transmit shift register. TDRE is a source of SCI interrupt
requests. The transmission complete interrupt enable bit
(TCIE) in SCCR2 is the local mask for TDRE interrupts.
– Transmission Complete (TC) — The TC bit in the SCSR
indicates that both the transmit shift register and the SCDR are
empty and that no break or idle character has been generated.
TC is a source of SCI interrupt requests. The transmission
complete interrupt enable bit (TCIE) in SCCR2 is the local
mask for TC interrupts.
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Serial Communications Interface (SCI)
SCI Operation
10.5.2 Receiver
16X
BAUD RATE
CLOCK
PIN BUFFER
AND CONTROL
STOP
DATA
RECOVERY
RECEIVE SHIFT REGISTER
8 7 6 5 4 3 2 1 0
DISABLE
DRIVER
IDLE MSB RDRF OR
RE
M
SCCR1 ($000E)
IDLE
OR
NF
FE
TDRE
TC
RDRF
M
WAKE
T8
WAKEUP
LOGIC
R8
INTERNAL DATA BUS
SCSR ($0010)
SCDR ($0011)
RDRF
IDLE
SCI TRANSMIT
REQUESTS
ILIE
OR
TCIE
RIE
ILIE
TE
RE
RWU
SBK
RIE
INTERNAL DATA BUS
RIE
TIE
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PD0/
RDI
÷16
START
Figure 10-4 shows the structure of the SCI receiver. Refer to
Figure 10-3 for a summary of the SCI receiver I/O registers.
SCCR2 ($000F)
SCI INTERRUPT
REQUEST
Figure 10-4. SCI Receiver
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Serial Communications Interface (SCI)
•
Character Length — The receiver can accommodate either 8-bit
or 9-bit data. The state of the M bit in SCI control register 1
(SCCR1) determines character length. When receiving 9-bit data,
bit R8 in SCCR1 is the ninth bit (bit 8).
•
Character Reception — During reception, the receive shift register
shifts characters in from the PD0/RDI pin. The SCI data register
(SCDR) is the read-only buffer between the internal data bus and
the receive shift register.
Freescale Semiconductor, Inc...
After a complete character shifts into the receive shift register, the
data portion of the character is transferred to the SCDR, setting
the receive data register full (RDRF) flag. The RDRF flag can be
used to generate an interrupt.
•
Receiver Wakeup — So that the MCU can ignore transmissions
intended only for other receivers in multiple-receiver systems, the
MCU can be put into a standby state. Setting the receiver wakeup
enable (RWU) bit in SCI control register 2 (SCCR2) puts the MCU
into a standby state during which receiver interrupts are disabled.
Either of two conditions on the PD0/RDI pin can bring the MCU out
of the standby state:
– Idle input line condition — If the PD0/RDI pin is at logic 1 long
enough for 10 or 11 logic 1s to shift into the receive shift
register, receiver interrupts are again enabled.
– Address mark — If a logic 1 occurs in the most significant bit
position of a received character, receiver interrupts are again
enabled.
The state of the WAKE bit in SCCR1 determines which of the two
conditions wakes up the MCU.
•
Receiver Noise Immunity — The data recovery logic samples
each bit 16 times to identify and verify the start bit and to detect
noise. Any conflict between noise detection samples sets the
noise flag (NF) in the SCSR. The NF bit is set at the same time
that the RDRF bit is set.
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Serial Communications Interface (SCI)
SCI I/O Registers
•
Framing Errors — If the data recovery logic does not detect a logic
1 where the stop bit should be in an incoming character, it sets the
framing error (FE) bit in the SCSR. The FE bit is set at the same
time that the RDRF bit is set.
•
Receiver Interrupts — These sources can generate SCI receiver
interrupt requests:
Freescale Semiconductor, Inc...
– Receive Data Register Full (RDRF) — The RDRF bit in the
SCSR indicates that the receive shift register has transferred a
character to the SCDR.
– Receiver Overrun (OR) — The OR bit in the SCSR indicates
that the receive shift register shifted in a new character before
the previous character was read from the SCDR.
– Idle Input (IDLE) — The IDLE bit in the SCSR indicates that 10
or 11 consecutive logic 1s shifted in from the PD0/RDI pin.
10.6 SCI I/O Registers
These I/O registers control and monitor SCI operation:
•
SCI data register (SCDR)
•
SCI control register 1 (SCCR1)
•
SCI control register 2 (SCCR2)
•
SCI status register (SCSR)
10.6.1 SCI Data Register
The SCI data register (SCDR) shown in Figure 10-5 is the buffer for
characters received and for characters transmitted.
Address:
$0011
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Read:
Write:
Reset:
Unaffected by reset
Figure 10-5. SCI Data Register (SCDR)
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10.6.2 SCI Control Register 1
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SCI control register 1 (SCCR1) shown in Figure 10-6 has these
functions:
•
Stores ninth SCI data bit received and ninth SCI data bit
transmitted
•
Controls SCI character length
•
Controls SCI wakeup method
Address:
$000E
Bit 7
6
R8
U
5
4
3
T8
M
WAKE
U
U
U
2
1
Bit 0
Read:
Write:
Reset:
= Unimplemented
U = Unaffected
Figure 10-6. SCI Control Register 1 (SCCR1)
R8 — Bit 8 (Received)
When the SCI is receiving 9-bit characters, R8 is the ninth bit of the
received character. R8 receives the ninth bit at the same time that the
SCDR receives the other eight bits. Reset has no effect on the R8 bit.
T8 — Bit 8 (Transmitted)
When the SCI is transmitting 9-bit characters, T8 is the ninth bit of the
transmitted character. T8 is loaded into the transmit shift register at
the same time that SCDR is loaded into the transmit shift register.
Reset has no effect on the T8 bit.
M — Character Length Bit
This read/write bit determines whether SCI characters are eight or
nine bits long. The ninth bit can be used as an extra stop bit, as a
receiver wakeup signal, or as a mark or space parity bit. Reset has no
effect on the M bit.
1 = 9-bit SCI characters
0 = 8-bit SCI characters
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Serial Communications Interface (SCI)
SCI I/O Registers
WAKE — Wakeup Bit
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This read/write bit determines which condition wakes up the SCI: a
logic 1 (address mark) in the most significant bit position of a received
character or an idle condition of the PD0/RDI pin. Reset has no effect
on the WAKE bit.
1 = Address mark wakeup
0 = Idle line wakeup
10.6.3 SCI Control Register 2
SCI control register 2 (SCCR2) shown in Figure 10-7 has these
functions:
•
Enables the SCI receiver and SCI receiver interrupts
•
Enables the SCI transmitter and SCI transmitter interrupts
•
Enables SCI receiver idle interrupts
•
Enables SCI transmission complete interrupts
•
Enables SCI wakeup
•
Transmits SCI break characters
Address:
$000F
Bit 7
6
5
4
3
2
1
Bit 0
TIE
TCIE
RIE
ILIE
TE
RE
RWU
SBK
0
0
0
0
0
0
0
0
Read:
Write:
Reset:
Figure 10-7. SCI Control Register 2 (SCCR2)
TIE — Transmit Interrupt Enable Bit
This read/write bit enables SCI interrupt requests when the TDRE bit
becomes set. Reset clears the TIE bit.
1 = TDRE interrupt requests enabled
0 = TDRE interrupt requests disabled
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TCIE — Transmission Complete Interrupt Enable Bit
This read/write bit enables SCI interrupt requests when the TC bit
becomes set. Reset clears the TCIE bit.
1 = TC interrupt requests enabled
0 = TC interrupt requests disabled
RIE — Receive Interrupt Enable Bit
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This read/write bit enables SCI interrupt requests when the RDRF bit
or the OR bit becomes set. Reset clears the RIE bit.
1 = RDRF interrupt requests enabled
0 = RDRF interrupt requests disabled
ILIE — Idle Line Interrupt Enable Bit
This read/write bit enables SCI interrupt requests when the IDLE bit
becomes set. Reset clears the ILIE bit.
1 = IDLE interrupt requests enabled
0 = IDLE interrupt requests disabled
TE — Transmit Enable Bit
Setting this read/write bit begins the transmission by sending a
preamble of 10 or 11 logic 1s from the transmit shift register to the
PD1/TDO pin. Reset clears the TE bit.
1 = Transmission enabled
0 = Transmission disabled
RE — Receive Enable Bit
Setting this read/write bit enables the receiver. Clearing the RE bit
disables the receiver and receiver interrupts but does not affect the
receiver interrupt flags. Reset clears the RE bit.
1 = Receiver enabled
0 = Receiver disabled
RWU — Receiver Wakeup Enable Bit
This read/write bit puts the receiver in a standby state. Typically, data
transmitted to the receiver clears the RWU bit and returns the receiver
to normal operation. The WAKE bit in SCCR1 determines whether an
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SCI I/O Registers
idle input or an address mark brings the receiver out of the standby
state. Reset clears the RWU bit.
1 = Standby state
0 = Normal operation
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SBK — Send Break Bit
Setting this read/write bit continuously transmits break codes in the
form of 10-bit or 11-bit groups of logic 0s. Clearing the SBK bit stops
the break codes and transmits a logic 1 as a start bit. Reset clears the
SBK bit.
1 = Break codes being transmitted
0 = No break codes being transmitted
10.6.4 SCI Status Register
The SCI status register (SCSR) shown in Figure 10-8 contains flags to
signal these conditions:
•
Transfer of SCDR data to transmit shift register complete
•
Transmission complete
•
Transfer of receive shift register data to SCDR complete
•
Receiver input idle
•
Receiver overrun
•
Noisy data
•
Framing error
Address:
Read:
$0010
Bit 7
6
5
4
3
2
1
TDRE
TC
RDRF
IDLE
OR
NF
FE
1
1
0
0
0
0
0
Bit 0
Write:
Reset:
= Unimplemented
U
U = Unaffected
Figure 10-8. SCI Status Register (SCSR)
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TDRE — Transmit Data Register Empty Bit
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This clearable, read-only bit is set when the data in the SCDR
transfers to the transmit shift register. TDRE generates an interrupt
request if the TIE bit in SCCR2 is also set. Clear the TDRE bit by
reading the SCSR with TDRE set and then writing to the SCDR. Reset
sets the TDRE bit. Software must initialize the TDRE bit to logic 0 to
avoid an instant interrupt request when turning on the transmitter.
1 = SCDR data transferred to transmit shift register
0 = SCDR data not transferred to transmit shift register
TC — Transmission Complete Bit
This clearable, read-only bit is set when the TDRE bit is set and no
data, preamble, or break character is being transmitted. TC generates
an interrupt request if the TCIE bit in SCCR2 is also set. Clear the TC
bit by reading the SCSR with TC set and then writing to the SCDR.
Reset sets the TC bit. Software must initialize the TC bit to logic 0 to
avoid an instant interrupt request when turning on the transmitter.
1 = No transmission in progress
0 = Transmission in progress
RDRF — Receive Data Register Full Bit
This clearable, read-only bit is set when the data in the receive shift
register transfers to the SCI data register. RDRF generates an
interrupt request if the RIE bit in SCCR2 is also set. Clear the RDRF
bit by reading the SCSR with RDRF set and then reading the SCDR.
Reset clears the RDRF bit.
1 = Received data available in SCDR
0 = Received data not available in SCDR
IDLE — Receiver Idle Bit
This clearable, read-only bit is set when 10 or 11 consecutive logic 1s
appear on the receiver input. IDLE generates an interrupt request if
the ILIE bit in SCCR2 is also set. Clear the IDLE bit by reading the
SCSR with IDLE set, and then reading the SCDR. Reset clears the
IDLE bit.
1 = Receiver input idle
0 = Receiver input not idle
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Serial Communications Interface (SCI)
SCI I/O Registers
OR — Receiver Overrun Bit
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This clearable, read-only bit is set if the SCDR is not read before the
receive shift register receives the next word. OR generates an
interrupt request if the RIE bit in SCCR2 is also set. The data in the
shift register is lost, but the data already in the SCDR is not affected.
Clear the OR bit by reading the SCSR with OR set and then reading
the SCDR. Reset clears the OR bit.
1 = Receiver shift register full and RDRF = 1
0 = No receiver overrun
NF — Receiver Noise Flag Bit
This clearable, read-only bit is set when noise is detected in data
received in the SCI data register. Clear the NF bit by reading the
SCSR and then reading the SCDR. Reset clears the NF bit.
1 = Noise detected in SCDR
0 = No noise detected in SCDR
FE — Receiver Framing Error Bit
This clearable, read-only flag is set when a logic 0 is located where a
stop bit should be in the character shifted into the receive shift
register. If the received word causes both a framing error and an
overrun error, the OR bit is set and the FE bit is not set. Clear the FE
bit by reading the SCSR and then reading the SCDR. Reset clears the
FE bit.
1 = Framing error
0 = No framing error
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10.6.5 Baud Rate Register
The baud rate register shown in Figure 10-9 selects the baud rate for
both the receiver and the transmitter.
Address:
$000D
Bit 7
6
5
4
SCP1
SCP0
0
0
3
2
1
Bit 0
SCR2
SCR1
SCR0
U
U
U
Read:
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Write:
Reset:
U
U
= Unimplemented
U
U = Unaffected
Figure 10-9. Baud Rate Register (Baud)
SCP1 and SCP0 — SCI Prescaler Select Bits
These read/write bits control prescaling of the baud rate generator
clock, as shown in Table 10-1. Resets clear both SCP1 and SCP0.
Table 10-1. Baud Rate Generator Clock Prescaling
SCP[1:0]
Baud Rate Generator Clock
00
Internal clock
÷1
01
Internal clock
÷3
10
Internal clock
÷4
11
Internal clock
÷ 13
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Serial Communications Interface (SCI)
SCI I/O Registers
SCR2–SCR0 — SCI Baud Rate Select Bits
These read/write bits select the SCI baud rate, as shown in
Table 10-2. Reset has no effect on the SCR2–SCR0 bits.
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Table 10-2. Baud Rate Selection
SCR[2:1:0]
SCI Baud Rate (Baud)
000
Prescaled clock ÷ 1
001
Prescaled clock ÷ 2
010
Prescaled clock ÷ 4
011
Prescaled clock ÷ 8
100
Prescaled clock ÷ 16
101
Prescaled clock ÷ 32
110
Prescaled clock ÷ 64
111
Prescaled clock
÷ 128
Table 10-3 shows all possible SCI baud rates derived from crystal
frequencies of 2 MHz, 4 MHz, and 4.194304 MHz.
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Table 10-3. Baud Rate Selection Examples
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SCI Baud Rate
SCP[1:0]
SCR[2:1:0]
00
fOSC = 2 MHz
fOSC = 4 MHz
fOSC = 4.194304 MHz
000
62.50 Kbaud
125 Kbaud
131.1 Kbaud
00
001
31.25 Kbaud
62.50 Kbaud
65.54 Kbaud
00
010
15.63 Kbaud
31.25 Kbaud
32.77 Kbaud
00
011
7813 baud
15.63 Kbaud
16.38 Kbaud
00
100
3906 baud
7813 baud
8192 baud
00
101
1953 baud
3906 baud
4096 baud
00
110
976.6 baud
1953 baud
2048 baud
00
111
488.3 baud
976.6 baud
1024 baud
01
000
20.83 Kbaud
41.67 Kbaud
43.69 Kbaud
01
001
10.42 Kbaud
20.83 Kbaud
21.85 Kbaud
01
010
5208 baud
10.42 Kbaud
10.92 Kbaud
01
011
2604 baud
5208 baud
5461 baud
01
100
1302 baud
2604 baud
2731 baud
01
101
651.0 baud
1302 baud
1365 baud
01
110
325.5 baud
651.0 baud
682.7 baud
01
111
162.8 baud
325.5 baud
341.3 baud
10
000
15.63 Kbaud
31.25 Kbaud
32.77 Kbaud
10
001
7813 baud
15.63 Kbaud
16.38 Kbaud
10
010
3906 baud
7813 baud
8192 baud
10
011
1953 baud
3906 baud
4906 baud
10
100
976.6 baud
1953 baud
2048 baud
10
101
488.3 baud
976.6 baud
1024 baud
10
110
244.1 baud
488.3 baud
512.0 baud
10
111
122.1 baud
244.1 baud
256.0 baud
11
000
4808 baud
9615 baud
10.08 Kbaud
11
001
2404 baud
4808 baud
5041 baud
11
010
1202 baud
2404 baud
2521 baud
11
011
601.0 baud
1202 baud
1260 baud
11
100
300.5 baud
601.0 baud
630.2 baud
11
101
150.2 baud
300.5 baud
315.1 baud
11
110
75.12 baud
150.2 baud
157.5 baud
11
111
37.56 baud
75.12 baud
78.77 baud
Technical Data
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Technical Data — MC68HC705C8A
Section 11. Serial Peripheral Interface (SPI)
Freescale Semiconductor, Inc...
11.1 Contents
11.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
11.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
11.4 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
11.4.1 Pin Functions in Master Mode . . . . . . . . . . . . . . . . . . . . . . 143
11.4.2 Pin Functions in Slave Mode . . . . . . . . . . . . . . . . . . . . . . .144
11.5
Multiple-SPI Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
11.6
Serial Clock Polarity and Phase . . . . . . . . . . . . . . . . . . . . . . .146
11.7 SPI Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
11.7.1 Mode Fault Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147
11.7.2 Write Collision Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
11.7.3 Overrun Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
11.8
SPI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148
11.9 SPI I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
11.9.1 SPI Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
11.9.2 SPI Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
11.9.3 SPI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
11.2 Introduction
The serial peripheral interface (SPI) module allows full-duplex,
synchronous, serial communication with peripheral devices.
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Serial Peripheral Interface (SPI)
11.3 Features
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Features of the SPI include:
•
Full-duplex operation
•
Master and slave modes
•
Four programmable master mode frequencies (1.05 MHz
maximum)
•
2.1-MHz maximum slave mode frequency
•
Serial clock with programmable polarity and phase
•
End of transmission interrupt flag
•
Write collision error flag
•
Bus contention error flag
Figure 11-1 shows the structure of the SPI module. Figure 11-2 is a
summary of the SPI input/output (I/O) registers.
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Serial Peripheral Interface (SPI)
Features
INTERNAL
CLOCK
(XTAL ÷2)
S
M
M
7 6 5 4 3 2 1 0
S
PIN CONTROL LOGIC
SPI SHIFT REGISTER
DIVIDER
÷2
÷4
÷6
÷32
SHIFT
CLOCK
SPDR ($000C)
SPI CLOCK (MASTER)
PD4/
SCK
PD5/
SS
SPR0
SPR1
CPOL
CPHA
MSTR
SPIE
DWOM
MSTR
SPE
DWOM
SPE
SPR1
SPR0
S
MSTR
SPE
SPIE
MODF
SPIF
PD3/
MOSI
M
CLOCK
LOGIC
SPI CONTROL
WCOL
Freescale Semiconductor, Inc...
SELECT
PD2/
MISO
SPCR ($000A)
SPSR ($000B)
SPI INTERRUPT
REQUEST
INTERNAL
DATA BUS
Figure 11-1. SPI Block Diagram
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Serial Peripheral Interface (SPI)
Addr.
$000A
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$000B
$000C
Register Name
Read:
SPI Control Register
(SPCR) Write:
See page 149.
Reset:
Read:
SPI Status Register
(SPSR) Write:
See page 151.
Reset:
Read:
SPI Data Register
(SPDR) Write:
See page 149.
Reset:
Bit 7
6
SPIE
5
4
3
2
1
Bit 0
SPE
MSTR
CPOL
CPHA
SPR1
SPR0
0
0
0
U
U
U
U
SPIF
WCOL
MODF
0
0
0
Bit 7
Bit 6
Bit 3
BIt 2
Bit 1
Bit 0
Bit 5
Bit 4
Unaffected by reset
= Unimplemented
U = Unaffected
Figure 11-2. SPI I/O Register Summary
11.4 Operation
The master/slave SPI allows full-duplex, synchronous, serial
communication between the microcontroller unit (MCU) and peripheral
devices, including other MCUs. As the 8-bit shift register of a master SPI
transmits each byte to another device, a byte from the receiving device
enters the master SPI shift register. A clock signal from the master SPI
synchronizes data transmission.
Only a master SPI can initiate transmissions. Software begins the
transmission from a master SPI by writing to the SPI data register
(SPDR). The SPDR does not buffer data being transmitted from the SPI.
Data written to the SPDR goes directly into the shift register and begins
the transmission immediately under the control of the serial clock. The
transmission ends after eight cycles of the serial clock when the SPI flag
(SPIF) becomes set. At the same time that SPIF becomes set, the data
shifted into the master SPI from the receiving device transfers to the
SPDR. The SPDR buffers data being received by the SPI. Before the
master SPI sends the next byte, software must clear the SPIF bit by
reading the SPSR and then accessing the SPDR.
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Serial Peripheral Interface (SPI)
Operation
In a slave SPI, data enters the shift register under the control of the serial
clock from the master SPI. After a byte enters the shift register of a slave
SPI, it transfers to the SPDR. To prevent an overrun condition, slave
software must then read the byte in the SPDR before another byte enters
the shift register and is ready to transfer to the SPDR.
Figure 11-3 shows how a master SPI exchanges data with a slave SPI.
Freescale Semiconductor, Inc...
PD3/MOSI
SPI SHIFT REGISTER
7 6 5 4 3 2 1 0
PD2/MISO
SPI SHIFT REGISTER
7 6 5 4 3 2 1 0
PD5/SS
SPDR ($000C)
SPDR ($000C)
PD4/SCK
MASTER MCU
SLAVE MCU
Figure 11-3. Master/Slave Connections
11.4.1 Pin Functions in Master Mode
Setting the MSTR bit in the SPI control register (SPCR) configures the
SPI for operation in master mode. The master-mode functions of the SPI
pins are:
•
PD4/SCK (serial clock) — In master mode, the PD4/SCK pin is the
synchronizing clock output.
•
PD3/MOSI (master output, slave input) — In master mode, the
PD3/MOSI pin is the serial output.
•
PD2/MISO (master input, slave output) — In master mode, the
PD2/MISO pin is configured as the serial input.
•
PD5/SS (slave select) — In master mode, the PD5/SS pin protects
against driver contention caused by the simultaneous operation of
two SPIs in master mode. A logic 0 on the PD5/SS pin of a master
SPI disables the SPI, clears the MSTR bit, and sets the mode-fault
flag (MODF).
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Serial Peripheral Interface (SPI)
11.4.2 Pin Functions in Slave Mode
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Clearing the MSTR bit in the SPCR configures the SPI for operation in
slave mode. The slave-mode functions of the SPI pins are:
•
PD4/SCK (serial clock) — In slave mode, the PD4/SCK pin is the
input for the synchronizing clock signal from the master SPI.
•
PD3/MOSI (master output, slave input) — In slave mode, the
PD3/MOSI pin is the serial input.
•
PD2/MISO (master input, slave output) — In slave mode, the
PD2/MISO pin is the serial output.
•
PD5/SS (slave select) — In slave mode, the PD5/SS pin enables
the SPI for data and serial clock reception from a master SPI.
When CPHA = 0, the shift clock is the OR of SS with SCK. In this clock
phase mode, SS must go high between successive characters in an SPI
message. When CPHA = 1, SS may be left low for several SPI
characters. In cases with only one SPI slave MCU, the slave MCU SS
line can be tied to VSS as long as CPHA = 1 clock modes are used.
The WCOL flag bit can be improperly set when attempting the first
transmission after a reset if these conditions are present: MSTR = 0,
CPOL = 0, CPHA = 1, SS pin = 0, and SCK pin = 1. The reset states of
the CPOL and CPHA bits are 0 and 1, respectively. Under normal
operating conditions (CPOL = 0, CPHA = 1), the SCK input will be low.
The incorrect setting of the WCOL bit can be prevented in two ways:
1. Send a dummy transmission after reset, clear the WCOL flag, and
then proceed with the real transmission.
2. Use the MSTR bit in the SPCR (SPI control register). This is
accomplished by setting the MSTR bit at the same time the CPOL
and CPHA bits are programmed to the desired logic levels. Then,
the data register can be written to if desired. After this, the MSTR
bit should be set to a logic 0, the SPE (SPI enable bit) should be
set to a logic 1, and the CPOL, CPHA, SPR1, and SPR0 bits set
to the desired logic levels. If this procedure is followed after a reset
and before the first access to the SPDR, the WCOL flag will not be
set.
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Serial Peripheral Interface (SPI)
Multiple-SPI Systems
Example:
LDA #$1C
STA SPCR
LDA #$4C
MSTR = 1, CPOL = 1, CPHA = 1,
SPR1 = SPR0 = 0
SPI control register
MSTR = 0, SPE = 1, CPOL = 1, CPHA = 1,
SPR1 = SPR0 = 0
SPI control register
11.5 Multiple-SPI Systems
In a multiple-SPI system, all PD4/SCK pins are connected together, all
PD3/MOSI pins are connected together, and all PD2/MISO pins are
connected together.
Before a transmission, one SPI is configured as master and the rest are
configured as slaves. Figure 11-4 is a block diagram showing a single
master SPI and three slave SPIs.
MASTER MCU
PD2/MISO
PD3/MOSI
PD4/SCK
PD5/SS
VDD
2
SLAVE MCU 2
SLAVE MCU 1
PD2/MISO
PD3/MOSI
PD5/SS
PD4/SCK
PD2/MISO
PD3/MOSI
PD5/SS
PD4/SCK
PD2/MISO
PD3/MOSI
PD5/SS
I/O
PORT 1
0
PD4/SCK
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STA SPCR
;
;
;
;
;
;
SLAVE MCU 0
Figure 11-4. One Master and Three Slaves Block Diagram
Figure 11-5 is another block diagram with two master/slave SPIs and
three slave SPIs.
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Serial Peripheral Interface (SPI)
MASTER/SLAVE
MCU 1
MASTER/SLAVE
MCU 2
PD2/MISO
PD2/MISO
PD3/MOSI
PD3/MOSI
PD4/SCK
PD4/SCK
PD5/SS
PD5/SS
SLAVE MCU 2
SLAVE MCU 1
I/O
PORT
PD2/MISO
PD3/MOSI
PD4/SCK
PD5/SS
PD2/MISO
PD3/MOSI
3
PD4/SCK
3
PD5/SS
2
PD2/MISO
2
PD3/MOSI
1
PD4/SCK
0
1
PD5/SS
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I/O
PORT
0
SLAVE MCU 0
Figure 11-5. Two Master/Slaves and Three Slaves Block Diagram
11.6 Serial Clock Polarity and Phase
To accommodate the different serial communication requirements of
peripheral devices, software can change the phase and polarity of the
SPI serial clock. The clock polarity bit (CPOL) and the clock phase bit
(CPHA), both in the SPCR, control the timing relationship between the
serial clock and the transmitted data. Figure 11-6 shows how the CPOL
and CPHA bits affect the clock/data timing.
SS
CPHA
CPOL
0
0
SCK (A)
1
0
SCK (B)
0
1
SCK (C)
1
1
SCK (D)
SDO/SDI
MSB
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
LSB
CAPTURE STROBE
Figure 11-6. SPI Clock/Data Timing
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Serial Peripheral Interface (SPI)
SPI Error Conditions
11.7 SPI Error Conditions
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These conditions produce SPI system errors:
•
Bus contention caused by multiple master SPIs (mode fault error)
•
Writing to the SPDR during a transmission (write-collision error)
•
Failing to read the SPDR before the next incoming byte sets the
SPIF bit (overrun error)
11.7.1 Mode Fault Error
A mode fault error results when a logic 0 occurs on the PD5/SS pin of a
master SPI. The MCU takes these actions when a mode fault error
occurs:
•
Puts the SPI in slave mode by clearing the MSTR bit
•
Disables the SPI by clearing the SPE bit
•
Sets the MODF bit
11.7.2 Write Collision Error
Writing to the SPDR during a transmission causes a write collision error
and sets the WCOL bit in the SPSR. Either a master SPI or a slave SPI
can generate a write collision error.
•
Master — A master SPI can cause a write collision error by writing
to the SPDR while the previously written byte is still being shifted
out to the PD3/MOSI pin. The error does not affect the
transmission of the previously written byte, but the byte that
caused the error is lost.
•
Slave — A slave SPI can cause a write collision error in either of
two ways, depending on the state of the CPHA bit:
– CPHA = 0 — A slave SPI can cause a write collision error by
writing to the SPDR while the PD5/SS pin is at logic 0. The
error does not affect the byte in the SPDR, but the byte that
caused the error is lost.
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Serial Peripheral Interface (SPI)
– CPHA = 1 — A slave SPI can cause a write collision error by
writing to the SPDR while receiving a transmission, that is,
between the first active SCK edge and the end of the eighth
SCK cycle. The error does not affect the transmission from the
master SPI, but the byte that caused the error is lost.
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11.7.3 Overrun Error
Failing to read the byte in the SPDR before a subsequent byte enters the
shift register causes an overrun condition. In an overrun condition, all
incoming data is lost until software clears SPIF. The overrun condition
has no flag.
11.8 SPI Interrupts
The SPIF bit in the SPSR indicates a byte has shifted into or out of the
SPDR. The SPIF bit is a source of SPI interrupt requests. The SPI
interrupt enable bit (SPIE) in the SPCR is the local mask for SPIF
interrupts.
The MODF bit in the SPSR indicates a mode error and is a source of SPI
interrupt requests. The MODF bit is set when a logic 0 occurs on the
PD5/SS pin while the MSTR bit is set. The SPI interrupt enable bit (SPIE)
in the SPCR is the local mask for MODF interrupts.
11.9 SPI I/O Registers
These input/output (I/O) registers control and monitor SPI operation:
•
SPI data register (SPDR)
•
SPI control register (SPCR)
•
SPI status register (SPSR)
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Serial Peripheral Interface (SPI)
SPI I/O Registers
11.9.1 SPI Data Register
The SPDR shown in Figure 11-7 is the read buffer for characters
received by the SPI. Writing a byte to the SPDR places the byte directly
into the SPI shift register.
Address:
$000C
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
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Read:
Write:
Reset:
Unaffected by reset
Figure 11-7. SPI Data Register (SPDR)
11.9.2 SPI Control Register
•
Enables SPI interrupt requests
•
Enables the SPI
•
Configures the SPI as master or slave
•
Selects serial clock polarity, phase, and frequency
Address:
$000A
Bit 7
6
SPIE
0
5
4
3
2
1
Bit 0
SPE
MSTR
CPOL
CPHA
SPR1
SPR0
0
0
U
U
U
U
Read:
Write:
Reset:
= Unimplemented
U = Unaffected
Figure 11-8. SPI Control Register (SPCR)
SPIE — SPI Interrupt Enable Bit
This read/write bit enables SPI interrupts. Reset clears the SPIE bit.
1 = SPI interrupts enabled
0 = SPI interrupts disabled
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Serial Peripheral Interface (SPI)
SPI — SPI Enable Bit
This read/write bit enables the SPI. Reset clears the SPE bit.
1 = SPI enabled
0 = SPI disabled
MSTR — Master Bit
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This read/write bit selects master mode operation or slave mode
operation. Reset clears the MSTR bit.
1 = Master mode
0 = Slave mode
CPOL — Clock Polarity Bit
This read/write bit determines the logic state of the PD4/SCK pin
between transmissions. To transmit data between SPIs, the SPIs
must have identical CPOL bits. Reset has no effect on the CPOL bit.
1 = PD4/SCK pin at logic 1 between transmissions
0 = PD4/SCK pin at logic 0 between transmissions
CPHA — Clock Phase Bit
This read/write bit controls the timing relationship between the serial
clock and SPI data. To transmit data between SPIs, the SPIs must
have identical CPHA bits. When CPHA = 0, the PD5/SS pin of the
slave SPI must be set to logic 1 between bytes. Reset has no effect
on the CPHA bit.
1 = Edge following first active edge on PD4/SCK latches data
0 = First active edge on PD4/SCK latches data
SPR1 and SPR0 — SPI Clock Rate Bits
These read/write bits select the master mode serial clock rate, as
shown in Table 11-1. The SPR1 and SPR0 bits of a slave SPI have
no effect on the serial clock. Reset has no effect on SPR1 and SPR0.
Table 11-1. SPI Clock Rate Selection
SPR[1:0]
SPI Clock Rate
00
Internal Clock
÷2
01
Internal Clock
÷4
10
Internal Clock
÷ 16
11
Internal Clock ÷ 32
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Serial Peripheral Interface (SPI)
SPI I/O Registers
11.9.3 SPI Status Register
The SPSR shown in Figure 11-9 contains flags to signal these
conditions:
•
SPI transmission complete
•
Write collision
•
Mode fault
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Address:
Read:
$000B
Bit 7
6
5
4
SPIF
WCOL
MODF
0
0
0
3
2
1
Bit 0
Write:
Reset:
= Unimplemented
Figure 11-9. SPI Status Register (SPSR)
SPIF — SPI Flag
This clearable, read-only bit is set each time a byte shifts out of or into
the shift register. SPIF generates an interrupt request if the SPIE bit
in the SPCR is also set. Clear SPIF by reading the SPSR with SPIF
set and then reading or writing the SPDR. Reset clears the SPIF bit.
1 = Transmission complete
0 = Transmission not complete
WCOL — Write Collision Bit
This clearable, read-only flag is set when software writes to the SPDR
while a transmission is in progress. Clear the WCOL bit by reading the
SPSR with WCOL set and then reading or writing the SPDR. Reset
clears WCOL.
1 = Invalid write to SPDR
0 = No invalid write to SPDR
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Serial Peripheral Interface (SPI)
MODF — Mode Fault Bit
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This clearable, read-only bit is set when a logic 0 occurs on the
PD5/SS pin while the MSTR bit is set. MODF generates an interrupt
request if the SPIE bit is also set. Clear the MODF bit by reading the
SPSR with MODF set and then writing to the SPCR. Reset clears
MODF.
1 = PD5/SS pulled low while MSTR bit set
0 = PD5/SS not pulled low while MSTR bit set
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Technical Data — MC68HC705C8A
Section 12. Instruction Set
12.1 Contents
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12.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
12.3 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
12.3.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
12.3.2 Immediate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
12.3.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
12.3.4 Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
12.3.5 Indexed, No Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
12.3.6 Indexed, 8-Bit Offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
12.3.7 Indexed, 16-Bit Offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
12.3.8 Relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
12.4 Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
12.4.1 Register/Memory Instructions. . . . . . . . . . . . . . . . . . . . . . .158
12.4.2 Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . . 159
12.4.3 Jump/Branch Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . 160
12.4.4 Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . .162
12.4.5 Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
12.5
Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
12.6
Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
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Instruction Set
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Instruction Set
12.2 Introduction
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The MCU instruction set has 62 instructions and uses eight addressing
modes. The instructions include all those of the M146805 CMOS Family
plus one more: the unsigned multiply (MUL) instruction. The MUL
instruction allows unsigned multiplication of the contents of the
accumulator (A) and the index register (X). The high-order product is
stored in the index register, and the low-order product is stored in the
accumulator.
12.3 Addressing Modes
The CPU uses eight addressing modes for flexibility in accessing data.
The addressing modes provide eight different ways for the CPU to find
the data required to execute an instruction.
The eight addressing modes are:
•
Inherent
•
Immediate
•
Direct
•
Extended
•
Indexed, no offset
•
Indexed, 8-bit offset
•
Indexed, 16-bit offset
•
Relative
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Addressing Modes
12.3.1 Inherent
Inherent instructions are those that have no operand, such as return
from interrupt (RTI) and stop (STOP). Some of the inherent instructions
act on data in the CPU registers, such as set carry flag (SEC) and
increment accumulator (INCA). Inherent instructions require no operand
address and are one byte long.
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12.3.2 Immediate
Immediate instructions are those that contain a value to be used in an
operation with the value in the accumulator or index register. Immediate
instructions require no operand address and are two bytes long. The
opcode is the first byte, and the immediate data value is the second byte.
12.3.3 Direct
Direct instructions can access any of the first 256 memory locations with
two bytes. The first byte is the opcode, and the second is the low byte of
the operand address. In direct addressing, the CPU automatically uses
$00 as the high byte of the operand address.
12.3.4 Extended
Extended instructions use three bytes and can access any address in
memory. The first byte is the opcode; the second and third bytes are the
high and low bytes of the operand address.
When using the Motorola assembler, the programmer does not need to
specify whether an instruction is direct or extended. The assembler
automatically selects the shortest form of the instruction.
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12.3.5 Indexed, No Offset
Indexed instructions with no offset are 1-byte instructions that can
access data with variable addresses within the first 256 memory
locations. The index register contains the low byte of the effective
address of the operand. The CPU automatically uses $00 as the high
byte, so these instructions can address locations $0000–$00FF.
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Indexed, no offset instructions are often used to move a pointer through
a table or to hold the address of a frequently used RAM or I/O location.
12.3.6 Indexed, 8-Bit Offset
Indexed, 8-bit offset instructions are 2-byte instructions that can access
data with variable addresses within the first 511 memory locations. The
CPU adds the unsigned byte in the index register to the unsigned byte
following the opcode. The sum is the effective address of the operand.
These instructions can access locations $0000–$01FE.
Indexed 8-bit offset instructions are useful for selecting the kth element
in an n-element table. The table can begin anywhere within the first 256
memory locations and could extend as far as location 510 ($01FE). The
k value is typically in the index register, and the address of the beginning
of the table is in the byte following the opcode.
12.3.7 Indexed, 16-Bit Offset
Indexed, 16-bit offset instructions are 3-byte instructions that can access
data with variable addresses at any location in memory. The CPU adds
the unsigned byte in the index register to the two unsigned bytes
following the opcode. The sum is the effective address of the operand.
The first byte after the opcode is the high byte of the 16-bit offset; the
second byte is the low byte of the offset.
Indexed, 16-bit offset instructions are useful for selecting the kth element
in an n-element table anywhere in memory.
As with direct and extended addressing, the Motorola assembler
determines the shortest form of indexed addressing.
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Instruction Types
12.3.8 Relative
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Relative addressing is only for branch instructions. If the branch
condition is true, the CPU finds the effective branch destination by
adding the signed byte following the opcode to the contents of the
program counter. If the branch condition is not true, the CPU goes to the
next instruction. The offset is a signed, two’s complement byte that gives
a branching range of –128 to +127 bytes from the address of the next
location after the branch instruction.
When using the Motorola assembler, the programmer does not need to
calculate the offset, because the assembler determines the proper offset
and verifies that it is within the span of the branch.
12.4 Instruction Types
The MCU instructions fall into five categories:
•
Register/memory instructions
•
Read-modify-write instructions
•
Jump/branch instructions
•
Bit manipulation instructions
•
Control instructions
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12.4.1 Register/Memory Instructions
These instructions operate on CPU registers and memory locations.
Most of them use two operands. One operand is in either the
accumulator or the index register. The CPU finds the other operand in
memory.
Table 12-1. Register/Memory Instructions
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Instruction
Add memory byte and carry bit to accumulator
ADC
Add memory byte to accumulator
ADD
AND memory byte with accumulator
AND
Bit test accumulator
BIT
Compare accumulator
CMP
Compare index register with memory byte
CPX
Exclusive OR accumulator with memory byte
EOR
Load accumulator with memory byte
LDA
Load Index register with memory byte
LDX
Multiply
MUL
OR accumulator with memory byte
ORA
Subtract memory byte and carry bit from
accumulator
SBC
Store accumulator in memory
STA
Store index register in memory
STX
Subtract memory byte from accumulator
SUB
Technical Data
158
Mnemonic
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Instruction Types
12.4.2 Read-Modify-Write Instructions
These instructions read a memory location or a register, modify its
contents, and write the modified value back to the memory location or to
the register.
NOTE:
Do not use read-modify-write operations on write-only registers.
Table 12-2. Read-Modify-Write Instructions
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Instruction
Mnemonic
Arithmetic shift left (same as LSL)
ASL
Arithmetic shift right
ASR
Bit clear
BCLR(1)
Bit set
BSET(1)
Clear register
CLR
Complement (one’s complement)
COM
Decrement
DEC
Increment
INC
Logical shift left (same as ASL)
LSL
Logical shift right
LSR
Negate (two’s complement)
NEG
Rotate left through carry bit
ROL
Rotate right through carry bit
ROR
Test for negative or zero
TST(2)
1. Unlike other read-modify-write instructions, BCLR and BSET use
only direct addressing.
2. TST is an exception to the read-modify-write sequence because it
does not write a replacement value.
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12.4.3 Jump/Branch Instructions
Jump instructions allow the CPU to interrupt the normal sequence of the
program counter. The unconditional jump instruction (JMP) and the
jump-to-subroutine instruction (JSR) have no register operand. Branch
instructions allow the CPU to interrupt the normal sequence of the
program counter when a test condition is met. If the test condition is not
met, the branch is not performed.
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The BRCLR and BRSET instructions cause a branch based on the state
of any readable bit in the first 256 memory locations. These 3-byte
instructions use a combination of direct addressing and relative
addressing. The direct address of the byte to be tested is in the byte
following the opcode. The third byte is the signed offset byte. The CPU
finds the effective branch destination by adding the third byte to the
program counter if the specified bit tests true. The bit to be tested and its
condition (set or clear) is part of the opcode. The span of branching is
from –128 to +127 from the address of the next location after the branch
instruction. The CPU also transfers the tested bit to the carry/borrow bit
of the condition code register.
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Instruction Types
Table 12-3. Jump and Branch Instructions
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Instruction
Branch if carry bit clear
BCC
Branch if carry bit set
BCS
Branch if equal
BEQ
Branch if half-carry bit clear
BHCC
Branch if half-carry bit set
BHCS
Branch if higher
BHI
Branch if higher or same
BHS
Branch if IRQ pin high
BIH
Branch if IRQ pin low
BIL
Branch if lower
BLO
Branch if lower or same
BLS
Branch if interrupt mask clear
BMC
Branch if minus
BMI
Branch if interrupt mask set
BMS
Branch if not equal
BNE
Branch if plus
BPL
Branch always
BRA
Branch if bit clear
Branch never
Branch if bit set
BRCLR
BRN
BRSET
Branch to subroutine
BSR
Unconditional jump
JMP
Jump to subroutine
JSR
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12.4.4 Bit Manipulation Instructions
The CPU can set or clear any writable bit in the first 256 bytes of
memory, which includes I/O registers and on-chip RAM locations. The
CPU can also test and branch based on the state of any bit in any of the
first 256 memory locations.
Table 12-4. Bit Manipulation Instructions
Instruction
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Bit clear
BCLR
Branch if bit clear
BRCLR
Branch if bit set
BRSET
Bit set
Technical Data
162
Mnemonic
BSET
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Instruction Types
12.4.5 Control Instructions
These instructions act on CPU registers and control CPU operation
during program execution.
Table 12-5. Control Instructions
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Instruction
Clear carry bit
CLC
Clear interrupt mask
CLI
No operation
NOP
Reset stack pointer
RSP
Return from interrupt
RTI
Return from subroutine
RTS
Set carry bit
SEC
Set interrupt mask
SEI
Stop oscillator and enable IRQ pin
STOP
Software interrupt
SWI
Transfer accumulator to index register
TAX
Transfer index register to accumulator
TXA
Stop CPU clock and enable interrupts
WAIT
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Technical Data
Instruction Set
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Instruction Set
12.5 Instruction Set Summary
#opr
opr
opr
opr,X
opr,X
,X
ADD
ADD
ADD
ADD
ADD
ADD
#opr
opr
opr
opr,X
opr,X
,X
AND #opr
AND opr
AND opr
AND opr,X
AND opr,X
AND ,X
ASL opr
ASLA
ASLX
ASL opr,X
ASL ,X
IMM
DIR
EXT
IX2
IX1
IX
ii
A9
2
B9 dd 3
C9 hh ll 4
D9 ee ff 5
E9 ff
4
F9
3
IMM
DIR
EXT
IX2
IX1
IX
AB ii
2
BB dd 3
CB hh ll 4
DB ee ff 5
EB ff
4
FB
3
—
IMM
DIR
EXT
IX2
IX1
IX
ii
A4
2
B4 dd 3
C4 hh ll 4
D4 ee ff 5
E4 ff
4
F4
3
38
48
58
68
78
dd
DIR
INH
INH
IX1
IX
DIR
INH
INH
IX1
IX
37
47
57
67
77
dd
REL
24
rr
3
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
— — — — —
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
11
13
15
17
19
1B
1D
1F
dd
dd
dd
dd
dd
dd
dd
dd
5
5
5
5
5
5
5
5
Effect on
CCR
Description
H I N Z C
A ← (A) ∧ (M)
Logical AND
Arithmetic Shift Left (Same as LSL)
C
BCC rel
Branch if Carry Bit Clear
—
—
— —
0
b7
Arithmetic Shift Right
A ← (A) + (M)
Add without Carry
ASR opr
ASRA
ASRX
ASR opr,X
ASR ,X
A ← (A) + (M) + (C)
Add with Carry
— —
b0
C
b7
— —
b0
PC ← (PC) + 2 + rel ? C = 0
Mn ← 0
— — — — —
ff
ff
Cycles
Opcode
ADC
ADC
ADC
ADC
ADC
ADC
Operation
Address
Mode
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Source
Form
Operand
Table 12-6. Instruction Set Summary (Sheet 1 of 6)
5
3
3
6
5
5
3
3
6
5
BCLR n opr
Clear Bit n
BCS rel
Branch if Carry Bit Set (Same as BLO)
PC ← (PC) + 2 + rel ? C = 1
— — — — —
REL
25
rr
3
BEQ rel
Branch if Equal
PC ← (PC) + 2 + rel ? Z = 1
— — — — —
REL
27
rr
3
BHCC rel
Branch if Half-Carry Bit Clear
PC ← (PC) + 2 + rel ? H = 0
— — — — —
REL
28
rr
3
BHCS rel
Branch if Half-Carry Bit Set
PC ← (PC) + 2 + rel ? H = 1
— — — — —
REL
29
rr
3
BHI rel
Branch if Higher
PC ← (PC) + 2 + rel ? C ∨ Z = 0 — — — — —
REL
22
rr
3
BHS rel
Branch if Higher or Same
REL
24
rr
3
PC ← (PC) + 2 + rel ? C = 0
Technical Data
164
— — — — —
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Instruction Set Summary
Address
Mode
Opcode
Operand
Cycles
Table 12-6. Instruction Set Summary (Sheet 2 of 6)
BIH rel
Branch if IRQ Pin High
PC ← (PC) + 2 + rel ? IRQ = 1
— — — — —
REL
2F
rr
3
BIL rel
Branch if IRQ Pin Low
PC ← (PC) + 2 + rel ? IRQ = 0
— — — — —
REL
2E
rr
3
—
IMM
DIR
EXT
IX2
IX1
IX
ii
A5
2
B5 dd 3
C5 hh ll 4
D5 ee ff 5
E5 ff
4
F5
3
— — — — —
REL
25
rr
3
PC ← (PC) + 2 + rel ? C ∨ Z = 1 — — — — —
REL
23
rr
3
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Source
Form
Operation
Description
Effect on
CCR
H I N Z C
BIT #opr
BIT opr
BIT opr
BIT opr,X
BIT opr,X
BIT ,X
Bit Test Accumulator with Memory Byte
BLO rel
Branch if Lower (Same as BCS)
BLS rel
Branch if Lower or Same
BMC rel
Branch if Interrupt Mask Clear
PC ← (PC) + 2 + rel ? I = 0
— — — — —
REL
2C
rr
3
BMI rel
Branch if Minus
PC ← (PC) + 2 + rel ? N = 1
— — — — —
REL
2B
rr
3
BMS rel
Branch if Interrupt Mask Set
PC ← (PC) + 2 + rel ? I = 1
— — — — —
REL
2D
rr
3
BNE rel
Branch if Not Equal
PC ← (PC) + 2 + rel ? Z = 0
— — — — —
REL
26
rr
3
BPL rel
Branch if Plus
PC ← (PC) + 2 + rel ? N = 0
— — — — —
REL
2A
rr
3
BRA rel
Branch Always
PC ← (PC) + 2 + rel ? 1 = 1
— — — — —
REL
20
rr
3
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
01
03
05
07
09
0B
0D
0F
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
5
5
5
5
5
5
5
5
BRCLR n opr rel Branch if Bit n Clear
BRN rel
Branch Never
BRSET n opr rel Branch if Bit n Set
BSET n opr
Set Bit n
(A) ∧ (M)
PC ← (PC) + 2 + rel ? C = 1
PC ← (PC) + 2 + rel ? Mn = 0
PC ← (PC) + 2 + rel ? 1 = 0
— —
— — — —
REL
21
rr
3
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
00
02
04
06
08
0A
0C
0E
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
5
5
5
5
5
5
5
5
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
— — — — —
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
10
12
14
16
18
1A
1C
1E
dd
dd
dd
dd
dd
dd
dd
dd
5
5
5
5
5
5
5
5
PC ← (PC) + 2; push (PCL)
SP ← (SP) – 1; push (PCH)
SP ← (SP) – 1
PC ← (PC) + rel
— — — — —
REL
AD
rr
6
PC ← (PC) + 2 + rel ? Mn = 1
Mn ← 1
— — — — —
— — — —
BSR rel
Branch to Subroutine
CLC
Clear Carry Bit
C←0
— — — — 0
INH
98
2
CLI
Clear Interrupt Mask
I←0
— 0 — — —
INH
9A
2
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Instruction Set
CMP #opr
CMP opr
CMP opr
CMP opr,X
CMP opr,X
CMP ,X
COM opr
COMA
COMX
COM opr,X
COM ,X
CPX
CPX
CPX
CPX
CPX
CPX
#opr
opr
opr
opr,X
opr,X
,X
DEC opr
DECA
DECX
DEC opr,X
DEC ,X
EOR
EOR
EOR
EOR
EOR
EOR
#opr
opr
opr
opr,X
opr,X
,X
INC opr
INCA
INCX
INC opr,X
INC ,X
JMP opr
JMP opr
JMP opr,X
JMP opr,X
JMP ,X
3F
4F
5F
6F
7F
dd
IMM
DIR
EXT
IX2
IX1
IX
ii
A1
2
B1 dd 3
C1 hh ll 4
D1 ee ff 5
E1 ff
4
F1
3
1
DIR
INH
INH
IX1
IX
33
43
53
63
73
IMM
DIR
EXT
IX2
IX1
IX
ii
A3
2
B3 dd 3
C3 hh ll 4
D3 ee ff 5
E3 ff
4
F3
3
DIR
INH
INH
IX1
IX
3A
4A
5A
6A
7A
—
IMM
DIR
EXT
IX2
IX1
IX
ii
A8
2
B8 dd 3
C8 hh ll 4
D8 ee ff 5
E8 ff
4
F8
3
—
DIR
INH
INH
IX1
IX
3C
4C
5C
6C
7C
DIR
EXT
IX2
IX1
IX
BC dd 2
CC hh ll 3
DC ee ff 4
EC ff
3
FC
2
H I N Z C
M ← $00
A ← $00
X ← $00
M ← $00
M ← $00
Clear Byte
Compare Accumulator with Memory Byte
Complement Byte (One’s Complement)
Compare Index Register with Memory Byte
EXCLUSIVE OR Accumulator with Memory
Byte
Unconditional Jump
M ← (M) = $FF – (M)
A ← (A) = $FF – (A)
X ← (X) = $FF – (X)
M ← (M) = $FF – (M)
M ← (M) = $FF – (M)
(X) – (M)
M ← (M) – 1
A ← (A) – 1
X ← (X) – 1
M ← (M) – 1
M ← (M) – 1
Decrement Byte
Increment Byte
(A) – (M)
A ← (A) ⊕ (M)
M ← (M) + 1
A ← (A) + 1
X ← (X) + 1
M ← (M) + 1
M ← (M) + 1
PC ← Jump Address
Technical Data
166
DIR
INH
INH
IX1
IX
Effect on
CCR
— — 0 1 —
— —
— —
— —
— —
— —
— —
—
— — — — —
ff
dd
ff
dd
ff
dd
ff
Cycles
Description
Operand
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CLR opr
CLRA
CLRX
CLR opr,X
CLR ,X
Operation
Opcode
Source
Form
Address
Mode
Table 12-6. Instruction Set Summary (Sheet 3 of 6)
5
3
3
6
5
5
3
3
6
5
5
3
3
6
5
5
3
3
6
5
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Instruction Set
Instruction Set Summary
LDA #opr
LDA opr
LDA opr
LDA opr,X
LDA opr,X
LDA ,X
LDX #opr
LDX opr
LDX opr
LDX opr,X
LDX opr,X
LDX ,X
LSL opr
LSLA
LSLX
LSL opr,X
LSL ,X
PC ← (PC) + n (n = 1, 2, or 3)
Push (PCL); SP ← (SP) – 1
Push (PCH); SP ← (SP) – 1
PC ← Effective Address
Jump to Subroutine
Logical Shift Left (Same as ASL)
ii
A6
2
B6 dd 3
C6 hh ll 4
D6 ee ff 5
E6 ff
4
F6
3
—
IMM
DIR
EXT
IX2
IX1
IX
AE ii
2
BE dd 3
CE hh ll 4
DE ee ff 5
EE ff
4
FE
3
38
48
58
68
78
dd
DIR
INH
INH
IX1
IX
0
DIR
INH
INH
IX1
IX
34
44
54
64
74
dd
0 — — — 0
INH
42
C
DIR
INH
INH
IX1
IX
30
40
50
60
70
Negate Byte (Two’s Complement)
NOP
No Operation
INH
9D
—
IMM
DIR
EXT
IX2
IX1
IX
AA ii
2
BA dd 3
CA hh ll 4
DA ee ff 5
EA ff
4
FA
3
DIR
INH
INH
IX1
IX
39
49
59
69
79
— — 0
b0
X : A ← (X) × (A)
NEG opr
NEGA
NEGX
NEG opr,X
NEG ,X
b0
0
b7
— —
M ← –(M) = $00 – (M)
A ← –(A) = $00 – (A)
X ← –(X) = $00 – (X)
M ← –(M) = $00 – (M)
M ← –(M) = $00 – (M)
— —
— — — — —
A ← (A) ∨ (M)
Logical OR Accumulator with Memory
Rotate Byte Left through Carry Bit
— —
C
— —
b7
b0
MC68HC705C8A — Rev. 3
ff
ff
Cycles
—
IMM
DIR
EXT
IX2
IX1
IX
— — — — —
— —
C
b7
Unsigned Multiply
MOTOROLA
BD dd 5
CD hh ll 6
DD ee ff 7
ED ff
6
FD
5
— —
X ← (M)
Load Index Register with Memory Byte
MUL
ROL opr
ROLA
ROLX
ROL opr,X
ROL ,X
A ← (M)
Load Accumulator with Memory Byte
Logical Shift Right
#opr
opr
opr
opr,X
opr,X
,X
DIR
EXT
IX2
IX1
IX
H I N Z C
LSR opr
LSRA
LSRX
LSR opr,X
LSR ,X
ORA
ORA
ORA
ORA
ORA
ORA
Description
Opcode
Freescale Semiconductor, Inc...
JSR opr
JSR opr
JSR opr,X
JSR opr,X
JSR ,X
Operation
Effect on
CCR
Address
Mode
Source
Form
Operand
Table 12-6. Instruction Set Summary (Sheet 4 of 6)
5
3
3
6
5
5
3
3
6
5
1
1
dd
ff
5
3
3
6
5
2
dd
ff
5
3
3
6
5
Technical Data
Instruction Set
For More Information On This Product,
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Freescale Semiconductor, Inc.
Instruction Set
Opcode
Operand
DIR
INH
INH
IX1
IX
36
46
56
66
76
dd
— — — — —
INH
9C
2
Return from Interrupt
SP ← (SP) + 1; Pull (CCR)
SP ← (SP) + 1; Pull (A)
SP ← (SP) + 1; Pull (X)
SP ← (SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCL)
INH
80
9
Return from Subroutine
SP ← (SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCL)
— — — — —
INH
81
6
IMM
DIR
EXT
IX2
IX1
IX
ii
A2
2
B2 dd 3
C2 hh ll 4
D2 ee ff 5
E2 ff
4
F2
3
Freescale Semiconductor, Inc...
Source
Form
Operation
Effect on
CCR
Description
H I N Z C
ROR opr
RORA
RORX
ROR opr,X
ROR ,X
Rotate Byte Right through Carry Bit
RSP
Reset Stack Pointer
SP ← $00FF
RTI
RTS
C
b7
— —
b0
ff
Cycles
Address
Mode
Table 12-6. Instruction Set Summary (Sheet 5 of 6)
5
3
3
6
5
SBC #opr
SBC opr
SBC opr
SBC opr,X
SBC opr,X
SBC ,X
Subtract Memory Byte and Carry Bit from
Accumulator
SEC
Set Carry Bit
C←1
— — — — 1
INH
99
2
SEI
Set Interrupt Mask
I←1
— 1 — — —
INH
9B
2
—
DIR
EXT
IX2
IX1
IX
B7 dd 4
C7 hh ll 5
D7 ee ff 6
E7 ff
5
F7
4
— 0 — — —
INH
8E
—
DIR
EXT
IX2
IX1
IX
BF dd 4
CF hh ll 5
DF ee ff 6
EF ff
5
FF
4
IMM
DIR
EXT
IX2
IX1
IX
ii
A0
2
B0 dd 3
C0 hh ll 4
D0 ee ff 5
E0 ff
4
F0
3
PC ← (PC) + 1; Push (PCL)
SP ← (SP) – 1; Push (PCH)
SP ← (SP) – 1; Push (X)
SP ← (SP) – 1; Push (A)
— 1 — — —
SP ← (SP) – 1; Push (CCR)
SP ← (SP) – 1; I ← 1
PCH ← Interrupt Vector High Byte
PCL ← Interrupt Vector Low Byte
INH
83
1
0
INH
97
2
STA opr
STA opr
STA opr,X
STA opr,X
STA ,X
Store Accumulator in Memory
STOP
Stop Oscillator and Enable IRQ Pin
STX opr
STX opr
STX opr,X
STX opr,X
STX ,X
SUB
SUB
SUB
SUB
SUB
SUB
#opr
opr
opr
opr,X
opr,X
,X
Store Index Register In Memory
Subtract Memory Byte from Accumulator
SWI
Software Interrupt
TAX
Transfer Accumulator to Index Register
A ← (A) – (M) – (C)
M ← (A)
M ← (X)
A ← (A) – (M)
X ← (A)
Technical Data
168
— —
— —
— —
— —
— — — — —
2
MC68HC705C8A — Rev. 3
Instruction Set
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Freescale Semiconductor, Inc.
Instruction Set
Opcode Map
Freescale Semiconductor, Inc...
Test Memory Byte for Negative or Zero
TXA
Transfer Index Register to Accumulator
WAIT
Stop CPU Clock and Enable Interrupts
Accumulator
Carry/borrow flag
Condition code register
Direct address of operand
Direct address of operand and relative offset of branch instruction
Direct addressing mode
High and low bytes of offset in indexed, 16-bit offset addressing
Extended addressing mode
Offset byte in indexed, 8-bit offset addressing
Half-carry flag
High and low bytes of operand address in extended addressing
Interrupt mask
Immediate operand byte
Immediate addressing mode
Inherent addressing mode
Indexed, no offset addressing mode
Indexed, 8-bit offset addressing mode
Indexed, 16-bit offset addressing mode
Memory location
Negative flag
Any bit
(M) – $00
— —
A ← (X)
—
— — — — —
—
opr
PC
PCH
PCL
REL
rel
rr
SP
X
Z
#
∧
∨
⊕
()
–( )
←
?
:
—
— — —
DIR
INH
INH
IX1
IX
3D
4D
5D
6D
7D
dd
INH
9F
2
INH
8F
2
ff
Cycles
H I N Z C
TST opr
TSTA
TSTX
TST opr,X
TST ,X
A
C
CCR
dd
dd rr
DIR
ee ff
EXT
ff
H
hh ll
I
ii
IMM
INH
IX
IX1
IX2
M
N
n
Description
Operand
Operation
Effect on
CCR
Opcode
Source
Form
Address
Mode
Table 12-6. Instruction Set Summary (Sheet 6 of 6)
4
3
3
5
4
Operand (one or two bytes)
Program counter
Program counter high byte
Program counter low byte
Relative addressing mode
Relative program counter offset byte
Relative program counter offset byte
Stack pointer
Index register
Zero flag
Immediate value
Logical AND
Logical OR
Logical EXCLUSIVE OR
Contents of
Negation (two’s complement)
Loaded with
If
Concatenated with
Set or cleared
Not affected
12.6 Opcode Map
See Table 12-7.
MC68HC705C8A — Rev. 3
MOTOROLA
Technical Data
Instruction Set
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170
Technical Data
Instruction Set
For More Information On This Product,
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F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
0
MSB
LSB
1
DIR
INH = Inherent
IMM = Immediate
DIR = Direct
EXT = Extended
5
5
BSET0
BRSET0
DIR
3
DIR 2
5
5
BCLR0
BRCLR0
DIR
3
DIR 2
5
5
BSET1
BRSET1
DIR
3
DIR 2
5
5
BCLR1
BRCLR1
DIR
3
DIR 2
5
5
BSET2
BRSET2
DIR
3
DIR 2
5
5
BCLR2
BRCLR2
DIR
3
DIR 2
5
5
BSET3
BRSET3
DIR
3
DIR 2
5
5
BCLR3
BRCLR3
DIR
3
DIR 2
5
5
BSET4
BRSET4
DIR
3
DIR 2
5
5
BCLR4
BRCLR4
DIR
3
DIR 2
5
5
BSET5
BRSET5
DIR
3
DIR 2
5
5
BCLR5
BRCLR5
DIR
3
DIR 2
5
5
BSET6
BRSET6
DIR
3
DIR 2
5
5
BCLR6
BRCLR6
DIR
3
DIR 2
5
5
BSET7
BRSET7
DIR
3
DIR 2
5
5
BCLR7
BRCLR7
DIR
3
DIR 2
0
DIR
Bit Manipulation
3
DIR
4
5
INH
6
IX1
Read-Modify-Write
INH
7
IX
REL = Relative
IX = Indexed, No Offset
IX1 = Indexed, 8-Bit Offset
IX2 = Indexed, 16-Bit Offset
1
1
1
1
1
1
1
2
TAX
INH
2
CLC
INH
2
SEC
INH
2
CLI
INH
2
SEI
INH
2
RSP
INH
2
NOP
INH
9
2
STOP
INH
2
2
TXA
WAIT
INH
INH 1
10
SWI
INH
9
RTI
INH
6
RTS
INH
8
INH
Control
INH
LSB of Opcode in Hexadecimal
5
6
3
3
5
3
NEG
NEG
NEGX
NEGA
NEG
BRA
IX 1
IX1 1
INH 2
INH 1
DIR 1
REL 2
3
BRN
2
REL
1
3
11
BHI
MUL
2
REL
1
INH
5
6
3
3
5
3
COM
COM
COMX
COMA
COM
BLS
IX 1
IX1 1
INH 2
INH 1
DIR 1
2
REL 2
5
6
3
3
5
3
LSR
LSR
LSRX
LSRA
LSR
BCC
IX
IX1 1
INH 2
INH 1
DIR 1
2
REL 2
3
BCS/BLO
2
REL
5
6
3
3
5
3
ROR
ROR
RORX
RORA
ROR
BNE
IX
IX1 1
INH 2
INH 1
DIR 1
2
REL 2
5
6
3
3
5
3
ASR
ASR
ASRX
ASRA
ASR
BEQ
IX
IX1 1
INH 2
INH 1
DIR 1
2
REL 2
5
6
3
3
5
3
ASL/LSL ASLA/LSLA ASLX/LSLX ASL/LSL ASL/LSL
BHCC
IX
IX1 1
INH 2
INH 1
DIR 1
2
REL 2
5
6
3
3
5
3
ROL
ROL
ROLX
ROLA
ROL
BHCS
IX
IX1 1
INH 2
INH 1
DIR 1
2
REL 2
5
6
3
3
5
3
DEC
DEC
DECX
DECA
DEC
BPL
IX
IX1 1
INH 2
INH 1
DIR 1
2
REL 2
3
BMI
2
REL
5
6
3
3
5
3
INC
INC
INCX
INCA
INC
BMC
IX
IX1 1
INH 2
INH 1
DIR 1
2
REL 2
4
5
3
3
4
3
TST
TST
TSTX
TSTA
TST
BMS
IX
IX1 1
INH 2
INH 1
DIR 1
2
REL 2
3
BIL
2
REL
1
5
6
3
3
5
3
CLR
CLR
CLRX
CLRA
CLR
BIH
IX 1
IX1 1
INH 2
INH 1
DIR 1
2
REL 2
2
2
REL
Branch
Table 12-7. Opcode Map
2
SUB
IMM
2
CMP
IMM
2
SBC
IMM
2
CPX
IMM
2
AND
IMM
2
BIT
IMM
2
LDA
IMM
2
2
2
2
2
2
2
2
2
2
2
2
2
MSB
0
LSB
0
3
SUB
DIR
3
CMP
DIR
3
SBC
DIR
3
CPX
DIR
3
AND
DIR
3
BIT
DIR
3
LDA
DIR
4
STA
DIR
3
EOR
DIR
3
ADC
DIR
3
ORA
DIR
3
ADD
DIR
2
JMP
DIR
5
JSR
DIR
3
LDX
DIR
4
STX
DIR
B
DIR
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
5
SUB
IX2
5
CMP
IX2
5
SBC
IX2
5
CPX
IX2
5
AND
IX2
5
BIT
IX2
5
LDA
IX2
6
STA
IX2
5
EOR
IX2
5
ADC
IX2
5
ORA
IX2
5
ADD
IX2
4
JMP
IX2
7
JSR
IX2
5
LDX
IX2
6
STX
IX2
D
IX2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
4
SUB
IX1 1
4
CMP
IX1 1
4
SBC
IX1 1
4
CPX
IX1 1
4
AND
IX1 1
4
BIT
IX1 1
4
LDA
IX1 1
5
STA
IX1 1
4
EOR
IX1 1
4
ADC
IX1 1
4
ORA
IX1 1
4
ADD
IX1 1
3
JMP
IX1 1
6
JSR
IX1 1
4
LDX
IX1 1
5
STX
IX1 1
E
IX1
MSB of Opcode in Hexadecimal
4
SUB
EXT
4
CMP
EXT
4
SBC
EXT
4
CPX
EXT
4
AND
EXT
4
BIT
EXT
4
LDA
EXT
5
STA
EXT
4
EOR
EXT
4
ADC
EXT
4
ORA
EXT
4
ADD
EXT
3
JMP
EXT
6
JSR
EXT
4
LDX
EXT
5
STX
EXT
C
EXT
Register/Memory
5 Number of Cycles
BRSET0 Opcode Mnemonic
3
DIR Number of Bytes/Addressing Mode
2
6
BSR
2
REL 2
2
LDX
2
IMM 2
2
EOR
IMM
2
ADC
2
IMM
2
ORA
2
IMM
2
ADD
2
IMM
2
2
2
2
2
2
2
2
A
IMM
Freescale Semiconductor, Inc...
STX
LDX
JSR
JMP
ADD
ORA
ADC
EOR
STA
LDA
BIT
AND
CPX
SBC
CMP
SUB
F
IX
3
IX
IX
4
IX
3
IX
5
IX
2
IX
3
IX
3
IX
3
IX
3
IX
4
IX
3
IX
3
IX
3
IX
3
IX
3
IX
3
F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
0
MSB
LSB
Freescale Semiconductor, Inc.
Instruction Set
MC68HC705C8A — Rev. 3
Freescale Semiconductor, Inc.
Technical Data — MC68HC705C8A
Section 13.
Electrical Specifications
Freescale Semiconductor, Inc...
13.1 Contents
13.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
13.3
Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
13.4
Operating Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . 173
13.5
Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
13.6
Power Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
13.7
5.0-Volt DC Electrical Characteristics. . . . . . . . . . . . . . . . . . .175
13.8
3.3-Volt DC Electrical Characteristics . . . . . . . . . . . . . . . . . .176
13.9
5.0-Volt Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
13.10 3.3-Volt Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
13.11 5.0-Volt Serial Peripheral Interface (SPI) Timing . . . . . . . . . . 185
13.12 3.3-Volt Serial Peripheral Interface (SPI) Timing . . . . . . . . . . 187
13.2 Introduction
This section contains electrical and timing specifications.
MC68HC705C8A — Rev. 3
MOTOROLA
Technical Data
Electrical Specifications
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Electrical Specifications
13.3 Maximum Ratings
Maximum ratings are the extreme limits to which the MCU can be
exposed without permanently damaging it.
Freescale Semiconductor, Inc...
The MCU contains circuitry to protect the inputs against damage from
high static voltages; however, do not apply voltages higher than those
shown in the table here. Keep VIn and VOut within the range
VSS ≤ (VIn or VOut) ≤ VDD. Connect unused inputs to the appropriate
voltage level, either VSS or VDD.
Rating(1)
Symbol
Value
Unit
Supply voltage
VDD
–0.3 to +7.0
V
Input voltage
VIn
VSS –0.3
to VDD +0.3
V
Programming voltage
VPP
VDD –0.3 to
16.0
Bootstrap mode (IRQ pin only)
VIn
VSS – 0.3
to 2 x VDD + 0.3
V
Current drain per pin excluding
VDD and VSS
I
25
mA
TSTG
–65 to +150
°C
Storage temperature range
1. Voltages referenced to VSS
NOTE:
This device is not guaranteed to operate properly at the maximum
ratings. Refer to 13.7 5.0-Volt DC Electrical Characteristics and
13.8 3.3-Volt DC Electrical Characteristics for guaranteed operating
conditions.
Technical Data
172
MC68HC705C8A — Rev. 3
Electrical Specifications
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Electrical Specifications
Operating Temperature Range
13.4 Operating Temperature Range
Rating(1)
Symbol
Value
Unit
TA
TL to TH
– 40 to + 85
°C
Symbol
Value
Unit
Freescale Semiconductor, Inc...
Operating temperature range(2)
MC68HC705C8ACB
MC68HC705C8ACFB
MC68HC705C8ACFS
MC68HC705C8ACP
MC68HC705C8ACFN
MC68HC705C8ACFS
1. Voltages referenced to VSS
2. C = Extended temperature range (– 40°C to + 85°C)
P = Plastic dual in-line package (PDIP)
B = Plastic shrink dual in-line package (SDIP)
S = Ceramic dual in-line package (cerdip)
FN = Plastic-leaded chip carrier (PLCC)
FB = Quad flat pack (QFP)
FS = Ceramic-leaded chip carrier (CLCC)
13.5 Thermal Characteristics
Characteristic
Thermal resistance
Plastic dual in-line package (DIP)
Ceramic dual in-line package (cerdip)
Plastic leaded chip carrier (PLCC)
Quad flat pack (QFP)
Plastic shrink DIP (SDIP)
60
50
70
95
60
θJA
°C/W
VDD = 4.5 V
VDD
Pins
R2
(SEE TABLE)
TEST
POINT
C
(SEE TABLE)
R1
(SEE TABLE)
PA7–PA0
PB7–PB0
PC7–PC0
PD4–PD1
R1
R2
C
3.26 kΩ
2.38 kΩ
50 pF
R1
R2
C
10.91 kΩ
6.32 kΩ
50 pF
6 kΩ
6 kΩ
200 pF
VDD = 3.0 V
Pins
PA7–PA0
PB7–PB0
PC7–PC0
PD4–PD1
PD7, PD5, PD0
Figure 13-1. Equivalent Test Load
MC68HC705C8A — Rev. 3
MOTOROLA
Technical Data
Electrical Specifications
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Freescale Semiconductor, Inc.
Electrical Specifications
13.6 Power Considerations
The average chip junction temperature, TJ, in °C can be obtained from:
TJ = TA + (PD x θJA)
(1)
Freescale Semiconductor, Inc...
Where:
TA = ambient temperature in °C
θJA = package thermal resistance, junction to ambient in °C/W
PD = PINT + PI/O
PINT = ICC × VCC = chip internal power dissipation
PI/O = power dissipation on input and output pins (user-determined)
For most applications, PI/O < PINT and can be neglected.
Ignoring PI/O, the relationship between PD and TJ is approximately:
K
PD =
(2)
TJ + 273°C
Solving equations (1) and (2) for K gives:
= PD x (TA + 273°C) + θJA x (PD)2
(3)
where K is a constant pertaining to the particular part. K can be
determined from equation (3) by measuring PD (at equilibrium) for a
known TA. Using this value of K, the values of PD and TJ can be obtained
by solving equations (1) and (2) iteratively for any value of TA.
Technical Data
174
MC68HC705C8A — Rev. 3
Electrical Specifications
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Electrical Specifications
5.0-Volt DC Electrical Characteristics
13.7 5.0-Volt DC Electrical Characteristics
Freescale Semiconductor, Inc...
Characteristic(1)
Symbol
Min
Typ(2)
Max
Unit
Output voltage, ILoad ≤ 10.0 µA
VOL
VOH
—
VDD – 0.1
—
—
0.1
—
V
Output high voltage
ILoad = –0.8 mA, PA7–PA0, PB7–PB0, PC6–PC0, TCMP
(see Figure 13-2)
ILoad = –1.6 mA, PD4–PD1 (see Figure 13-3)
ILoad = –5.0 mA, PC7
VOH
VDD – 0.8
—
—
—
—
—
—
Output low voltage (see Figure 13-4)
ILoad = 1.6 mA
PA7–PA0, PB7–PB0, PC6–PC0, PD4–PD1
ILoad = 20 mA, PC7
VOL
—
—
—
—
0.4
0.4
VIH
0.7 x VDD
—
VDD
V
VIL
VSS
—
0.2 x VDD
V
EPROM programming voltage
VPP
14.5
14.75
15.0
V
EPROM/OTPROM programming current
IPP
—
5
10
mA
User mode current
IPP
—
—
± 10
mA
Data-retention mode (0°C to 70°C)
VRM
2.0
—
—
V
—
—
5.0
1.95
7.0
3.0
mA
mA
—
—
5.0
5.0
50
50
µµA
µµA
IIL
—
—
± 10
µA
IIn
—
—
±1
µA
COut
CIn
—
—
—
—
12
8
pF
Input high voltage
PA7–PA0, PB7–PB0, PC7–PC0, PD5–PD0, PD7,
TCAP, IRQ, RESET, OSC1
Input low voltage
PA7–PA0, PB7–PB0, PC7–PC0, PD5–PD0, PD7,
TCAP, IRQ, RESET, OSC1
V
V
(3)
Supply current
Run(4)
Wait(5)
Stop(6)
25°C
–40°C to +85°C
I/O ports hi-z leakage current
PA7–PA0, PB7–PB0, PC7–PC0, PD4–PD1, PD7, RESET
Input current, IRQ, TCAP, OSC1, PD0, PD5
Capacitance
Ports (as input or output)
RESET, IRQ, TCAP, PD0–PD5, PD7
IDD
1. VDD = 5 V ± 10%; VSS = 0 Vdc, TA = TL to TH, unless otherwise noted
2. Typical values reflect average measurements at midpoint of voltage range at 25°C.
3. IDD measured with port B pullup devices disabled.
4. Run (operating) IDD measured using external square wave clock source (fOSC = 4.2 MHz). All inputs 0.2 V from rail. No dc
loads. Less than 50 pF on all outputs. CL = 20 pF on OSC2. OSC2 capacitance linearly affects run IDD.
5. Wait IDD measured using external square wave clock source (fOSC = 4.2 MHz). All inputs 0.2 V from rail. No dc loads. Less
than 50 pF on all outputs. CL = 20 pF on OSC2. VIL = 0.2 V, VIH = VDD – 0.2 V. All ports configured as inputs. SPI and SCI
disabled. If SPI and SCI enabled, add 10% current draw. OSC2 capacitance linearly affects wait IDD.
6. Stop IDD measured with OSC1 = V DD. All ports configured as inputs. VIL = 0.2 V, VIH = VDD – 0.2 V.
MC68HC705C8A — Rev. 3
MOTOROLA
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Electrical Specifications
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Electrical Specifications
13.8 3.3-Volt DC Electrical Characteristics
Freescale Semiconductor, Inc...
Characteristic(1)
Symbol
Min
Typ(2)
Max
Unit
Output voltage, ILoad ≤ 10.0 µA
VOL
VOH
—
VDD – 0.1
—
—
0.1
—
V
Output high voltage
ILoad = –0.2 mA
PA7–PA0, PB7–PB0, PC6–PC0, TCMP
(see Figure 13-2)
ILoad = –0.4 mA
PD4–PD1 (see Figure 13-3)
ILoad = –1.5 mA
PC7
VOH
VDD – 0.3
—
—
—
—
—
—
Output low voltage (see Figure 13-4)
ILoad = 0.4 mA
PA7–PA0, PB7–PB0, PC6–PC0, PD4–PD1
ILoad = 6.0 mA
PC7
VOL
—
—
0.3
—
—
0.3
Input high voltage
PA7–PA0, PB7–PB0, PC7–PC0, PD5–PD0,
PD7, TCAP, IRQ, RESET, OSC1
VIH
0.7 x VDD
—
VDD
V
Input low voltage
PA7–PA0, PB7–PB0, PC7–PC0, PD5–PD0,
PD7, TCAP, IRQ, RESET, OSCI
VIL
VSS
—
0.2 x VDD
V
Data-retention mode (0°C to 70°C)
VRM
2.0
—
—
V
Supply current(3)
Run(4)
Wait(5)
Stop(6)
IDD
—
—
—
1.53
0.711
2.0
3.0
1.0
20
mA
mA
µA
I/O ports hi-z leakage current
PA7–PA0, PB7–PB0, PC7–PC0, PD4–PD1,
PD7, RESET
IIL
—
—
± 10
µA
Input current
IRQ, TCAP, OSC1, PD5, PD0
IIn
—
—
±1
µA
V
V
1. VDD = 3.3 V ± 10%; VSS = 0 Vdc, TA = TL to TH, unless otherwise noted
2. Typical values at midpoint of voltage range, 25°C only.
3. IDD measured with port B pullup devices disabled.
4. Run (operating) IDD measured using external square wave clock source (fOSC = 2.0 MHz). All inputs 0.2 V from rail. No dc
loads. Less than 50 pF on all outputs. CL = 20 pF on OSC2. OSC2 capacitance linearly affects run IDD.
5. Wait IDD measured using external square wave clock source (fOSC = 2.0 MHz). All inputs 0.2 V from rail. No dc loads. Less
than 50 pF on all outputs. C L = 20 pF on OSC2. V IL = 0.2 V, VIH = VDD – 0.2 V. All ports configured as inputs. SPI and SCI
disabled. If SPI and SCI enabled, add 10% current draw. OSC2 capacitance linearly affects wait IDD.
6. Stop IDD measured with OSC1 = V DD. All ports configured as inputs. VIL = 0.2 V; VIH = VDD – 0.2 V.
Technical Data
176
MC68HC705C8A — Rev. 3
Electrical Specifications
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Electrical Specifications
3.3-Volt DC Electrical Characteristics
5.0
4.0
V DD
=5
.0 V
IOH (mA)
3.0
2.0
V DD
= 3.
0V
SEE NOTE 1
Freescale Semiconductor, Inc...
1.0
0.8
SEE NOTE 2
0.2
0
0
0.2
0.4
0.6
0.8
VDD – VOH (VOLTS)
Notes:
1. At VDD = 5.0 V, devices are specified and tested for (VDD – VOH )
≤ 800 mV @ IOH = –0.8 mA.
2. At VDD = 3.3 V, devices are specified and tested for (VDD – VOH )
≤ 300 mV @ IOH = –0.2 mA.
(a) VOH versus IOH for Ports A, B, PC6–PC0, and TCMP
8.0
6.0
IOH (mA)
V
.0
=5
V DD
4.0
2.0
1.6
V DD
.0
=3
SEE NOTE 1
V
SEE NOTE 2
0.4
0
0
0.2
0.4
0.6
VDD – VOH (VOLTS)
Notes:
1. At VDD = 5.0 V, devices are specified and tested for
(V DD – VOH) ≤ 800 mV @ IOH = –1.6 mA.
2. At VDD = 3.3 V, devices are specified and tested for
(V DD – VOH) ≤ 300 mV @ IOH = –0.4 mA.
(b) VOH versus IOH for PD4–PD1
Figure 13-2. Typical Voltage Compared to Current
MC68HC705C8A — Rev. 3
MOTOROLA
Technical Data
Electrical Specifications
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Freescale Semiconductor, Inc.
Electrical Specifications
6.0
5.0
4.0
IOL (MA)
V DD
.0
V
3.0
V DD
2.0
Freescale Semiconductor, Inc...
=5
.0
=3
V
SEE NOTE 1
1.6
1.0
SEE NOTE 2
0.4
0
0
0.1
0.2
0.3
0.4
VOL (VOLTS)
Notes:
1. At VDD = 5.0 V, devices are specified and tested for
VOL ≤ 400 mV @ IOL = 1.6 mA.
2. At VDD = 3.3 V, devices are specified and tested for
VOL ≤ 300 mV @ IOL = 0.4 mA.
(c) VOL versus IOL for All Ports Except PC7
Figure 13-2. Typical Voltage Compared to Current (Continued)
Technical Data
178
MC68HC705C8A — Rev. 3
Electrical Specifications
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Freescale Semiconductor, Inc.
Electrical Specifications
3.3-Volt DC Electrical Characteristics
2.0
1.8
1.6
=5
.0
V
1.4
DD
V
IDD (mA)
1.2
1.0
Freescale Semiconductor, Inc...
0.8
0.6
=3
0.4
.3
V
V DD
0.2
0.0
0.0
0.5
1.0
1.5
INTERNAL FREQUENCY 1 tCYC (MHz)
2.0
(a) Wait Mode
5.5
5.0
4.5
=5
.0
V
4.0
V
DD
3.5
IDD (mA)
3.0
2.5
2.0
1.5
1.0
V DD
=3
V
.3
0.5
0.0
0.0
0.5
1.0
1.5
INTERNAL FREQUENCY 1 tCYC (MHz)
2.0
(b) Run Mode
Figure 13-3. Typical Current versus Internal
Frequency for Run and Wait Modes
MC68HC705C8A — Rev. 3
MOTOROLA
Technical Data
Electrical Specifications
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Electrical Specifications
3.0 mA
T = –40°C to 85°C
VDD = 3.3 V ± 10%
2.5 mA
Freescale Semiconductor, Inc...
SUPPLY CURRENT (IDD)
D
2.0 mA
N
RU
1.5 mA
G
TIN
RA
E
P
(O
)ID
1.0 mA
WAIT
I DD
500 mA
(20 µA)
STOP IDD
0
0
250 kHz
500 kHz
750 kHz
1 MHz
INTERNAL CLOCK FREQUENCY (XTAL ÷ 2)
(a) Maximum Current Drain versus Frequency @ 3.3 V ± 10 %
7.0 mA
T = –40°C to 85°C
VDD = 5.0 V ± 10%
6.0 mA
SUPPLY CURRENT (IDD)
5.0 mA
4.0 mA
N
RU
(O
PE
G
TIN
A
R
)ID
D
3.0 mA
WA
2.0 mA
IT I DD
1.0 mA
STOP IDD
(50 µA)
0
0
500 kHz
1 MHz
1.5 MHz
2 MHz
INTERNAL CLOCK FREQUENCY (XTAL ÷ 2)
(b) Maximum Current Drain versus Frequency @ 5 V ± 10%
Figure 13-4. Total Current Drain versus Frequency
Technical Data
180
MC68HC705C8A — Rev. 3
Electrical Specifications
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Electrical Specifications
5.0-Volt Control Timing
13.9 5.0-Volt Control Timing
Freescale Semiconductor, Inc...
Characteristic(1)
Symbol
Min
Max
Unit
Frequency of operation
Crystal option
External clock option
fOSC
—
dc
4.2
4.2
MHz
Internal operating frequency
Crystal (fOSC ÷ 2)
External clock (fOSC ÷ 2)
fOP
—
dc
2.1
2.1
MHz
Cycle time (see Figure 13-7)
tCYC
480
—
ns
Crystal oscillator startup time (see Figure 13-7)
tOXOV
—
100
ms
Stop recovery startup time (crystal oscillator)
(see Figure 13-6)
tILCH
—
100
ms
tRL
8
—
tCYC
Timer
Resolution(2)
Input capture pulse width (see Figure 13-5)
Input capture pulse period (see Figure 13-5)
tRESL
tTH, tTL
tTLTL
4.0
125
(3)
—
—
—
tCYC
ns
tCYC
Interrupt pulse width low (edge-triggered)
(see Figure 4-2. External Interrupt Timing)
tILIH
125
—
ns
Interrupt pulse period
(see Figure 4-2. External Interrupt Timing)
tILIL
(4)
—
tCYC
tOH, tOL
90
—
ns
RESET pulse width (see Figure 13-7)
OSC1 pulse width
1. V DD = 5.0 Vdc ± 10%, V SS = 0 Vdc; TA = TL to TH
2. Since a 2-bit prescaler in the timer must count four internal cycles (tCYC), this is the limiting minimum factor in determining
the timer resolution.
3. The minimum period, tTLTL, should not be less than the number of cycle times it takes to execute the capture interrupt service routine plus 24 tCYC.
4. The minimum period, tILIL, should not be less than the number of cycle times it takes to execute the interrupt service routine
plus 19 tCYC.
MC68HC705C8A — Rev. 3
MOTOROLA
Technical Data
Electrical Specifications
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Electrical Specifications
13.10 3.3-Volt Control Timing
Freescale Semiconductor, Inc...
Characteristic(1)
Symbol
Min
Max
Unit
Frequency of operation
Crystal option
External clock option
fOSC
—
dc
2.0
2.0
MHz
Internal operating frequency
Crystal (fOSC ÷ 2)
External clock (fOSC ÷ 2)
fOP
—
dc
1.0
1.0
MHz
Cycle time (see Figure 13-7)
tCYC
1000
—
ns
Crystal oscillator startup time (see Figure 13-7)
tOXOV
—
100
ms
Stop recovery startup time (crystal oscillator)
(see Figure 13-6)
tILCH
—
100
ms
tRL
8
—
tCYC
Timer
Resolution(2)
Input capture pulse width (see Figure 13-5)
Input capture pulse period (see Figure 13-5)
tRESL
tTH, tTL
tTLTL
4.0
250
(3)
—
—
—
tCYC
ns
tCYC
Interrupt pulse width low (edge-triggered)
(see Figure 4-2. External Interrupt Timing)
tILIH
250
—
ns
Interrupt pulse period
(see Figure 4-2. External Interrupt Timing)
tILIL
(4)
—
tCYC
tOH, tOL
200
—
ns
RESET pulse width, excluding power-up
(see Figure 13-7)
OSC1 pulse width
1. V DD = 3.3 Vdc ± 0.3 Vdc, VSS = 0 Vdc; TA = TL to TH
2. Since a 2-bit prescaler in the timer must count four internal cycles (tCYC), this is the limiting minimum factor in determining
the timer resolution.
3. The minimum period, tTLTL, should not be less than the number of cycle times it takes to execute the capture interrupt service routine plus 24 tCYC.
4. The minimum period, tILIL, should not be less than the number of cycle times it takes to execute the interrupt service routine
plus 19 tCYC.
tTLTL*
tTH*
tTL*
EXTERNAL SIGNAL
(TCAP PIN 37)
*
Refer to timer resolution data in Figure 13-6 and Figure 13-7.
Figure 13-5. Timer Relationships
Technical Data
182
MC68HC705C8A — Rev. 3
Electrical Specifications
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Electrical Specifications
3.3-Volt Control Timing
(1)
OSC1
RESET
IRQ(2)
Freescale Semiconductor, Inc...
IRQ
(3)
tRL
tILIH
tILCH
4064 tCYC
INTERNAL
CLOCK
INTERNAL
ADDRESS
BUS
1FFE
1FFE
1FFE
1FFE
1FFF(4)
RESET OR INTERRUPT
VECTOR FETCH
Notes:
1. Represents the internal gating of the OSC1 pin
2. IRQ pin edge-sensitive option
3. IRQ pin level and edge-sensitive option
4. RESET vector address shown for timing example
Figure 13-6. Stop Recovery Timing Diagram
MC68HC705C8A — Rev. 3
MOTOROLA
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184
NEW
PCH
INTERNAL
DATA
BUS ***
Technical Data
Electrical Specifications
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NEW
PCL
1FFF
tCYC
OP
CODE
NEW PC
* * *
tRL
1FFE
1FFE
1FFE
PCH
1FFE
Figure 13-7. Power-On Reset and External Reset Timing Diagram
* OSC1 line is not meant to represent frequency. It is only used to represent time.
** Internal timing signal and bus information are not available externally.
*** The next rising edge of the internal processor clock following the rising edge of RESET initiates the reset sequence.
RESET
1FFE
tOXOV
VDD THRESHOLD (1-2 V TYPICAL)
INTERNAL
ADDRESS
BUS **
INTERNAL
PROCESSOR
CLOCK
OSC1*
VDD
tVDDR
Freescale Semiconductor, Inc...
PCL
1FFF
OP
CODE
NEW PC
Freescale Semiconductor, Inc.
Electrical Specifications
MC68HC705C8A — Rev. 3
Freescale Semiconductor, Inc.
Electrical Specifications
5.0-Volt Serial Peripheral Interface (SPI) Timing
13.11 5.0-Volt Serial Peripheral Interface (SPI) Timing
Freescale Semiconductor, Inc...
Number(1)
Characteristic(2)
Symbol
Min
Max
Unit
Operating frequency
Master
Slave
fOP(M)
fOP(S)
dc
dc
0.5
2.1
fOP
MHz
1
Cycle time
Master
Slave
tCYC(M)
tCYC(S)
2.0
480
—
—
tCYC
ns
2
Enable lead time
Master
Slave
tLead(M)
tLead(S)
(3)
ns
240
—
—
Enable lag time
Master
Slave
tLag(M)
tLag(S)
—
—
ns
720
3
(2)
4
Clock (SCK) high time
Master
Slave
tW(SCKH)M
tW(SCKH)S
340
190
—
—
ns
5
Clock (SCK) low time
Master
Slave
tW(SCKL)M
tW(SCKL)S
340
190
—
—
ns
6
Data setup time (inputs)
Master
Slave
tSU(M)
tSU(S)
100
100
—
—
ns
7
Data hold time (inputs)
Master
Slave
tH(M)
tH(S)
100
100
—
—
ns
8
Access time(4)
Slave
tA
0
120
ns
9
Disable time(5)
Slave
tDIS
—
240
ns
10
Data valid time
Master (before capture edge)
Slave (after enable edge)(6)
tV(M)
tV(S)
0.25
—
—
240
tCYC(M)
ns
Continued
MC68HC705C8A — Rev. 3
MOTOROLA
Technical Data
Electrical Specifications
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Electrical Specifications
Freescale Semiconductor, Inc...
Number(1)
Characteristic(2)
Symbol
Min
Max
Unit
tHO(M)
tHO(S)
0.25
0
—
—
tCYC(M)
ns
11
Data hold time (outputs)
Master (after capture edge)
Slave (after enable edge)
12
Rise time(7)
SPI outputs (SCK, MOSI, MISO)
SPI inputs (SCK, MOSI, MISO, SS)
tR(M)
tR(S)
—
—
100
2.0
ns
µs
13
Fall time(8)
SPI outputs (SCK, MOSI, MISO)
SPI inputs (SCK, MOSI, MISO, SS)
tF(M)
tF(S)
—
—
100
2.0
ns
µs
1. Numbers refer to dimensions in Figure 13-8 and Figure 13-9.
2. V DD = 5.0 Vdc ± 10%
3. Signal production depends on software.
4. Time to data active from high-impedance state
5. Hold time to high-impedance state
6. With 200 pF on all SPI pins
7. 20% of V DD to 70% of VDD; CL = 200 pF
8. 70% of V DD to 20% of VDD; CL = 200 pF
Technical Data
186
MC68HC705C8A — Rev. 3
Electrical Specifications
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Electrical Specifications
3.3-Volt Serial Peripheral Interface (SPI) Timing
13.12 3.3-Volt Serial Peripheral Interface (SPI) Timing
Freescale Semiconductor, Inc...
Number(1)
Characteristic (2)
Symbol
Min
Max
Unit
Operating frequency
Master
Slave
fOP(M)
fOP(S)
dc
0.5
2.1
fOP
MHz
1
Cycle time
Master
Slave
tCYC(M)
tCYC(S)
2.0
1
—
—
tCYC
ns
2
Enable lead time
Master
Slave
tLead(M)
tLead(S)
(3)
ns
500
—
—
Enable lag time
Master
Slave
tLag(M)
tLag(S)
—
—
ns
1500
3
(2)
4
Clock (SCK) high time
Master
Slave
tW(SCKH)M
tW(SCKH)S
720
400
—
—
ns
5
Clock (SCK) low time
Master
Slave
tW(SCKL)M
tW(SCKL)S
720
400
—
—
ns
6
Data setup time (inputs)
Master
Slave
tSU(M)
tSU(S)
200
200
—
—
ns
7
Data hold time (inputs)
Master
Slave
tH(M)
tH(S)
200
200
—
—
ns
8
Access time(4)
Slave
tA
0
250
ns
9
Disable time(5)
Slave
tDIS
—
500
ns
10
Data valid time
Master (before capture edge)
Slave (after enable edge)(6)
tV(M)
tV(S)
0.25
—
—
500
tCYC(M)
ns
Continued
MC68HC705C8A — Rev. 3
MOTOROLA
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Electrical Specifications
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Electrical Specifications
Freescale Semiconductor, Inc...
Number(1)
Characteristic (2)
Symbol
Min
Max
Unit
tHO(M)
tHO(S)
0.25
0
—
—
tCYC(M)
ns
11
Data hold time (outputs)
Master (after capture edge)
Slave (after enable edge)
12
Rise time(7)
SPI outputs (SCK, MOSI, MISO)
SPI inputs (SCK, MOSI, MISO, SS)
tR(M)
tR(S)
—
—
200
2.0
ns
µs
13
Fall time (8)
SPI outputs (SCK, MOSI, MISO)
SPI inputs (SCK, MOSI, MISO, SS)
tF(M)
tF(S)
—
—
200
2.0
ns
µs
1. Numbers refer to dimensions in Figure 13-8 and Figure 13-9.
2. V DD = 3.3 Vdc ± 10%
3. Signal production depends on software.
4. Time to data active from high-impedance state
5. Hold time to high-impedance state
6. With 200 pF on all SPI pins
7. 20% of V DD to 70% of VDD; CL = 200 pF
8. 70% of V DD to 20% of VDD; CL = 200 pF
Technical Data
188
MC68HC705C8A — Rev. 3
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Electrical Specifications
3.3-Volt Serial Peripheral Interface (SPI) Timing
SS
INPUT
SS pin of master held high.
12
1
SCK (CPOL = 0)
OUTPUT
13
12
5
NOTE
4
12
SCK (CPOL = 1)
OUTPUT
13
5
NOTE
4
6
Freescale Semiconductor, Inc...
MISO
INPUT
MSB IN
BITS 6–1
10
11
MOSI
OUTPUT
7
LSB IN
10
MASTER MSB OUT
11
BITS 6–1
MASTER LSB OUT
13
12
Note: This first clock edge is generated internally, but is not seen at the SCK pin.
a) SPI Master Timing (CPHA = 0)
SS
INPUT
SS pin of master held high.
1
SCK (CPOL = 0)
OUTPUT
13
12
5
NOTE
4
12
SCK (CPOL = 1)
OUTPUT
13
5
NOTE
4
6
MISO
INPUT
MSB IN
10
BITS 6–1
11
MOSI
OUTPUT
MASTER MSB OUT
7
LSB IN
10
BITS 6–1
13
11
MASTER LSB OUT
12
Note: This last clock edge is generated internally, but is not seen at the SCK pin.
b) SPI Master Timing (CPHA = 1)
Figure 13-8. SPI Master Timing
MC68HC705C8A — Rev. 3
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Electrical Specifications
SS
INPUT
1
SCK (CPOL = 0)
(INPUT
13
12
12
13
3
11
5
4
2
SCK (CPOL = 1)
INPUT
5
4
8
Freescale Semiconductor, Inc...
MISO
INPUT
SLAVE
MSB OUT
6
MOSI
OUTPUT
BITS 6–1
7
SLAVE LSB OUT
NOTE
11
10
MSB IN
9
BITS 6–1
LSB IN
Note: Not defined, but normally MSB of character just received
a) SPI Slave Timing (CPHA = 0)
SS
INPUT
13
1
SCK (CPOL = 0)
INPUT
12
5
4
2
3
SCK (CPOL = 1)
INPUT
8
MISO
OUTPUT
MOSI
INPUT
5
4
10
NOTE
12
SLAVE
MSB OUT
6
7
13
BITS 6–1
10
MSB IN
9
SLAVE LSB OUT
11
BITS 6–1
LSB IN
Note: Not defined, but normally LSB of character previously transmitted
b) SPI Slave Timing (CPHA = 1)
Figure 13-9. SPI Slave Timing
Technical Data
190
MC68HC705C8A — Rev. 3
Electrical Specifications
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Technical Data — MC68HC705C8A
Section 14. Mechanical Specifications
Freescale Semiconductor, Inc...
14.1 Contents
14.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
14.3
40-Pin Plastic Dual In-Line Package (PDIP). . . . . . . . . . . . . .192
14.4
40-Pin Ceramic Dual In-Line Package (Cerdip) . . . . . . . . . . . 193
14.5
44-Lead Plastic-Leaded Chip Carrier (PLCC) . . . . . . . . . . . . 194
14.6
44-Lead Ceramic-Leaded Chip Carrier (CLCC) . . . . . . . . . . . 195
14.7
44-Pin Quad Flat Pack (QFP). . . . . . . . . . . . . . . . . . . . . . . . . 196
14.8
42-Pin Shrink Dual In-Line Package (SDIP) . . . . . . . . . . . . . .197
14.2 Introduction
Package dimensions available at the time of this publication for the
MC68HC705C8A are provided in this section. The packages are:
•
40-pin plastic dual in-line package (PDIP)
•
40-pin ceramic dual-in-line package (cerdip)
•
44-lead plastic-leaded chip carrier (PLCC)
•
44-lead ceramic-leaded chip carrier (CLCC)
•
44-pin quad flat pack (QFP)
•
42-pin shrink dual in-line package (SDIP)
MC68HC705C8A — Rev. 3
MOTOROLA
Technical Data
Mechanical Specifications
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Mechanical Specifications
14.3 40-Pin Plastic Dual In-Line Package (PDIP)
40
21
DIM
A
B
C
D
F
G
H
J
K
L
M
N
B
1
20
L
A
Freescale Semiconductor, Inc...
C
N
J
H
G
F
D
K
SEATING
PLANE
MILLIMETERS
MIN
MAX
51.69
52.45
13.72
14.22
3.94
5.08
0.36
0.56
1.02
1.52
2.54 BSC
1.65
2.16
0.20
0.38
2.92
3.43
15.24 BSC
0°
1°
0.51
1.02
INCHES
MIN
MAX
2.035
2.065
0.540
0.560
0.155
0.200
0.014
0.022
0.040
0.060
0.100 BSC
0.065
0.085
0.008
0.015
0.115
0.135
0.600 BSC
0°
1°
0.020
0.040
M
NOTES:
1.POSITION TOLERANCE OF LEADS (D), SHALL
BEWITHIN 0.25 (0.010) AT MAXIMUM MATERIAL
CONDITIONS, IN RELATION TO SEATING PLANE
AND EACH OTHER.
2.DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3.DIMENSION B DOES NOT INCLUDE MOLD FLASH.
Figure 14-1. MC68HC705C8AP Package Dimensions (Case #711)
Technical Data
192
MC68HC705C8A — Rev. 3
Mechanical Specifications
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Mechanical Specifications
40-Pin Ceramic Dual In-Line Package (Cerdip)
14.4 40-Pin Ceramic Dual In-Line Package (Cerdip)
40
21
B
1
20
A
L
Freescale Semiconductor, Inc...
N
C
T
K
SEATING
PLANE
DATUM
PLANE
G
DIM
J
M
F
D 40 PL
φ 0.25(0.010) M T A M
A
B
C
D
F
G
J
K
L
M
N
INCHES
MILLIMETERS
MIN
MAX
MIN MAX
2.020 2.096 51.31 53.23
0.500 0.610 12.70 15.94
0.160 0.240 4.06 6.09
0.015 0.022 0.38 0.55
0.050 0.065 1.27 1.65
0.100 BSC
2.54 BSC
0.008 0.012 0.20 0.30
0.125 0.160 3.17 4.06
0.600 BSC
15.24 BSC
0°
15°
0°
15°
0.020 0.050 0.51 1.27
Figure 14-2. MC68HC705C8AS Package Dimensions (Case #734A)
MC68HC705C8A — Rev. 3
MOTOROLA
Technical Data
Mechanical Specifications
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Mechanical Specifications
14.5 44-Lead Plastic-Leaded Chip Carrier (PLCC)
-N-
Y BRK
0.007(0.180) M T
B
D
L-M S
0.007(0.180) M T
U
N S
L-M
S
N S
Z
-M-
Freescale Semiconductor, Inc...
-L-
V
44
X
D
W
1
G1
0.010 (0.25) S T
VIEW D-D
A
0.007(0.180) M T
L-M
S
N S
R
0.007(0.180) M T
L-M
S
N S
0.007(0.180) M T
H
L-M S
L-M S
N S
N S
Z
J
K1
E
0.004 (0.10)
G
C
-TG1
0.010 (0.25) S T
L-M S
N S
K
SEATING
PLANE
F
VIEW S
0.007(0.180) M T
L-M S
N S
VIEW S
NOTES:
1. DATUMS -L-, -M-, AND -N- ARE DETERMINED
WHERE TOP OF LEAD SHOLDERS EXITS
PLASTIC BODY AT MOLD PARTING LINE.
2. DIMENSION G1, TRUE POSITION TO BE
MEASURED AT DATUM -T-, SEATING PLANE.
3. DIMENSION R AND U DO NOT INCLUDE MOLD
FLASH. ALLOWABLE MOLD FLASH IS 0.010
(0.25) PER SIDE.
4. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
5. CONTROLLING DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN
THE PACKAGE BOTTOM BY UP TO 0.012
(0.300). DIMENSIONS R AND U ARE DETERMINED
AT THE OUTERMOST EXTREMES OF THE
PLASTIC BODY EXCLUSIVE OF THE MOLD
FLASH, TIE BAR BURRS, GATE BURRS AND
INTERLEAD FLASH, BUT INCLUDING ANY
MISMATCH BETWEEN THE TOP AND BOTTOM
OF THE PLASTIC BODY.
7. DIMINSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTUSION(S) SHALL NOT CAUSE THE H
DIMINSION TO BE GREATER THAN 0.037
(0.940198). THE DAMBAR INTRUSION(S) SHALL
NOT CAUSE THE H DIMINISION TO SMALLER
THAN 0.025 (0.635).
INCHES
DIM
A
B
C
E
F
G
H
J
K
R
U
V
W
X
Y
Z
G1
K1
MIN
MAX
0.685
0.695
0.685
0.695
0.165
0.180
0.090
0.110
0.013
0.019
0.050 BSC
0.026
0.032
0.020
0.025
0.650
0.656
0.650
0.656
0.042
0.048
0.042
0.048
0.042
0.056
0.020
2°
10°
0.610
0.630
0.040
MILLIMETERS
MIN
MAX
17.40
17.65
17.40
17.65
4.20
4.57
2.29
2.79
0.33
0.48
1.27 BSC
0.66
0.81
0.51
0.64
16.51
16.66
16.51
16.66
1.07
1.21
1.07
1.21
1.07
1.42
0.50
2°
10°
15.50
16.00
1.02
Figure 14-3. MC68HC705C8AFN Package Dimensions (Case #777)
Technical Data
194
MC68HC705C8A — Rev. 3
Mechanical Specifications
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Mechanical Specifications
44-Lead Ceramic-Leaded Chip Carrier (CLCC)
14.6 44-Lead Ceramic-Leaded Chip Carrier (CLCC)
0.18 (0.007) M T N S -P S
B
-N-
Y BRK
U
L S
0.18 (0.007) M T N S -P S
L S
D
Freescale Semiconductor, Inc...
-L-
W
44
D
1
DETAIL D-D
S
-P-
G1
0.25 (0.010) M T N S -P S
L S
0.20 (0.008) M T L M N M -P M
V
A
0.18 (0.007) M T L S N S -P S
R
0.18 (0.007) M T L S N S -P S
C
NOTES:
1. DATUMS -L-, -N-, AND -P- DETERMINED
WHERE TOP OF LEAD SHOULDER EXIT
BODY.
2. DIMINSION G1, TRUE POSITION TO BE
MEASURED AT DATUM -T-, SEATING
PLANE.
3. DIMINSIONS R AND U DO NOT INCLUDE
GLASS MENISCUS. ALLOWABLE GLASS
RUNOUT IS 0.25 (0.010) PER SIDE.
4. DIMINSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
E
J
G
DETAIL S
G1
0.10 (0.004)
-T-
SEATING
PLANE
0.25 (0.010) S T L S N S -P S
0.18 (0.007) M T L S N S -P S
H
0.18 (0.007) M T N S -P S L S
K1
DIM
A
B
C
E
F
G
H
J
K
R
S
U
V
W
Y
G1
K1
MILLIMETERS
MIN
MAX
17.40 17.65
17.40 17.65
4.20
4.57
2.29
2.79
0.33
0.48
1.27 BSC
0.66
0.81
0.51
--0.64
--16.51 16.66
6.94
7.26
16.51 16.66
1.07
1.21
1.07
1.21
--0.50
14.99 16.00
1.02
---
INCHES
MIN
MAX
0.685
0.695
0.685
0.695
0.165
0.180
0.090
0.110
0.013
0.019
0.050 BSC
0.026
0.032
0.020
--0.025
--0.650
0.656
0.273
0.286
0.650
0.656
0.042
0.048
0.042
0.048
--0.020
0.590
0.630
0.040
---
K
F
0.18 (0.007) M T L S N S -P S
0.18 (0.007) M T N S -P S L S
DETAIL S
Figure 14-4. MC68HC705C8AFS Package Dimensions (Case #777B)
MC68HC705C8A — Rev. 3
MOTOROLA
Technical Data
Mechanical Specifications
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Mechanical Specifications
14.7 44-Pin Quad Flat Pack (QFP)
B
L
B
33
23
44
S
D
S
0.20
V
(0.008) M
H A-B
S
S
0.05 (0.002) A-B
DETAIL A
B
0.20 (0.008) M C A-B
-B-
L
Freescale Semiconductor, Inc...
-A-
D
22
34
11
S
D
S
S
D
S
0.05 (0.002) A-B
S
0.20 (0.008) M H A-B
M
DETAIL C
C E
-H-
-CSEATING
PLANE
DATUM
PLANE
0.01 (0.004)
H
G
M
M
T
DATUM
PLANE -H-
R
K
W
X
DETAIL C
Q
F
BASE METAL
J
N
S
D
S
SECTION B-B
-DA
0.20 (0.008) M C A-B
DETAIL A
D
0.20 (0.008) M C A-B
12
1
-A-, -B-, -D-
MILLIMETERS
DIM MIN
MAX
A
9.90 10.10
B
9.90 10.10
C
2.10
2.45
D
0.30
0.45
E
2.00
2.10
F
0.30
0.40
G
0.80 BSC
H
--0.25
J 0.013
0.23
K
0.65
0.95
L
8.00 REF
M
5°
10 °
N
0.13
0.17
Q
0°
7°
R
0.13
0.30
S 12.95 13.45
T
0.13
--U
0°
--V 12.95 13.45
W
0.40
--X
1.6 REF
NOTES:
1. 1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. 2. CONTROLLING DIMENSION: MILLIMETER.
3. 3. DATUM PLANE -H- IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD WHERE
THE LEAD EXITS THE PLASTIC BODY AT THE
BOTTOM OF THE PARTING LINE.
4. 4. DATUMS -A-, -B- AND -D- TO BE DETERMINED AT
DATUM PLANE -H-.
5. 5. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE -C-.
6. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS 0.25
(0.010) PER SIDE. DIMENSIONS A AND B DO
INCLUDE MOLD MISMATCH AND ARE DETERMINED
AT DATUM PLANE -H-.
7. 7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE D DIMENSION AT MAXIMUM
MATERIAL CONDITION. DAMBAR CANNOT BE
LOCATED ON THE LOWER RADIUS OR THE FOOT.
INCHES
MIN MAX
0.390 0.398
0.390 0.398
0.083 0.096
0.012 0.018
0.079 0.083
0.012 0.016
0.031 BSC
--- 0.010
0.005 0.009
0.026 0.037
0.315 REF
5°
10 °
0.005 0.007
0°
7°
0.005 0.012
0.510 0.530
0.005
--0°
--0.510 0.530
0.016
--0.063 REF
Figure 14-5. MC68HC705C8AFB Package Dimensions (Case #824A)
Technical Data
196
MC68HC705C8A — Rev. 3
Mechanical Specifications
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Mechanical Specifications
42-Pin Shrink Dual In-Line Package (SDIP)
14.8 42-Pin Shrink Dual In-Line Package (SDIP)
-A42
NOTES:
1. DIMENSIONS AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSIONS A AND B DO NOT INCLUDE MOLD
FLASH. MAXIMUM MOLD FLASH 0.25 (0.010).
22
-B1
21
L
H
C
Freescale Semiconductor, Inc...
DIM
A
B
C
D
F
G
H
J
K
L
M
N
-TSEATING
PLANE
0.25 (0.010)
N
G
F
D 42 PL
K
M
T A
S
M
J 42 PL
0.25 (0.010)
M
T B
INCHES
MIN
MAX
1.435 1.465
0.540 0.560
0.155 0.200
0.014 0.022
0.032 0.046
0.070 BSC
0.300 BSC
0.008 0.015
0.115 0.135
0.600 BSC
0°
15°
0.020 0.040
MILLIMETERS
MIN
MAX
36.45 37.21
13.72 14.22
3.94
5.08
0.36
0.56
0.81
1.17
1.778 BSC
7.62 BSC
0.20
0.38
2.92
3.43
15.24 BSC
0°
15°
0.51
1.02
S
Figure 14-6. MC68HC705C8AB Package Dimensions (Case #858)
MC68HC705C8A — Rev. 3
MOTOROLA
Technical Data
Mechanical Specifications
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Mechanical Specifications
Technical Data
198
MC68HC705C8A — Rev. 3
Mechanical Specifications
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Technical Data — MC68HC705C8A
Section 15. Ordering Information
Freescale Semiconductor, Inc...
15.1 Contents
15.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
15.3
MCU Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
15.2 Introduction
This section contains ordering information for the available package
types.
15.3 MCU Order Numbers
Table 15-1 lists the MC order numbers.
Table 15-1. MC68HC705C8A Order Numbers
Package Type
Temperature Range
Order Number
40-pin plastic dual in-line package (PDIP)
–40°C to +85°C
MC68HC705C8AC (1)P(2)
44-lead plastic-leaded chip carrier (PLCC)
–40°C to +85°C
MC68HC705C8ACFN(3)
44-lead ceramic-leaded chip carrier (CLCC)
–40°C to +85°C
MC68HC705C8ACFS(4)
40-pin windowed ceramic DIP (Cerdip)
–40°C to +85°C
MC68HC705C8ACS(5)
44-pin quad flat pack (QFP)
–40°C to +85°C
MC68HC705C8ACFB(6)
42-pin shrink dual in-line package (SDIP)
–40°C to +85°C
MC68HC705C8ACB(7)
1. C = Extended temperature range (–40°C to +85°C)
2. P = Plastic dual in-line package (PDIP)
3. FN = Plastic-leaded chip carrier (PLCC)
4. FS = Ceramic-leaded chip carrier (CLCC)
5. S = Windowed ceramic dual in-line package (Cerdip)
6. FB = Quad flat pack (QFP)
7. B = Shrink dual in-line package (SDIP)
MC68HC705C8A — Rev. 3
MOTOROLA
Technical Data
Ordering Information
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Ordering Information
Technical Data
200
MC68HC705C8A — Rev. 3
Ordering Information
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Technical Data — MC68HC705C8A
Appendix A. MC68HSC705C8A
Freescale Semiconductor, Inc...
A.1 Contents
A.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
A.3
5.0-Volt High-Speed DC Electrical Characteristics. . . . . . . . .202
A.4
3.3-Volt High-Speed DC Electrical Characteristics . . . . . . . . 203
A.5
5.0-Volt High-Speed Control Timing . . . . . . . . . . . . . . . . . . . . 204
A.6
3.3-Volt High-Speed Control Timing . . . . . . . . . . . . . . . . . . . . 204
A.7
5.0-Volt High-Speed SPI Timing . . . . . . . . . . . . . . . . . . . . . . 205
A.8
3.3-Volt High-Speed SPI Timing. . . . . . . . . . . . . . . . . . . . . . .207
A.9
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
A.2 Introduction
The MC68HSC705C8A is an enhanced, high-speed version of the
MC68HC705C8A, featuring a 4-MHz bus speed.
The data in this document, MC68HC705C8A Technical Data Rev. 3,
applies to the MC68HSC705C8A with the exceptions given in this
appendix.
The computer operating properly (COP) mode bits (CM1 and CM0 in the
COP control register) select the timeout period of the programmable
COP watchdog, as shown in Table A-1. See Figure 5-3.
Programmable COP Control Register (COPCR).
MC68HC705C8A — Rev. 3
MOTOROLA
Technical Data
MC68HSC705C8A
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MC68HSC705C8A
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Table A-1. Programmable COP Timeout Period Selection
CM1:CM0
COP
Timeout
Rate
00
Programmable COP Timeout Period
fOSC = 8.0 MHz
fOP = 4.0 MHz
fOSC = 4.0 MHz
fOP = 2.0 MHz
fOSC = 3.5795 MHz
fOP = 1.7897 MHz
fOSC = 2.0 MHz
fOP = 1.0 MHz
fOP ÷ 215
8.192 ms
16.38 ms
18.31 ms
32.77 ms
01
fOP ÷ 217
32.77 ms
65.54 ms
73.24 ms
131.07 ms
10
fOP ÷ 219
131.07 ms
262.14 ms
292.95 ms
524.29 ms
11
fOP ÷ ÷221
524.29 ms
1.048 s
1.172 s
2.097 s
A.3 5.0-Volt High-Speed DC Electrical Characteristics
Characteristic(1)
Typ(2)
Max
—
—
—
—
—
—
—
—
0.4
—
—
0.4
—
—
5.92
2.27
14
7.0
mA
mA
—
—
5
2.0
50
50
µA
µA
Symbol
Min
Output high voltage
ILoad = –0.8 mA
PA7–PA0, PB7–PB0, PC6–PC0, TCMP
ILoad = –1.6 mA
PD4–PD1
ILoad = –5.0 mA
PC7
VOH
VDD – 0.8
Output low voltage
ILoad = 1.6 mA
PA7–PA0, PB7–PB0, PC6–PC0, PD4–PD1
ILoad = 20 mA
PC7
VOL
Supply current(3)
Run(4)
Wait(5)
Stop(6)
25°C
–40°C to +85°C
IDD
Unit
V
V
1. VDD = 5 V ± 10%; VSS = 0 Vdc, TA = TL to TH, unless otherwise noted
2. Typical values reflect average measurements at midpoint of voltage range at 25°C.
3. IDD measured with port B pullup devices disabled.
4. Run (operating) IDD measured using external square wave clock source (fOSC = 8.0 MHz). All inputs 0.2 V from rail. No dc
loads. Less than 50 pF on all outputs. CL = 20 pF on OSC2. OSC2 capacitance linearly affects run IDD.
5. Wait IDD measured using external square wave clock source (fOSC = 8.0 MHz). All inputs 0.2 V from rail. No dc loads. Less
than 50 pF on all outputs. CL = 20 pF on OSC2. VIL = 0.2 V, VIH = VDD – 0.2 V. All ports configured as inputs. SPI and SCI
disabled. If SPI and SCI enabled, add 10% current draw. OSC2 capacitance linearly affects wait IDD.
6. Stop IDD measured with OSC1 = V DD. All ports configured as inputs. VIL = 0.2 V, VIH = VDD – 0.2 V.
Technical Data
202
MC68HC705C8A — Rev. 3
MC68HSC705C8A
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MC68HSC705C8A
A.4 3.3-Volt High-Speed DC Electrical Characteristics
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Characteristic(1)
Typ(2)
Max
—
—
—
—
—
—
—
—
0.3
—
—
0.3
—
—
—
1.91
0.915
2.0
6.0
2.0
20
Symbol
Min
Output high voltage
ILoad = –0.2 mA
PA7–PA0, PB7–PB0, PC6–PC0, TCMP
ILoad = –0.4 mA
PD4–PD1
ILoad = –1.5 mA
PC7
VOH
VDD – 0.3
Output low voltage
ILoad = 0.4 mA
PA7–PA0, PB7–PB0, PC6–PC0, PD4–PD1
ILoad = 6.0 mA
PC7
VOL
Supply current(3)
Run(4)
Wait(5)
Stop(6)
IDD
Unit
V
V
mA
mA
µA
1. VDD = 3.3 V ± 10%; VSS = 0 Vdc, TA = TL to TH, unless otherwise noted
2. Typical values reflect average measurements at midpoint of voltage range at 25°C.
3. IDD measured with port B pullup devices disabled.
4. Run (operating) IDD measured using external square wave clock source (fOSC = 4.2 MHz). All inputs 0.2 V from rail. No dc
loads. Less than 50 pF on all outputs. CL = 20 pF on OSC2. OSC2 capacitance linearly affects run IDD.
5. Wait IDD measured using external square wave clock source (fOSC = 4.2 MHz). All inputs 0.2 V from rail. No dc loads. Less
than 50 pF on all outputs. C L = 20 pF on OSC2. V IL = 0.2 V, VIH = VDD – 0.2 V. All ports configured as inputs. SPI and SCI
disabled. If SPI and SCI enabled, add 10% current draw. OSC2 capacitance linearly affects wait IDD.
6. Stop IDD measured with OSC1 = V DD. All ports configured as inputs. VIL = 0.2 V; VIH = VDD – 0.2 V.
MC68HC705C8A — Rev. 3
MOTOROLA
Technical Data
MC68HSC705C8A
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MC68HSC705C8A
A.5 5.0-Volt High-Speed Control Timing
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Characteristic(1)
Symbol
Min
Max
Unit
Oscillator frequency
Crystal oscillator
External clock
fOSC
—
dc
8.0
8.0
MHz
Internal operating frequency (fOSC ÷ 2)
Crystal oscillator
External clock
fOP
—
dc
4.0
4.0
MHz
Cycle time
tCYC
250
—
ns
tTH, tTL
65
—
ns
tILIH
65
—
ns
tOH, tOL
45
—
ns
Symbol
Min
Max
Unit
Oscillator frequency
Crystal oscillator
External clock
fOSC
—
dc
4.0
4.0
MHz
Internal operating frequency (fOSC ÷ 2)
Crystal oscillator
External clock
fOP
—
dc
2.0
2.0
MHz
Cycle time
tCYC
476
—
ns
tTH, tTL
125
—
ns
tILIH
125
—
ns
tOH, tOL
90
—
ns
Input capture pulse width
Interrupt pulse width low (edge-triggered)
OSC1 pulse width
1. VDD = 5 V ± 10%; VSS = 0 Vdc, TA = TL to TH, unless otherwise noted
A.6 3.3-Volt High-Speed Control Timing
Characteristic(1)
Input capture pulse width
Interrupt pulse width low (edge-triggered)
OSC1 pulse width
1. VDD = 3.3 V ± 10%; VSS = 0 Vdc, TA = TL to TH, unless otherwise noted
Technical Data
204
MC68HC705C8A — Rev. 3
MC68HSC705C8A
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MC68HSC705C8A
A.7 5.0-Volt High-Speed SPI Timing
Diagram
Number(1)
Characteristic(2)
Freescale Semiconductor, Inc...
Operating frequency
Master
Slave
Symbol
Min
Max
Unit
fOP(S)
fOP(S)
dc
dc
0.5
4.0
fOP
MHz
1
Cycle time
Master
Slave
tCYC(M)
tCYC(S)
2.0
250
—
—
tCYC
ns
2
Enable lead time
Master
Slave
tLead(M)
tLead(S)
Note (3)
125
—
—
ns
3
Enable lag time
Master
Slave
tLag(M)
tLag(S)
Note(2)
375
—
—
ns
4
Clock (SCK) high time
Master
Slave
tW(SCKH)M
tW(SCKH)S
170
95
—
—
ns
5
Clock (SCK) low time
Master
Slave
tW(SCKL)M
tW(SCKL)S
170
95
—
—
ns
6
Data setup time (inputs)
Master
Slave
tSU(M)
tSU(S)
50
50
—
—
ns
7
Data hold time (inputs)
Master
Slave
tH(M)
tH(S)
50
50
—
—
ns
8
Access time(4)
Slave
tA
0
60
ns
9
Disable time(5)
Slave
tDIS
—
120
ns
tV(M)
tV(S)
0.25
—
—
120
tCYC(M)
ns
10
Data valid time
Master (before capture edge)
(6)
Slave (after enable edge)
Continued
MC68HC705C8A — Rev. 3
MOTOROLA
Technical Data
MC68HSC705C8A
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Diagram
Number(1)
Characteristic(2)
Symbol
Min
Max
Unit
tHO(M)
tHO(S)
0.25
0
—
—
tCYC(M)
ns
11
Data hold time (outputs)
Master (after capture edge)
Slave (after enable edge)
12
Rise time(7)
SPI outputs (SCK, MOSI, MISO)
SPI inputs (SCK, MOSI, MISO, SS)
tRM
tRS
—
—
50
2.0
ns
µs
13
Fall time(8)
SPI outputs (SCK, MOSI, MISO)
SPI inputs (SCK, MOSI, MISO, SS)
tFM
tFS
—
—
50
2.0
ns
µs
1. Diagram numbers refer to dimensions in Figure 13-8. SPI Master Timing and Figure 13-9. SPI Slave Timing.
2. VDD = 5 V ± 10%; VSS = 0 Vdc, TA = TL to TH, unless otherwise noted
3. Signal production depends on software.
4. Time to data active from high-impedance state
5. Hold time to high-impedance state
6. With 200 pF on all SPI pins.
7. 20% of VDD to 70% of VDD; CL = 200 pF
8. 70% of VDD to 20% of VDD; CL = 200 pF
Technical Data
206
MC68HC705C8A — Rev. 3
MC68HSC705C8A
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MC68HSC705C8A
A.8 3.3-Volt High-Speed SPI Timing
Diagram
Number(1)
Characteristic(2)
Freescale Semiconductor, Inc...
Operating frequency
Master
Slave
Symbol
Min
Max
Unit
fOP(S)
fOP(S)
dc
dc
0.5
2.1
fOP
MHz
1
Cycle time
Master
Slave
tCYC(M)
tCYC(S)
2.0
480
—
—
tCYC
ns
2
Enable lead time
Master
Slave
tLead(M)
tLead(S)
Note (3)
240
—
—
ns
3
Enable lag time
Master
Slave
tLag(M)
tLag(S)
Note(2)
720
—
—
ns
4
Clock (SCK) high time
Master
Slave
tW(SCKH)M
tW(SCKH)S
340
190
—
—
ns
5
Clock (SCK) low time
Master
Slave
tW(SCKL)M
tW(SCKL)S
340
190
—
—
ns
6
Data setup time (inputs)
Master
Slave
tSU(M)
tSU(S)
100
100
—
—
ns
7
Data hold time (inputs)
Master
Slave
tH(M)
tH(S)
100
100
—
—
ns
8
Access time(4)
Slave
tA
0
120
9
Disable time(5)
Slave
tDIS
—
240
10
Data valid time
Master (before capture edge)
Slave (after enable edge)(6)
tV(M)
tV(S)
0.25
—
—
240
ns
ns
tCYC(M)
ns
Continued
MC68HC705C8A — Rev. 3
MOTOROLA
Technical Data
MC68HSC705C8A
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MC68HSC705C8A
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Diagram
Number(1)
Characteristic(2)
Symbol
Min
Max
Unit
tHO(M)
tHO(S)
0.25
0
—
—
tCYC(M)
ns
11
Data hold time (outputs)
Master (after capture edge)
Slave (after enable edge)
12
Rise time(7)
SPI outputs (SCK, MOSI, MISO)
SPI inputs (SCK, MOSI, MISO, SS)
tRM
tRS
—
—
100
2.0
ns
µs
13
Fall time(8)
SPI outputs (SCK, MOSI, MISO)
SPI inputs (SCK, MOSI, MISO, SS)
tFM
tFS
—
—
100
2.0
ns
µs
1. Diagram numbers refer to dimensions in Figure 13-8. SPI Master Timing and Figure 13-9. SPI Slave Timing.
2. VDD = 3.3 V ± 10%; VSS = 0 Vdc, TA = TL to TH, unless otherwise noted
3. Signal production depends on software.
4. Time to data active from high-impedance state
5. Hold time to high-impedance state
6. With 200 pF on all SPI pins
7. 20% of VDD to 70% of VDD; CL = 200 pF
8. 70% of VDD to 20% of VDD; CL = 200 pF
Technical Data
208
MC68HC705C8A — Rev. 3
MC68HSC705C8A
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MC68HSC705C8A
A.9 Ordering Information
Table A-2 provides ordering information for the MC68HSC705C8A.
Table A-2. MC68HSC705C8A Order Numbers
Freescale Semiconductor, Inc...
Package Type
Temperature Range
Order Number
40-pin plastic dual in-line package (PDIP)
–40°C to +85°C
MC68HSC705C8AC(1)P(2)
44-lead plastic-leaded chip carrier (PLCC)
–40°C to +85°C
MC68HSC705C8ACFN (3)
44-lead ceramic-leaded chip carrier (CLCC)
–40°C to +85°C
MC68HSC705C8ACFS (4)
40-pin ceramic DIP (cerdip)
–40°C to +85°C
MC68HSC705C8ACS(5)
44-pin quad flat pack (QFP)
–40°C to +85°C
MC68HSC705C8ACFB (6)
42-pin shrink dual in-line package (SDIP)
–40°C to +85°C
MC68HSC705C8ACB(7)
1. C = Extended temperature range (–40°C to +85°C)
2. P = Plastic dual in-line package (PDIP)
3. FN = Plastic-leaded chip carrier (PLCC)
4. FS = Ceramic-leaded chip carrier (CLCC)
5. S = Windowed ceramic dual in-line package (cerdip)
6. FB = Quad flat pack (QFP)
7. B = Shrink dual in-line package (SDIP)
MC68HC705C8A — Rev. 3
MOTOROLA
Technical Data
MC68HSC705C8A
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MC68HSC705C8A
Technical Data
210
MC68HC705C8A — Rev. 3
MC68HSC705C8A
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Technical Data — MC68HC705C8A
Index
A
accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45, 154, 155, 158
Freescale Semiconductor, Inc...
addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
arithmetic/logic unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
B
block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
bootloader ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
C
C bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
condition code register (CCR) . . . . . . . . . . . . . . . . . . . . . . . . . . 47, 160
COP watchdog (non-programmable)
diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
in stop mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
timeout period formula . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
when clock monitor enabled. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
67
73
73
66
66
73
COP watchdog (programmable)
COP control register (COPCR) . . . . . . . . . . . . . . . . . . . . . . . . . .
COP reset register (COPRST) . . . . . . . . . . . . . . . . . . . . . . . . . . .
diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
in stop mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
timeout period selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
64
64
63
71
71
63
66
MC68HC705C8A — Rev. 3
MOTOROLA
Technical Data
Index
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Index
CPU
instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
instruction types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
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CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155, 158, 163
accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154, 155, 158
condition code register (CCR) . . . . . . . . . . . . . . . . . . . . . . . . . . 160
index register (X) . . . . . . . . . . . . . . . . . . . . . . . . 154, 155, 156, 158
program counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157, 160
D
data-retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
E
electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . .
power considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
171
181
176
174
electrical specifications (high-speed part)
control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . .
ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
204
202
209
205
EPROM/OTPROM (PROM) . . . . . . . . . . . . . . . . . . . . . . . . . . . 37, 103
control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
EPROM erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
mask option register 1 (MOR1) . . . . . . . . . . . . . . . . . . . . . . . . . 117
mask option register 2 (MOR2) . . . . . . . . . . . . . . . . . . . . . . . . . 118
option register (option) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
preprogramming steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
program register (PROG). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
MC68HC05PGMR programmer board . . . . . . . . . . . . . . . . . 104
programming circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Technical Data
212
MC68HC705C8A — Rev. 3
Index
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Index
programming flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
programming routines . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108, 111
F
features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
H
high-speed part (MC68HSC705C8A) . . . . . . . . . . . . . . . . . . . . . . . 201
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I
I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36, 77
data direction register A (DDRA) . . . . . . . . . . . . . . . . . . . . . . . . . 79
data direction register B (DDRB) . . . . . . . . . . . . . . . . . . . . . . . . . 82
data direction register C (DDRC) . . . . . . . . . . . . . . . . . . . . . . . . . 86
port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
port A data register (PORTA). . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
port A I/O logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
port A pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
port B data register (PORTB). . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
port B I/O logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
port B pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
port C data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
port C I/O logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
port C pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
I/O bits
C bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
I/O register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
index register (X) . . . . . . . . . . . . . . . . . . . . . . . . 45, 154, 155, 156, 158
instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
instruction types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MC68HC705C8A — Rev. 3
MOTOROLA
153
154
164
157
170
Technical Data
Index
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Index
interrupt processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
reset/interrupt vector addresses. . . . . . . . . . . . . . . . . . . . . . . . . .
stacking order. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
57
59
57
58
interrupts
external interrupt (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
internal function diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .
timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
masking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
port B interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
enabling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
port B I/O logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SCI interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
software interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
timer interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
51
52
52
50
50
53
53
54
55
50
49
56
55
IRQ pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
J
junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
L
low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
data-retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stop mode
non-programmable COP in stop mode flowchart . . . . . . . . . .
non-programmable COP watchdog in stop mode. . . . . . . . . .
programmable COP in stop mode flowchart. . . . . . . . . . . . . .
programmable COP watchdog in stop mode . . . . . . . . . . . . .
SCI during stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI during stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stop/wait mode function flowchart. . . . . . . . . . . . . . . . . . . . . .
wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
non-programmable COP watchdog in wait mode . . . . . . . . . .
programmable COP watchdog in wait mode . . . . . . . . . . . . .
Technical Data
214
69
75
74
73
72
71
71
71
70
73
75
75
MC68HC705C8A — Rev. 3
Index
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Go to: www.freescale.com
Freescale Semiconductor, Inc.
Index
M
mask option registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23, 117, 118
MC68HSC705C8A (high-speed part) . . . . . . . . . . . . . . . . . . . . . . .
control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . .
ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
programmable COP timeout period selection . . . . . . . . . . . . . .
SPI timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
201
204
202
209
202
205
Freescale Semiconductor, Inc...
mechanical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
memory
bootloader ROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
I/O register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35, 38
PROM (EPROM/OTPROM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35, 38
O
on-chip memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
opcode map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
option register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
OSC1 pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
OSC2 pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
oscillator
ceramic resonator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
crystal resonator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
external clock signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
MC68HC705C8A — Rev. 3
MOTOROLA
Technical Data
Index
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Index
P
pin assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33, 78
data direction register A (DDRA) . . . . . . . . . . . . . . . . . . . . . . . . . 79
port A data register (PORT A) . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
port A I/O logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
port A pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Freescale Semiconductor, Inc...
port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33, 81
data direction register B (DDRB) . . . . . . . . . . . . . . . . . . . . . . . . . 82
port B data register (PORTB). . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
port B I/O logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
port B pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
port C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33, 85
data direction register C (DDRC) . . . . . . . . . . . . . . . . . . . . . . . . . 86
port C data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
port C I/O logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
port C pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
port D. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33, 88
power dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
program counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46, 157, 160
programmable options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
programming model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
PROM (EPROM/OTPROM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
R
RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
registers
I/O register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
reset and interrupt processing flowchart . . . . . . . . . . . . . . . . . . . . . . 59
RESET pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
resets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
clock monitor reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65, 67
with STOP instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Technical Data
216
MC68HC705C8A — Rev. 3
Index
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Index
COP watchdog resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
non-programmable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
non-programmable COP watchdog diagram . . . . . . . . . . . . .
programmable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
programmable COP watchdog diagram . . . . . . . . . . . . . . . . .
enabling both programmable and non-programmable COPs . . .
external reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
power-on reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
reset sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
62
66
67
63
63
65
62
62
61
Freescale Semiconductor, Inc...
ROM (bootloader) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
S
serial communications interface (SCI). . . . . . . . . . . . . . . . . . . . . . . 121
baud rate generator clock prescaling . . . . . . . . . . . . . . . . . . . . . 136
baud rate register (baud) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
baud rate selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
baud rate selection examples . . . . . . . . . . . . . . . . . . . . . . . . . . 138
during stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
SCI control register 1 (SCCR1) . . . . . . . . . . . . . . . . . . . . . . . . . 130
SCI control register 2 (SCCR2) . . . . . . . . . . . . . . . . . . . . . . . . . 131
SCI data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
SCI data register (SCDR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
SCI I/O registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
SCI interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
SCI operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
SCI receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
SCI status register (SCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
SCI transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
serial peripheral interface (SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
during stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
master/slave connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
multiple-SPI systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
pin functions in master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
pin functions in slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
serial clock polarity and phase . . . . . . . . . . . . . . . . . . . . . . . . . . 146
MC68HC705C8A — Rev. 3
MOTOROLA
Technical Data
Index
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Index
Freescale Semiconductor, Inc...
SPI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI clock/data timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI control register (SPCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI data register (SPDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI I/O register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI I/O registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI status register (SPSR). . . . . . . . . . . . . . . . . . . . . . . . . . . . .
141
146
149
149
147
142
148
148
142
151
stack pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
stop mode
non-programmable COP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
non-programmable COP flowchart. . . . . . . . . . . . . . . . . . . . . . . .
programmable COP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
programmable COP flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . .
SCI during stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI during stop mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stop/wait mode function flowchart . . . . . . . . . . . . . . . . . . . . . . . .
73
74
71
72
71
71
69
70
T
TCAP pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
TCMP pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
alternate timer registers (ATRH and ATRL) . . . . . . . . . . . . . . . . . 99
I/O registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
input capture registers (ICRH and ICRL) . . . . . . . . . . . . . . . . . . 100
output compare registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
timer control register (TCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
timer I/O register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
timer interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
timer operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
timer registers (TRH and TRL). . . . . . . . . . . . . . . . . . . . . . . . . . . 97
timer status register (TSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Technical Data
218
MC68HC705C8A — Rev. 3
Index
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Go to: www.freescale.com
Freescale Semiconductor, Inc.
Index
V
VDD pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
VSS pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
VPP pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
W
Freescale Semiconductor, Inc...
wait mode
non-programmable COP watchdog in wait mode . . . . . . . . . . . . 75
programmable COP watchdog in wait mode . . . . . . . . . . . . . . . . 75
stop/wait mode function flowchart . . . . . . . . . . . . . . . . . . . . . . . . 70
MC68HC705C8A — Rev. 3
MOTOROLA
Technical Data
Index
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
Index
Technical Data
220
MC68HC705C8A — Rev. 3
Index
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc.
Home Page:
www.freescale.com
email:
[email protected]
USA/Europe or Locations Not Listed:
Freescale Semiconductor
Technical Information Center, CH370
1300 N. Alma School Road
Chandler, Arizona 85224
(800) 521-6274
480-768-2130
[email protected]
Europe, Middle East, and Africa:
Freescale Halbleiter Deutschland GmbH
Technical Information Center
Schatzbogen 7
81829 Muenchen, Germany
+44 1296 380 456 (English)
+46 8 52200080 (English)
+49 89 92103 559 (German)
+33 1 69 35 48 48 (French)
[email protected]
Japan:
Freescale Semiconductor Japan Ltd.
Headquarters
ARCO Tower 15F
1-8-1, Shimo-Meguro, Meguro-ku
Tokyo 153-0064, Japan
0120 191014
+81 2666 8080
[email protected]
Asia/Pacific:
Freescale Semiconductor Hong Kong Ltd.
Technical Information Center
2 Dai King Street
Tai Po Industrial Estate,
Tai Po, N.T., Hong Kong
+800 2666 8080
[email protected]
For Literature Requests Only:
Freescale Semiconductor
Literature Distribution Center
P.O. Box 5405
Denver, Colorado 80217
(800) 441-2447
303-675-2140
Fax: 303-675-2150
LDCForFreescaleSemiconductor
@hibbertgroup.com
RoHS-compliant and/or Pb- free versions of Freescale products have the functionality
and electrical characteristics of their non-RoHS-compliant and/or non-Pb- free
counterparts. For further information, see http://www.freescale.com or contact your
Freescale sales representative.
For information on Freescale.s Environmental Products program, go to
http://www.freescale.com/epp.
Information in this document is provided solely to enable system and software
implementers to use Freescale Semiconductor products. There are no express or
implied copyright licenses granted hereunder to design or fabricate any integrated
circuits or integrated circuits based on the information in this document.
Freescale Semiconductor reserves the right to make changes without further notice to
any products herein. Freescale Semiconductor makes no warranty, representation or
guarantee regarding the suitability of its products for any particular purpose, nor does
Freescale Semiconductor assume any liability arising out of the application or use of
any product or circuit, and specifically disclaims any and all liability, including without
limitation consequential or incidental damages. “Typical” parameters which may be
provided in Freescale Semiconductor data sheets and/or specifications can and do
vary in different applications and actual performance may vary over time. All operating
parameters, including “Typicals” must be validated for each customer application by
customer’s technical experts. Freescale Semiconductor does not convey any license
under its patent rights nor the rights of others. Freescale Semiconductor products are
not designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life,
or for any other application in which the failure of the Freescale Semiconductor product
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MC68HC705C8A/D
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