bq2018 Power Minder™ IC Features General Description ➤ Multifunction charge/discharge counter The bq2018 is a low-cost charge/discharge counter peripheral packaged in an 8-pin TSSOP or SOIC. It works with an intelligent host controller, providing state-of-charge information for rechargeable batteries. ➤ Resolves signals less than 12.5µV ➤ Internal offset calibration improves accuracy ➤ 1024 bits of NVRAM configured as 128 x 8 ➤ Internal temperature sensor for self-discharge estimation ➤ Single-wire serial interface ➤ Dual operating modes: - Operating: <80µA - Sleep: <10µA ➤ REG output for low-cost microregulation The bq2018 measures the voltage drop across a low-value series sense resistor between the negative terminal of the battery and the battery pack ground contact. By using the accumulated counts in the charge, discharge, and self-discharge registers, an intelligent host controller can determine battery state-of-charge information. To improve accuracy, an offset count register is available. The system host controller is responsible for the register maintenance by resetting the charge in/out and selfdischarge registers as needed. The bq2018 also features 128 bytes of NVRAM registers. The upper 13 bytes of NVRAM contain the capacity monitoring and status information. The RBI input operates from an external power storage source such as a capacitor or a series cell in the battery pack, providing register nonvolatility for periods when the battery is shorted to ground or when the battery charge state is not sufficient to operate the bq2018. During this mode, the register backup current is less than 100nA. Packaged in an 8-pin TSSOP or SOIC, the bq2018 is small enough to fit in the crevice between two Asize cells or within the width of a prismatic cell. ➤ Internal timebase eliminates external components ➤ 8-pin TSSOP or SOIC allows battery pack integration Pin Connections Pin Names REG 1 8 WAKE VCC 2 7 SR1 VSS 3 6 SR2 HDQ 4 5 RBI REG Regulator output WAKE Wake-up output VCC Supply voltage input SR1 Current sense input 1 VSS Ground SR2 Current sense input 2 HDQ Data input/output RBI Register backup input 8-Pin TSSOP or Narrow SOIC PN-201801.eps SLUS003–JUNE 1999 C 1 bq2018 Pin Descriptions REG Functional Description General Operation Regulator output REG is the output of the operational transconductance amplifier (OTA) that drives an external pass n-channel JFET to provide an optional regulated supply. The supply is regulated at 3.7V nominal. VCC A host can use the bq2018 internal counters and timers to measure battery state-of-charge, estimate selfdischarge, and calculate the average charge and discharge current into and out of a rechargeable battery. The bq2018 needs an external host system to perform all register maintenance. Using information from the bq2018, the system host can determine the battery state-of-charge, estimate self-discharge, and calculate the average charge and discharge currents. During pack storage periods, the use of an internal temperature sensor doubles the self-discharge count rate every 10° above 25°C. Supply voltage input When regulated by the REG output, VCC is 3.7V ±200mV. When the REG output is not used, the valid operating range is 2.8V to 5.5V. VSS Ground SR1– SR2 Current sense inputs To reduce cost, power to the bq2018 may be derived using a low-cost external FET in conjunction with the REG pin. The bq2018 operating current is less than 80µA. When the HDQ line remains low for greater than ten seconds and VSRO (VSR + VOS where VSR is the voltage drop between SR1 and SR2 and VOS is the offset voltage) is below the programmed minimal level (WAKE is in High Z), the bq2018 enters a sleep mode of <10µA where all operations are suspended. HDQ transitioning high reinitiates the bq2018. The bq2018 interprets charge and discharge activity by monitoring and integrating the voltage drop (VSR) across pins SR1 and SR2. The SR1 input connects to the sense resistor and the negative terminal of the battery. The SR2 input connects to the sense resistor and the negative terminal of the pack. VSR1 < VSR2 indicates discharge, and VSR1 > VSR2 indicates charge. The effective voltage drop, VSRO, as seen by the bq2018, is VSR + VOS. Valid input range is ± 200mV. HDQ A register is available to store the calculated offset, allowing current calibration. The offset cancellation register is written by the bq2018 during pack assembly and is available to the host system to adjust the current measurements. By adding or subtracting the offset value stored in the OFR, the true charge and discharge counts can be calculated to a high degree of certainty. Data input/output This bi-directional input/output communicates the register information to the host system. HDQ is open drain and requires a pullup/down resistor in the battery pack to disable/enable sleep mode if the pack is removed from the system. RBI Figure 1 shows a block diagram of the bq2018, and Table 1 outlines the bq2018 operational states. REG Output The bq2018 can operate directly from three or four nickel-chemistry cells or a single Li-Ion cell as long as VCC is limited to 2.8 to 5.5V. To facilitate the power supply requirements of the bq2018, a REG output is present to regulate an external low-threshold n-JFET. A micropower VCC source for the bq2018 can inexpensively be built using this FET. Register backup input This input maintains the internal register states during periods when VCC is below the minimum operating voltage. WAKE Wake-up output When asserted, this output is used to indicate that the charge or discharge activity is above a programmed minimal level. 2 bq2018 System I/O and Control WAKE Differential Dynamically Balanced VFC SR1 SR2 Bandgap Voltage Reference RAM and Counters 128 x 8 Calibration and Power Control TemperatureCompensated Precision Oscillator HDQ Timer RBI Counter Control Temperature Sensor d s VCC VDD (Internal) g Optional (External) REG Vref VSS BD201801.eps Figure 1. bq2018 Block Diagram Table 1. Operational States Note: HDQ Pin DCR/CCR/SCR WOE WAKE HDQ High yes |VSRO| > VWOE Low Normal HDQ High yes |VSRO| < VWOE High Z Normal HDQ Low no |VSRO| < VWOE High Z Sleep VSRO is the voltage difference between SR1 and SR2 plus the offset voltage VOS. 3 Operating State bq2018 BAT+ R6 d WAKE Q1 1K SST113 s C5 2 D2 BZX84C5V6 U1 0.01µF 1 2 3 4 VCC REG VCC VSS HDQ VCC WAKE SR1 SR2 RBI R2 8 7 6 5 BATC2 100K BQ2018 R1 0.1µF C1 R3 0.1µF 0.05 1W PACK100K C3 R5 HDQ 0.1µF 100 D3 2 D1 R4 BZX84C5V6 RBI C4 BAV99 1M 0.1µF 2018typAp.eps Figure 2. Typical Application counts by sensing the voltage difference across a lowvalue resistor between the negative terminal of the battery pack and the negative terminal of the battery. The DCR or CCR counts depending on the signal between SR1 and SR2. RBI Input The RBI input pin is used with a storage capacitor or external supply to provide back-up potential to the internal RAM when VCC drops below 2.4V. The maximum discharge current is 100nA in this mode. The bq2018 outputs VCC on RBI when the supply is above 2.4V, so a diode is required to isolate an external supply. During discharge, the DCR and the Discharge Time Counter (DTC) are active. If VSR1 is less than VSR2, indicating a discharge, the DCR counts at a rate equivalent to 12.5µV every hour, and the DTC counts at a rate of 1 count/0.8789 seconds (4096 counts per 1 hour). For example, a -100mV signal produces 8000 DCR counts and 4096 DTC counts each hour. The amount of charge removed from the battery can easily be calculated. Charge/Discharge Count Operation Table 2 shows the main counters and registers of the bq2018. The bq2018 accumulates charge and discharge counts into two main count registers, the Discharge Count Register (DCR) and the Charge Count Register (CCR). The bq2018 produces charge and discharge Table 2. bq2018 Counters Name DCR Range RAM Size Discharge count register Description VSR1 < VSR2 (Max. =-200mV) 12.5µVh increments 16-bit VSR1 > VSR2 (Max. = +200mV) 12.5µVh increments 16-bit 1 count/hour @ 25°C 16-bit CCR Charge count register SCR Self-discharge count register DTC Discharge time counter 1 count/0.8789s default 1 count/225s if STD is set 16-bit CTC Charge time counter 1 count/0.8789s default 1 count/225s if STC is set 16-bit MODE/ WOE MODE/ Wake output enable — 8-bit 4 bq2018 7f 7f Discharge count high byte 7e Discharge count low byte 7d Charge count high byte 7c Charge count low byte 7b Self-discharge high byte 7a Self-discharge low byte 73 72 79 Discharge time high byte 78 Discharge time low byte User RAM 77 Charge time high byte 76 Charge time low byte 75 Mode/wake output enable 74 Temperature/clear 73 Offset register 00 FG201801.eps Figure 3. Address Map useful in determining an estimation of the battery selfdischarge based on capacity and storage temperature conditions. During charge, the CCR and the Charge Time Counter (CTC) are active. If VSR1 is greater than VSR2, indicating a charge, the CCR counts at a rate equivalent to 12.5µV every hour, and the CTC counts at a rate of 1 count/0.8789 seconds. For example, a +100mV signal produces 8000 CCR counts and 4096 CTC counts each hour. The amount of charge added to the battery can easily be calculated. The bq2018 may be programmed to measure the voltage offset between SR1 and SR2 during pack assembly or at any time by invoking the Calibration mode. The Offset Register (OFR) is used to store the bq2018 offset. The 8bit 2’s complement value stored in the OFR is scaled to the same units as the DCR and CCR, representing the amount of positive or negative offset in the bq2018. The maximum offset for the bq2018 is specified as ± 500µV. Care should be taken to ensure proper PCB layout. Using OFR, the system host can cancel most of the effects of bq2018 offset for greater resolution and accuracy. The DTC and the CTC are 16-bit registers, and roll over beyond ffffh. If a rollover occurs, the corresponding bit in the MODE/WOE register is set, and the counter will subsequently increment at 1/256 of the normal rate (16 counts/hr.). Whenever the signal between SR1 and SR2 is above the Wakeup Output Enable (WOE) threshold and the HDQ pin is high, the bq2018 is in its full operating state. In this state, the DCR, CCR, DTC, CTC, and SCR are fully operational, and the WAKE output is low. During this mode, the internal RAM registers of the bq2018 may be accessed over the HDQ pin, as described in the section “Communicating With the 2018.” Figure 3 shows the bq2018 register address map. The bq2018 uses the upper 13 locations. The remaining memory can store user-specific information such as chemistry, serial number, and manufacturing date. WAKE Output This output is used to inform the system that the voltage difference between SR1 and SR2 is above or below the Wake Output Enable (WOE) threshold programmed in the MODE/WOE register. When the voltage difference between SR1 and SR2 is below VWOE, the WAKE output goes into High Z and remains in this state until the discharge or charge current increases above the specified value. The MODE/WOE resets to 0eh after a power-on reset. VWOE is set by dividing 3.84mV by a value between 1 and 7 (1–7h) according to Table 3. If the signal between SR1 and SR2 is below the WOE threshold (refer to the WAKE section for details) and HDQ remains low for greater than 10 seconds, the bq2018 enters a sleep mode where all register counting is suspended. The bq2018 remains in this mode until HDQ returns high. For self-discharge calculation, the self-discharge count register (SCR) counts at a rate equivalent to 1 count every hour at a nominal 25°C and doubles approximately every 10°C up to 60°C. The SCR count rate is halved every 10 °C below 25°C down to 0°C. The value in SCR is 5 bq2018 Table 3. WOE Thresholds Table 4. Temperature Steps WOE3–1 (hex) VWOE (mV) 0h n/a 1h 3.840 2h 1.920 10–20° 2h × 1/2 3h 1.280 20–30° 3h 1 count/hr. 4h 0.960 30–40° 4h ×2 5h 0.768 40–50° 5h ×4 6h 0.640 50–60° 6h ×8 7h* 0.549 >60° 7h × 16 Temp Value (hex) SDR Count Rate <0° 0h × 1/8 0–10° 1h × 1/4 * Default value after POR. Temperature The bq2018 has an internal temperature sensor which is used to set the value in the temperature register (TMP/CLR) and set the self-discharge count rate value. The register reports the temperature in 8 steps of 10°C from <0°C to >60°C as Table 4 specifies. The bq2018 temperature sensor has typical accuracy of ± 2°C at 25°C. See the TMP/CLR register description for more details. the CTC register clears the STC bit and sets the CTC count rate to the default value of 1 count per 0.8789s. Calibration Mode The system can enable bq2018 VOS calibration by setting the calibration bit in the MODE/WOE register (Bit 6) to 1. The bq2018 then enters calibration mode when the HDQ line is low for greater than 10 seconds and when the signal between SR1 and SR2 is below VWOE. Caution: Take care to ensure that no low-level external signal is present between SR1 and SR2 because this affects the calibration value that the bq2018 calculates. Clear Register The host system is responsible for register maintenance. To facilitate this maintenance, the bq2018 has a Clear Register (TMP/CLR) designed to reset the specific counter or register pair to zero. The host system clears a register by writing the corresponding register bit to 1. When the bq2018 completes the reset, the corresponding bit in the TMP/CLR register is automatically reset to 0, which saves the host an extra write/read cycle. Clearing the DTC register clears the STD bit and sets the DTC count rate to the default value of 1 count per 0.8789s. Clearing If HDQ remains low for one hour and |VSR| < VWOE for the entire time, the measured VOS is latched into the OFR register, and the calibration bit is reset to zero, indicating to the system that the calibration cycle is complete. Once calibration is complete, the bq2018 enters a Received by Host from bq2018 Written by Host to bq2018 CMDR = 73h Break 0 1 MSB Data (OFR) = 65h LSB MSB LSB 1 2 3 4 5 6 7 0 1 0 0 1 1 1 0 1 LSB MSB 1 2 3 0 1 0 MSB 4 5 6 7 0 1 1 0 LSB 65h = 0 1 1 0 0 1 0 1 73h = 0 1 1 1 0 0 1 1 TD201801.eps Figure 4. Typical Communication with the bq2018 6 bq2018 Table 5. bq2018 Command and Status Registers Symbol CMDR DCRH DCRL CCRH CCRL SCRH SCRL DTCH DTCL CTCH CTCL MODE/ WOE TMP/CLR OFR RAM Notes: Register Name Loc. (hex) Command register Discharge count register high 7f byte Discharge count register 7e low byte Charge count register 7d high byte Charge count register 7c low byte Self-discharge count register 7b high byte Self-discharge count register 7a low byte Discharge time count 79 high byte Discharge time count 78 low byte Charge time count 77 high byte Charge time count 76 low byte MODE/ wakeup output 75 enable Temperature/Clear 74 register Offset 73 register User 72-00 memory Read/ Write 7(MSB) 6 5 Write W/R AD6 AD5 Control Field 4 3 AD4 AD3 2 1 0(LSB) AD2 AD1 AD0 Read DCRH7 DCRH6 DCRH5 DCRH4 DCRH3 DCRH2 DCRH1 DCRH0 Read DCRL7 DCRL6 DCRL5 DCRL4 DCRL3 DCRL2 DCRL1 DCRL0 Read CCRH7 CCRH6 CCRH5 CCRH4 CCRH3 CCRH2 CCRH1 CCRH0 Read CCRL7 CCRL6 CCRL5 CCRL4 CCRL3 CCRL2 CCRL1 CCRL0 Read SCRH7 SCRH6 SCRH5 SCRH4 SCRH3 SCRH2 SCRH1 SCRH0 Read SCRL7 SCRL6 SCRL5 SCRL4 SCRL3 SCRL2 SCRL1 SCRL0 Read DTCH7 DTCH6 DTCH5 DTCH4 DTCH3 DTCH2 DTCH1 DTCH0 Read DTCL7 DTCL6 DTCL5 DTCL4 DTCL3 DTCL2 DTCL1 DTCL0 Read CTCH7 CTCH6 CTCH5 CTCH4 CTCH3 CTCH2 CTCH1 CTCH0 Read CTCL7 CTCL6 CTCL5 CTCL4 CTCL3 CTCL2 CTCL1 CTCL0 Read/ OVRDQ write Read/ write Read/ write Read/ write CAL STC STD WOE3 WOE2 WOE1 0 TMP2 TMP1 TMP0 CTC DTC SCR CCR DCR OFR7 OFR6 OFR5 OFR4 OFR3 OFR2 OFR1 OFR0 - - - - - - - - 1. MODE/WOE register bit 0 is set to zero at startup and should not be written to 1 for proper bq2018 operation. 2. OFR value is in two’s complement. 7 bq2018 The final section is used to stop the transmission by returning the HDQ pin to a logic-high state by at least a period, tSSU,B, after the negative edge used to start communication. The final logic-high state should be held until a period, tCYCH,B, to allow time to ensure that the bit transmission ceased properly. The serial communication timing specification and illustration sections give the timings for data and break communication. low-power mode until HDQ goes high, indicating an external system is ready to access the bq2018. If HDQ transitions high prior to completion of the VOS calculation or if |VSR| > VWOE, then the calibration cycle is reset. The bq2018 then postpones the calibration cycle until the conditions are met. The calibration bit does not reset to zero until a valid calibration cycle is completed. The requirement for HDQ to remain low for the calibration cycle can be disabled by setting the OVRDQ bit to 1. In this case, calibration continues as long as |VSR| < VWOE. The OVRDQ bit is reset to zero at the end of a valid calibration cycle. Communication with the bq2018 always occurs with the least-significant bit being transmitted first. Figure 4 shows an example of a communication sequence to read the bq2018 OFR register. Communicating with the bq2018 bq2018 Registers The bq2018 includes a simple single-pin (referenced to VSS) serial data interface. A host processor uses the interface to access various bq2018 registers. Battery activity may be easily monitored by adding a single contact to the battery pack. Note: The HDQ pin requires an external pull-up or pull-down resistor. The bq2018 command and status registers are listed in Table 5 and described below. Command (CMDR) The write-only command register is accessed when the bq2018 has received eight contiguous valid command bits. The command register contains two fields: The interface uses a command-based protocol, where the host processor sends a command byte to the bq2018. The command directs the bq2018 either to store the next eight bits of data received to a register specified by the command byte or to output the eight bits of data from a register specified by the command byte. n W/R n Command address The W/R bit of the command register is used to select whether the received command is for a read or a write function. The W/R values are The communication protocol is asynchronous return-toone. Command and data bytes consist of a stream of eight bits that have a maximum transmission rate of 5K bits/sec. The least-significant bit of a command or data byte is transmitted first. The protocol is simple enough that it can be implemented by most host processors using either polled or interrupt processing. Data input from the bq2018 may be sampled using the pulse-width capture timers available on some microcontrollers. A UART may also be used to communicate through the HDQ pin. CMDR Bits 7 6 5 4 3 2 1 0 W/R - - - - - - - Where W/R is If a communication time-out occurs, e.g., the host waits longer than tCYCB for the bq2018 to respond or if this is the first access command, then a BREAK should be sent by the host. The host may then resend the command. The bq2018 detects a BREAK when the HDQ pin is driven to a logic-low state for a time, tB or greater. The HDQ pin then returns to its normal ready-high logic state for a time, tBR. The bq2018 is then ready to receive a command from the host processor. 0 The bq2018 outputs the requested register contents specified by the address portion of the CMDR 1 The following eight bits should be written to the register specified by the address portion of the CMDR The lower seven-bit field of CMDR contains the address portion of the register to be accessed. The return-to-one data bit frame consists of three distinct sections. The first section is used to start the transmission by either the host or the bq2018 taking the HDQ pin to a logic-low state for a period, tSTRH,B. The next section is the actual data transmission, where the data should be valid by a period, tDSU,B, after the negative edge used to start communication. The data should be held for a period, tDV/tDH, to allow the host or bq2018 to sample the data bit. CMDR Bits 7 - 6 5 AD6 AD5 4 3 2 1 0 AD4 AD3 AD2 AD1 AD0 Discharge Count Registers (DCRH/DCRL) The DCRH high-byte register (address = 7fh) and the DCRL low-byte register (address = 7eh) contain the count 8 bq2018 DTCH and DTCL increment at a rate of 16 counts per hour. Note: If a second rollover occurs, STC is cleared. Access to the bq2018 should be timed to clear CTCH/CTCL more often than every 170 days. The TMP/CLR register is used to force the reset of both the CTCH and CTCL to zero. of the discharge, and are incremented whenever VSR1 < VSR2. These registers continue to count beyond ffffh, so proper register maintenance should be done by the host system. The TMP/CLR register is used to force the reset of both the DCRH and DCRL to zero. Charge Count Registers (CCRH/CCRL) Mode/Wake-up Enable Register The CCRH high-byte register (address = 7dh) and the CCRL low-byte register (address = 7ch) contain the count of the charge, and are incremented whenever VSR1 > VSR2. These registers continue to count beyond ffffh, so proper register maintenance should be done by the host system. The TMP/CLR register is used to force the reset of both the CCRH and CCRL to zero. The Mode/WOE register (address = 75h) contains the calibration, wakeup enable information, and the STC and STD bits as described below. The Override DQ(OVRDQ) bit (bit 7) is used to override the requirement for HDQ to be low prior to initiating VOS calibration. This bit is normally set to zero. If OVRDQ is written to one, the bq2018 begins offset calibration when |VSR|<VWOE where HDQ = Don’t care. Self-discharge Count Registers (SCRH/SCRL) The OVRDQ location is The SCRH high-byte register (address = 7bh) and the SCRL low-byte register (address = 7ah) contain the selfdischarge count. This register is continually updated whenever the bq2018 is in its normal operating mode. The counts in these registers are incremented based on time and temperature. The SCR counts at a rate of 1 count per hour at 20–30°C and doubles every 10°C to greater than 60°C (16 counts/hour). The count will half every 10°C below 20–30°C to less than 0°C (1 count/8 hours). These registers continue to count beyond ffffh, so proper register maintenance should be done by the host system. The TMP/CLR register is used to force the reset of both the SCRH and SCRL to zero. MODE/WOE Bits 7 6 5 4 3 2 1 0 OVRDQ - - - - - - - Where OVRDQ is 0 HDQ = 0 and |VSR|<VWOE for VOS calibration to begin 1 HDQ = Don’t care and |VSR|<VWOE for VOS calibration to begin Note: The OVRDQ bit should only be used in conjunction with a calibration cycle. Normal operation of the bq2018 cannot be guaranteed when this bit is set. After a valid calibration cycle, bit 7 is reset to zero. Discharge Time Count Registers (DTCH/DTCL) The DTCH high-byte register (address = 79h) and the DTCL low-byte register (address = 78h) are used to determine the length of time the VSR1 < VSR2 indicating a discharge. The counts in these registers are incremented at a rate of 4096 counts per hour. If the DTCH/DTCL register continues to count beyond ffffh, the STD bit is set in the MODE/WOE register indicating a rollover. Once set, DTCH and DTCL increment at a rate of 16 counts per hour. Note: If a second rollover occurs, STD is cleared. Access to the bq2018 should be timed to clear DTCH/DTCL more often than every 170 days. The TMP/CLR register is used to force the reset of both the DTCH and DTCL to zero. The calibration (CAL) bit 6 is used to enable the bq2018 offset calibration test. Setting this bit to 1 enables a VOS calibration whenever HDQ is low (default), and |VSRO|< VWOE. This bit is cleared to 0 by the bq2018 whenever a valid VOS calibration is completed, and the OFR register is updated with the new calculated offset. The bit remains 1 if the offset calibration was not completed. The CAL location is MODE/WOE Bits Charge Time Count Registers (CTCH/CTCL) 7 6 5 4 3 2 1 0 The CTCH high-byte register (address = 77h) and the CTCL low-byte register (address = 76h) are used to determine the length of time the VSR1 > VSR2 indicating a charge. The counts in these registers are incremented at a rate of 4096 counts per hour. If the CTCH/CTCL registers continue to count beyond ffffh, the STC bit is set in the MODE/WOE register indicating a rollover. Once set, - CAL - - - - - - Where CAL is 9 0 Valid offset calibration 1 Offset calibration pending bq2018 The slow time charge (STC) and slow time discharge (STD) flags indicate if the CTC or DTC registers have rolled over beyond ffffh. STC set to 1 indicates a CTC rollover; STD set to 1 indicates a DTC rollover. Temperature and Clear Register The TMP/CLR register (address = 74h) is used to give the present temperature step between < 0°C to > 60°C and clear the various count registers. The values of the TMP0–TMP2 (bits 5–7) denote the current temperature step sense by the bq2018 as outlined in Table 4. The bq2018 temperature sense is trimmed to ± 2°C typical (± 4°C maximum). The STC and STD locations are MODE/WOE Bits 7 6 5 4 3 2 1 0 - - STC STD - - - - The TMP2–0 locations are Where STC/STD is TMP/CLR Bits 7 0 No rollover 1 Rollover occurred in the corresponding CTC/DTC register. 4 - - - - 3 2 1 WOE3 WOE2 WOE1 3 2 1 0 - - - - - The Clear bits (Bits 0–4) are used to reset the various bq2018 counters and STC and STD bits to zero. Writing the bits to 1 resets the corresponding register to 0. The clear bit resets to 0 indicating a successful register reset. Each clear bit is independent, so it is possible to clear the DCRH/DCRL registers without affecting the values in any other bq2018 register. The high-byte and low-byte registers are both cleared when the corresponding bit is written to 1 per the figure below. MODE/WOE Bits 5 4 Where TMP2–0 is the temperature step sensed by this bq2018. The WOE 3–1 locations are 6 5 TMP2 TMP1 TMP0 The Wake Up Output Enable (WOE) bits (bits 3–1) are used to set the Wake-Up Enable signal level. Whenever |VSRO |<VWOE, the WAKE output is in High Z. If |VSRO| is greater than VWOE, WAKE transitions low. On bq2018 initialization (power-on reset) these bits are set to 1. Setting all of these bits to zero is not valid. Refer to Table 3 for the various WOE values. 7 6 0 - Where WOE3–1 is determined by dividing 3.84mV by the value in WOE. Bit 0 is reserved and must remain 0. Send Host to bq-HDQ Send Host to bq-HDQ or Receive from bq-HDQ Data CDMR R/W MSB Bit7 Address Break tRR LSB Bit0 tRSPS Start-bit Address-Bit/ Data-Bit Stop-Bit TD201807.eps Figure 5. Communications Frame Example 10 bq2018 The Clear bit locations are Offset Register (OFR) The OFR register (address = 73h) is used to store the calculated VOS of the bq2018. The OFR value can be used to cancel the voltage offset between VSR1 and VSR2. The up/down offset counter is centered at zero. The actual offset is an 8-bit two’s complement value located in OFR. TMP/CLR Bits 7 6 5 4 3 2 1 0 - - - CTC DTC SCR CCR DCR Where: The OFR locations are CTC bit (bit 4) resets both the CTCH and CTCL registers and the STC bit to 0. OFR Bits The DTC bit (bit 3) resets both the DTCH and DTCL registers and the STD bit to 0. OFR7 OFR6 OFR5 OFR4 OFR3 OFR2 OFR1 OFR0 7 The SCR bit (bit 2) resets both the SCRH and SCRL registers to 0. 6 5 Where OFR7 is The CCR bit (bit 1) resets both the CCRH and CCRL registers to 0. The DCR bit (bit 0) resets both the DCRH and DCRL registers to 0. 11 1 Discharge 0 Charge 4 3 2 1 0 bq2018 Absolute Maximum Ratings Symbol Parameter Minimum Maximum Uni t VCC Relative to VSS -0.3 +6.0 V HDQ Relative to VSS -0.3 +6.0 V VSS -0.3V VCC +3.0V V 1.0 mA All other pins IREG REG to VSS VSR1 / VSR2 Relative to VSS -0.3 +6.0 V TOPR Operating temperature - 20 +70 °C Note: Notes A 100kΩ series resistor is recommended to protect SR1 / SR2 in case of a shorted battery. Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation should be limited to the Recommended DC Operating Conditions detailed in this data sheet. Exposure to conditions beyond the operational limits for extended periods of time may affect device reliability. DC Electrical Characteristics (TA = TOPR) Symbol Parameter VCC Supply voltage ICC Operating current ICC2 IRBI VSR Sense resistor input RSR SR1 / SR2 input impedance IOL Open-drain sink current VIHDQ VILDQ Notes: Minimum Typical Maximum Unit Notes 2.8 4.25 5.5 V REG = No connect 3.5 3.7 3.9 V VCC derived from REG, Note 3 - 60 70 µA VCC,HDQ = 3.7V - 70 80 µA VCC,HDQ = 5.5V Sleep - - 10 µA VCC = 5.5V RBI current - - 100 nA VCC < 2.4V -200 - 200 mV VSR1 < VSR2 = discharge; VSR1 > VSR2 = charge Note 2 10 - - MΩ -200mV < VSR < 200mV - - 2.0 mA VOL = VSS + 0.3V WAKE, HDQ HDQ input high 2.5 - - V HDQ input low - - 0.8 V 1. All voltages relative to VSS. 2. VSR1/SR2 + VOS. VOS is affected by PC board layout. Follow proper layout guidelines for optimal performance. 3. Can be guaranteed by design when using an SST108 or equivalent JFET. 12 bq2018 Performance Characteristics (TA = TOPR) Symbol Parameter Typical Maximum Unit Notes VOS Offset voltage ±500 µV Voltage offset between SR1 and SR2 OSC Timer accuracy 1.5 ±3.0 % VCC =3.5 - 3.9V (TA = 0–70°C) INR Integrated nonrepeatability error 0.5 1.0 % Measured repeatability given similar operating conditions INL Integrated non-linearity 1.0 2.0 % Add 0.05% per °C above or below 25°C and 0.5% per volt above or below 3.7V. Standard Serial Communication Timing Specification (TA = TOPR) Symbol Parameter Minimum tCYCH Cycle time, host to bq2018 (write) 190 - - µs tCYCB Cycle time, bq2018 to host (read) 190 205 250 µs tSTRH Start hold, host to bq2018 (write) 5 - - ns tSTRB Start hold, bq2018 to host (read) 32 - - µs tDSU,B Data setup - - 50 µs tDH Data hold 90 - - µs tDV Data valid - - 80 µs tSSUB Stop setup (bq2018 to host) - - 95 µs tSSU Stop setup (host to bq2018) - - 145 µs tB Break 190 - - µs tBR Break recovery 40 - - µs tRSPS Response time, bq2018 to host 190 - 320 µs tRR Read recovery 40 - - µs 13 Typical Maximum Unit Notes Host read to next cycle bq2018 Break Timing tBR tB Host to bq2018 Write "1" Write "0" tSTRH tDSU tDH tSSU tCYCH bq2018 to Host Read "1" Read "0" tSTRB tDSUB tDV tSSUB tCYCB 14 bq2018 8-Pin SOIC Narrow ~ SN Package Suffix Millimeters Inches Dimension A Min. Max. Min. Max. 1.52 1.78 0.060 0.070 A1 0.10 0.25 0.004 0.010 B 0.33 0.51 0.013 0.020 C 0.18 0.25 0.007 0.010 D 4.70 5.08 0.185 0.200 E 3.81 4.06 0.150 0.160 e 1.14 1.40 0.045 0.055 H 5.72 6.22 0.225 0.245 L 0.38 0.89 0.015 0.035 15 bq2018 8-Pin TSSOP ~ TS Package Suffix Millimeters Inches Dimension A Min. Max. Min. Max. - 1.10 - 0.043 A1 0.05 0.15 0.002 0.006 B 0.18 0.30 0.007 0.012 C 0.09 0.18 0.004 0.007 D 2.90 3.10 0.115 0.122 E 4.30 4.48 0.169 0.176 e 0.65BSC 0.0256BSC H 6.25 6.50 0.246 0.256 L 0.50 0.70 0.020 0.028 Notes: 1. Controlling dimension: millimeters. Inches shown for reference only. 2 'D' and 'E' do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15mm per side 3 Each lead centerline shall be located within ±0.10mm of its exact true position. 4. Leads shall be coplanar within 0.08mm at the seating plane. 5 Dimension 'B' does not include dambar protrusion. The dambar protrusion(s) shall not cause the lead width to exceed 'B' maximum by more than 0.08mm. 6 Dimension applies to the flat section of the lead between 0.10mm and 0.25mm from the lead tip. 7 'A1' is defined as the distance from the seating plane to the lowest point of the package body (base plane). 16 bq2018 Data Sheet Revision History Change No. Page No. 1 All 2 12 Note: Description Nature of Change Clarification of absolute maximum pin ratings Change 1 = Jan. 1999 B changes to Final from Dec. 1998 Preliminary data sheet. Change 2 = June 1999 C changes from Jan. 1999 B. 17 bq2018 Ordering Information bq2018 Temperature Range: blank = Commercial (-20 to +70°C) Package Option: SN = 8-pin narrow SOIC TS = 8 pin TSSOP Device: bq2018 Power Minder IC 18 Notes 19 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof. Copyright © 1999, Texas Instruments Incorporated 20 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof. Copyright 2000, Texas Instruments Incorporated