SN54AHCT273, SN74AHCT273 OCTAL D-TYPE FLIP-FLOPS WITH CLEAR SCLS375D – JUNE 1997 – REVISED JANUARY 2000 D D D CLR 1Q 1D 2D 2Q 3Q 3D 4D 4Q GND 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC 8Q 8D 7D 7Q 6Q 6D 5D 5Q CLK SN54AHCT273 . . . FK PACKAGE (TOP VIEW) 2D 2Q 3Q 3D 4D 8Q D D D SN54AHCT273 . . . J OR W PACKAGE SN74AHCT273 . . . DB, DGV, DW, N, OR PW PACKAGE (TOP VIEW) 1D 1Q CLR VCC D D EPIC (Enhanced-Performance Implanted CMOS) Process Inputs Are TTL-Voltage Compatible Contain Eight Flip-Flops With Single-Rail Outputs Direct Clear Input Individual Data Input to Each Flip-Flop Applications Include: – Buffer/Storage Registers – Shift Registers – Pattern Generators Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), Thin Very Small-Outline (DGV), Thin Shrink Small-Outline (PW), and Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) DIPs 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 8D 7D 7Q 6Q 6D 4Q GND CLK 5Q 5D D description These devices are positive-edge-triggered D-type flip-flops with a direct clear (CLR) input. Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When CLK is at either the high or low level, the D input has no effect at the output. The SN54AHCT273 is characterized for operation over the full military temperature range of –55°C to 125°C. The SN74AHCT273 is characterized for operation from –40°C to 85 °C. FUNCTION TABLE (each flip-flop) INPUTS CLR CLK D OUTPUT Q L X X L H ↑ H H H ↑ L L H L X Q0 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Instruments Incorporated. Copyright 2000, Texas Instruments Incorporated UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54AHCT273, SN74AHCT273 OCTAL D-TYPE FLIP-FLOPS WITH CLEAR SCLS375D – JUNE 1997 – REVISED JANUARY 2000 logic symbol† CLR CLK 1D 2D 3D 4D 5D 6D 7D 8D 1 R 11 C1 3 2 1D 4 5 7 6 8 9 13 12 14 15 17 16 18 19 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. logic diagram (positive logic) CLK 1D 2D 3D 4D 3 4 7 8 6D 13 7D 14 8D 17 18 11 1D 1D C1 1D C1 R CLR 5D 1D C1 R 1D C1 R 1D C1 R 1D C1 R 1D C1 R C1 R R 1 2 5 6 1Q 2Q 3Q 9 12 4Q 15 5Q 6Q 16 19 7Q 8Q logic diagram, each flip-flop (positive logic) D C C TG TG Q C C C C TG CLK(I) TG C C C C R 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54AHCT273, SN74AHCT273 OCTAL D-TYPE FLIP-FLOPS WITH CLEAR SCLS375D – JUNE 1997 – REVISED JANUARY 2000 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±75 mA Package thermal impedance, θJA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92°C/W DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51. recommended operating conditions (see Note 3) SN54AHCT273 SN74AHCT273 MIN MAX MIN MAX 4.5 5.5 4.5 5.5 UNIT VCC VIH Supply voltage VIL VI Low-level input voltage 0.8 V Input voltage 0 5.5 0 5.5 V VO IOH Output voltage 0 0 VCC –8 V High-level output current VCC –8 IOL ∆t/∆v Low-level output current 8 8 mA 20 20 ns/V High-level input voltage 2 2 0.8 Input transition rise or fall time V V mA TA Operating free-air temperature –55 125 –40 85 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54AHCT273, SN74AHCT273 OCTAL D-TYPE FLIP-FLOPS WITH CLEAR SCLS375D – JUNE 1997 – REVISED JANUARY 2000 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VOH VOL II ICC ∆ICC‡ TEST CONDITIONS VCC IOH = –50 mA MIN TA = 25°C TYP MAX 4.4 45V 4.5 IOH = –8 mA IOL = 50 mA 4.5 3.94 MAX SN74AHCT273 MIN 4.4 4.4 3.8 3.8 MAX UNIT V 0.1 0.1 0.36 0.44 0.44 ±0.1 ±1* ±1 mA 5.5 V 4 40 40 mA 5.5 V 1.35 1.5 1.5 mA 10 pF 0 V to 5.5 V VI = VCC or GND, IO = 0 One input at 3.4 V, Other inputs at VCC or GND MIN 0.1 45V 4.5 IOL = 8 mA VI = VCC or GND SN54AHCT273 Ci VI = VCC or GND 5V 2.5 10 * On products compliant to MIL-PRF-38535, this parameter is not production tested at VCC = 0 V. † This is the increase in supply current for each input at one of the specified TTL voltage levels rather than 0 V or VCC. V timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) TA = 25°C MIN MAX tw Pulse duration tsu Setup time th Hold time, data after CLK↑ SN54AHCT273 MIN MAX SN74AHCT273 MIN CLR low 5 6 6 CLK high or low 5 6.5 6.5 Data before CLK↑ 5 5 5 CLR before CLK↑ 2.5 2.5 2.5 0 0 0 MAX UNIT ns ns ns switching characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) fmax tPHL tPLH tPHL tPHL tPLH tPHL tsk(o) 75** 120** 65** 65 CL = 50 pF 50 75 45 45 CL = 15 pF CLK Q CL = 15 pF CLR Q CL = 50 pF CL = 50 pF MAX MIN MAX 1** 11.6** 1 11.6 5.5** 7.5** 1** 8.8** 1 8.8 5.8** 8.2** 1** 10** 1 10 8.5 11 1 12.6 1 12.6 6.5 8.5 1 9.8 1 9.8 6.8 9.2 1 11 1 11 1*** • DALLAS, TEXAS 75265 UNIT MHz 10** PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 MIN 7.5** CL = 50 pF ** On products compliant to MIL-PRF-38535, this parameter is not production tested. *** On products compliant to MIL-PRF-38535, this parameter does not apply. 4 SN74AHCT273 CL = 15 pF Q Q SN54AHCT273 MIN CLR CLK TA = 25°C TYP MAX LOAD CAPACITANCE 1 ns ns ns ns ns SN54AHCT273, SN74AHCT273 OCTAL D-TYPE FLIP-FLOPS WITH CLEAR SCLS375D – JUNE 1997 – REVISED JANUARY 2000 noise characteristics, VCC = 5 V, CL = 50 pF, TA = 25°C (see Note 4) SN74AHCT273 PARAMETER MIN TYP MAX UNIT VOL(P) VOL(V) Quiet output, maximum dynamic VOL 0.76 V Quiet output, minimum dynamic VOL –0.48 V VOH(V) VIH(D) Quiet output, minimum dynamic VOH 4.4 High-level dynamic input voltage V 2 VIL(D) Low-level dynamic input voltage NOTE 4: Characteristics are for surface-mount packages only. V 0.8 V TYP UNIT operating characteristics, TA = 25°C PARAMETER Cpd TEST CONDITIONS Power dissipation capacitance No load, POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 f = 1 MHz 27 pF 5 SN54AHCT273, SN74AHCT273 OCTAL D-TYPE FLIP-FLOPS WITH CLEAR SCLS375D – JUNE 1997 – REVISED JANUARY 2000 PARAMETER MEASUREMENT INFORMATION Test Point From Output Under Test RL = 1 kΩ From Output Under Test VCC Open S1 TEST GND CL (see Note A) CL (see Note A) S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain Open VCC GND VCC LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS 3V 1.5 V Timing Input 0V tw 3V 1.5 V Input 1.5 V th tsu 3V 1.5 V Data Input 1.5 V 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3V 1.5 V Input 1.5 V 0V tPLH In-Phase Output tPHL 50% VCC tPHL Out-of-Phase Output VOH 50% VCC VOL Output Waveform 1 S1 at VCC (see Note B) VOH 50% VCC VOL 1.5 V tPLZ ≈VCC 50% VCC Output Waveform 2 S1 at GND (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 1.5 V 0V tPZL tPZH tPLH 50% VCC 3V Output Control VOL + 0.3 V VOL tPHZ 50% VCC VOH – 0.3 V VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns. D. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuit and Voltage Waveforms 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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