SN54HCT273, SN74HCT273 OCTAL D-TYPE FLIP-FLOPS WITH CLEAR SCLS068C – NOVEMBER 1988 – REVISED MAY 1997 D D D D D Inputs Are TTL-Voltage Compatible Contain Eight D-Type Flip-Flops Direct Clear Input Applications Include: – Buffer/Storage Registers – Shift Registers – Pattern Generators Package Options Include Plastic Small-Outline (DW) and Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs SN54HCT273 . . . J OR W PACKAGE SN74HCT273 . . . DW, N, OR PW PACKAGE (TOP VIEW) CLR 1Q 1D 2D 2Q 3Q 3D 4D 4Q GND 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC 8Q 8D 7D 7Q 6Q 6D 5D 5Q CLK description 1D 1Q CLR VCC 2D 2Q 3Q 3D 4D 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 8D 7D 7Q 6Q 6D 4Q GND CLK 5Q 5D Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not directly related to the positive-going pulse. When CLK is at either the high or low level, the D input has no effect at the output. The circuits are designed to prevent false clocking by transitions at CLR. 8Q SN54HCT273 . . . FK PACKAGE (TOP VIEW) These devices are positive-edge-triggered D-type flip-flops with a common enable input. The ’HCT273 are similar to the ’HCT377, but feature a common clear enable (CLR) input instead of a latched clock. The SN54HCT273 is characterized for operation over the full military temperature range of –55°C to 125°C. The SN74HCT273 is characterized for operation from –40°C to 85°C. FUNCTION TABLE (each flip-flop) INPUTS CLR CLK D OUTPUT Q L X X L H ↑ H H H ↑ L L H L X Q0 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1997, Texas Instruments Incorporated UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54HCT273, SN74HCT273 OCTAL D-TYPE FLIP-FLOPS WITH CLEAR SCLS068C – NOVEMBER 1988 – REVISED MAY 1997 logic symbol† 1 CLR R 11 CLK C1 3 1D 2D 3D 4D 5D 6D 7D 8D 2 1D 4 5 7 6 8 9 13 12 14 15 17 16 18 19 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. logic diagram (positive logic) 1D CLK 2D 3 11 3D 4 1D 7 1D C1 5D 8 1D C1 R CLR 4D 13 1D C1 R 6D R 14 1D C1 7D 17 1D C1 R 8D 1D C1 R 18 1D C1 R C1 R R 1 2 1Q 5 6 2Q 3Q 9 12 4Q 15 5Q 6Q 16 7Q 19 8Q logic diagram, each flip-flop (positive logic) D C C TG TG Q C C C C TG CLK(I) TG C C C C R 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54HCT273, SN74HCT273 OCTAL D-TYPE FLIP-FLOPS WITH CLEAR SCLS068C – NOVEMBER 1988 – REVISED MAY 1997 absolute maximum ratings over operating free-air temperature range† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Package thermal impedance, θJA (see Note 2): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace length of zero. recommended operating conditions SN54HCT273 VCC VIH Supply voltage VIL VI Low-level input voltage VO tt TA Operating free-air temperature High-level input voltage VCC = 4.5 V to 5.5 V VCC = 4.5 V to 5.5 V SN74HCT273 MIN NOM MAX MIN NOM MAX 4.5 5 5.5 4.5 5 5.5 2 2 UNIT V V 0 0.8 0 0.8 V Input voltage 0 0 VCC VCC V 0 VCC VCC 0 Output voltage Input transition (rise and fall) times 0 500 0 500 ns –55 125 –40 85 °C V electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TA = 25°C TYP MAX SN54HCT273 MIN MAX SN74HCT273 MIN MAX UNIT VOH VI = VIH or VIL IOH = –20 µA IOH = –4 mA 4.5 V 4.4 4.499 4.4 4.4 4.5 V 3.98 4.30 3.7 3.84 VOL VI = VIH or VIL IOL = 20 µA IOL = 4 mA 4.5 V 0.001 0.1 0.1 0.1 4.5 V 0.17 0.26 0.4 0.33 II ICC VI = VCC or 0 VI = VCC or 0, 5.5 V ±0.1 ±100 ±1000 ±1000 nA 8 160 80 µA 1.4 2.4 3 2.9 mA 3 10 10 10 pF ∆ICC‡ IO = 0 One input at 0.5 V or 2.4 V, Other inputs at 0 or VCC Ci 5.5 V 5.5 V 4.5 V to 5.5 V V V ‡ This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54HCT273, SN74HCT273 OCTAL D-TYPE FLIP-FLOPS WITH CLEAR SCLS068C – NOVEMBER 1988 – REVISED MAY 1997 timing requirements over recommended operating free-air temperature range (unless otherwise noted) VCC fclock l k Clock frequency CLK high or low tw Pulse duration CLR low Data tsu ↑ Setup time before CLK↑ CLR inactive th Hold time data after CLK↑ TA = 25°C MIN MAX SN54HCT273 SN74HCT273 MIN MAX MIN MAX 4.5 V 0 25 0 16 0 20 5.5 V 0 28 0 19 0 23 4.5 V 20 30 25 5.5 V 18 25 22 4.5 V 16 24 20 5.5 V 14 20 17 4.5 V 20 30 25 5.5 V 17 25 21 4.5 V 20 30 25 5.5 V 17 25 21 4.5 V 0 0 0 5.5 V 0 0 0 UNIT MHz ns ns ns switching characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V, CL = 50 pF (unless otherwise noted) (see Figure 1) SN54HCT273 PARAMETER FROM (INPUT) TO (OUTPUT) VCC MIN fmax tpd d CLR Any tPHL CLR Any tt Any TA = 25°C TYP MAX MIN 4.5 V 25 31 16 5.5 V 28 37 19 MAX UNIT MHz 4.5 V 15 34 50 5.5 V 12 29 42 4.5 V 17 15 50 5.5 V 15 34 42 4.5 V 8 18 22 5.5 V 7 19 21 ns ns ns switching characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V, CL = 50 pF (unless otherwise noted) (see Figure 1) SN74HCT273 PARAMETER FROM (INPUT) TO (OUTPUT) fmax tpd d CLR Any tPHL CLR Any tt Any VCC POST OFFICE BOX 655303 MIN 4.5 V 25 31 20 5.5 V 28 37 23 MAX 15 34 42 5.5 V 12 29 36 4.5 V 17 34 42 5.5 V 15 29 36 4.5 V 8 15 19 5.5 V 7 14 17 • DALLAS, TEXAS 75265 UNIT MHz 4.5 V PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 4 TA = 25°C MIN TYP MAX ns ns ns SN54HCT273, SN74HCT273 OCTAL D-TYPE FLIP-FLOPS WITH CLEAR SCLS068C – NOVEMBER 1988 – REVISED MAY 1997 operating characteristics, VCC = 5 V, TA = 25°C PARAMETER Cpd TEST CONDITIONS Power dissipation capacitance No load TYP 30 UNIT pF PARAMETER MEASUREMENT INFORMATION From Output Under Test Test Point 3V High-Level Pulse 1.3 V 0V CL = 50 pF (see Note A) tw 1.3 V 1.3 V 0V 3V 1.3 V 3V Low-Level Pulse LOAD CIRCUIT Input 1.3 V VOLTAGE WAVEFORMS PULSE DURATIONS 1.3 V 0V tPLH In-Phase Output 1.3 V 10% tPHL 90% 90% tr Out-ofPhase Output tPHL 90% VOH Reference 1.3 V Input 10% V OL tf tPLH 1.3 V 10% 1.3 V 10% 90% tf VOH Data Input 1.3 V 0.3 V 3V 1.3 V 0V tsu 2.7 V VOL tr tr VOLTAGE WAVEFORMS SETUP AND HOLD AND INPUT RISE AND FALL TIMES th 2.7 V 3V 1.3 V 0.3 V 0 V tf VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT RISE AND FALL TIMES NOTES: A. CL includes probe and test-fixture capacitance. B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. C. The outputs are measured one at a time with one input transition per measurement. D. For clock inputs, fmax is measured when the input duty cycle is 50%. E. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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