MICROCHIP 24FC515

24AA515/24LC515/24FC515
512K I2C™ CMOS Serial EEPROM
Device Selection Table
Package Type
VCC
Range
Max Clock
Frequency
Temp
Ranges
24AA515
1.8-5.5V
400 kHz†
24LC515
2.5-5.5V
24FC515
2.5-5.5V
†100
PDIP
A0
1
I
A1
2
400 kHz
I
A2
3
1 MHz
I
VSS
4
24AA515/
Part
Number
8
VCC
7
WP
6
SCL
5
SDA
kHz for VCC < 2.5V.
Features
SOIC
1
A1
2
A2
3
VSS
4
8
VCC
7
WP
6
SCL
5
SDA
Block Diagram
A0 A1
I/O
Control
Logic
WP
Memory
Control
Logic
HV Generator
XDEC
EEPROM
Array
Page Latches
I/O
SCL
YDEC
SDA
Description
The Microchip Technology Inc. 24AA515/24LC515/
24FC515 (24XX515*) is a 64K x 8 (512K bit) Serial
Electrically Erasable PROM, capable of operation
across a broad voltage range (1.8V to 5.5V). It has
been developed for advanced, low power applications
such as personal communications or data acquisition.
This device has both byte write and page write capability of up to 64 bytes of data. This device is capable of
both random and sequential reads. Reads may be
sequential within address boundaries 0000h to 7FFFh
& 8000h to FFFFh. Functional address lines allow up to
four devices on the same data bus. This allows for up
to 2 Mbits total system EEPROM memory. This device
is available in the standard 8-pin plastic DIP and SOIC
packages.
 2003 Microchip Technology Inc.
A0
24AA515/
• Low-power CMOS technology
- Maximum write current 3 mA at 5.5V
- Maximum read current 400 µA at 5.5V
- Standby current 100 nA typical at 5.5V
• 2-wire serial interface bus, I2C™ compatible
• Cascadable for up to four devices
• Self-timed ERASE/WRITE cycle
• 64-byte Page Write mode available
• 5 ms max write cycle time
• Hardware write-protect for entire array
• Output slope control to eliminate ground bounce
• Schmitt Trigger inputs for noise suppression
• 100,000 erase/write cycles
• Electrostatic discharge protection > 4000V
• Data retention > 200 years
• 8-pin PDIP, SOIC packages
• Temperature ranges:
- Industrial (I):
-40°C to +85°C
VCC
VSS
Sense AMP
R/W Control
24XX515 is used in this document as a generic part number
for the 24AA515/24LC515/24FC515 devices.
Preliminary
DS21673C-page 1
24AA515/24LC515/24FC515
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings(†)
VCC .............................................................................................................................................................................6.5V
All inputs and outputs w.r.t. VSS ......................................................................................................... -0.6V to VCC +1.0V
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature with power applied ................................................................................................-65°C to +125°C
ESD protection on all pins ......................................................................................................................................................≥ 4 kV
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
TABLE 1-1:
DC CHARACTERISTICS
DC CHARACTERISTICS
Param.
No.
Sym
D1
Characteristic
Industrial (I): VCC = +1.8V to 5.5V TA = -40°C to +85°C
Min
Max
Units
Conditions
A0, A1, SCL, SDA, and
WP pins:
D2
VIH
High-level input voltage
0.7 VCC
—
V
VCC ≥ 2.5V
D3
VIL
Low-level input voltage
—
0.3 VCC
0.2 VCC
V
V
VCC ≥ 2.5V
VCC < 2.5V
D4
VHYS
Hysteresis of Schmitt
Trigger inputs
(SDA, SCL pins)
0.05 VCC
—
V
VCC ≥ 2.5V (Note)
D5
VOL
Low-level output voltage
—
0.40
V
IOL = 3.0 mA @ VCC = 4.5V
IOL = 2.1 mA @ VCC = 2.5V
D6
ILI
Input leakage current
—
±1
µA
VIN = VSS or VCC, WP = VSS
VIN = VSS or VCC, WP = VCC
D7
ILO
Output leakage current
—
±1
µA
VOUT = VSS or VCC
D8
CIN,
COUT
Pin capacitance
(all inputs/outputs)
—
10
pF
VCC = 5.0V (Note)
TA = 25°C, fC= 1 MHz
D9
ICC Read Operating current
—
400
µA
VCC = 5.5V, SCL = 400 kHz
—
3
mA
VCC = 5.5V
—
5
µA
SCL = SDA = VCC = 5.5V
A0, A1, WP = VSS, A2 = VCC
ICC Write
D10
Note:
Iccs
Standby current
This parameter is periodically sampled and not 100% tested.
DS21673C-page 2
Preliminary
 2003 Microchip Technology Inc.
24AA515/24LC515/24FC515
TABLE 1-2:
AC CHARACTERISTICS
AC CHARACTERISTICS
Param.
No.
Sym
Industrial (I):
Characteristic
VCC = +1.8V to 5.5V TA = -40°C to +85°C
Min.
Max.
Units
Conditions
1
FCLK
Clock frequency
—
—
—
100
400
1000
kHz
1.8V ≤ VCC ≤ 2.5V
2.5V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V (24FC515 only)
2
THIGH
Clock high time
4000
600
500
—
—
—
ns
1.8V ≤ VCC ≤ 2.5V
2.5V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V (24FC515 only)
3
TLOW
Clock low time
4700
1300
500
—
—
—
ns
1.8V ≤ VCC ≤ 2.5V
2.5V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V (24FC515 only)
4
TR
SDA and SCL rise time
(Note 1)
—
—
—
1000
300
300
ns
1.8V ≤ VCC ≤ 2.5V
2.5V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V (24FC515 only)
5
TF
SDA and SCL fall time
(Note 1)
—
—
300
100
ns
All except, 24FC515
2.5V ≤ VCC ≤ 5.5V (24FC515 only)
6
THD:STA Start condition hold time
4000
600
250
—
—
—
ns
1.8V ≤ VCC ≤ 2.5V
2.5V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V (24FC515 only)
7
TSU:STA
4700
600
250
—
—
—
ns
1.8V ≤ VCC ≤ 2.5V
2.5V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V (24FC515 only)
Start condition setup time
8
THD:DAT Data input hold time
9
TSU:DAT
10
0
—
ns
(Note 2)
250
100
100
—
—
—
ns
1.8V ≤ VCC ≤ 2.5V
2.5V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V (24FC515 only)
TSU:STO Stop condition setup time
4000
600
250
—
—
—
ns
1.8V ≤ VCC ≤ 2.5V
2.5V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V (24FC515 only)
11
TSU:WP
WP setup time
4000
600
600
—
—
—
ns
1.8V ≤ VCC ≤ 2.5V
2.5V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V (24FC515 only)
12
THD:WP
WP hold time
4700
1300
1300
—
—
—
ns
1.8V ≤ VCC ≤ 2.5V
2.5V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V (24FC515 only)
13
TAA
Output valid from clock
(Note 2)
—
—
—
3500
900
400
ns
1.8V ≤ VCC ≤ 2.5V
2.5V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V (24FC515 only)
14
TBUF
Bus free time: Time the bus
must be free before a new
transmission can start
4700
1300
500
—
—
—
ns
1.8V ≤ VCC ≤ 2.5V
2.5V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V (24FC515 only)
15
TOF
Output fall time from VIH
minimum to VIL maximum
CB ≤ 100 pF
10 + 0.1CB
250
250
ns
All except, 24FC515 (Note 1)
24FC515 (Note 1)
16
TSP
Input filter spike suppression
(SDA and SCL pins)
—
50
ns
All except, 24FC515 (Notes 1 and 3)
17
TWC
Write cycle time (byte or page)
—
5
ms
1M
—
cycles
18
Data input setup time
Endurance
Note 1:
25°C, VCC = 5.0V, Block mode (Note 4)
Not 100% tested. CB = total capacitance of one bus line in pF.
2:
As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum
300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
3:
The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs which provide improved noise spike
suppression. This eliminates the need for a TI specification for standard operation.
4:
This parameter is not tested but established by characterization. For endurance estimates in a specific application,
please consult the Total Endurance™ Model which can be obtained from Microchip’s web site @www.microchip.com.
 2003 Microchip Technology Inc.
Preliminary
DS21673C-page 3
24AA515/24LC515/24FC515
FIGURE 1-1:
BUS TIMING DATA
5
SCL
7
SDA
IN
3
4
D4
2
8
10
9
6
16
14
13
SDA
OUT
WP
DS21673C-page 4
(protected)
(unprotected)
Preliminary
11
12
 2003 Microchip Technology Inc.
24AA515/24LC515/24FC515
2.0
PIN DESCRIPTIONS
2.4
This input is used to synchronize the data transfer from
and to the device.
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1:
PIN FUNCTION TABLE
Name PDIP SOIC
A0
1
1
2.5
Function
User Configurable Chip Select
A1
2
2
User Configurable Chip Select
A2
3
3
Non-Configurable Chip Select.
This pin must be hard wired to
logical 1 state (VCC). Device
will not operate with this pin
left floating or held to logical 0
(VSS).
VSS
4
4
Ground
SDA
5
5
Serial Data
SCL
6
6
Serial Clock
WP
7
7
Write-Protect Input
VCC
8
8
+1.8 to 5.5V (24AA515)
+2.5 to 5.5V (24LC515)
+4.5 to 5.5V (24FC515)
2.1
Serial Clock (SCL)
This pin can be connected to either VSS, VCC or left
floating. An internal pull-down resistor on this pin will
keep this device in the unprotected state if left floating.
If tied to VSS or left floating, normal memory operation
is enabled (read/write the entire memory 0000hFFFFh).
If tied to VCC, write operations are inhibited. Read
operations are not affected.
3.0
A0, A1 Chip Address Inputs
The A0, A1 inputs are used by the 24XX515 for multiple
device operations. The levels on these inputs are
compared with the corresponding bits in the slave
address. The chip is selected if the compare is true.
Write-Protect (WP)
FUNCTIONAL DESCRIPTION
The 24XX515 supports a bidirectional 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as a transmitter, and a device
receiving data as a receiver. The bus must be
controlled by a master device which generates the
serial clock (SCL), controls the bus access, and
generates the Start and Stop conditions while the
24XX515 works as a slave. Both master and slave can
operate as a transmitter or receiver, but the master
device determines which mode is activated.
Up to four devices may be connected to the same bus
by using different Chip Select bit combinations. If left
unconnected, these inputs will be pulled down
internally to VSS.
2.2
A2 Chip Address Input
The A2 input is non-configurable Chip Select. This pin
must be tied to VCC in order for this device to operate.
2.3
Serial Data (SDA)
This is a bidirectional pin used to transfer addresses
and data into and data out of the device. It is an opendrain terminal, therefore, the SDA bus requires a pullup resistor to VCC (typical 10 kΩ for 100 kHz, 2 kΩ for
400 kHz and 1 MHz).
For normal data transfer SDA is allowed to change only
during SCL low. Changes during SCL high are
reserved for indicating the Start and Stop conditions.
 2003 Microchip Technology Inc.
Preliminary
DS21673C-page 5
24AA515/24LC515/24FC515
4.0
BUS CHARACTERISTICS
The data on the line must be changed during the low
period of the clock signal. There is one bit of data per
clock pulse.
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus
is not busy.
• During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
the data line while the clock line is high will be
interpreted as a Start or Stop condition.
Each data transfer is initiated with a Start condition and
terminated with a Stop condition. The number of the
data bytes transferred between the Start and Stop
conditions is determined by the master device.
4.5
Accordingly, the following bus conditions have been
defined (Figure 4-1).
4.1
Acknowledge
Each receiving device, when addressed, is obliged to
generate an Acknowledge signal after the reception of
each byte. The master device must generate an extra
clock pulse which is associated with this Acknowledge
bit.
Bus not Busy (A)
Both data and clock lines remain high.
Note:
4.2
Start Data Transfer (B)
A high-to-low transition of the SDA line while the clock
(SCL) is high determines a Start condition. All
commands must be preceded by a Start condition.
4.3
A device that acknowledges must pull-down the SDA
line during the Acknowledge clock pulse in such a way
that the SDA line is stable low during the high period of
the acknowledge related clock pulse. Of course, setup
and hold times must be taken into account. During
reads, a master must signal an end of data to the slave
by NOT generating an Acknowledge bit on the last byte
that has been clocked out of the slave. In this case, the
slave (24XX515) will leave the data line high to enable
the master to generate the Stop condition.
Stop Data Transfer (C)
A low-to-high transition of the SDA line while the clock
(SCL) is high determines a Stop condition. All
operations must end with a Stop condition.
4.4
The 24XX515 does not generate any
Acknowledge bits if an internal programming cycle is in progress.
Data Valid (D)
The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.
FIGURE 4-1:
(A)
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(B)
(D)
(D)
Start
Condition
Address or
Acknowledge
Valid
(C)
(A)
SCL
SDA
FIGURE 4-2:
Data
Allowed
To Change
Stop
Condition
ACKNOWLEDGE TIMING
Acknowledge
Bit
SCL
SDA
1
2
3
4
5
6
7
8
1
2
3
Data from transmitter
Data from transmitter
Transmitter must release the SDA line at this point
allowing the Receiver to pull the SDA line low to
acknowledge the previous eight bits of data.
DS21673C-page 6
9
Preliminary
Receiver must release the SDA line at this point
so the Transmitter can continue sending data.
 2003 Microchip Technology Inc.
24AA515/24LC515/24FC515
5.0
DEVICE ADDRESSING
FIGURE 5-1:
A control byte is the first byte received following the
Start condition from the master device (Figure 5-1).
The control byte consists of a 4-bit control code; for the
24XX515, this is set as ‘1010’ binary for read and write
operations. The next bit of the control byte is the block
select bit (B0). This bit acts as the A15 address bit for
accessing the entire array. The next two bits of the
control byte are the Chip Select bits (A1, A0). The Chip
Select bits allow the use of up to four 24XX515 devices
on the same bus and are used to select which device is
accessed. The Chip Select bits in the control byte must
correspond to the logic levels on the corresponding A1
and A0 pins for the device to respond. These bits are in
effect the two Most Significant bits of the word address.
The last bit of the control byte defines the operation to
be performed. When set to a one, a read operation is
selected, and when set to a zero, a write operation is
selected. The next two bytes received define the
address of the first data byte (Figure 5-2). Because
only A14…A0 are used, the upper address bit is a don’t
care. The upper address bits are transferred first,
followed by the less significant bits.
Following the Start condition, the 24XX515 monitors
the SDA bus checking the device type identifier being
transmitted. Upon receiving a ‘1010’ code and appropriate device select bits, the slave device outputs an
Acknowledge signal on the SDA line. Depending on the
state of the R/W bit, the 24XX515 will select a read or
write operation.
CONTROL BYTE
FORMAT
Read/Write Bit
Chip Select
Bits
Control Code
S
1
0
1
0
B0
A1
A0 R/W ACK
Slave Address
Start Bit
5.1
Acknowledge Bit
Contiguous Addressing Across
Multiple Devices
The Chip Select bits A1, A0 can be used to expand the
contiguous address space for up to 2 Mbit by adding up
to four 24XX515's on the same bus. In this case,
software can use A0 of the control byte as address bit
A16 and A1 as address bit A17. It is not possible to
sequentially read across device boundaries.
Each device has internal addressing boundary
limitations. This divides each part into two segments of
256K bits. The block select bit ‘B0’ controls access to
each “half” rather than address bit location A15.
Sequential read operations are limited to 256K blocks.
To read through four devices on the same bus, eight
random Read commands must be given.
This device has an internal addressing boundary
limitation that is divided into two segments of 256K bits.
Block select bit ‘B0’ is used in place of address bit
location ‘A15’ to control access to each segment.
FIGURE 5-2:
ADDRESS SEQUENCE BIT ASSIGNMENTS
CONTROL BYTE
1
0
1
0
B
0
A
1
ADDRESS HIGH BYTE
A
0 R/W
X
A A A A A
14 13 12 11 10
A
9
CONTROL BLOCK CHIP
SELECT SELECT
CODE
BIT
BITS
 2003 Microchip Technology Inc.
ADDRESS LOW BYTE
A
8
A
7
•
•
•
•
•
•
A
0
X = Don’t Care Bit
Preliminary
DS21673C-page 7
24AA515/24LC515/24FC515
6.0
WRITE OPERATIONS
6.1
Byte Write
6.3
Following the Start condition from the master, the
control code (four bits), the block select (one bit) the
Chip Select (two bits), and the R/W bit (which is a logic
low) are clocked onto the bus by the master transmitter.
This indicates to the addressed slave receiver that the
address high byte will follow after it has generated an
Acknowledge bit during the ninth clock cycle. Therefore, the next byte transmitted by the master is the
high-order byte of the word address and will be written
into the address pointer of the 24XX515. The next byte
is the Least Significant Address Byte. After receiving
another Acknowledge signal from the 24XX515, the
master device will transmit the data word to be written
into the addressed memory location. The 24XX515
acknowledges again and the master generates a Stop
condition. This initiates the internal write cycle and during this time, the 24XX515 will not generate Acknowledge signals (Figure 6-1). If an attempt is made to write
to the array with the WP pin held high, the device will
acknowledge the command but no write cycle will
occur, no data will be written, and the device will
immediately accept a new command. After a byte Write
command, the internal address counter will point to the
address location following the one that was just written.
6.2
Write Protection
The WP pin allows the user to write-protect the entire
array (0000-FFFF) when the pin is tied to VCC. If tied to
VSS or left floating, the write protection is disabled. The
WP pin is sampled at the Stop bit for every Write
command (Figure 1-1) Toggling the WP pin after the
Stop bit will have no effect on the execution of the write
cycle.
Note:
Page write operations are limited to writing
bytes within a single physical page,
regardless of the number of bytes actually
being written. Physical page boundaries
start at addresses that are integer
multiples of the page buffer size (or ‘page
size’) and end at addresses that are
integer multiples of [page size - 1]. If a
Page Write command attempts to write
across a physical page boundary, the
result is that the data wraps around to the
beginning of the current page (overwriting
data previously stored there), instead of
being written to the next page as might be
expected. It is therefore necessary for the
application software to prevent page write
operations that would attempt to cross a
page boundary.
Page Write
The write control byte, word address, and the first data
byte are transmitted to the 24XX515 in the same way
as in a byte write. But instead of generating a Stop
condition, the master transmits up to 63 additional
bytes, which are temporarily stored in the on-chip page
buffer and will be written into memory after the master
has transmitted a Stop condition. After receipt of each
word, the six lower address pointer bits are internally
incremented by one. If the master should transmit more
than 64 bytes prior to generating the Stop condition, the
address counter will roll over and the previously
received data will be overwritten. As with the byte write
operation, once the Stop condition is received, an
internal write cycle will begin (Figure 6-2). If an attempt
is made to write to the array with the WP pin held high,
the device will acknowledge the command but no write
cycle will occur, no data will be written, and the device
will immediately accept a new command.
DS21673C-page 8
Preliminary
 2003 Microchip Technology Inc.
24AA515/24LC515/24FC515
FIGURE 6-1:
BYTE WRITE
BUS ACTIVITY
MASTER
S
T
A
R
T
CONTROL
BYTE
ADDRESS
HIGH BYTE
AA
S1 0 1 0B
0 10 0
SDA LINE
S
T
O
P
DATA
X
P
A
C
K
BUS ACTIVITY
ADDRESS
LOW BYTE
A
C
K
A
C
K
A
C
K
X = don’t care bit
FIGURE 6-2:
BUS ACTIVITY
MASTER
SDA LINE
PAGE WRITE
S
T
A
R
T
CONTROL
BYTE
ADDRESS
HIGH BYTE
BAA
S10 1 0 0 1 00
BUS ACTIVITY
ADDRESS
LOW BYTE
DATA BYTE 0
S
T
O
P
DATA BYTE 63
X
A
C
K
P
A
C
K
A
C
K
A
C
K
A
C
K
X = don’t care bit
 2003 Microchip Technology Inc.
Preliminary
DS21673C-page 9
24AA515/24LC515/24FC515
7.0
ACKNOWLEDGE POLLING
FIGURE 7-1:
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (This feature can be used to maximize bus
throughput.) Once the Stop condition for a Write
command has been issued from the master, the device
initiates the internally timed write cycle. ACK polling
can be initiated immediately. This involves the master
sending a Start condition, followed by the control byte
for a Write command (R/W = 0). If the device is still
busy with the write cycle, then no ACK will be returned.
If no ACK is returned, then the Start bit and control byte
must be resent. If the cycle is complete, then the device
will return the ACK, and the master can then proceed
with the next Read or Write command. See Figure 7-1
for flow diagram.
ACKNOWLEDGE
POLLING FLOW
Send
Write Command
Send Stop
Condition to
Initiate Write Cycle
Send Start
Send Control Byte
with R/W = 0
Did Device
Acknowledge
(ACK = 0)?
NO
YES
Next
Operation
DS21673C-page 10
Preliminary
 2003 Microchip Technology Inc.
24AA515/24LC515/24FC515
8.0
READ OPERATION
8.2
Read operations are initiated in the same way as write
operations with the exception that the R/W bit of the
control byte is set to one. There are three basic types
of read operations: current address read, random read,
and sequential read.
8.1
Current Address Read
The 24XX515 contains an address counter that maintains the address of the last word accessed, internally
incremented by one. Therefore, if the previous read
access was to address n (n is any legal address), the
next current address read operation would access data
from address n + 1.
Upon receipt of the control byte with R/W bit set to one,
the 24XX515 issues an acknowledge and transmits the
8-bit data word. The master will not acknowledge the
transfer but does generate a Stop condition and the
24XX515 discontinues transmission (Figure 8-1).
FIGURE 8-1:
CURRENT ADDRESS
READ
BUS ACTIVITY
MASTER
S
T
A
R
T
SDA LINE
S 1 0 1 0 B AA 1
0 1 0
CONTROL
BYTE
BUS ACTIVITY
 2003 Microchip Technology Inc.
S
T
O
P
DATA
BYTE
P
A
C
K
N
O
A
C
K
Random Read
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, first the word address must
be set. This is done by sending the word address to the
24XX515 as part of a write operation (R/W bit set to 0).
After the word address is sent, the master generates a
Start condition following the acknowledge. This terminates the write operation, but not before the internal
address pointer is set. Then, the master issues the
control byte again but with the R/W bit set to a one. The
24XX515 will then issue an acknowledge and transmit
the 8-bit data word. The master will not acknowledge
the transfer but does generate a Stop condition which
causes the 24XX515 to discontinue transmission
(Figure 8-2). After a random Read command, the internal address counter will point to the address location
following the one that was just read.
8.3
Sequential Read
Sequential reads are initiated in the same way as a
random read except that after the 24XX515 transmits
the first data byte, the master issues an acknowledge
as opposed to the Stop condition used in a random
read. This acknowledge directs the 24XX515 to transmit the next sequentially addressed 8-bit word
(Figure 8-3). Following the final byte transmitted to the
master, the master will NOT generate an acknowledge
but will generate a Stop condition. To provide sequential reads, the 24XX515 contains an internal address
pointer which is incremented by one at the completion
of each operation. This address pointer allows half the
memory contents to be serially read during one operation. Sequential read address boundaries are 0000h to
7FFFh and 8000h to FFFFh. The internal address
pointer will automatically roll over from address 7FFF to
address 0000 if the master acknowledges the byte
received from the array address 7FFF. The internal
address counter will automatically roll over from
address FFFFh to address 8000h if the master
acknowledges the byte received from the array
address FFFFh.
Preliminary
DS21673C-page 11
24AA515/24LC515/24FC515
FIGURE 8-2:
BUS ACTIVITY
MASTER
SDA LINE
RANDOM READ
S
T
A
R
T
CONTROL
BYTE
S 1 0 1 0
ADDRESS
HIGH BYTE
B A A
0
0 1 0
X
CONTROL
BYTE
S 1 0 1 0
A
C
K
BUS ACTIVITY
S
T
A
R
T
ADDRESS
LOW BYTE
A
C
K
A
C
K
DATA n + 1
DATA n + 2
S
T
O
P
DATA
BYTE
B A A
1
0 1 0
P
N
O
A
C
K
A
C
K
X = Don’t Care Bit
FIGURE 8-3:
BUS ACTIVITY
MASTER
SEQUENTIAL READ
CONTROL
BYTE
DATA n
S
T
O
P
DATA n + X
P
SDA LINE
BUS ACTIVITY
DS21673C-page 12
A
C
K
A
C
K
Preliminary
A
C
K
A
C
K
N
O
A
C
K
 2003 Microchip Technology Inc.
24AA515/24LC515/24FC515
9.0
PACKAGING INFORMATION
9.1
Package Marking Information
8-Lead PDIP (300 mil)
Example:
XXXXXXXX
XXXXXNNN
YYWW
24LC515
I/PNNN
YYWW
8-Lead SOIC (208 mil)
Example:
XXXXXXXX
XXXXXXXX
YYWWNNN
Legend:
Note:
*
XX...X
YY
WW
NNN
24LC515
I/SM
YYWWNNN
Customer specific information*
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line thus limiting the number of available characters
for customer specific information.
Standard marking consists of Microchip part number, year code, week code, traceability code (facility
code, mask rev#, and assembly code). For marking beyond this, certain price adders apply. Please
 2003 Microchip Technology Inc.
Preliminary
DS21673C-page 13
24AA515/24LC515/24FC515
8-Lead Plastic Dual In-line (P) – 300 mil (PDIP)
E1
D
2
n
1
α
E
A2
A
L
c
A1
β
B1
p
eB
B
Units
Dimension Limits
n
p
Number of Pins
Pitch
Top to Seating Plane
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
Tip to Seating Plane
Lead Thickness
Upper Lead Width
Lower Lead Width
Overall Row Spacing
Mold Draft Angle Top
Mold Draft Angle Bottom
* Controlling Parameter
§ Significant Characteristic
A
A2
A1
E
E1
D
L
c
§
B1
B
eB
α
β
MIN
.140
.115
.015
.300
.240
.360
.125
.008
.045
.014
.310
5
5
INCHES*
NOM
MAX
8
.100
.155
.130
.170
.145
.313
.250
.373
.130
.012
.058
.018
.370
10
10
.325
.260
.385
.135
.015
.070
.022
.430
15
15
MILLIMETERS
NOM
8
2.54
3.56
3.94
2.92
3.30
0.38
7.62
7.94
6.10
6.35
9.14
9.46
3.18
3.30
0.20
0.29
1.14
1.46
0.36
0.46
7.87
9.40
5
10
5
10
MIN
MAX
4.32
3.68
8.26
6.60
9.78
3.43
0.38
1.78
0.56
10.92
15
15
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-018
DS21673C-page 14
Preliminary
 2003 Microchip Technology Inc.
24AA515/24LC515/24FC515
8-Lead Plastic Small Outline (SM) – Medium, 208 mil (SOIC)
E
E1
p
D
2
1
n
B
α
c
A2
A
φ
β
L
Units
Dimension Limits
n
p
Number of Pins
Pitch
Overall Height
Molded Package Thickness
Standoff §
Overall Width
Molded Package Width
Overall Length
Foot Length
Foot Angle
Lead Thickness
Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
A
A2
A1
E
E1
D
L
φ
c
B
α
β
MIN
.070
.069
.002
.300
.201
.202
.020
0
.008
.014
0
0
INCHES*
NOM
8
.050
.075
.074
.005
.313
.208
.205
.025
4
.009
.017
12
12
A1
MAX
.080
.078
.010
.325
.212
.210
.030
8
.010
.020
15
15
MILLIMETERS
NOM
8
1.27
1.78
1.97
1.75
1.88
0.05
0.13
7.62
7.95
5.11
5.28
5.13
5.21
0.51
0.64
0
4
0.20
0.23
0.36
0.43
0
12
0
12
MIN
MAX
2.03
1.98
0.25
8.26
5.38
5.33
0.76
8
0.25
0.51
15
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
Drawing No. C04-056
 2003 Microchip Technology Inc.
Preliminary
DS21673C-page 15
24AA515/24LC515/24FC515
APPENDIX A:
REVISION HISTORY
Revision C
Corrections to Section 1.0, Electrical Characteristics.
DS21673C-page 16
Preliminary
 2003 Microchip Technology Inc.
24AA515/24LC515/24FC515
ON-LINE SUPPORT
Microchip provides on-line support on the Microchip
World Wide Web site.
The web site is used by Microchip as a means to make
files and information easily available to customers. To
view the site, the user must have access to the Internet
and a web browser, such as Netscape® or Microsoft®
Internet Explorer. Files are also available for FTP
download from our FTP site.
SYSTEMS INFORMATION AND
UPGRADE HOT LINE
The Systems Information and Upgrade Line provides
system users a listing of the latest versions of all of
Microchip's development systems software products.
Plus, this line provides information on how customers
can receive the most current upgrade kits. The Hot Line
Numbers are:
1-800-755-2345 for U.S. and most of Canada, and
1-480-792-7302 for the rest of the world.
Connecting to the Microchip Internet
Web Site
042003
The Microchip web site is available at the following
URL:
www.microchip.com
The file transfer site is available by using an FTP
service to connect to:
ftp://ftp.microchip.com
The web site and file transfer site provide a variety of
services. Users may download files for the latest
Development Tools, Data Sheets, Application Notes,
User's Guides, Articles and Sample Programs. A variety of Microchip specific business information is also
available, including listings of Microchip sales offices,
distributors and factory representatives. Other data
available for consideration is:
• Latest Microchip Press Releases
• Technical Support Section with Frequently Asked
Questions
• Design Tips
• Device Errata
• Job Postings
• Microchip Consultant Program Member Listing
• Links to other useful web sites related to
Microchip Products
• Conferences for products, Development Systems,
technical information and more
• Listing of seminars and events
 2003 Microchip Technology Inc.
Preliminary
DS21673C-page 17
24AA515/24LC515/24FC515
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this document.
To:
Technical Publications Manager
RE:
Reader Response
Total Pages Sent ________
From: Name
Company
Address
City / State / ZIP / Country
Telephone: (_______) _________ - _________
FAX: (______) _________ - _________
Application (optional):
Would you like a reply?
Y
N
Device: 24AA515/24LC515/24FC515
Literature Number: DS21673C
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
DS21673C-page 18
Preliminary
 2003 Microchip Technology Inc.
24AA515/24LC515/24FC515
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
Device
X
/XX
Temperature
Range
Examples:
Package
a)
b)
Device
512K Bit 1.8V I2C CMOS Serial EEPROM
512K Bit 1.8V I2C CMOS Serial EEPROM
(Tape and Reel)
512K Bit 2.5V I2C CMOS Serial EEPROM
512K Bit 2.5V I2C CMOS Serial EEPROM
(Tape and Reel)
512K Bit 2.5V I2C CMOS Serial EEPROM
512K Bit 2.5V I2C CMOS Serial EEPROM
(Tape and Reel)
24AA515: =
24AA515T: =
24LC515: =
24LC515T: =
24FC515: =
24FC515T: =
Temperature Range
I
Package
P
SM
=
c)
d)
24AA515T-I/SM: Tape and Reel, Industrial
Temperature, SOIC package.
24LC515-I/P: Industrial Temperature, PDIP
package.
24LC515-I/SM: Industrial Temperature,
SOIC package.
24LC515T-I/SM: Tape and Reel, Industrial
Temperature, SOIC package.
-40°C to +85°C
=
=
Plastic DIP (300 mil Body), 8-lead
Plastic SOIC (208 mil Body), 8-lead
SALES AND SUPPORT
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1.
2.
3.
Your local Microchip sales office
The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277
The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
New Customer Notification System
Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
 2003 Microchip Technology Inc.
Preliminary
DS21673C-page 19
24AA515/24LC515/24FC515
NOTES:
DS21673C-page 20
Preliminary
 2003 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is intended through suggestion only
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
No representation or warranty is given and no liability is
assumed by Microchip Technology Incorporated with respect
to the accuracy or use of such information, or infringement of
patents or other intellectual property rights arising from such
use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with
express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property
rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, MPLAB, PIC, PICmicro, PICSTART,
PRO MATE and PowerSmart are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
AmpLab, FilterLab, microID, MXDEV, MXLAB, PICMASTER,
SEEVAL and The Embedded Control Solutions Company are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.
Application Maestro, dsPICDEM, dsPICDEM.net, ECAN,
ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, microPort,
Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM,
PICkit, PICDEM, PICDEM.net, PowerCal, PowerInfo,
PowerMate, PowerTool, rfLAB, rfPIC, Select Mode,
SmartSensor, SmartShunt, SmartTel and Total Endurance are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
Serialized Quick Turn Programming (SQTP) is a service mark
of Microchip Technology Incorporated in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2003, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999
and Mountain View, California in March 2002.
The Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals,
non-volatile memory and analog products. In
addition, Microchip’s quality system for the
design and manufacture of development
systems is ISO 9001 certified.
 2003 Microchip Technology Inc.
Preliminary
DS21673C-page 21
WORLDWIDE SALES AND SERVICE
AMERICAS
ASIA/PACIFIC
Korea
Corporate Office
Australia
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support: 480-792-7627
Web Address: http://www.microchip.com
Suite 22, 41 Rawson Street
Epping 2121, NSW
Australia
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
168-1, Youngbo Bldg. 3 Floor
Samsung-Dong, Kangnam-Ku
Seoul, Korea 135-882
Tel: 82-2-554-7200 Fax: 82-2-558-5932 or
82-2-558-5934
Atlanta
Unit 915
Bei Hai Wan Tai Bldg.
No. 6 Chaoyangmen Beidajie
Beijing, 100027, No. China
Tel: 86-10-85282100
Fax: 86-10-85282104
3780 Mansell Road, Suite 130
Alpharetta, GA 30022
Tel: 770-640-0034
Fax: 770-640-0307
Boston
2 Lan Drive, Suite 120
Westford, MA 01886
Tel: 978-692-3848
Fax: 978-692-3821
Chicago
333 Pierce Road, Suite 180
Itasca, IL 60143
Tel: 630-285-0071
Fax: 630-285-0075
Dallas
4570 Westgrove Drive, Suite 160
Addison, TX 75001
Tel: 972-818-7423
Fax: 972-818-2924
Detroit
Tri-Atria Office Building
32255 Northwestern Highway, Suite 190
Farmington Hills, MI 48334
Tel: 248-538-2250
Fax: 248-538-2260
Kokomo
2767 S. Albright Road
Kokomo, IN 46902
Tel: 765-864-8360
Fax: 765-864-8387
Los Angeles
China - Beijing
China - Chengdu
Rm. 2401-2402, 24th Floor,
Ming Xing Financial Tower
No. 88 TIDU Street
Chengdu 610016, China
Tel: 86-28-86766200
Fax: 86-28-86766599
China - Fuzhou
Unit 28F, World Trade Plaza
No. 71 Wusi Road
Fuzhou 350001, China
Tel: 86-591-7503506
Fax: 86-591-7503521
China - Hong Kong SAR
Unit 901-6, Tower 2, Metroplaza
223 Hing Fong Road
Kwai Fong, N.T., Hong Kong
Tel: 852-2401-1200
Fax: 852-2401-3431
China - Shanghai
Room 701, Bldg. B
Far East International Plaza
No. 317 Xian Xia Road
Shanghai, 200051
Tel: 86-21-6275-5700
Fax: 86-21-6275-5060
China - Shenzhen
18201 Von Karman, Suite 1090
Irvine, CA 92612
Tel: 949-263-1888
Fax: 949-263-1338
Rm. 1812, 18/F, Building A, United Plaza
No. 5022 Binhe Road, Futian District
Shenzhen 518033, China
Tel: 86-755-82901380
Fax: 86-755-8295-1393
Phoenix
China - Shunde
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7966
Fax: 480-792-4338
Room 401, Hongjian Building
No. 2 Fengxiangnan Road, Ronggui Town
Shunde City, Guangdong 528303, China
Tel: 86-765-8395507 Fax: 86-765-8395571
San Jose
China - Qingdao
2107 North First Street, Suite 590
San Jose, CA 95131
Tel: 408-436-7950
Fax: 408-436-7955
Rm. B505A, Fullhope Plaza,
No. 12 Hong Kong Central Rd.
Qingdao 266071, China
Tel: 86-532-5027355 Fax: 86-532-5027205
Toronto
India
6285 Northam Drive, Suite 108
Mississauga, Ontario L4V 1X5, Canada
Tel: 905-673-0699
Fax: 905-673-6509
Divyasree Chambers
1 Floor, Wing A (A3/A4)
No. 11, O’Shaugnessey Road
Bangalore, 560 025, India
Tel: 91-80-2290061 Fax: 91-80-2290062
Japan
Benex S-1 6F
3-18-20, Shinyokohama
Kohoku-Ku, Yokohama-shi
Kanagawa, 222-0033, Japan
Tel: 81-45-471- 6166 Fax: 81-45-471-6122
DS21673C-page 22
Preliminary
Singapore
200 Middle Road
#07-02 Prime Centre
Singapore, 188980
Tel: 65-6334-8870 Fax: 65-6334-8850
Taiwan
Kaohsiung Branch
30F - 1 No. 8
Min Chuan 2nd Road
Kaohsiung 806, Taiwan
Tel: 886-7-536-4818
Fax: 886-7-536-4803
Taiwan
Taiwan Branch
11F-3, No. 207
Tung Hua North Road
Taipei, 105, Taiwan
Tel: 886-2-2717-7175 Fax: 886-2-2545-0139
EUROPE
Austria
Durisolstrasse 2
A-4600 Wels
Austria
Tel: 43-7242-2244-399
Fax: 43-7242-2244-393
Denmark
Regus Business Centre
Lautrup hoj 1-3
Ballerup DK-2750 Denmark
Tel: 45-4420-9895 Fax: 45-4420-9910
France
Parc d’Activite du Moulin de Massy
43 Rue du Saule Trapu
Batiment A - ler Etage
91300 Massy, France
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
Germany
Steinheilstrasse 10
D-85737 Ismaning, Germany
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Italy
Via Quasimodo, 12
20025 Legnano (MI)
Milan, Italy
Tel: 39-0331-742611
Fax: 39-0331-466781
Netherlands
P. A. De Biesbosch 14
NL-5152 SC Drunen, Netherlands
Tel: 31-416-690399
Fax: 31-416-690340
United Kingdom
505 Eskdale Road
Winnersh Triangle
Wokingham
Berkshire, England RG41 5TU
Tel: 44-118-921-5869
Fax: 44-118-921-5820
07/28/03
 2003 Microchip Technology Inc.