STM32F101xC STM32F101xD STM32F101xE High-density access line, ARM-based 32-bit MCU with 256 to 512 KB Flash, 9 timers, 1 ADC and 10 communication interfaces Features ■ ■ ■ ■ ■ Core: ARM 32-bit Cortex™-M3 CPU – 36 MHz maximum frequency, 1.25 DMIPS/MHz (Dhrystone 2.1) performance – Single-cycle multiplication and hardware division Memories – 256 to 512 Kbytes of Flash memory – up to 48 Kbytes of SRAM – Flexible static memory controller with 4 Chip Select. Supports Compact Flash, SRAM, PSRAM, NOR and NAND memories – LCD parallel interface, 8080/6800 modes Clock, reset and supply management – 2.0 to 3.6 V application supply and I/Os – POR, PDR, and programmable voltage detector (PVD) – 4-to-16 MHz crystal oscillator – Internal 8 MHz factory-trimmed RC – Internal 40 kHz RC with calibration capability – 32 kHz oscillator for RTC with calibration Low power – Sleep, Stop and Standby modes – VBAT supply for RTC and backup registers 1 x 12-bit, 1 µs A/D converters (up to 16 channels) – Conversion range: 0 to 3.6 V – Temperature sensor ■ 2 × 12-bit D/A converters ■ DMA – 12-channel DMA controller – Peripherals supported: timers, ADC, DAC, SPIs, I2Cs and USARTs ■ LQFP144 20 × 20 mm LQFP100 14 × 14 mm LQFP64 10 × 10 mm – 51/80/112 I/Os, all mappable on 16 external interrupt vectors and almost all 5 V-tolerant ■ Debug mode – Serial wire debug (SWD) & JTAG interfaces – Cortex-M3 Embedded Trace Macrocell™ ■ Up to 9 timers – Up to four 16-bit timers, each with up to 4 IC/OC/PWM or pulse counters – 2 × watchdog timers (Independent and Window) – SysTick timer: a 24-bit downcounter – 2 × 16-bit basic timers to drive the DAC ■ Up to 10 communication interfaces – Up to 2 x I2C interfaces (SMBus/PMBus) – Up to 5 USARTs (ISO 7816 interface, LIN, IrDA capability, modem control) – Up to 3 SPIs (18 Mbit/s) ■ CRC calculation unit, 96-bit unique ID ■ ECOPACK® packages Table 1. Device summary Reference Part number STM32F101xC STM32F101RC STM32F101VC STM32F101ZC STM32F101xD STM32F101RD STM32F101VD STM32F101ZD STM32F101xE STM32F101RE STM32F101ZE STM32F101VE Up to 112 fast I/O ports April 2011 Doc ID 14610 Rev 8 1/112 www.st.com 1 Contents STM32F101xC, STM32F101xD, STM32F101xE Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 2/112 2.1 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2 Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.3 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.3.1 ARM® Cortex™-M3 core with embedded Flash and SRAM . . . . . . . . . 14 2.3.2 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.3 CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . 15 2.3.4 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.5 FSMC (flexible static memory controller) . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.6 LCD parallel interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.7 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 16 2.3.8 External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . 16 2.3.9 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.3.10 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.3.11 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.3.12 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.3.13 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.3.14 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.3.15 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.3.16 RTC (real-time clock) and backup registers . . . . . . . . . . . . . . . . . . . . . . 18 2.3.17 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.3.18 I²C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.3.19 Universal synchronous/asynchronous receiver transmitters (USARTs) 20 2.3.20 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.3.21 GPIOs (general-purpose inputs/outputs) . . . . . . . . . . . . . . . . . . . . . . . . 20 2.3.22 ADC (analog to digital converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.3.23 DAC (digital-to-analog converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.3.24 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.3.25 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.3.26 Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Pinouts and pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Doc ID 14610 Rev 8 STM32F101xC, STM32F101xD, STM32F101xE Contents 4 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.1 6 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.3.2 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 38 5.3.3 Embedded reset and power control block characteristics . . . . . . . . . . . 39 5.3.4 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 5.3.5 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 5.3.6 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 5.3.7 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 5.3.8 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 5.3.9 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 5.3.10 FSMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 5.3.11 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 5.3.12 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 78 5.3.13 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 5.3.14 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 5.3.15 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 5.3.16 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 5.3.17 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 5.3.18 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 5.3.19 DAC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 5.3.20 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 6.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 6.2 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Doc ID 14610 Rev 8 3/112 Contents STM32F101xC, STM32F101xD, STM32F101xE 6.2.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 6.2.2 Evaluating the maximum junction temperature for an application . . . . 105 7 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 4/112 Doc ID 14610 Rev 8 STM32F101xC, STM32F101xD, STM32F101xE List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 STM32F101xC, STM32F101xD and STM32F101xE features and peripheral counts . . . . 11 STM32F101xx family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 High-density STM32F101xx pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 FSMC pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 39 Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Maximum current consumption in Run mode, code with data processing running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Maximum current consumption in Run mode, code with data processing running from RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Maximum current consumption in Sleep mode, code running from Flash or RAM. . . . . . . 43 Typical and maximum current consumptions in Stop and Standby modes . . . . . . . . . . . . 43 Typical current consumption in Run mode, code with data processing running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Typical current consumption in Sleep mode, code running from Flash or RAM . . . . . . . . . 47 Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Low-speed user external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 HSE 4-16 MHz oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . . 58 Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . 59 Asynchronous multiplexed NOR/PSRAM read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Asynchronous multiplexed NOR/PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . 67 Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Switching characteristics for PC Card/CF read and write cycles . . . . . . . . . . . . . . . . . . . . 73 Switching characteristics for NAND Flash read and write cycles . . . . . . . . . . . . . . . . . . . . 76 EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Doc ID 14610 Rev 8 5/112 List of tables Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. 6/112 STM32F101xC, STM32F101xD, STM32F101xE I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 SCL frequency (fPCLK1= 36 MHz, VDD = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 STM32F10xxx SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 RAIN max for fADC = 14 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 ADC accuracy - limited test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 LQFP144, 20 x 20 mm, 144-pin thin quad flat package mechanical data . . . . . . . . . . . . 101 LQPF100 – 14 x 14 mm, 100-pin low-profile quad flat package mechanical data . . . . . . 102 LQFP64 – 10 x 10 mm, 64 pin low-profile quad flat package mechanical data . . . . . . . . 103 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Doc ID 14610 Rev 8 STM32F101xC, STM32F101xD, STM32F101xE List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. STM32F101xC, STM32F101xD and STM32F101xE access line block diagram . . . . . . . . 12 Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 STM32F101xC, STM32F101xD and STM32F101xE access line LQFP144 pinout . . . . . . 23 STM32F101xC, STM32F101xD and STM32F101xE LQFP100 pinout . . . . . . . . . . . . . . . 24 STM32F101xC, STM32F101xD and STM32F101xE LQFP64 pinout . . . . . . . . . . . . . . . . 25 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Typical current consumption in Run mode versus frequency (at 3.6 V) code with data processing running from RAM, peripherals enabled. . . . . . . . . . . . . . . . . . 42 Typical current consumption in Run mode versus frequency (at 3.6 V) code with data processing running from RAM, peripherals disabled . . . . . . . . . . . . . . . . . 42 Typical current consumption on VBAT with RTC on vs. temperature at different VBAT values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Typical current consumption in Stop mode with regulator in run mode versus temperature at different VDD values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Typical current consumption in Stop mode with regulator in low-power mode versus temperature at different VDD values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Typical current consumption in Standby mode versus temperature at different VDD values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . . 58 Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . . 59 Asynchronous multiplexed NOR/PSRAM read waveforms. . . . . . . . . . . . . . . . . . . . . . . . . 60 Asynchronous multiplexed NOR/PSRAM write waveforms . . . . . . . . . . . . . . . . . . . . . . . . 62 Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . 67 Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 PC Card/CompactFlash controller waveforms for common memory read access . . . . . . . 69 PC Card/CompactFlash controller waveforms for common memory write access . . . . . . . 70 PC Card/CompactFlash controller waveforms for attribute memory read access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 PC Card/CompactFlash controller waveforms for attribute memory write access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 PC Card/CompactFlash controller waveforms for I/O space read access . . . . . . . . . . . . . 72 PC Card/CompactFlash controller waveforms for I/O space write access . . . . . . . . . . . . . 73 NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . . 75 NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . . 76 Standard I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Standard I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Doc ID 14610 Rev 8 7/112 List of figures Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. Figure 48. Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. 8/112 STM32F101xC, STM32F101xD, STM32F101xE 5 V tolerant I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 5 V tolerant I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 I2C bus AC waveforms and measurement circuit(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 SPI timing diagram - slave mode and CPHA=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 SPI timing diagram - slave mode and CPHA=1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . . 96 Power supply and reference decoupling (VREF+ connected to VDDA) . . . . . . . . . . . . . . . 97 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 LQFP144, 20 x 20 mm, 144-pin thin quad flat package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 LQFP100 – 14 x 14 mm, 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . 102 Recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 LQFP64 – 10 x 10 mm, 64 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . 103 Recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 LQFP64 PD max vs. TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Doc ID 14610 Rev 8 STM32F101xC, STM32F101xD, STM32F101xE 1 Introduction Introduction This datasheet provides the ordering information and mechanical device characteristics of the STM32F101xC, STM32F101xD and STM32F101xE high-density access line microcontrollers. For more details on the whole STMicroelectronics STM32F101xx family, please refer to Section 2.2: Full compatibility throughout the family. The high-density STM32F101xx datasheet should be read in conjunction with the STM32F10xxx reference manual. For information on programming, erasing and protection of the internal Flash memory please refer to the STM32F10xxx Flash programming manual. The reference and Flash programming manuals are both available from the STMicroelectronics website www.st.com. For information on the Cortex™-M3 core please refer to the Cortex™-M3 Technical Reference Manual, available from the www.arm.com website at the following address: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0337e/. Doc ID 14610 Rev 8 9/112 Description 2 STM32F101xC, STM32F101xD, STM32F101xE Description The STM32F101xC, STM32F101xD and STM32F101xE access line family incorporates the high-performance ARM® Cortex™-M3 32-bit RISC core operating at a 36 MHz frequency, high-speed embedded memories (Flash memory up to 512 Kbytes and SRAM up to 48 Kbytes), and an extensive range of enhanced I/Os and peripherals connected to two APB buses. All devices offer one 12-bit ADC, four general-purpose 16-bit timers, as well as standard and advanced communication interfaces: up to two I2Cs, three SPIs and five USARTs. The STM32F101xx high-density access line family operates in the –40 to +85 °C temperature range, from a 2.0 to 3.6 V power supply. A comprehensive set of power-saving mode allows the design of low-power applications. These features make the STM32F101xx high-density access line microcontroller family suitable for a wide range of applications such as medical and handheld equipment, PC peripherals and gaming, GPS platforms, industrial applications, PLC, printers, scanners alarm systems and video intercom. 10/112 Doc ID 14610 Rev 8 STM32F101xC, STM32F101xD, STM32F101xE 2.1 Description Device overview The STM32F101xx high-density access line family offers devices in 3 different package types: from 64 pins to 144 pins. Depending on the device chosen, different sets of peripherals are included, the description below gives an overview of the complete range of peripherals proposed in this family. ● Figure 1 shows the general block diagram of the device family. Table 2. STM32F101xC, STM32F101xD and STM32F101xE features and peripheral counts Peripherals STM32F101Rx Flash memory in Kbytes 256 SRAM in Kbytes 32 FSMC Timers Comm 384 512 STM32F101Vx 256 48 No 384 32 512 48 (1) Yes Generalpurpose 4 Basic 2 SPI 3 I2C 2 USART 5 STM32F101Zx 256 384 32 48 Yes GPIOs 51 80 112 12-bit ADC Number of channels 1 16 1 16 1 16 12-bit DAC Number of channels 1 2 CPU frequency 36 MHz Operating voltage Operating temperatures Package 512 2.0 to 3.6 V Ambient temperature: –40 to +85 °C (see Table 10) Junction temperature: –40 to +105 °C (see Table 10) LQFP64 LQFP100 LQFP144 1. For the LQFP100 package, only FSMC Bank1 and Bank2 are available. Bank1 can only support a multiplexed NOR/PSRAM memory using the NE1 Chip Select. Bank2 can only support a 16- or 8-bit NAND Flash memory using the NCE2 Chip Select. The interrupt line cannot be used since Port G is not available in this package. Doc ID 14610 Rev 8 11/112 Description STM32F101xC, STM32F101xD, STM32F101xE NJTRST JTDI JTCK/SWCLK JTMS/SWDIO JTDO as AF TPIU SW/JTAG Trace/trig Ibus Cortex-M3 CPU Fmax: 36 MHz VDD Flash 512 Kbytes 64 bit Dbus System NVIC @VDD Trace controller Pbus Flash obl interface TRACECLK TRACED[0:3] as AS STM32F101xC, STM32F101xD and STM32F101xE access line block diagram SRAM 48 KB Bus Matrix Figure 1. @VDDA RC 8 MHz GP DMA1 RC 40 kHz 7 channels PLL GP DMA2 5 channels Reset & Clock control PVD @VDD XTAL OSC 4-16 MHz Standby interface @VBAT FSMC XTAL32kHz RTC Backup reg AWU Backup interface AHB2 APB2 AHB2 APB1 EXT.IT WKUP PA[15:0] GPIO port A PB[15:0] GPIO port B PC[15:0] GPIO port C PD[15:0] GPIO port D PE[15:0] GPIO port E PF[15:0] GPIO port F PG[15:0] GPIO port G MOSI, MISO, SCK, NSS as AF SPI1 RX, TX, CTS, RTS as AF USART1 APB2: Fmax = 24/36 MHz 112AF Int @VDDA Supply supervision POR /PDR WWDG VSS NRST VDDA VSSA OSC_IN OSC_OUT IWDG PCLK1 PCLK2 HCLK FCLK APB1: Fmax = 24/36 MHz A[25:0] D[15:0] CLK NOE NWE NE[4:1] NBL[1:0] NWAIT NL as AF POR Reset Power Volt. reg. 3.3 V to 1.8 V VBAT =1.8 V to 3.6 V OSC32_IN OSC32_OUT TAMPER-RTC/ ALARM/SECOND OUT TIM2 4 channels as AF TIM3 4 channels as AF TIM4 4 channels as AF TIM5 USART2 USART3 4 channels as AF RX, TX, CTS, RTS , CK, as AF RX, TX, CTS, RTS, CK, as AF UART4 RX,TX as AF UART5 RX,TX as AF SPI2 MOSI, MISO SCK, NSS as AF SPI3 MOSI, MISO SCK, NSS as AF I2C1 SCL, SDA, SMBA as AF I2C2 SCL, SDA, SMBA as AF Temp. sensor ADC_IN[0:15] VREF– VREF+ 12-bit ADC IF TIM6 IF 12bit DAC1 IF DAC_OUT1 as AF TIM7 12bit DAC 2 DAC_OUT2 as AF @ VDDA @VDDA ai14693d 1. TA = –40 °C to +85 °C (junction temperature up to 105 °C). 2. AF = alternate function on I/O port pin. 12/112 Doc ID 14610 Rev 8 STM32F101xC, STM32F101xD, STM32F101xE Figure 2. Description Clock tree 8 MHz HSI RC FLITFCLK to Flash programming interface HSI FSMCCLK Peripheral clock enable 36 MHz max /2 PLLSRC /8 SW PLLMUL HSI ..., x16 x2, x3, x4 PLL SYSCLK AHB Prescaler 36 MHz /1, 2..512 max PLLCLK HCLK to AHB bus, core, memory and DMA Clock Enable (7 bits) APB1 Prescaler /1, 2, 4, 8, 16 to FSMC to Cortex System timer FCLK Cortex free running clock 36 MHz max PCLK1 to APB1 peripherals Peripheral Clock HSE Enable (18 bits) TIM2,3,4,5,6,7 If (APB1 prescaler =1) x1 else x2 CSS to TIM2,3,4,5,6 and 7 TIMXCLK Peripheral Clock Enable (6 bits) APB2 Prescaler /1, 2, 4, 8, 16 PLLXTPRE OSC_OUT OSC_IN 4-16 MHz HSE OSC OSC32_OUT peripherals to APB2 Peripheral Clock Enable (11 bits) /2 ADC Prescaler /2, 4, 6, 8 /128 OSC32_IN PCLK2 36 MHz max LSE OSC 32.768 kHz to ADC ADCCLK to RTC LSE RTCCLK RTCSEL[1:0] LSI RC 40 kHz to Independent Watchdog (IWDG) LSI IWDGCLK Main Clock Output /2 MCO PLLCLK Legend: HSE = High Speed External clock signal HSI HSI = High Speed Internal clock signal HSE LSI = Low Speed Internal clock signal SYSCLK LSE = Low Speed External clock signal MCO ai15100 1. When the HSI is used as a PLL clock input, the maximum system clock frequency that can be achieved is 36 MHz. 2. To have an ADC conversion time of 1 µs, APB2 must be at 14 MHz or 28 MHz. Doc ID 14610 Rev 8 13/112 Description 2.2 STM32F101xC, STM32F101xD, STM32F101xE Full compatibility throughout the family The STM32F101xx is a complete family whose members are fully pin-to-pin, software and feature compatible. In the reference manual, the STM32F101x4 and STM32F101x6 are identified as low-density devices, the STM32F101x8 and STM32F101xB are referred to as medium-density devices, and the STM32F101xC, STM32F101xD and STM32F101xE are referred to as high-density devices. Low- and high-density devices are an extension of the STM32F101x8/B medium-density devices, they are specified in the STM32F101x4/6 and STM32F101xC/D/E datasheets, respectively. Low-density devices feature lower Flash memory and RAM capacities, less timers and peripherals. High-density devices have higher Flash memory and RAM densities, and additional peripherals like FSMC and DACwhile remaining fully compatible with the other members of the family. The STM32F101x4, STM32F101x6, STM32F101xC, STM32F101xD and STM32F101xE are a drop-in replacement for the STM32F101x8/B devices, allowing the user to try different memory densities and providing a greater degree of freedom during the development cycle. Moreover, the STM32F101xx access line family is fully compatible with all existing STM32F103xx performance line and STM32F102xx USB access line devices. Table 3. STM32F101xx family Memory size Low-density devices Pinout 16 KB Flash 32 KB Flash(1) Medium-density devices 64 KB Flash 128 KB Flash 4 KB RAM 6 KB RAM 10 KB RAM 16 KB RAM 144 100 64 48 36 2 × USARTs 2 × 16-bit timers 1 × SPI, 1 × I2C 1 × ADC 3 × USARTs 3 × 16-bit timers 2 × SPIs, 2 × I2Cs, 1 × ADC High-density devices 256 KB Flash 384 KB Flash 512 KB Flash 32 KB RAM 48 KB RAM 48 KB RAM 5 × USARTs 4 × 16-bit timers, 2 × basic timers 3 × SPIs, 2 × I2Cs, 1 × ADC, 2 × DACs FSMC (100 and 144 pins) 1. For orderable part numbers that do not show the A internal code after the temperature range code (6), the reference datasheet for electrical characteristics is that of the STM32F101x8/B medium-density devices. 2.3 Overview 2.3.1 ARM® Cortex™-M3 core with embedded Flash and SRAM The ARM Cortex™-M3 processor is the latest generation of ARM processors for embedded systems. It has been developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced system response to interrupts. 14/112 Doc ID 14610 Rev 8 STM32F101xC, STM32F101xD, STM32F101xE Description The ARM Cortex™-M3 32-bit RISC processor features exceptional code-efficiency, delivering the high-performance expected from an ARM core in the memory size usually associated with 8- and 16-bit devices. The STM32F101xC, STM32F101xD and STM32F101xE access line family having an embedded ARM core, is therefore compatible with all ARM tools and software. Figure 1 shows the general block diagram of the device family. 2.3.2 Embedded Flash memory 256 to 512 Kbytes of embedded Flash are available for storing programs and data. 2.3.3 CRC (cyclic redundancy check) calculation unit The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a fixed generator polynomial. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location. 2.3.4 Embedded SRAM Up to 48 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait states. 2.3.5 FSMC (flexible static memory controller) The FSMC is embedded in the STM32F101xC, STM32F101xD and STM32F101xE access line family. It has four Chip Select outputs supporting the following modes: PC Card/Compact Flash, SRAM, PSRAM, NOR and NAND. Functionality overview: 2.3.6 ● The three FSMC interrupt lines are ORed in order to be connected to the NVIC ● Write FIFO ● Code execution from external memory except for NAND Flash and PC Card ● The targeted frequency is HCLK/2, so external access is at 18 MHz when HCLK is at 36 MHz LCD parallel interface The FSMC can be configured to interface seamlessly with most graphic LCD controllers. It supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to specific LCD interfaces. This LCD parallel interface capability makes it easy to build costeffective graphic applications using LCD modules with embedded controllers or highperformance solutions using external controllers with dedicated acceleration. Doc ID 14610 Rev 8 15/112 Description 2.3.7 STM32F101xC, STM32F101xD, STM32F101xE Nested vectored interrupt controller (NVIC) The STM32F101xC, STM32F101xD and STM32F101xE access line embeds a nested vectored interrupt controller able to handle up to 60 maskable interrupt channels (not including the 16 interrupt lines of Cortex™-M3) and 16 priority levels. ● Closely coupled NVIC gives low-latency interrupt processing ● Interrupt entry vector table address passed directly to the core ● Closely coupled NVIC core interface ● Allows early processing of interrupts ● Processing of late arriving higher priority interrupts ● Support for tail-chaining ● Processor state automatically saved ● Interrupt entry restored on interrupt exit with no instruction overhead This hardware block provides flexible interrupt management features with minimal interrupt latency. 2.3.8 External interrupt/event controller (EXTI) The external interrupt/event controller consists of 19 edge detector lines used to generate interrupt/event requests. Each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect an external line with a pulse width shorter than the Internal APB2 clock period. Up to 112 GPIOs can be connected to the 16 external interrupt lines. 2.3.9 Clocks and startup System clock selection is performed on startup, however the internal RC 8 MHz oscillator is selected as default CPU clock on reset. An external 4-16 MHz clock can be selected, in which case it is monitored for failure. If failure is detected, the system automatically switches back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full interrupt management of the PLL clock is available when necessary (for example with failure of an indirectly used external oscillator). Several prescalers are used to configure the AHB frequency, the high-speed APB (APB2) domain and the low-speed APB (APB1) domain. The maximum frequency of the AHB and APB domains is 36 MHz. See Figure 2 for details on the clock tree. 2.3.10 Boot modes At startup, boot pins are used to select one of three boot options: ● Boot from user Flash: you have an option to boot from any of two memory banks. By default, boot from Flash memory bank 1 is selected. You can choose to boot from Flash memory bank 2 by setting a bit in the option bytes. ● Boot from system memory ● Boot from embedded SRAM The bootloader is located in system memory. It is used to reprogram the Flash memory by using USART1. 16/112 Doc ID 14610 Rev 8 STM32F101xC, STM32F101xD, STM32F101xE 2.3.11 Description Power supply schemes ● VDD = 2.0 to 3.6 V: external power supply for I/Os and the internal regulator. Provided externally through VDD pins. ● VSSA, VDDA = 2.0 to 3.6 V: external analog power supplies for ADC, DAC, Reset blocks, RCs and PLL (minimum voltage to be applied to VDDA is 2.4 V when the ADC or DAC is used). VDDA and VSSA must be connected to VDD and VSS, respectively. ● VBAT = 1.8 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when VDD is not present. For more details on how to connect power pins, refer to Figure 9: Power supply scheme. 2.3.12 Power supply supervisor The device has an integrated power-on reset (POR)/power-down reset (PDR) circuitry. It is always active, and ensures proper operation starting from/down to 2 V. The device remains in reset mode when VDD is below a specified threshold, VPOR/PDR, without the need for an external reset circuit. The device features an embedded programmable voltage detector (PVD) that monitors the VDD/VDDA power supply and compares it to the VPVD threshold. An interrupt can be generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is higher than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software. Refer to Table 12: Embedded reset and power control block characteristics for the values of VPOR/PDR and VPVD. 2.3.13 Voltage regulator The regulator has three operation modes: main (MR), low power (LPR) and power down. ● MR is used in the nominal regulation mode (Run) ● LPR is used in the Stop modes. ● Power down is used in Standby mode: the regulator output is in high impedance: the kernel circuitry is powered down, inducing zero consumption (but the contents of the registers and SRAM are lost) This regulator is always enabled after reset. It is disabled in Standby mode. 2.3.14 Low-power modes The STM32F101xC, STM32F101xD and STM32F101xE access line supports three lowpower modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources: ● Sleep mode In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs. ● Stop mode Stop mode achieves the lowest power consumption while retaining the content of SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC and the HSE crystal oscillators are disabled. The voltage regulator can also be put either in normal or in low power mode. Doc ID 14610 Rev 8 17/112 Description STM32F101xC, STM32F101xD, STM32F101xE The device can be woken up from Stop mode by any of the EXTI line. The EXTI line source can be one of the 16 external lines, the PVD output or the RTC alarm. ● Standby mode The Standby mode is used to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire 1.8 V domain is powered off. The PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering Standby mode, SRAM and register contents are lost except for registers in the Backup domain and Standby circuitry. The device exits Standby mode when an external reset (NRST pin), a IWDG reset, a rising edge on the WKUP pin, or an RTC alarm occurs. Note: The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop or Standby mode. 2.3.15 DMA The flexible 12-channel general-purpose DMAs (7 channels for DMA1 and 5 channels for DMA2) are able to manage memory-to-memory, peripheral-to-memory and memory-toperipheral transfers. The two DMA controllers support circular buffer management, removing the need for user code intervention when the controller reaches the end of the buffer. Each channel is connected to dedicated hardware DMA requests, with support for software trigger on each channel. Configuration is made by software and transfer sizes between source and destination are independent. DMA can be used with the main peripherals: SPI, I2C, USART, general-purpose and basic timers TIMx, DAC and ADC. 2.3.16 RTC (real-time clock) and backup registers The RTC and the backup registers are supplied through a switch that takes power either on VDD supply when present or through the VBAT pin. The backup registers are forty-two 16-bit registers used to store 84 bytes of user application data when VDD power is not present. They are not reset by a system or power reset, and they are not reset when the device wakes up from the Standby mode. The real-time clock provides a set of continuously running counters which can be used with suitable software to provide a clock calendar function, and provides an alarm interrupt and a periodic interrupt. It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the internal low power RC oscillator or the high speed external clock divided by 128. The internal low-speed RC has a typical frequency of 40 kHz. The RTC can be calibrated using an external 512 Hz output to compensate for any natural quartz deviation. The RTC features a 32-bit programmable counter for long term measurement using the Compare register to generate an alarm. A 20-bit prescaler is used for the time base clock and is by default configured to generate a time base of 1 second from a clock at 32.768 kHz. 2.3.17 Timers and watchdogs The high-density STM32F101xx access line devices include up to four general-purpose timers, two basic timers, two watchdog timers and a SysTick timer. Table 4 compares the features of the general-purpose and basic timers. 18/112 Doc ID 14610 Rev 8 STM32F101xC, STM32F101xD, STM32F101xE Table 4. Description Timer feature comparison Timer Counter resolution Counter type Prescaler factor DMA request Capture/compare Complementary generation channels outputs TIM2, TIM3, TIM4, TIM5 16-bit Up, down, up/down Any integer between 1 and 65536 Yes 4 No TIM6, TIM7 16-bit Up Any integer between 1 and 65536 Yes 0 No General-purpose timers (TIMx) There are up to 4 synchronizable general-purpose timers (TIM2, TIM3, TIM4 and TIM5) embedded in the STM32F101xC, STM32F101xD and STM32F101xE access line devices. These timers are based on a 16-bit auto-reload up/down counter, a 16-bit prescaler and feature 4 independent channels each for input capture/output compare, PWM or one-pulse mode output. This gives up to 16 input captures / output compares / PWMs on the largest packages. The general-purpose timers can work together with the advanced-control timer via the Timer Link feature for synchronization or event chaining. Their counter can be frozen in debug mode. Any of the general-purpose timers can be used to generate PWM outputs. They all have independent DMA request generation. These timers are capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 3 hall-effect sensors. Basic timers TIM6 and TIM7 These timers are mainly used for DAC trigger generation. They can also be used as a generic 16-bit time base. Independent watchdog The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 40 kHz internal RC and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free running timer for application timeout management. It is hardware or software configurable through the option bytes. The counter can be frozen in debug mode. Window watchdog The window watchdog is based on a 7-bit downcounter that can be set as free running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode. Doc ID 14610 Rev 8 19/112 Description STM32F101xC, STM32F101xD, STM32F101xE SysTick timer This timer is dedicated to real-time operating systems, but could also be used as a standard down counter. It features: 2.3.18 ● A 24-bit down counter ● Autoreload capability ● Maskable system interrupt generation when the counter reaches 0. ● Programmable clock source I²C bus Up to two I²C bus interfaces can operate in multi-master and slave modes. They support standard and fast modes. They support 7/10-bit addressing mode and 7-bit dual addressing mode (as slave). A hardware CRC generation/verification is embedded. They can be served by DMA and they support SMBus 2.0/PMBus. 2.3.19 Universal synchronous/asynchronous receiver transmitters (USARTs) The STM32F101xC, STM32F101xD and STM32F101xE access line embeds three universal synchronous/asynchronous receiver transmitters (USART1, USART2 and USART3) and two universal asynchronous receiver transmitters (UART4 and UART5). These five interfaces provide asynchronous communication, IrDA SIR ENDEC support, multiprocessor communication mode, single-wire half-duplex communication mode and have LIN Master/Slave capability. The five interfaces are able to communicate at speeds of up to 2.25 Mbit/s. USART1, USART2 and USART3 also provide hardware management of the CTS and RTS signals, Smart Card mode (ISO 7816 compliant) and SPI-like communication capability. All interfaces can be served by the DMA controller except for UART5. 2.3.20 Serial peripheral interface (SPI) Up to three SPIs are able to communicate up to 18 Mbits/s in slave and master modes in full-duplex and simplex communication modes. The 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC generation/verification supports basic SD Card/MMC modes. All SPIs can be served by the DMA controller. 2.3.21 GPIOs (general-purpose inputs/outputs) Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high currentcapable except for analog inputs. The I/Os alternate function configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the I/Os registers. 20/112 Doc ID 14610 Rev 8 STM32F101xC, STM32F101xD, STM32F101xE 2.3.22 Description ADC (analog to digital converter) A 12-bit analog-to-digital converter is embedded into STM32F101xC, STM32F101xD and STM32F101xE access line devices. It has up to 16 external channels, performing conversions in single-shot or scan modes. In scan mode, automatic conversion is performed on a selected group of analog inputs. The ADC can be served by the DMA controller. An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds. The events generated by the general-purpose timers (TIMx) can be internally connected to the ADC start trigger and injection trigger, respectively, to allow the application to synchronize A/D conversion and timers. 2.3.23 DAC (digital-to-analog converter) The two 12-bit buffered DAC channels can be used to convert two digital signals into two analog voltage signal outputs. The chosen design structure is composed of integrated resistor strings and an amplifier in inverting configuration. This dual digital Interface supports the following features: ● two DAC converters: one for each output channel ● 8-bit or 12-bit monotonic output ● left or right data alignment in 12-bit mode ● synchronized update capability ● noise-wave generation ● triangular-wave generation ● dual DAC channel independent or simultaneous conversions ● DMA capability for each channel ● external triggers for conversion ● input voltage reference VREF+ Seven DAC trigger inputs are used in the STM32F101xC, STM32F101xD and STM32F101xE access line family. The DAC channels are triggered through the timer update outputs that are also connected to different DMA channels. 2.3.24 Temperature sensor The temperature sensor has to generate a voltage that varies linearly with temperature. The conversion range is between 2 V < VDDA < 3.6 V. The temperature sensor is internally connected to the ADC_IN16 input channel which is used to convert the sensor output voltage into a digital value. 2.3.25 Serial wire JTAG debug port (SWJ-DP) The ARM SWJ-DP Interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target. The JTAG TMS and TCK pins are shared respectively with SWDIO and SWCLK and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP. Doc ID 14610 Rev 8 21/112 Description 2.3.26 STM32F101xC, STM32F101xD, STM32F101xE Embedded Trace Macrocell™ The ARM® Embedded Trace Macrocell provides a greater visibility of the instruction and data flow inside the CPU core by streaming compressed data at a very high rate from the STM32F10xxx through a small number of ETM pins to an external hardware trace port analyzer (TPA) device. The TPA is connected to a host computer using Ethernet, or any other high-speed channel. Real-time instruction and data flow activity can be recorded and then formatted for display on the host computer running debugger software. TPA hardware is commercially available from common development tool vendors. It operates with third party debugger software tools. 22/112 Doc ID 14610 Rev 8 STM32F101xC, STM32F101xD, STM32F101xE Pinouts and pin descriptions Pinouts and pin descriptions Figure 3. STM32F101xC, STM32F101xD and STM32F101xE access line LQFP144 pinout 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 VDD_3 VSS_3 PE1 PE0 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PG15 VDD_11 VSS_11 PG14 PG13 PG12 PG11 PG10 PG9 PD7 PD6 VDD_10 VSS_10 PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PA15 PA14 3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 VDD_2 VSS_2 NC PA13 PA12 PA11 PA10 PA9 PA8 PC9 PC8 PC7 PC6 VDD_9 VSS_9 PG8 PG7 PG6 PG5 PG4 PG3 PG2 PD15 PD14 VDD_8 VSS_8 PD13 PD12 PD11 PD10 PD9 PD8 PB15 PB14 PB13 PB12 VSS_6 VDD_6 PF13 PF14 PF15 PG0 PG1 PE7 PE8 PE9 VSS_7 VDD_7 PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 VSS_1 VDD_1 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 LQFP144 PA3 VSS_4 VDD_4 PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PF11 PF12 PE2 PE3 PE4 PE5 PE6 VBAT PC13-TAMPER-RTC PC14-OSC32_IN PC15-OSC32_OUT PF0 PF1 PF2 PF3 PF4 PF5 VSS_5 VDD_5 PF6 PF7 PF8 PF9 PF10 OSC_IN OSC_OUT NRST PC0 PC1 PC2 PC3 VSSA VREFVREF+ VDDA PA0-WKUP PA1 PA2 ai14667 Doc ID 14610 Rev 8 23/112 Pinouts and pin descriptions STM32F101xC, STM32F101xD and STM32F101xE LQFP100 pinout 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 VDD_3 VSS_3 PE1 PE0 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PA15 PA14 Figure 4. STM32F101xC, STM32F101xD, STM32F101xE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 LQFP100 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 VDD_2 VSS_2 NC PA 13 PA 12 PA 11 PA 10 PA 9 PA 8 PC9 PC8 PC7 PC6 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PB15 PB14 PB13 PB12 PA3 VSS_4 VDD_4 PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 VSS_1 VDD_1 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 PE2 PE3 PE4 PE5 PE6 VBAT PC13-TAMPER-RTC PC14-OSC32_IN PC15-OSC32_OUT VSS_5 VDD_5 OSC_IN OSC_OUT NRST PC0 PC1 PC2 PC3 VSSA VREFVREF+ VDDA PA0-WKUP PA1 PA2 ai14391 24/112 Doc ID 14610 Rev 8 STM32F101xC, STM32F101xD, STM32F101xE STM32F101xC, STM32F101xD and STM32F101xE LQFP64 pinout VDD_3 VSS_3 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD2 PC12 PC11 PC10 PA15 PA14 Figure 5. Pinouts and pin descriptions 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 1 47 2 46 3 45 4 44 5 43 6 42 7 41 8 LQFP64 40 9 39 10 38 11 37 12 36 13 35 14 34 15 33 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 VDD_2 VSS_2 PA13 PA12 PA11 PA10 PA9 PA8 PC9 PC8 PC7 PC6 PB15 PB14 PB13 PB12 PA3 VSS_4 VDD_4 PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PB10 PB11 VSS_1 VDD_1 VBAT PC13-TAMPER-RTC PC14-OSC32_IN PC15-OSC32_OUT PD0-OSC_IN PD1-OSC_OUT NRST PC0 PC1 PC2 PC3 VSSA VDDA PA0-WKUP PA1 PA2 ai14392 High-density STM32F101xx pin definitions LQFP64 LQFP100 Pin name Type(1) I / O Level(2) Alternate functions(4) LQFP144 Table 5. Main function(3) (after reset) 1 - 1 PE2 I/O FT PE2 TRACECLK/ FSMC_A23 2 - 2 PE3 I/O FT PE3 TRACED0/FSMC_A19 3 - 3 PE4 I/O FT PE4 TRACED1/FSMC_A20 4 - 4 PE5 I/O FT PE5 TRACED2/FSMC_A21 5 - 5 PE6 I/O FT PE6 TRACED3/FSMC_A22 6 1 6 VBAT Pins (5) S VBAT Default 7 2 7 PC13-TAMPER-RTC I/O PC13(6) TAMPER-RTC 8 3 8 PC14-OSC32_IN(5) I/O PC14(6) OSC32_IN 9 4 9 PC15-OSC32_OUT(5) I/O PC15(6) OSC32_OUT 10 - - PF0 I/O FT PF0 FSMC_A0 11 - - PF1 I/O FT PF1 FSMC_A1 12 - - PF2 I/O FT PF2 FSMC_A2 13 - - PF3 I/O FT PF3 FSMC_A3 14 - - PF4 I/O FT PF4 FSMC_A4 15 - - PF5 I/O FT PF5 FSMC_A5 16 - 10 VSS_5 S VSS_5 17 - 11 VDD_5 S VDD_5 Doc ID 14610 Rev 8 Remap 25/112 Pinouts and pin descriptions High-density STM32F101xx pin definitions (continued) Alternate functions(4) LQFP100 Default LQFP64 Main function(3) (after reset) LQFP144 Type(1) Pins I / O Level(2) Table 5. STM32F101xC, STM32F101xD, STM32F101xE 18 - - PF6 I/O PF6 FSMC_NIORD 19 - - PF7 I/O PF7 FSMC_NREG 20 - - PF8 I/O PF8 FSMC_NIOWR 21 - - PF9 I/O PF9 FSMC_CD 22 - - PF10 I/O PF10 FSMC_INTR 23 5 12 OSC_IN I OSC_IN 24 6 13 OSC_OUT O OSC_OUT 25 7 14 NRST I/O NRST 26 8 15 PC0 I/O PC0 ADC_IN10 27 9 16 PC1 I/O PC1 ADC_IN11 28 10 17 PC2 I/O PC2 ADC_IN12 29 11 18 PC3 I/O PC3 ADC_IN13 30 12 19 VSSA S VSSA 31 - 20 VREF- S VREF- 32 - 21 VREF+ S VREF+ 33 13 22 VDDA S VDDA 34 14 23 PA0-WKUP I/O PA0 WKUP/ USART2_CTS(7)/ ADC_IN0/TIM5_CH1/ TIM2_CH1_ETR(7) PA1 USART2_RTS(7)/ ADC_IN1/TIM5_CH2 TIM2_CH2(7) 35 15 24 Pin name PA1 I/O 36 16 25 PA2 I/O PA2 USART2_TX(7)/ TIM5_CH3/ADC_IN2/ TIM2_CH3(7) 37 17 26 PA3 I/O PA3 USART2_RX(7)/ TIM5_CH4 / ADC_IN3/ TIM2_CH4(7) 38 18 27 VSS_4 S VSS_4 39 19 28 VDD_4 S VDD_4 40 20 29 PA4 I/O PA4 SPI1_NSS/ DAC_OUT1 ADC_IN4 / USART2_CK(7) 41 21 30 PA5 I/O PA5 SPI1_SCK/ DAC_OUT2/ADC_IN5 42 22 31 PA6 I/O PA6 SPI1_MISO / ADC_IN6 / TIM3_CH1(7) 26/112 Doc ID 14610 Rev 8 Remap STM32F101xC, STM32F101xD, STM32F101xE High-density STM32F101xx pin definitions (continued) Alternate functions(4) LQFP64 LQFP100 Main function(3) (after reset) LQFP144 Type(1) Pins I / O Level(2) Table 5. Pinouts and pin descriptions 43 23 32 PA7 I/O PA7 SPI1_MOSI / ADC_IN7/ TIM3_CH2(7) 44 24 33 PC4 I/O PC4 ADC_IN14 45 25 34 PC5 I/O PC5 ADC_IN15 46 26 35 PB0 I/O PB0 ADC_IN8 / TIM3_CH3(7) 47 27 36 PB1 I/O PB1 ADC_IN9/TIM3_CH4(7) 48 28 37 PB2 I/O FT PB2/BOOT1 49 - - PF11 I/O FT PF11 FSMC_NIOS16 50 - - PF12 I/O FT PF12 FSMC_A6 51 - - VSS_6 S VSS_6 52 - - VDD_6 S VDD_6 53 - - PF13 I/O FT PF13 FSMC_A7 54 - - PF14 I/O FT PF14 FSMC_A8 55 - - PF15 I/O FT PF15 FSMC_A9 56 - - PG0 I/O FT PG0 FSMC_A10 57 - - PG1 I/O FT PG1 FSMC_A11 58 - 38 PE7 I/O FT PE7 FSMC_D4 59 - 39 PE8 I/O FT PE8 FSMC_D5 60 - 40 PE9 I/O FT PE9 FSMC_D6 61 - - VSS_7 S VSS_7 62 - - VDD_7 S VDD_7 63 - 41 PE10 I/O FT PE10 FSMC_D7 64 - 42 PE11 I/O FT PE11 FSMC_D8 65 - 43 PE12 I/O FT PE12 FSMC_D9 66 - 44 PE13 I/O FT PE13 FSMC_D10 67 - 45 PE14 I/O FT PE14 FSMC_D11 68 - 46 PE15 I/O FT PE15 FSMC_D12 69 29 47 PB10 I/O FT PB10 I2C2_SCL/ USART3_TX(7) TIM2_CH3 70 30 48 PB11 I/O FT PB11 I2C2_SDA/ USART3_RX(7) TIM2_CH4 71 31 49 VSS_1 S VSS_1 72 32 50 VDD_1 S VDD_1 73 33 51 PB12 Pin name I/O FT PB12 Doc ID 14610 Rev 8 Default Remap SPI2_NSS(7)/ I2C2_SMBA USART3_CK(7) 27/112 Pinouts and pin descriptions High-density STM32F101xx pin definitions (continued) Alternate functions(4) LQFP64 LQFP100 Main function(3) (after reset) LQFP144 Type(1) Pins I / O Level(2) Table 5. STM32F101xC, STM32F101xD, STM32F101xE 74 34 52 PB13 I/O FT PB13 SPI2_SCK(7)/ USART3_CTS(7) 75 35 53 PB14 I/O FT PB14 SPI2_MISO(7)/ USART3_RTS(7) 76 36 54 PB15 I/O FT PB15 SPI2_MOSI(7) 77 - 55 PD8 I/O FT PD8 FSMC_D13 USART3_TX 78 - 56 PD9 I/O FT PD9 FSMC_D14 USART3_RX 79 - 57 PD10 I/O FT PD10 FSMC_D15 USART3_CK 80 - 58 PD11 I/O FT PD11 FSMC_A16 USART3_CTS 81 - 59 PD12 I/O FT PD12 FSMC_A17 TIM4_CH1 / USART3_RTS 82 - 60 PD13 I/O FT PD13 FSMC_A18 TIM4_CH2 83 - - VSS_8 S VSS_8 84 - - VDD_8 S VDD_8 85 - 61 PD14 I/O FT PD14 FSMC_D0 TIM4_CH3 86 - 62 PD15 I/O FT PD15 FSMC_D1 TIM4_CH4 87 - - PG2 I/O FT PG2 FSMC_A12 88 - - PG3 I/O FT PG3 FSMC_A13 89 - - PG4 I/O FT PG4 FSMC_A14 90 - - PG5 I/O FT PG5 FSMC_A15 91 - - PG6 I/O FT PG6 FSMC_INT2 92 - - PG7 I/O FT PG7 FSMC_INT3 93 - - PG8 I/O FT PG8 94 - - VSS_9 S VSS_9 95 - - VDD_9 S VDD_9 96 37 63 PC6 I/O FT PC6 TIM3_CH1 97 38 64 PC7 I/O FT PC7 TIM3_CH2 98 39 65 PC8 I/O FT PC8 TIM3_CH3 99 40 66 PC9 I/O FT PC9 TIM3_CH4 100 41 67 PA8 I/O FT PA8 USART1_CK/ MCO 101 42 68 PA9 I/O FT PA9 USART1_TX(7) 102 43 69 PA10 I/O FT PA10 USART1_RX(7) 103 44 70 PA11 I/O FT PA11 USART1_CTS 28/112 Pin name Doc ID 14610 Rev 8 Default Remap STM32F101xC, STM32F101xD, STM32F101xE High-density STM32F101xx pin definitions (continued) Alternate functions(4) USART1_RTS LQFP100 Default LQFP64 Main function(3) (after reset) LQFP144 Type(1) Pins I / O Level(2) Table 5. Pinouts and pin descriptions 104 45 71 PA12 I/O FT PA12 105 46 72 PA13 I/O FT JTMS-SWDIO 106 - 73 107 47 74 VSS_2 S VSS_2 108 48 75 VDD_2 S VDD_2 109 49 76 PA14 I/O FT JTCK-SWCLK 110 50 77 PA15 I/O FT JTDI SPI3_NSS TIM2_CH1_ETR/ PA15 /SPI1_NSS 111 51 78 PC10 I/O FT PC10 UART4_TX USART3_TX 112 52 79 PC11 I/O FT PC11 UART4_RX USART3_RX 113 53 80 PC12 I/O FT PC12 UART5_TX USART3_CK FSMC_D2(9) Pin name Remap PA13 Not connected PA14 114 5 81 PD0 I/O FT OSC_IN(8) 115 6 82 PD1 I/O FT OSC_OUT(8) FSMC_D3(9) 116 54 83 PD2 I/O FT PD2 TIM3_ETR/UART5_RX 117 - 84 PD3 I/O FT PD3 FSMC_CLK USART2_CTS 118 - 85 PD4 I/O FT PD4 FSMC_NOE USART2_RTS 119 - 86 PD5 I/O FT PD5 FSMC_NWE USART2_TX 120 - - VSS_10 S VSS_10 121 - - VDD_10 S VDD_10 122 - 87 PD6 I/O FT PD6 FSMC_NWAIT USART2_RX 123 - 88 PD7 I/O FT PD7 FSMC_NE1/ FSMC_NCE2 USART2_CK 124 - - PG9 I/O FT PG9 FSMC_NE2/ FSMC_NCE3 125 - - PG10 I/O FT PG10 FSMC_NE3/ FSMC_NCE4_1 126 - - PG11 I/O FT PG11 FSMC_NCE4_2 127 - - PG12 I/O FT PG12 FSMC_NE4 128 - - PG13 I/O FT PG13 FSMC_A24 129 - - PG14 I/O FT PG14 FSMC_A25 130 - - VSS_11 S VSS_11 131 - - VDD_11 S VDD_11 132 - - PG15 I/O FT PG15 Doc ID 14610 Rev 8 29/112 Pinouts and pin descriptions High-density STM32F101xx pin definitions (continued) Alternate functions(4) Remap LQFP100 Default LQFP64 Main function(3) (after reset) LQFP144 Type(1) Pins I / O Level(2) Table 5. STM32F101xC, STM32F101xD, STM32F101xE 133 55 89 PB3 I/O FT JTDO SPI3_SCK TIM2_CH2 /PB3 TRACESWO SPI1_SCK 134 56 90 PB4 I/O FT NJTRST SPI3_MISO PB4 / TIM3_CH1 SPI1_MISO 135 57 91 PB5 I/O PB5 I2C1_SMBA/ SPI3_MOSI TIM3_CH2 / SPI1_MOSI 136 58 92 PB6 I/O FT PB6 I2C1_SCL/ TIM4_CH1(7) USART1_TX 137 59 93 PB7 I/O FT PB7 I2C1_SDA/FSMC_NADV TIM4_CH2(7) USART1_RX 138 60 94 BOOT0 139 61 95 PB8 PB8 TIM4_CH3 (7) I2C1_SCL PB9 (7) I2C1_SDA 140 62 96 Pin name PB9 I BOOT0 I/O FT I/O FT TIM4_CH4 (7)/ 141 - 97 PE0 I/O FT PE0 TIM4_ETR FSMC_NBL0 142 - 98 PE1 I/O FT PE1 FSMC_NBL1 143 63 99 VSS_3 S VSS_3 144 64 100 VDD_3 S VDD_3 1. I = input, O = output, S = supply. 2. FT = 5 V tolerant. 3. Function availability depends on the chosen device. 4. If several peripherals share the same I/O pin, to avoid conflict between these alternate functions only one peripheral should be enabled at a time through the peripheral clock enable bit (in the corresponding RCC peripheral clock enable register). 5. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 in output mode is limited: the speed should not exceed 2 MHz with a maximum load of 30 pF and these IOs must not be used as a current source (e.g. to drive an LED). 6. Main function after the first backup domain power-up. Later on, it depends on the contents of the Backup registers even after reset (because these registers are not reset by the main reset). For details on how to manage these IOs, refer to the Battery backup domain and BKP register description sections in the STM32F10xxx reference manual, available from the STMicroelectronics website: www.st.com. 7. This alternate function can be remapped by software to some other port pins (if available on the used package). For more details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual, available from the STMicroelectronics website: www.st.com. 8. For the LQFP64 package, the pins number 5 and 6 are configured as OSC_IN/OSC_OUT after reset, however the functionality of PD0 and PD1 can be remapped by software on these pins. For the LQFP100 and LQFP144 packages, PD0 and PD1 are available by default, so there is no need for remapping. For more details, refer to Alternate function I/O and debug configuration section in the STM32F10xxx reference manual 9. For devices delivered in LQFP64 packages, the FSMC function is not available. 30/112 Doc ID 14610 Rev 8 STM32F101xC, STM32F101xD, STM32F101xE Table 6. Pinouts and pin descriptions FSMC pin definition FSMC Pins LQFP100(1) NOR/PSRAM/ SRAM NOR/PSRAM Mux PE2 A23 A23 Yes PE3 A19 A19 Yes PE4 A20 A20 Yes PE5 A21 A21 Yes PE6 A22 A22 Yes CF CF/IDE NAND 16 bit PF0 A0 A0 A0 - PF1 A1 A1 A1 - PF2 A2 A2 A2 - PF3 A3 A3 - PF4 A4 A4 - PF5 A5 A5 - PF6 NIORD NIORD - PF7 NREG NREG - PF8 NIOWR NIOWR - PF9 CD CD - PF10 INTR INTR - PF11 NIOS16 NIOS16 - PF12 A6 A6 - PF13 A7 A7 - PF14 A8 A8 - PF15 A9 A9 - PG0 A10 A10 - A11 - PG1 PE7 D4 D4 D4 DA4 D4 Yes PE8 D5 D5 D5 DA5 D5 Yes PE9 D6 D6 D6 DA6 D6 Yes PE10 D7 D7 D7 DA7 D7 Yes PE11 D8 D8 D8 DA8 D8 Yes PE12 D9 D9 D9 DA9 D9 Yes PE13 D10 D10 D10 DA10 D10 Yes PE14 D11 D11 D11 DA11 D11 Yes PE15 D12 D12 D12 DA12 D12 Yes PD8 D13 D13 D13 DA13 D13 Yes Doc ID 14610 Rev 8 31/112 Pinouts and pin descriptions Table 6. STM32F101xC, STM32F101xD, STM32F101xE FSMC pin definition (continued) FSMC Pins CF/IDE NOR/PSRAM/ SRAM NOR/PSRAM Mux NAND 16 bit PD9 D14 D14 D14 DA14 D14 Yes PD10 D15 D15 D15 DA15 D15 Yes PD11 A16 A16 CLE Yes PD12 A17 A17 ALE Yes PD13 A18 A18 Yes PD14 D0 D0 D0 DA0 D0 Yes PD15 D1 D1 D1 DA1 D1 Yes PG2 A12 - PG3 A13 - PG4 A14 - PG5 A15 - PG6 INT2 - PG7 INT3 - PD0 D2 D2 D2 DA2 D2 Yes PD1 D3 D3 D3 DA3 D3 Yes CLK CLK PD3 Yes PD4 NOE NOE NOE NOE NOE Yes PD5 NWE NWE NWE NWE NWE Yes PD6 NWAIT NWAIT NWAIT NWAIT NWAIT Yes PD7 NE1 NE1 NCE2 Yes PG9 NE2 NE2 NCE3 - NE3 NE3 PG10 NCE4_1 NCE4_1 PG11 NCE4_2 NCE4_2 - PG12 NE4 NE4 - PG13 A24 A24 - PG14 A25 A25 - PB7 NADV NADV Yes PE0 NBL0 NBL0 Yes PE1 NBL1 NBL1 Yes 1. Ports F and G are not available in devices delivered in 100-pin packages. 32/112 LQFP100(1) CF Doc ID 14610 Rev 8 STM32F101xC, STM32F101xD, STM32F101xE 4 Memory mapping Memory mapping The memory map is shown in Figure 6. Figure 6. Memory map 0xFFFF FFFF 0xE000 0000 0xDFFF FFFF Reserved FSMC register 0xA000 0000 - 0xA000 0FFF FSMC bank 4 PCCARD 0x9000 0000 - 0x9FFF FFFF FSMC bank 3 NAND (NAND2) 0x8000 0000 - 0x8FFF FFFF FSMC bank 2 NAND (NAND1) 0x7000 0000 - 0x7FFF FFFF FSMC bank 1 NOR/PSRAM 4 0x6C00 0000 - 0x6FFF FFFF FSMC bank 1 NOR/PSRAM 3 0x6800 0000 - 0x6BFF FFFF FSMC bank 1 NOR/PSRAM 2 0x6400 0000 - 0x67FF FFFF FSMC bank 1 NOR/PSRAM 1 Reserved 0x6000 0000 - 0x63FF FFFF 0x4002 3400 - 0x5FFF FFFF 512-Mbyte block 7 Cortex-M3's internal peripherals 512-Mbyte block 5 FSMC register 0xA000 0000 0x9FFF FFFF 512-Mbyte block 4 FSMC bank3 & bank4 512-Mbyte block 3 FSMC bank1 & bank2 512-Mbyte block 2 Peripherals 0x4000 0000 0x3FFF FFFF 512-Mbyte block 1 SRAM 0x2000 0000 0x1FFF FFFF 512-Mbyte block 0 Code 0x0000 0000 0x4002 3000 - 0x4002 33FF 0x4002 2400 - 0x4002 2FFF Flash interface Reserved 0x4002 1400 - 0x4002 1FFF Reserved SRAM (48 KB aliased by bit-banding) Option Bytes System memory Reserved Flash Reserved Aliased to Flash or system memory depending on BOOT pins Doc ID 14610 Rev 8 0x4002 2000 - 0x4002 23FF RCC 0x4002 1000 - 0x4002 13FF Reserved 0x4002 0400 - 0x4002 0FFF DMA2 0x4002 0400 - 0x4002 07FF DMA1 Reserved Reserved 0x4002 0000 - 0x4002 03FF 0x4001 8400 - 0x4001 FFFF 0x4001 8000 - 0x4001 83FF Reserved 0x4001 3C00 - 0x4001 7FFF 0x4001 3800 - 0x4001 3BFF 0x4001 3400 - 0x4001 37FF 0x4001 3000 - 0x4001 33FF 0x4001 2800 - 0x4001 2FFF ADC1 0x4001 2400 - 0x4001 27FF Port G Port F 0x4001 2000 - 0x4001 23FF 0x4001 1C00 - 0x4001 1FFF 0x4001 1800 - 0x4001 1BFF 0x4001 1400 - 0x4001 17FF 0x4001 1000 - 0x4001 13FF 0x4001 0C00 - 0x4001 0FFF 0x4001 0800 - 0x4001 0BFF 0x4001 0400 - 0x4001 07FF 0x4001 0000 - 0x4001 03FF 0x4000 7800 - 0x4000 FFFF Port E Port D Port C Port B Port A EXTI AFIO Reserved DAC PWR 0xC000 0000 0xBFFF FFFF 0x6000 0000 0x5FFF FFFF CRC Reserved USART1 Reserved SPI1 Reserved 512-Mbyte block 6 Not used 0x8000 0000 0x7FFF FFFF 0xA000 1000 - 0xBFFF FFFF 0x4000 7400 - 0x4000 77FF 0x4000 7000 - 0x4000 73FF BKP 0x4000 6C00 - 0x4000 6FFF Reserved 0x4000 5C00 - 0x4000 6BFF I2C2 I2C1 0x4000 5800 - 0x4000 5BFF 0x4000 5400 - 0x4000 57FF UART5 0x4000 5000 - 0x4000 53FF UART4 0x4000 4C00 - 0x4000 4FFF USART3 USART2 0x4000 4800 - 0x4000 4BFF 0x4000 4400 - 0x4000 47FF Reserved 0x4000 4000 - 0x4000 43FF SPI3 0x4000 3C00 - 0x4000 3FFF SPI2 0x4000 3800 - 0x4000 3BFF Reserved IWDG 0x4000 3000 - 0x4000 33FF WWDG 0x4000 2C00 - 0x4000 2FFF RTC 0x4000 2800 - 0x4000 2BFF Reserved 0x4000 1800 - 0x4000 27FF TIM7 0x4000 1400 - 0x4000 17FF 0x4000 3400 - 0x4000 37FF TIM6 0x4000 1000 - 0x4000 13FF TIM5 0x4000 0C00 - 0x4000 0FFF TIM4 0x4000 0800 - 0x4000 0BFF TIM3 0x4000 0400 - 0x4000 07FF TIM2 0x4000 0000 - 0x4000 03FF 0x3FFF FFFF 0x2000 C000 0x2000 BFFF 0x2000 0000 0x1FFF F800 - 0x1FFF F80F 0x1FFF F000- 0x1FFF F7FF 0x1FFF EFFF 0x0808 0000 0x0807 FFFF 0x0800 0000 0x07FF FFFF 0x0008 0000 0x0007 FFFF 0x0000 0000 ai14811c 33/112 Electrical characteristics STM32F101xC, STM32F101xD, STM32F101xE 5 Electrical characteristics 5.1 Parameter conditions Unless otherwise specified, all voltages are referenced to VSS. 5.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean±3Σ). 5.1.2 Typical values Unless otherwise specified, typical data are based on TA = 25 °C, VDD = 3.3 V (for the 2 V ≤ VDD ≤ 3.6 V voltage range). They are given only as design guidelines and are not tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean±2Σ). 5.1.3 Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 5.1.4 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 7. 34/112 Doc ID 14610 Rev 8 STM32F101xC, STM32F101xD, STM32F101xE 5.1.5 Electrical characteristics Pin input voltage The input voltage measurement on a pin of the device is described in Figure 8. Figure 7. Pin loading conditions Figure 8. Pin input voltage STM32F101 PIN STM32F101 PIN C=50pF VIN ai14123 5.1.6 ai14124 Power supply scheme Figure 9. Power supply scheme 6"!4 6 "ACKUPCIRCUITRY /3#+24# 7AKEUPLOGIC "ACKUPREGISTERS /54 '0)/S ). ,EVELSHIFTER 0O WERSWI TCH )/ ,OGIC +ERNELLOGIC #05 $IGITAL -EMORIES 6$$ 6$$ 2EGULATOR §N& §& 633 6$$ 6$$! 62%& N& & N& & 62%& 62%& !$# $!# !NALOG 2#S0,, 633! AI Caution: In Figure 9, the 4.7 µF capacitor must be connected to VDD3. Doc ID 14610 Rev 8 35/112 Electrical characteristics 5.1.7 STM32F101xC, STM32F101xD, STM32F101xE Current consumption measurement Figure 10. Current consumption measurement scheme IDD_VBAT VBAT IDD VDD VDDA ai14126 5.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 7: Voltage characteristics, Table 8: Current characteristics, and Table 9: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 7. Symbol VDD − VSS VIN (2) |ΔVDDx| |VSSX − VSS| VESD(HBM) Voltage characteristics Ratings Min Max –0.3 4.0 Input voltage on five volt tolerant pin VSS − 0.3 VDD + 4.0 Input voltage on any other pin VSS − 0.3 4.0 External main supply voltage (including VDDA and VDD)(1) Variations between different VDD power pins 50 Variations between all the different ground pins 50 Electrostatic discharge voltage (human body model) Unit V mV see Section 5.3.12: Absolute maximum ratings (electrical sensitivity) 1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. 2. VIN maximum must always be respected. Refer to Table 8: Current characteristics for the maximum allowed injected current values. 36/112 Doc ID 14610 Rev 8 STM32F101xC, STM32F101xD, STM32F101xE Table 8. Electrical characteristics Current characteristics Symbol Ratings Max. Total current into VDD/VDDA power lines (source)(1) IVDD Total current out of VSS ground lines (sink) IVSS 150 (1) 150 Output current sunk by any I/O and control pin IIO 25 − 25 Output current source by any I/Os and control pin (3) Injected current on five volt tolerant pins IINJ(PIN)(2) Injected current on any other pin ΣIINJ(PIN) mA -5/+0 (4) Total injected current (sum of all I/O and control pins) Unit ±5 (5) ± 25 1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. 2. Negative injection disturbs the analog performance of the device. See note 3 below Table 58 on page 95. 3. Positive injection is not possible on these I/Os. A negative injection is induced by VIN<VSS. IINJ(PIN) must never be exceeded. Refer to Table 7: Voltage characteristics for the maximum allowed input voltage values. 4. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. IINJ(PIN) must never be exceeded. Refer to Table 7: Voltage characteristics for the maximum allowed input voltage values. 5. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values). Table 9. Thermal characteristics Symbol TSTG TJ Ratings Storage temperature range Maximum junction temperature Doc ID 14610 Rev 8 Value Unit –65 to +150 °C 150 °C 37/112 Electrical characteristics STM32F101xC, STM32F101xD, STM32F101xE 5.3 Operating conditions 5.3.1 General operating conditions Table 10. Symbol General operating conditions Parameter Conditions Min Max fHCLK Internal AHB clock frequency 0 36 fPCLK1 Internal APB1 clock frequency 0 36 fPCLK2 Internal APB2 clock frequency 0 36 Standard operating voltage 2 3.6 2 3.6 VDD VDDA(1) Analog operating voltage (ADC not used) Analog operating voltage (ADC used) VBAT Backup operating voltage PD Power dissipation at TA = 85 °C(3) TA TJ Ambient temperature Must be the same potential as VDD(2) Unit MHz V V 2.4 3.6 1.8 3.6 LQFP144 666 LQFP100 434 LQFP64 444 V mW Maximum power dissipation –40 85 °C Low power dissipation(4) –40 105 °C –40 105 °C Junction temperature range 1. When the ADC is used, refer to Table 55: ADC characteristics. 2. It is recommended to power VDD and VDDA from the same source. A maximum difference of 300 mV between VDD and VDDA can be tolerated during power-up and operation. 3. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax (see Table 6.2: Thermal characteristics on page 104). 4. In low power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax (see Table 6.2: Thermal characteristics on page 104). 5.3.2 Operating conditions at power-up / power-down The parameters given in Table 11 are derived from tests performed under the ambient temperature condition summarized in Table 10. Table 11. Symbol tVDD 38/112 Operating conditions at power-up / power-down Parameter Conditions Min Max VDD rise time rate 0 ∞ VDD fall time rate 20 ∞ Doc ID 14610 Rev 8 Unit µs/V STM32F101xC, STM32F101xD, STM32F101xE 5.3.3 Electrical characteristics Embedded reset and power control block characteristics The parameters given in Table 12 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 10. . Table 12. Embedded reset and power control block characteristics Symbol Parameter Conditions Programmable voltage detector level selection VPVD VPVDhyst(2) PVD hysteresis VPOR/PDR Power on/power down reset threshold VPDRhyst (2) tRSTTEMPO(2) Min Typ Max Unit PLS[2:0]=000 (rising edge) 2.1 2.18 2.26 V PLS[2:0]=000 (falling edge) 2 2.08 2.16 V PLS[2:0]=001 (rising edge) 2.19 2.28 2.37 V PLS[2:0]=001 (falling edge) 2.09 2.18 2.27 V PLS[2:0]=010 (rising edge) 2.28 2.38 2.48 V PLS[2:0]=010 (falling edge) 2.18 2.28 2.38 V PLS[2:0]=011 (rising edge) 2.38 2.48 2.58 V PLS[2:0]=011 (falling edge) 2.28 2.38 2.48 V PLS[2:0]=100 (rising edge) 2.47 2.58 2.69 V PLS[2:0]=100 (falling edge) 2.37 2.48 2.59 V PLS[2:0]=101 (rising edge) 2.57 2.68 2.79 V PLS[2:0]=101 (falling edge) 2.47 2.58 2.69 V PLS[2:0]=110 (rising edge) 2.66 2.78 2.9 V PLS[2:0]=110 (falling edge) 2.56 2.68 2.8 V PLS[2:0]=111 (rising edge) 2.76 2.88 3 V PLS[2:0]=111 (falling edge) 2.66 2.78 2.9 V 100 mV Falling edge 1.8(1) 1.88 1.96 V Rising edge 1.84 1.92 2.0 V PDR hysteresis 40 Reset temporization 1.5 2.5 mV 3.5 ms 1. The product behavior is guaranteed by design down to the minimum VPOR/PDR value. 2. Guaranteed by design, not tested in production. Doc ID 14610 Rev 8 39/112 Electrical characteristics 5.3.4 STM32F101xC, STM32F101xD, STM32F101xE Embedded reference voltage The parameters given in Table 13 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 10. Table 13. Symbol VREFINT Embedded internal reference voltage Parameter Internal reference voltage TS_vrefint(1) ADC sampling time when reading the internal reference voltage VRERINT(2) Internal reference voltage spread over the temperature range TCoeff(2) Conditions Min Typ Max Unit –40 °C < TA < +85 °C 1.16 1.20 1.24 V 5.1 17.1(2) µs 10 mV 100 ppm/ °C VDD = 3 V ±10 mV Temperature coefficient 1. Shortest sampling time can be determined in the application by multiple iterations. 2. Guaranteed by design, not tested in production. 5.3.5 Supply current characteristics The current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code. The current consumption is measured as described in Figure 10: Current consumption measurement scheme. All Run-mode current consumption measurements given in this section are performed with a reduced code that gives a consumption equivalent to Dhrystone 2.1 code. Maximum current consumption The MCU is placed under the following conditions: ● All I/O pins are in input mode with a static value at VDD or VSS (no load) ● All peripherals are disabled except if it is explicitly mentioned ● The Flash access time is adjusted to fHCLK frequency (0 wait state from 0 to 24 MHz, 1 wait state from 24 to 36 MHz) ● Prefetch in on (reminder: this bit must be set before clock setting and bus prescaling) ● When the peripherals are enabled fPCLK1 = fHCLK/2, fPCLK2 = fHCLK The parameters given in Table 14 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 10. 40/112 Doc ID 14610 Rev 8 STM32F101xC, STM32F101xD, STM32F101xE Table 14. Electrical characteristics Maximum current consumption in Run mode, code with data processing running from Flash Max(1) Symbol Parameter Conditions fHCLK Unit TA = 85 °C External clock (2), all peripherals enabled IDD Supply current in Run mode 36 MHz 39 24 MHz 27 16 MHz 20 8 MHz 11 36 MHz 22 24 MHz 16.5 16 MHz 12.5 8 MHz 8 mA External clock (2), all peripherals disabled 1. Based on characterization, not tested in production. 2. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz. Table 15. Maximum current consumption in Run mode, code with data processing running from RAM Max(1) Symbol Parameter Conditions fHCLK Unit TA = 85 °C External clock (2), all peripherals enabled IDD Supply current in Run mode 36 MHz 34 24 MHz 24 16 MHz 17 8 MHz 10 36 MHz 18 24 MHz 13 16 MHz 10 8 MHz 6 mA External clock(2) all peripherals disabled 1. Based on characterization, tested in production at VDD max, fHCLK max. 2. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz. Doc ID 14610 Rev 8 41/112 Electrical characteristics STM32F101xC, STM32F101xD, STM32F101xE Figure 11. Typical current consumption in Run mode versus frequency (at 3.6 V) code with data processing running from RAM, peripherals enabled 35 30 8 MHz 16 MHz Consumption (mA) 25 24 MHz 36 MHz 20 15 10 5 0 -45 25 70 85 Temperature (°C) Figure 12. Typical current consumption in Run mode versus frequency (at 3.6 V) code with data processing running from RAM, peripherals disabled 18 16 Consumption (mA) 8 MHz 14 16 MHz 12 24 MHz 36 MHz 10 8 6 4 2 0 -45 25 70 Temperature (°C) 42/112 Doc ID 14610 Rev 8 85 STM32F101xC, STM32F101xD, STM32F101xE Table 16. Electrical characteristics Maximum current consumption in Sleep mode, code running from Flash or RAM Max(1) Symbol Parameter Conditions fHCLK Unit TA = 85 °C External clock(2) all peripherals enabled IDD Supply current in Sleep mode 36 MHz 24 24 MHz 17 16 MHz 12.5 8 MHz 8 36 MHz 6 24 MHz 5 16 MHz 4.5 8 MHz 4 mA External clock(2), all peripherals disabled 1. Based on characterization, tested in production at VDD max, fHCLK max with peripherals enabled. 2. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz. Table 17. Typical and maximum current consumptions in Stop and Standby modes Typ(1) Symbol Parameter Supply current in Stop mode IDD Supply current in Standby mode IDD_VBAT Conditions Max VDD/ VBAT VDD/ VBAT VDD/VBAT TA = = 2.0 V = 2.4 V = 3.3 V 85 °C Regulator in Run mode, Low-speed and high-speed internal RC oscillators and high-speed oscillator OFF (no independent watchdog) 34.5 35 379 Regulator in Low-power mode, Low-speed and high-speed internal RC oscillators and high-speed oscillator OFF (no independent watchdog) 24.5 25 365 Low-speed internal RC oscillator and independent watchdog ON 3 3.8 - Low-speed internal RC oscillator ON, independent watchdog OFF 2.8 3.6 - Low-speed internal RC oscillator and independent watchdog OFF, low-speed oscillator and RTC OFF 1.9 2.1 5(2) 1.1 1.4 2(2) Backup domain Low-speed oscillator and RTC ON supply current 1.05 Unit µA 1. Typical values are measured at TA = 25 °C. 2. Based on characterization, not tested in production. Doc ID 14610 Rev 8 43/112 Electrical characteristics STM32F101xC, STM32F101xD, STM32F101xE Figure 13. Typical current consumption on VBAT with RTC on vs. temperature at different VBAT values 2.5 Consumption (µA) 2 1.8 V 1.5 2V 2.4 V 3.3 V 1 3.6 V 0.5 0 –45 25 85 105 Temperature (°C) ai17337 Figure 14. Typical current consumption in Stop mode with regulator in run mode versus temperature at different VDD values 300 Consumption (µA) 250 200 150 100 2.4V 2.7V 3.0V 3.3V 3.6V 50 0 -45 25 70 Temperature (°C) 44/112 Doc ID 14610 Rev 8 85 STM32F101xC, STM32F101xD, STM32F101xE Electrical characteristics Figure 15. Typical current consumption in Stop mode with regulator in low-power mode versus temperature at different VDD values 300 Consumption (µA) 250 200 150 100 2.4V 2.7V 3.0V 3.3V 3.6V 50 0 -45 25 70 85 Temperature (°C) Figure 16. Typical current consumption in Standby mode versus temperature at different VDD values 3.5 3 Consumption (µA) 2.5 2 1.5 1 2.4V 2.7V 3.0V 3.3V 3.6V 0.5 0 -45 25 70 85 Temperature (°C) Doc ID 14610 Rev 8 45/112 Electrical characteristics STM32F101xC, STM32F101xD, STM32F101xE Typical current consumption The MCU is placed under the following conditions: ● All I/O pins are in input mode with a static value at VDD or VSS (no load) ● All peripherals are disabled except if it is explicitly mentioned ● The Flash access time is adjusted to fHCLK frequency (0 wait state from 0 to 24 MHz, 1 wait state from 24 to 36 MHz) ● Prefetch is on (reminder: this bit must be set before clock setting and bus prescaling) ● When the peripherals are enabled fPCLK1 = fHCLK/4, fPCLK2 = fHCLK/2, fADCCLK = fPCLK2/4 ● When the peripherals are enabled fPCLK1 = fHCLK, fPCLK2 = fHCLK, fADCCLK = fPCLK2/2 The parameters given in Table 18 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 10. Table 18. Symbol Typical current consumption in Run mode, code with data processing running from Flash Parameter Conditions External clock(3) IDD Supply current in Run mode Typ(1) Typ(1) All peripherals enabled(2) All peripherals disabled 36 MHz 26.6 16.2 24 MHz 18.5 11.4 16 MHz 12.8 8.2 8 MHz 7.2 5 4 MHz 4.2 3.1 2 MHz 2.7 2.1 1 MHz 2 1.7 500 kHz 1.6 1.4 125 kHz 1.3 1.2 36 MHz 26 15.6 24 MHz 17.9 10.8 16 MHz 12.2 7.6 8 MHz 6.6 4.4 4 MHz 3.6 2.5 2 MHz 2.1 1.5 1 MHz 1.4 1.1 500 kHz 1 0.8 125 kHz 0.7 0.6 fHCLK mA Running on high speed internal RC (HSI), AHB prescaler used to reduce the frequency 1. Typical values are measures at TA = 25 °C, VDD = 3.3 V. 2. Add an additional power consumption of 0.8 mA per ADC for the analog part. In applications, this consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register). 3. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz. 46/112 Unit Doc ID 14610 Rev 8 STM32F101xC, STM32F101xD, STM32F101xE Table 19. Electrical characteristics Typical current consumption in Sleep mode, code running from Flash or RAM Typ(1) Symbol Parameter Conditions (3) External clock Supply current in Sleep mode IDD fHCLK Typ(1) All peripherals All peripherals enabled(2) disabled 36 MHz 15.1 3.6 24 MHz 10.4 2.6 16 MHz 7.2 2 8 MHz 3.9 1.3 4 MHz 2.6 1.2 2 MHz 1.85 1.15 1 MHz 1.5 1.1 500 kHz 1.3 1.05 125 kHz 1.2 1.05 36 MHz 14.5 3 24 MHz 9.8 2 16 MHz 6.6 1.4 8 MHz 3.3 0.7 4 MHz 2 0.6 2 MHz 1.25 0.55 1 MHz 0.9 0.5 500 kHz 0.7 0.45 125 kHz 0.6 0.45 Unit mA Running on High Speed Internal RC (HSI), AHB prescaler used to reduce the frequency 1. Typical values are measures at TA = 25 °C, VDD = 3.3 V. 2. Add an additional power consumption of 0.8 mA per ADC for the analog part. In applications, this consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register). 3. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz. On-chip peripheral current consumption The current consumption of the on-chip peripherals is given in Table 20. The MCU is placed under the following conditions: ● all I/O pins are in input mode with a static value at VDD or VSS (no load) ● all peripherals are disabled unless otherwise mentioned ● the given value is calculated by measuring the current consumption ● – with all peripherals clocked off – with only one peripheral clocked on ambient operating temperature and VDD supply voltage conditions summarized in Table 7. Doc ID 14610 Rev 8 47/112 Electrical characteristics Table 20. STM32F101xC, STM32F101xD, STM32F101xE Peripheral current consumption Peripheral APB1 Typical consumption at 25 °C(1) TIM2 0.6 TIM3 0.6 TIM4 0.6 TIM5 0.6 TIM6 0.2 TIM7 0.2 SPI2 0.15 SPI3 0.15 USART2 0.25 USART3 0.25 UART4 0.3 UART5 0.3 I2C1 0.22 I2C2 0.22 DAC 0.72 GPIOA 0.3 GPIOB 0.4 GPIOC 0.4 GPIOD 0.3 GPIOE 0.5 GPIOF 0.4 GPIOG 0.5 (2) ADC 1.4 SPI1 0.3 USART1 0.6 APB2 48/112 Unit mA mA Doc ID 14610 Rev 8 STM32F101xC, STM32F101xD, STM32F101xE Table 20. Peripheral current consumption (continued) Peripheral APB2 Electrical characteristics Typical consumption at 25 °C(1) GPIOA 0.35 GPIOB 0.4 GPIOC 0.4 GPIOD 0.4 GPIOE 0.4 GPIOF 0.4 GPIOG 0.4 TIM1 1 TIM8 1 TIM9 0.5 TIM10 0.4 TIM11 0.4 (3) 1.4 ADC2(3) 1.4 (3) 1.4 ADC1 ADC3 SPI1 0.3 USART1 0.6 Unit mA 1. fHCLK = 36 MHz, fAPB1 = fHCLK/2, fAPB2 = fHCLK, default prescaler value for each peripheral. 2. Specific conditions for ADC: fHCLK = 28 MHz, fAPB1 = fHCLK/2, fAPB2 = fHCLK, fADCCLK = fAPB2/2, ADON bit in the ADC_CR2 register is set to 1. 3. Specific conditions for ADC: fHCLK = 28 MHz, fAPB1 = fHCLK/2, fAPB2 = fHCLK, fADCCLK = fAPB2/2, ADON bit in the ADC_CR2 register is set to 1. 5.3.6 External clock source characteristics High-speed external user clock generated from an external source The characteristics given in Table 21 result from tests performed using an high-speed external clock source, and under ambient temperature and supply voltage conditions summarized in Table 10. Doc ID 14610 Rev 8 49/112 Electrical characteristics Table 21. STM32F101xC, STM32F101xD, STM32F101xE High-speed external user clock characteristics Symbol Parameter Conditions Min Typ Max Unit 8 25 MHz fHSE_ext User external clock source frequency(1) 1 VHSEH OSC_IN input pin high level voltage 0.7VDD VDD VHSEL OSC_IN input pin low level voltage VSS 0.3VDD tw(HSE) tw(HSE) OSC_IN high or low time(1) 5 tr(HSE) tf(HSE) OSC_IN rise or fall time(1) V Cin(HSE) ns 20 OSC_IN input capacitance(1) 5 DuCy(HSE) Duty cycle IL pF 45 VSS ≤ VIN ≤ VDD OSC_IN Input leakage current 55 % ±1 µA 1. Guaranteed by design, not tested in production Low-speed external user clock generated from an external source The characteristics given in Table 22 result from tests performed using an low-speed external clock source, and under ambient temperature and supply voltage conditions summarized in Table 10. Table 22. Symbol Low-speed user external clock characteristics Parameter Conditions Min fLSE_ext User external clock source frequency(1) VLSEH OSC32_IN input pin high level voltage VLSEL OSC32_IN input pin low level voltage VSS tw(LSE) tw(LSE) OSC32_IN high or low time(1) 450 Typ Max Unit 32.768 1000 kHz VDD 0.7VDD V tr(LSE) tf(LSE) Cin(LSE) ns OSC32_IN rise or fall time(1) 50 OSC32_IN input capacitance(1) 5 DuCy(LSE) Duty cycle IL 30 OSC32_IN Input leakage current VSS ≤ VIN ≤ VDD 1. Guaranteed by design, not tested in production. 50/112 0.3VDD Doc ID 14610 Rev 8 pF 70 % ±1 µA STM32F101xC, STM32F101xD, STM32F101xE Electrical characteristics Figure 17. High-speed external clock source AC timing diagram VHSEH 90% VHSEL 10% tr(HSE) tf(HSE) tW(HSE) t tW(HSE) THSE External clock source fHSE_ext OSC _IN IL STM32F10xxx ai14127b Figure 18. Low-speed external clock source AC timing diagram VLSEH 90% VLSEL 10% tr(LSE) tf(LSE) tW(LSE) OSC32_IN IL tW(LSE) t TLSE External clock source fLSE_ext STM32F10xxx ai14140c Doc ID 14610 Rev 8 51/112 Electrical characteristics STM32F101xC, STM32F101xD, STM32F101xE High-speed external clock generated from a crystal/ceramic resonator The high-speed external (HSE) clock can be supplied with a 4 to 16 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 23. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). Table 23. Symbol fOSC_IN HSE 4-16 MHz oscillator characteristics(1)(2) Parameter Conditions Oscillator frequency Min Typ Max Unit 4 8 16 MHz RF Feedback resistor 200 kΩ C Recommended load capacitance versus equivalent serial RS = 30 Ω resistance of the crystal (RS)(3) 30 pF i2 HSE driving current VDD = 3.3 V VIN = VSS with 30 pF load gm Oscillator transconductance Startup tSU(HSE)(4) Startup time 1 25 VDD is stabilized mA mA/V 2 ms 1. Resonator characteristics given by the crystal/ceramic resonator manufacturer. 2. Based on characterization results, not tested in production. 3. The relatively low value of the RF resistor offers a good protection against issues resulting from use in a humid environment, due to the induced leakage and the bias condition change. However, it is recommended to take this point into account if the MCU is used in tough humidity conditions. 4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the 5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see Figure 19). CL1 and CL2 are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing CL1 and CL2. Refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com. 52/112 Doc ID 14610 Rev 8 STM32F101xC, STM32F101xD, STM32F101xE Electrical characteristics Figure 19. Typical application with an 8 MHz crystal Resonator with integrated capacitors CL1 fHSE OSC_IN 8 MH z resonator CL2 REXT(1) RF Bias controlled gain STM32F10xxx OSC_OU T ai14128b 1. REXT value depends on the crystal characteristics. Low-speed external clock generated from a crystal/ceramic resonator The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 24. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). Table 24. Symbol LSE oscillator characteristics (fLSE = 32.768 kHz)(1) (2) Parameter Conditions Min Typ Max RF Feedback resistor C Recommended load capacitance versus equivalent serial resistance of the crystal (RS) RS = 30 KΩ 15 pF I2 LSE driving current VDD = 3.3 V VIN = VSS 1.4 µA gm Oscillator transconductance tSU(LSE)(3) 5 Unit 5 VDD is stabilized Startup time MΩ µA/V TA = 50 °C 1.5 TA = 25 °C 2.5 TA = 10 °C 4 TA = 0 °C 6 TA = -10 °C 10 TA = -20 °C 17 TA = -30 °C 32 TA = -40 °C 60 s 1. Based on characterization, not tested in production. 2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for ST microcontrollers”. 3. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is reached. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer Doc ID 14610 Rev 8 53/112 Electrical characteristics STM32F101xC, STM32F101xD, STM32F101xE Note: For CL1 and CL2, it is recommended to use high-quality ceramic capacitors in the 5 pF to 15 pF range selected to match the requirements of the crystal or resonator. CL1 and CL2, are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2. Load capacitance CL has the following formula: CL = CL1 x CL2 / (CL1 + CL2) + Cstray where Cstray is the pin capacitance and board or trace PCB-related capacitance. Typically, it is between 2 pF and 7 pF. Caution: To avoid exceeding the maximum value of CL1 and CL2 (15 pF) it is strongly recommended to use a resonator with a load capacitance CL ≤ 7 pF. Never use a resonator with a load capacitance of 12.5 pF. Example: if you choose a resonator with a load capacitance of CL = 6 pF, and Cstray = 2 pF, then CL1 = CL2 = 8 pF. Figure 20. Typical application with a 32.768 kHz crystal Resonator with integrated capacitors CL1 fLSE OSC32_IN 32.768 KH z resonator CL2 Bias controlled gain RF STM32F10xxx OSC32_OU T ai14129b 5.3.7 Internal clock source characteristics The parameters given in Table 25 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 10. High-speed internal (HSI) RC oscillator Table 25. Symbol fHSI HSI oscillator characteristics(1) Parameter Conditions Min Frequency Typ 8 DuCy(HSI) Duty cycle 45 Accuracy of the HSI oscillator TA = –40 to 105 °C TA = –10 to 85 °C Factory(4) calibrated TA = 0 to 70 °C TA = 25 °C tsu(HSI)(4) HSI oscillator startup time IDD(HSI)(4) HSI oscillator power consumption 54/112 Doc ID 14610 Rev 8 MHz % 1(3) % –2 2.5 % –1.5 2.2 % –1.3 2 % –1.1 1.8 % 1 2 µs 100 µA 80 1. VDD = 3.3 V, TA = –40 to 85 °C unless otherwise specified. Unit 55 User-trimmed with the RCC_CR register(2) ACCHSI Max STM32F101xC, STM32F101xD, STM32F101xE Electrical characteristics 2. Refer to application note AN2868 “STM32F10xxx internal RC oscillator (HSI) calibration” available from the ST website www.st.com. 3. Guaranteed by design, not tested in production. 4. Based on characterization, not tested in production. Low-speed internal (LSI) RC oscillator LSI oscillator characteristics (1) Table 26. Symbol fLSI(2) Parameter Frequency tsu(LSI)(3) LSI oscillator startup time IDD(LSI)(3) LSI oscillator power consumption Min Typ Max Unit 30 40 60 kHz 85 µs 1.2 µA 0.65 1. VDD = 3 V, TA = –40 to 85 °C unless otherwise specified. 2. Based on characterization, not tested in production. 3. Guaranteed by design, not tested in production. Wakeup time from low-power mode The wakeup times given in Table 27 are measured on a wakeup phase with an 8-MHz HSI RC oscillator. The clock source used to wake up the device depends from the current operating mode: ● Stop or Standby mode: the clock source is the RC oscillator ● Sleep mode: the clock source is the clock that was set before entering Sleep mode. All timings are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 10. Table 27. Low-power mode wakeup timings Symbol tWUSLEEP(1) tWUSTOP(1) tWUSTDBY(1) Parameter Typ Unit Wakeup from Sleep mode 1.8 µs Wakeup from Stop mode (regulator in run mode) 3.6 Wakeup from Stop mode (regulator in low-power mode) 5.4 Wakeup from Standby mode 50 µs µs 1. The wakeup times are measured from the wakeup event to the point at which the user application code reads the first instruction. Doc ID 14610 Rev 8 55/112 Electrical characteristics 5.3.8 STM32F101xC, STM32F101xD, STM32F101xE PLL characteristics The parameters given in Table 28 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 10. Table 28. PLL characteristics Value Symbol Parameter Unit Min(1) Typ Max(1) PLL input clock(2) 1 8.0 25 MHz PLL input clock duty cycle 40 60 % fPLL_OUT PLL multiplier output clock 16 36 MHz tLOCK PLL lock time 200 µs Jitter Cycle-to-cycle jitter 300 ps fPLL_IN 1. Based on characterization, not tested in production. 2. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with the range defined by fPLL_OUT. 5.3.9 Memory characteristics Flash memory The characteristics are given at TA = –40 to 85 °C unless otherwise specified. Table 29. Symbol Flash memory characteristics Parameter Conditions Min Typ Max(1) Unit 52.5 70 µs tprog 16-bit programming time TA = –40 to +85 °C 40 tERASE Page (2 KB) erase time TA = –40 to +85 °C 20 40 ms Mass erase time TA = –40 to +85 °C 20 40 ms Read mode fHCLK = 36 MHz with 1 wait state, VDD = 3.3 V 28 mA Write mode fHCLK = 36 MHz, VDD = 3.3 V 7 mA Erase mode fHCLK = 36 MHz, VDD = 3.3 V 5 mA Power-down mode / Halt, VDD = 3.0 to 3.6 V 50 µA 3.6 V tME IDD Vprog Supply current Programming voltage 1. Guaranteed by design, not tested in production. 56/112 Doc ID 14610 Rev 8 2 STM32F101xC, STM32F101xD, STM32F101xE Table 30. Electrical characteristics Flash memory endurance and data retention Value Symbol NEND Parameter Endurance Conditions TA = –40 °C to 85 °C (2) tRET Data retention Min(1) 10 TA = 85 °C, 1 kcycle 30 TA = 55 °C, 10 kcycle(2) 20 Unit kcycles Years 1. Based on characterization, not tested in production. 2. Cycling performed over the whole temperature range. 5.3.10 FSMC characteristics Asynchronous waveforms and timings Figure 21 through Figure 24 represent asynchronous waveforms and Table 31 through Table 34 provide the corresponding timings. The results shown in these tables are obtained with the following FSMC configuration: ● AddressSetupTime = 0 ● AddressHoldTime = 1 ● DataSetupTime = 1 Doc ID 14610 Rev 8 57/112 Electrical characteristics STM32F101xC, STM32F101xD, STM32F101xE Figure 21. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms TW.% &3-#?.% T V./%?.% T W./% T H.%?./% &3-#?./% &3-#?.7% TV!?.% &3-#?!;= T H!?./% !DDRESS TV",?.% T H",?./% &3-#?.",;= T H$ATA?.% T SU$ATA?./% TH$ATA?./% T SU$ATA?.% $ATA &3-#?$;= T V.!$6?.% TW.!$6 &3-#?.!$6 -36 1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used. Table 31. Symbol 58/112 Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings(1) (2) Parameter Min Max Unit tw(NE) FSMC_NE low time 5tHCLK – 1.5 5tHCLK + 2 ns tv(NOE_NE) FSMC_NEx low to FSMC_NOE low 0.5 1.5 ns tw(NOE) FSMC_NOE low time 5tHCLK – 1.5 5tHCLK + 1.5 ns th(NE_NOE) FSMC_NOE high to FSMC_NE high hold time –1.5 tv(A_NE) FSMC_NEx low to FSMC_A valid th(A_NOE) Address hold time after FSMC_NOE high tv(BL_NE) FSMC_NEx low to FSMC_BL valid th(BL_NOE) FSMC_BL hold time after FSMC_NOE high 0 ns tsu(Data_NE) Data to FSMC_NEx high setup time 2tHCLK + 25 ns tsu(Data_NOE) Data to FSMC_NOEx high setup time 2tHCLK + 25 ns th(Data_NOE) Data hold time after FSMC_NOE high 0 ns th(Data_NE) Data hold time after FSMC_NEx high 0 ns Doc ID 14610 Rev 8 ns 7 0.1 ns ns 0 ns STM32F101xC, STM32F101xD, STM32F101xE Electrical characteristics Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings(1) (2) Table 31. Symbol Parameter Min Max Unit tv(NADV_NE) FSMC_NEx low to FSMC_NADV low 5 ns tw(NADV) FSMC_NADV low time tHCLK + 1.5 ns 1. CL = 15 pF. 2. Based on characterization, not tested in production. Figure 22. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms tw(NE) FSMC_NEx FSMC_NOE tv(NWE_NE) tw(NWE) t h(NE_NWE) FSMC_NWE tv(A_NE) FSMC_A[25:0] th(A_NWE) Address tv(BL_NE) FSMC_NBL[1:0] th(BL_NWE) NBL tv(Data_NE) th(Data_NWE) Data FSMC_D[15:0] t v(NADV_NE) tw(NADV) FSMC_NADV(1) ai14990 1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used. Table 32. Symbol Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings(1)(2) Parameter Min Max Unit tw(NE) FSMC_NE low time 3tHCLK – 1 3tHCLK + 2 ns tv(NWE_NE) FSMC_NEx low to FSMC_NWE low tHCLK – 0.5 tHCLK + 1.5 ns tw(NWE) FSMC_NWE low time tHCLK – 0.5 tHCLK + 1.5 ns th(NE_NWE) FSMC_NWE high to FSMC_NE high hold time tHCLK tv(A_NE) FSMC_NEx low to FSMC_A valid th(A_NWE) Address hold time after FSMC_NWE high tv(BL_NE) FSMC_NEx low to FSMC_BL valid th(BL_NWE) FSMC_BL hold time after FSMC_NWE high tv(Data_NE) FSMC_NEx low to Data valid th(Data_NWE) Data hold time after FSMC_NWE high Doc ID 14610 Rev 8 ns 7.5 tHCLK ns 1.5 tHCLK – 0.5 ns ns tHCLK + 7 tHCLK ns ns ns 59/112 Electrical characteristics STM32F101xC, STM32F101xD, STM32F101xE Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings(1)(2) Table 32. Symbol Parameter Min Max Unit tv(NADV_NE) FSMC_NEx low to FSMC_NADV low 5.5 ns tw(NADV) FSMC_NADV low time tHCLK + 1.5 ns 1. CL = 15 pF. 2. Based on characterization, not tested in production. Figure 23. Asynchronous multiplexed NOR/PSRAM read waveforms tw(NE) FSMC_NE tv(NOE_NE) t h(NE_NOE) FSMC_NOE t w(NOE) FSMC_NWE tv(A_NE) FSMC_A[25:16] t h(A_NOE) Address tv(BL_NE) th(BL_NOE) FSMC_NBL[1:0] NBL th(Data_NE) tsu(Data_NE) t v(A_NE) tsu(Data_NOE) Address FSMC_AD[15:0] t v(NADV_NE) th(Data_NOE) Data th(AD_NADV) tw(NADV) FSMC_NADV ai14892b Table 33. Symbol 60/112 Asynchronous multiplexed NOR/PSRAM read timings(1)(2) Parameter Min Max Unit tw(NE) FSMC_NE low time 7tHCLK – 2 7tHCLK + 2 ns tv(NOE_NE) FSMC_NEx low to FSMC_NOE low 3tHCLK – 0.5 3tHCLK + 1.5 ns tw(NOE) FSMC_NOE low time 4tHCLK – 1 4tHCLK + 2 ns th(NE_NOE) FSMC_NOE high to FSMC_NE high hold time –1 tv(A_NE) FSMC_NEx low to FSMC_A valid tv(NADV_NE) FSMC_NEx low to FSMC_NADV low tw(NADV) ns 0 ns 3 5 ns FSMC_NADV low time tHCLK –1.5 tHCLK + 1.5 ns th(AD_NADV) FSMC_AD (address) valid hold time after FSMC_NADV high tHCLK ns th(A_NOE) Address hold time after FSMC_NOE high tHCLK ns Doc ID 14610 Rev 8 STM32F101xC, STM32F101xD, STM32F101xE Table 33. Symbol Electrical characteristics Asynchronous multiplexed NOR/PSRAM read timings(1)(2) (continued) Parameter Min Max 0 Unit th(BL_NOE) FSMC_BL hold time after FSMC_NOE high ns tv(BL_NE) FSMC_NEx low to FSMC_BL valid tsu(Data_NE) Data to FSMC_NEx high setup time 2tHCLK + 24 ns tsu(Data_NOE) Data to FSMC_NOE high setup time 2tHCLK + 25 ns 0 ns th(Data_NE) Data hold time after FSMC_NEx high 0 ns th(Data_NOE) Data hold time after FSMC_NOE high 0 ns 1. CL = 15 pF. 2. Based on characterization, not tested in production. Doc ID 14610 Rev 8 61/112 Electrical characteristics STM32F101xC, STM32F101xD, STM32F101xE Figure 24. Asynchronous multiplexed NOR/PSRAM write waveforms tw(NE) FSMC_NEx FSMC_NOE tv(NWE_NE) tw(NWE) t h(NE_NWE) FSMC_NWE tv(A_NE) FSMC_A[25:16] th(A_NWE) Address tv(BL_NE) th(BL_NWE) FSMC_NBL[1:0] NBL t v(A_NE) t v(Data_NADV) Address FSMC_AD[15:0] t v(NADV_NE) th(Data_NWE) Data th(AD_NADV) tw(NADV) FSMC_NADV ai14891B Table 34. Symbol Asynchronous multiplexed NOR/PSRAM write timings(1)(2) Parameter Min Unit tw(NE) FSMC_NE low time 5tHCLK – 1 5tHCLK + 2 ns tv(NWE_NE) FSMC_NEx low to FSMC_NWE low 2tHCLK 2tHCLK + 1 ns tw(NWE) FSMC_NWE low time 2tHCLK – 1 2tHCLK + 2 ns th(NE_NWE) FSMC_NWE high to FSMC_NE high hold time tHCLK – 1 tv(A_NE) FSMC_NEx low to FSMC_A valid tv(NADV_NE) FSMC_NEx low to FSMC_NADV low tw(NADV) ns 7 ns 3 5 ns FSMC_NADV low time tHCLK – 1 tHCLK + 1 ns th(AD_NADV) FSMC_AD (address) valid hold time after FSMC_NADV high tHCLK – 3 ns th(A_NWE) Address hold time after FSMC_NWE high 4tHCLK ns tv(BL_NE) FSMC_NEx low to FSMC_BL valid th(BL_NWE) FSMC_BL hold time after FSMC_NWE high 1.6 tHCLK – 1.5 tv(Data_NADV) FSMC_NADV high to Data valid th(Data_NWE) Data hold time after FSMC_NWE high 1. CL = 15 pF. 2. Based on characterization, not tested in production. 62/112 Max Doc ID 14610 Rev 8 ns tHCLK + 1.5 tHCLK – 5 ns ns ns STM32F101xC, STM32F101xD, STM32F101xE Electrical characteristics Synchronous waveforms and timings Figure 25 through Figure 28 represent synchronous waveforms and Table 36 through Table 38 provide the corresponding timings. The results shown in these tables are obtained with the following FSMC configuration: ● BurstAccessMode = FSMC_BurstAccessMode_Enable; ● MemoryType = FSMC_MemoryType_CRAM; ● WriteBurst = FSMC_WriteBurst_Enable; ● CLKDivision = 1; (0 is not supported, see the STM32F10xxx reference manual) ● DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM Figure 25. Synchronous multiplexed NOR/PSRAM read timings "53452. TW#,+ TW#,+ &3-#?#,+ $ATALATENCY TD#,+,.%X, T D#,+,.%X( &3-#?.%X TD#,+,.!$6, TD#,+,.!$6( &3-#?.!$6 TD#,+,!)6 TD#,+,!6 &3-#?!;= TD#,+,./%, TD#,+,./%( &3-#?./% TD#,+,!$)6 TSU!$6#,+( TD#,+,!$6 &3-#?!$;= !$;= TH#,+(!$6 TSU!$6#,+( $ TSU.7!)46#,+( TH#,+(!$6 $ $ TH#,+(.7!)46 &3-#?.7!)4 7!)4#&'B7!)40/,B TSU.7!)46#,+( TH#,+(.7!)46 &3-#?.7!)4 7!)4#&'B7!)40/,B TSU.7!)46#,+( TH#,+(.7!)46 AIH Doc ID 14610 Rev 8 63/112 Electrical characteristics Table 35. STM32F101xC, STM32F101xD, STM32F101xE Synchronous multiplexed NOR/PSRAM read timings(1)(2) Symbol Parameter Max Unit tw(CLK) FSMC_CLK period td(CLKL-NExL) FSMC_CLK low to FSMC_NEx low (x = 0...2) td(CLKL-NExH) FSMC_CLK low to FSMC_NEx high (x = 0...2) td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high td(CLKL-AV) FSMC_CLK low to FSMC_Ax valid (x = 16...25) td(CLKL-AIV) FSMC_CLK low to FSMC_Ax invalid (x = 16...25) td(CLKL-NOEL) FSMC_CLK low to FSMC_NOE low td(CLKL-NOEH) FSMC_CLK low to FSMC_NOE high td(CLKL-ADV) FSMC_CLK low to FSMC_AD[15:0] valid td(CLKL-ADIV) FSMC_CLK low to FSMC_AD[15:0] invalid 0 ns tsu(ADV-CLKH) FSMC_A/D[15:0] valid data before FSMC_CLK high 6 ns th(CLKH-ADV) FSMC_A/D[15:0] valid data after FSMC_CLK high 0 ns tsu(NWAITV-CLKH) FSMC_NWAIT valid before FSMC_CLK high th(CLKH-NWAITV) FSMC_NWAIT valid after FSMC_CLK high 1. CL = 15 pF. 2. Based on characterization, not tested in production. 64/112 Min Doc ID 14610 Rev 8 55.5 ns 1.5 2 ns ns 4 5 ns ns 0 2 ns ns 1 0.5 ns ns 12 ns 8 ns 2 ns STM32F101xC, STM32F101xD, STM32F101xE Electrical characteristics Figure 26. Synchronous multiplexed PSRAM write timings "53452. TW#,+ TW#,+ &3-#?#,+ $ATALATENCY TD#,+,.%X, TD#,+,.%X( &3-#?.%X TD#,+,.!$6, TD#,+,.!$6( &3-#?.!$6 TD#,+,!6 TD#,+,!)6 &3-#?!;= TD#,+,.7%, TD#,+,.7%( &3-#?.7% TD#,+,!$)6 D#,+,$ATA TD#,+,$ATA TD#,+,!$6 &3-#?!$;= T !$;= $ $ &3-#?.7!)4 7!)4#&'B7!)40/,B TSU.7!)46#,+( TH#,+(.7!)46 TD#,+,.",( &3-#?.", AIG Doc ID 14610 Rev 8 65/112 Electrical characteristics Table 36. STM32F101xC, STM32F101xD, STM32F101xE Synchronous multiplexed PSRAM write timings(1)(2) Symbol Parameter Max Unit tw(CLK) FSMC_CLK period td(CLKL-NExL) FSMC_CLK low to FSMC_Nex low (x = 0...2) td(CLKL-NExH) FSMC_CLK low to FSMC_NEx high (x = 0...2) td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high td(CLKL-AV) FSMC_CLK low to FSMC_Ax valid (x = 16...25) td(CLKL-AIV) FSMC_CLK low to FSMC_Ax invalid (x = 16...25) td(CLKL-NWEL) FSMC_CLK low to FSMC_NWE low td(CLKL-NWEH) FSMC_CLK low to FSMC_NWE high td(CLKL-ADV) FSMC_CLK low to FSMC_AD[15:0] valid td(CLKL-ADIV) FSMC_CLK low to FSMC_AD[15:0] invalid td(CLKL-Data) FSMC_A/D[15:0] valid after FSMC_CLK low tsu(NWAITV-CLKH) FSMC_NWAIT valid before FSMC_CLK high 7 ns th(CLKH-NWAITV) FSMC_NWAIT valid after FSMC_CLK high 2 ns td(CLKL-NBLH) FSMC_CLK low to FSMC_NBL high 1 ns 1. CL = 15 pF. 2. Based on characterization, not tested in production. 66/112 Min Doc ID 14610 Rev 8 55.5 ns 2 2 ns ns 4 5 ns ns 0 2 ns ns 1 1 ns ns 12 3 ns ns 6 ns STM32F101xC, STM32F101xD, STM32F101xE Electrical characteristics Figure 27. Synchronous non-multiplexed NOR/PSRAM read timings "53452. TW#,+ TW#,+ &3-#?#,+ TD#,+,.%X, TD#,+,.%X( $ATALATENCY &3-#?.%X TD#,+,.!$6, TD#,+,.!$6( &3-#?.!$6 TD#,+,!)6 TD#,+,!6 &3-#?!;= TD#,+,./%, TD#,+,./%( &3-#?./% TSU$6#,+( TH#,+($6 TSU$6#,+( TH#,+($6 $ &3-#?$;= TSU.7!)46#,+( $ $ TH#,+(.7!)46 &3-#?.7!)4 7!)4#&'B7!)40/,B TSU.7!)46#,+( T H#,+(.7!)46 &3-#?.7!)4 7!)4#&'B7!)40/,B TSU.7!)46#,+( TH#,+(.7!)46 AIG Table 37. Synchronous non-multiplexed NOR/PSRAM read timings(1)(2) Symbol Parameter Min Max tw(CLK) FSMC_CLK period td(CLKL-NExL) FSMC_CLK low to FSMC_NEx low (x = 0...2) td(CLKL-NExH) FSMC_CLK low to FSMC_NEx high (x = 0...2) td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high td(CLKL-AV) FSMC_CLK low to FSMC_Ax valid (x = 0...25) td(CLKL-AIV) FSMC_CLK low to FSMC_Ax invalid (x = 0...25) td(CLKL-NOEL) FSMC_CLK low to FSMC_NOE low td(CLKL-NOEH) FSMC_CLK low to FSMC_NOE high 1.5 ns tsu(DV-CLKH) FSMC_D[15:0] valid data before FSMC_CLK high 6.5 ns th(CLKH-DV) FSMC_D[15:0] valid data after FSMC_CLK high 7 ns tsu(NWAITV-CLKH) FSMC_NWAIT valid before FSMC_SMCLK high 7 ns th(CLKH-NWAITV) 2 ns FSMC_NWAIT valid after FSMC_CLK high 55.5 Unit ns 1.5 2 ns ns 4 5 ns ns 0 4 ns ns 1.5 ns 1. CL = 15 pF. 2. Based on characterization, not tested in production. Doc ID 14610 Rev 8 67/112 Electrical characteristics STM32F101xC, STM32F101xD, STM32F101xE Figure 28. Synchronous non-multiplexed PSRAM write timings TW#,+ "53452. TW#,+ &3-#?#,+ TD#,+,.%X, TD#,+,.%X( $ATALATENCY &3-#?.%X TD#,+,.!$6, TD#,+,.!$6( &3-#?.!$6 TD#,+,!6 TD#,+,!)6 &3-#?!;= TD#,+,.7%, TD#,+,.7%( &3-#?.7% TD#,+,$ATA &3-#?$;= TD#,+,$ATA $ $ &3-#?.7!)4 7!)4#&'B7!)40/,B TSU.7!)46#,+( TD#,+,.",( TH#,+(.7!)46 &3-#?.", AIH Table 38. Synchronous non-multiplexed PSRAM write timings(1)(2) Symbol Parameter Max FSMC_CLK period td(CLKL-NExL) FSMC_CLK low to FSMC_NEx low (x = 0...2) td(CLKL-NExH) FSMC_CLK low to FSMC_NEx high (x = 0...2) td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high td(CLKL-AV) FSMC_CLK low to FSMC_Ax valid (x = 16...25) td(CLKL-AIV) FSMC_CLK low to FSMC_Ax invalid (x = 16...25) td(CLKL-NWEL) FSMC_CLK low to FSMC_NWE low td(CLKL-NWEH) FSMC_CLK low to FSMC_NWE high td(CLKL-Data) FSMC_D[15:0] valid data after FSMC_CLK low tsu(NWAITV-CLKH) FSMC_NWAIT valid before FSMC_CLK high 7 ns th(CLKH-NWAITV) FSMC_NWAIT valid after FSMC_CLK high 2 ns td(CLKL-NBLH) FSMC_CLK low to FSMC_NBL high 1 ns 2. Based on characterization, not tested in production. Doc ID 14610 Rev 8 55.5 Unit tw(CLK) 1. CL = 15 pF. 68/112 Min ns 2 2 ns ns 4 5 ns ns 0 2 ns ns 1 1 ns ns 6 ns STM32F101xC, STM32F101xD, STM32F101xE Electrical characteristics PC Card/CompactFlash controller waveforms and timings Figure 29 through Figure 34 represent synchronous waveforms and Table 39 provides the corresponding timings. The results shown in this table are obtained with the following FSMC configuration: ● COM.FSMC_SetupTime = 0x04; ● COM.FSMC_WaitSetupTime = 0x07; ● COM.FSMC_HoldSetupTime = 0x04; ● COM.FSMC_HiZSetupTime = 0x00; ● ATT.FSMC_SetupTime = 0x04; ● ATT.FSMC_WaitSetupTime = 0x07; ● ATT.FSMC_HoldSetupTime = 0x04; ● ATT.FSMC_HiZSetupTime = 0x00; ● IO.FSMC_SetupTime = 0x04; ● IO.FSMC_WaitSetupTime = 0x07; ● IO.FSMC_HoldSetupTime = 0x04; ● IO.FSMC_HiZSetupTime = 0x00; ● TCLRSetupTime = 0; ● TARSetupTime = 0; Figure 29. PC Card/CompactFlash controller waveforms for common memory read access FSMC_NCE4_2(1) FSMC_NCE4_1 th(NCEx-AI) tv(NCEx-A) FSMC_A[10:0] th(NCEx-NREG) th(NCEx-NIORD) th(NCEx-NIOWR) td(NREG-NCEx) td(NIORD-NCEx) FSMC_NREG FSMC_NIOWR FSMC_NIORD FSMC_NWE td(NCE4_1-NOE) tw(NOE) FSMC_NOE tsu(D-NOE) th(NOE-D) FSMC_D[15:0] ai14895b 1. FSMC_NCE4_2 remains high (inactive during 8-bit access. Doc ID 14610 Rev 8 69/112 Electrical characteristics STM32F101xC, STM32F101xD, STM32F101xE Figure 30. PC Card/CompactFlash controller waveforms for common memory write access FSMC_NCE4_1 FSMC_NCE4_2 High tv(NCE4_1-A) th(NCE4_1-AI) FSMC_A[10:0] th(NCE4_1-NREG) th(NCE4_1-NIORD) th(NCE4_1-NIOWR) td(NREG-NCE4_1) td(NIORD-NCE4_1) FSMC_NREG FSMC_NIOWR FSMC_NIORD td(NCE4_1-NWE) tw(NWE) td(NWE-NCE4_1) FSMC_NWE FSMC_NOE MEMxHIZ =1 td(D-NWE) tv(NWE-D) th(NWE-D) FSMC_D[15:0] ai14896b 70/112 Doc ID 14610 Rev 8 STM32F101xC, STM32F101xD, STM32F101xE Electrical characteristics Figure 31. PC Card/CompactFlash controller waveforms for attribute memory read access FSMC_NCE4_1 tv(NCE4_1-A) FSMC_NCE4_2 th(NCE4_1-AI) High FSMC_A[10:0] FSMC_NIOWR FSMC_NIORD td(NREG-NCE4_1) th(NCE4_1-NREG) FSMC_NREG FSMC_NWE td(NCE4_1-NOE) tw(NOE) td(NOE-NCE4_1) FSMC_NOE tsu(D-NOE) th(NOE-D) FSMC_D[15:0](1) ai14897b 1. Only data bits 0...7 are read (bits 8...15 are disregarded). Doc ID 14610 Rev 8 71/112 Electrical characteristics STM32F101xC, STM32F101xD, STM32F101xE Figure 32. PC Card/CompactFlash controller waveforms for attribute memory write access FSMC_NCE4_1 FSMC_NCE4_2 High tv(NCE4_1-A) th(NCE4_1-AI) FSMC_A[10:0] FSMC_NIOWR FSMC_NIORD td(NREG-NCE4_1) th(NCE4_1-NREG) FSMC_NREG td(NCE4_1-NWE) tw(NWE) FSMC_NWE td(NWE-NCE4_1) FSMC_NOE tv(NWE-D) FSMC_D[7:0](1) ai14898b 1. Only data bits 0...7 are driven (bits 8...15 remains HiZ). Figure 33. PC Card/CompactFlash controller waveforms for I/O space read access FSMC_NCE4_1 FSMC_NCE4_2 th(NCE4_1-AI) tv(NCEx-A) FSMC_A[10:0] FSMC_NREG FSMC_NWE FSMC_NOE FSMC_NIOWR tw(NIORD) td(NIORD-NCE4_1) FSMC_NIORD tsu(D-NIORD) td(NIORD-D) FSMC_D[15:0] ai14899B 72/112 Doc ID 14610 Rev 8 STM32F101xC, STM32F101xD, STM32F101xE Electrical characteristics Figure 34. PC Card/CompactFlash controller waveforms for I/O space write access FSMC_NIOWR tv(NCEx-A) th(NCE4_1-AI) FSMC_A[10:0] FSMC_NREG FSMC_NWE FSMC_NOE FSMC_NIORD td(NCE4_1-NIOWR) tw(NIOWR) FSMC_NIOWR ATTxHIZ =1 tv(NIOWR-D) th(NIOWR-D) FSMC_D[15:0] ai14900b Table 39. Switching characteristics for PC Card/CF read and write cycles(1)(2) Symbol Parameter Min Max Unit tv(NCEx-A) tv(NCE4_1-A) FSMC_NCEx low (x = 4_1/4_2) to FSMC_Ay valid (y = 0...10) FSMC_NCE4_1 low (x = 4_1/4_2) to FSMC_Ay valid (y = 0...10) th(NCEx-AI) th(NCE4_1-AI) FSMC_NCEx high (x = 4_1/4_2) to FSMC_Ax invalid (x = 0...10) FSMC_NCE4_1 high (x = 4_1/4_2) to FSMC_Ax invalid (x = 0...10) td(NREG-NCEx) td(NREG-NCE4_1) FSMC_NCEx low to FSMC_NREG valid FSMC_NCE4_1 low to FSMC_NREG valid th(NCEx-NREG) th(NCE4_1-NREG) FSMC_NCEx high to FSMC_NREG invalid FSMC_NCE4_1 high to FSMC_NREG invalid td(NCE4_1-NOE) FSMC_NCE4_1 low to FSMC_NOE low tw(NOE) FSMC_NOE low width 8tHCLK –1.5 td(NOE-NCE4_1 FSMC_NOE high to FSMC_NCE4_1 high 5tHCLK + 2 ns tsu(D-NOE) FSMC_D[15:0] valid data before FSMC_NOE high 25 ns th(NOE-D) FSMC_D[15:0] valid data after FSMC_NOE high 15 ns tw(NWE) FSMC_NWE low width 8tHCLK – 1 td(NWE-NCE4_1) FSMC_NWE high to FSMC_NCE4_1 high 5tHCLK + 2 td(NCE4_1-NWE) FSMC_NCE4_1 low to FSMC_NWE low 5tHCLK + 1.5 ns tv(NWE-D) FSMC_NWE low to FSMC_D[15:0] valid 0 ns th(NWE-D) FSMC_NWE high to FSMC_D[15:0] invalid Doc ID 14610 Rev 8 0 2.5 ns 5 tHCLK + 3 11tHCLK ns ns ns 5tHCLK + 2 ns 8tHCLK + 1 ns 8tHCLK + 2 ns ns ns 73/112 Electrical characteristics Table 39. STM32F101xC, STM32F101xD, STM32F101xE Switching characteristics for PC Card/CF read and write cycles(1)(2) (continued) Symbol Parameter Min Max Unit td(D-NWE) FSMC_D[15:0] valid before FSMC_NWE high 13tHCLK ns tw(NIOWR) FSMC_NIOWR low width 8tHCLK + 3 ns tv(NIOWR-D) FSMC_NIOWR low to FSMC_D[15:0] valid th(NIOWR-D) FSMC_NIOWR high to FSMC_D[15:0] invalid 5tHCLK +1 11tHCLK td(NCE4_1-NIOWR) FSMC_NCE4_1 low to FSMC_NIOWR valid FSMC_NCEx high to FSMC_NIOWR invalid th(NCEx-NIOWR) th(NCE4_1-NIOWR) FSMC_NCE4_1 high to FSMC_NIOWR invalid ns 5tHCLK+3ns 5tHCLK – 5 td(NIORD-NCEx) FSMC_NCEx low to FSMC_NIORD valid td(NIORD-NCE4_1) FSMC_NCE4_1 low to FSMC_NIORD valid ns ns ns 5tHCLK + 2.5 ns th(NCEx-NIORD) FSMC_NCEx high to FSMC_NIORD invalid th(NCE4_1-NIORD) FSMC_NCE4_1 high to FSMC_NIORD invalid 5tHCLK – 5 ns tsu(D-NIORD) FSMC_D[15:0] valid before FSMC_NIORD high 4.5 ns td(NIORD-D) FSMC_D[15:0] valid after FSMC_NIORD high 9 ns tw(NIORD) FSMC_NIORD low width 8tHCLK + 2 ns 1. CL = 15 pF. 2. Based on characterization, not tested in production. NAND controller waveforms and timings Figure 35 through Figure 38 represent synchronous waveforms and Table 40 provides the corresponding timings. The results shown in this table are obtained with the following FSMC configuration: 74/112 ● COM.FSMC_SetupTime = 0x01; ● COM.FSMC_WaitSetupTime = 0x03; ● COM.FSMC_HoldSetupTime = 0x02; ● COM.FSMC_HiZSetupTime = 0x01; ● ATT.FSMC_SetupTime = 0x01; ● ATT.FSMC_WaitSetupTime = 0x03; ● ATT.FSMC_HoldSetupTime = 0x02; ● ATT.FSMC_HiZSetupTime = 0x01; ● Bank = FSMC_Bank_NAND; ● MemoryDataWidth = FSMC_MemoryDataWidth_16b; ● ECC = FSMC_ECC_Enable; ● ECCPageSize = FSMC_ECCPageSize_512Bytes; ● TCLRSetupTime = 0; ● TARSetupTime = 0; Doc ID 14610 Rev 8 STM32F101xC, STM32F101xD, STM32F101xE Electrical characteristics Figure 35. NAND controller waveforms for read access FSMC_NCEx Low ALE (FSMC_A17) CLE (FSMC_A16) FSMC_NWE td(ALE-NOE) th(NOE-ALE) FSMC_NOE (NRE) tsu(D-NOE) th(NOE-D) FSMC_D[15:0] ai14901b Figure 36. NAND controller waveforms for write access FSMC_NCEx Low ALE (FSMC_A17) CLE (FSMC_A16) td(ALE-NWE) th(NWE-ALE) FSMC_NWE FSMC_NOE (NRE) tv(NWE-D) th(NWE-D) FSMC_D[15:0] ai14902b Figure 37. NAND controller waveforms for common memory read access FSMC_NCEx Low ALE (FSMC_A17) CLE (FSMC_A16) td(ALE-NOE) th(NOE-ALE) FSMC_NWE tw(NOE) FSMC_NOE tsu(D-NOE) th(NOE-D) FSMC_D[15:0] ai14912b Doc ID 14610 Rev 8 75/112 Electrical characteristics STM32F101xC, STM32F101xD, STM32F101xE Figure 38. NAND controller waveforms for common memory write access FSMC_NCEx Low ALE (FSMC_A17) CLE (FSMC_A16) td(ALE-NWE) tw(NWE) th(NWE-ALE) FSMC_NWE FSMC_NOE td(D-NWE) tv(NWE-D) th(NWE-D) FSMC_D[15:0] ai14913b Table 40. Symbol td(D-NWE)(2) Switching characteristics for NAND Flash read and write cycles(1) Parameter Min FSMC_D[15:0] valid before FSMC_NWE high 5tHCLK + 12 FSMC_NOE low width 4tHCLK – 1.5 tsu(D-NOE)(2) FSMC_D[15:0] valid data before FSMC_NOE high 25 th(NOE-D)(2) FSMC_D[15:0] valid data after FSMC_NOE high 7 tw(NOE) (2) tw(NWE) (2) FSMC_NWE low width tv(NWE-D)(2) FSMC_NWE low to FSMC_D[15:0] valid th(NWE-D)(2) FSMC_NWE high to FSMC_D[15:0] invalid td(ALE-NWE)(3) FSMC_ALE valid before FSMC_NWE low th(NWE-ALE)(3) FSMC_NWE high to FSMC_ALE invalid 4tHCLK – 1 FSMC_NWE high to FSMC_ALE invalid 1. CL = 15 pF. 2. Based on characterization, not tested in production. 3. Guaranteed by design, not tested in production. 76/112 Doc ID 14610 Rev 8 4tHCLK + 1.5 ns ns ns 4tHCLK + 2.5 ns 0 ns ns 3tHCLK + 1.5 3tHCLK + 4.5 ns ns 3tHCLK + 2 3tHCLK + 4.5 Unit ns 2tHCLK + 4ns td(ALE-NOE)(3) FSMC_ALE valid before FSMC_NOE low th(NOE-ALE)(3) Max ns ns STM32F101xC, STM32F101xD, STM32F101xE 5.3.11 Electrical characteristics EMC characteristics Susceptibility tests are performed on a sample basis during device characterization. Functional EMS (Electromagnetic susceptibility) While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs: ● Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard. ● FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant with the IEC 61000-4-4 standard. A device reset allows normal operations to be resumed. The test results are given in Table 41. They are based on the EMS levels and classes defined in application note AN1709. Table 41. EMS characteristics Symbol Parameter Conditions Level/Class VFESD VDD = 3.3 V, LQFP144, Voltage limits to be applied on any I/O pin to TA = +25 °C, fHCLK= 36 MHz induce a functional disturbance conforms to IEC 61000-4-2 2B VEFTB Fast transient voltage burst limits to be applied through 100 pF on VDD and VSS pins to induce a functional disturbance VDD = 3.3 V, LQFP144, TA = +25 °C, fHCLK = 36 MHz conforms to IEC 61000-4-4 4A Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and pre qualification tests in relation with the EMC level requested for his application. Software recommendations The software flowchart must include the management of runaway conditions such as: ● Corrupted program counter ● Unexpected reset ● Critical Data corruption (control registers...) Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015). Doc ID 14610 Rev 8 77/112 Electrical characteristics STM32F101xC, STM32F101xD, STM32F101xE Electromagnetic Interference (EMI) The electromagnetic field emitted by the device is monitored while a simple application is executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with IEC 61967-2 standard which specifies the test board and the pin loading. Table 42. EMI characteristics Symbol Parameter SEMI 5.3.12 Peak level Conditions Max vs. [fHSE/fHCLK] Monitored frequency band Unit 8/36 MHz 0.1 MHz to 30 MHz VDD = 3.3 V, TA = 25 °C, 30 MHz to 130 MHz LQFP144 package compliant with 130 MHz to 1 GHz IEC 61967-2 SAE EMI Level 8 27 dBµV 26 4 - Absolute maximum ratings (electrical sensitivity) Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity. Electrostatic discharge (ESD) Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test conforms to the JESD22-A114/C101 standard. Table 43. ESD absolute maximum ratings Symbol Ratings Conditions Class Maximum value(1) Unit VESD(HBM) Electrostatic discharge TA = +25 °C, conforming 2 voltage (human body model) to JESD22-A114 2000 VESD(CDM) Electrostatic discharge TA = +25 °C, conforming II voltage (charge device model) to JESD22-C101 500 V 1. Based on characterization results, not tested in production. Static latch-up Two complementary static tests are required on six parts to assess the latch-up performance: ● A supply overvoltage is applied to each power supply pin ● A current injection is applied to each input, output and configurable I/O pin These tests are compliant with EIA/JESD 78 IC latch-up standard. Table 44. Symbol LU 78/112 Electrical sensitivities Parameter Static latch-up class Conditions TA = +85 °C conforming to JESD78A Doc ID 14610 Rev 8 Class II level A STM32F101xC, STM32F101xD, STM32F101xE 5.3.13 Electrical characteristics I/O current injection characteristics As a general rule, current injection to the I/O pins, due to external voltage below VSS or above VDD (for standard, 3 V-capable I/O pins) should be avoided during normal product operation. However, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization. Functional susceptibilty to I/O current injection While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures. The failure is indicated by an out of range parameter: ADC error above a certain limit (>5 LSB TUE), out of spec current injection on adjacent pins or other functional failure (for example reset, oscillator frequency deviation). The test results are given in Table 45 Table 45. I/O current injection susceptibility Functional susceptibility Symbol IINJ Description Negative injection Positive injection Injected current on OSC_IN32, OSC_OUT32, PA4, PA5, PC13 -0 +0 Injected current on all FT pins -5 +0 Injected current on any other pin -5 +5 Doc ID 14610 Rev 8 Unit mA 79/112 Electrical characteristics 5.3.14 STM32F101xC, STM32F101xD, STM32F101xE I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in Table 46 are derived from tests performed under the conditions summarized in Table 10. All I/Os are CMOS and TTL compliant. Table 46. Symbol VIL VIH Vhys Ilkg I/O static characteristics Parameter Conditions Min Typ Max Unit Standard IO input low level voltage –0.3 0.28*(VDD-2 V)+0.8 V V IO FT(1) input low level voltage –0.3 0.32*(VDD-2V)+0.75 V V Standard IO input high level voltage 0.41*(VDD-2 V)+1.3 V VDD+0.3 V IO FT(1) input high level voltage 5.5 VDD > 2 V 0.42*(VDD-2 V)+1 V VDD ≤ 2 V V 5.2 Standard IO Schmitt trigger voltage hysteresis(2) 200 mV IO FT Schmitt trigger voltage hysteresis(2) 5% VDD(3) mV Input leakage current (4) VSS ≤ VIN ≤ VDD Standard I/Os ±1 µA VIN = 5 V I/O FT 3 RPU Weak pull-up equivalent resistor(5) VIN = VSS 30 40 50 kΩ RPD Weak pull-down equivalent resistor(5) VIN = VDD 30 40 50 kΩ CIO I/O pin capacitance 5 pF 1. FT = Five-volt tolerant. In order to sustain a voltage higher than VDD+0.3 the internal pull-up/pull-down resistors must be disabled. 2. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization, not tested in production. 3. With a minimum of 100 mV. 4. Leakage could be higher than max. if negative current is injected on adjacent pins. 5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This PMOS/NMOS contribution to the series resistance is minimum (~10% order). All I/Os are CMOS and TTL compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters. The coverage of these requirements is shown in Figure 39 and Figure 40 for standard I/Os, and in Figure 41 and Figure 42 for 5 V tolerant I/Os. 80/112 Doc ID 14610 Rev 8 STM32F101xC, STM32F101xD, STM32F101xE Electrical characteristics Figure 39. Standard I/O input characteristics - CMOS port 6)(6),6 6 6 )( $$ 6 $$ MENT6 )( QUIRE NDARDRE TA #-/3S 7)(MIN 7),MAX 6 6), $$ 6 $$ IREMENT6 ), RDREQU #-/3STANDA )NPUTRANGE NOTGUARANTEED 6$$6 AIB Figure 40. Standard I/O input characteristics - TTL port 6)(6),6 7)(MIN 44,REQUIREMENTS 6)( 6 6 6 )( $$ )NPUTRANGE NOTGUARANTEED 7),MAX 6 ),6 $$ 44,REQUIREMENTS 6),6 6$$6 AI Doc ID 14610 Rev 8 81/112 Electrical characteristics STM32F101xC, STM32F101xD, STM32F101xE Figure 41. 5 V tolerant I/O input characteristics - CMOS port 6)(6),6 6 $$ TS6 )( UIREMEN REQ TANDARD #-/3S )NPUTRANGE NOTGUARANTEED 6 ),6 $$ T6 ),6 $$ REQUIRMEN /3STANDARD #- 6 )(6 $$ 6$$6 6$$ AIB Figure 42. 5 V tolerant I/O input characteristics - TTL port 6)(6),6 44,REQUIREMENT6 )(6 6 6 )( $$ 7)(MIN 7),MAX )NPUTRANGE NOTGUARANTEED 6 ), 6 $$ 44,REQUIREMENTS6 ),6 6$$6 AI Output driving current The GPIOs (general purpose input/outputs) can sink or source up to +/-8 mA, and sink or source up to +/- 20 mA (with a relaxed VOL/VOH). In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in Section 5.2: 82/112 ● The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating IVDD (see Table 8). ● The sum of the currents sunk by all the I/Os on VSS plus the maximum Run consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating IVSS (see Table 8). Doc ID 14610 Rev 8 STM32F101xC, STM32F101xD, STM32F101xE Electrical characteristics Output voltage levels Unless otherwise specified, the parameters given in Table 47 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 10. All I/Os are CMOS and TTL compliant. Table 47. Output voltage characteristics Symbol Parameter VOL(1) VOH (3) VOL(1) VOH (3) VOL(1) VOH (3) VOL(1) VOH (3) Output Low level voltage for an I/O pin when 8 pins are sunk at the same time Output High level voltage for an I/O pin when 8 pins are sourced at the same time Output low level voltage for an I/O pin when 8 pins are sunk at the same time Output high level voltage for an I/O pin when 8 pins are sourced at the same time Output low level voltage for an I/O pin when 8 pins are sunk at the same time Output high level voltage for an I/O pin when 8 pins are sourced at the same time Output low level voltage for an I/O pin when 8 pins are sunk at the same time Output high level voltage for an I/O pin when 8 pins are sourced at the same time Conditions CMOS port(2), IIO = +8 mA, 2.7 V < VDD < 3.6 V TTL port(2) IIO = +8 mA 2.7 V < VDD < 3.6 V IIO = +20 mA(4) 2.7 V < VDD < 3.6 V IIO = +6 mA(4) 2 V < VDD < 2.7 V Min Max Unit 0.4 V VDD–0.4 0.4 V 2.4 1.3 V VDD–1.3 0.4 V VDD–0.4 1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 8 and the sum of IIO (I/O ports and control pins) must not exceed IVSS. 2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52. 3. The IIO current sourced by the device must always respect the absolute maximum rating specified in Table 8 and the sum of IIO (I/O ports and control pins) must not exceed IVDD. 4. Based on characterization data, not tested in production. Doc ID 14610 Rev 8 83/112 Electrical characteristics STM32F101xC, STM32F101xD, STM32F101xE Input/output AC characteristics The definition and values of input/output AC characteristics are given in Figure 43 and Table 48, respectively. Unless otherwise specified, the parameters given in Table 48 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 10. Table 48. MODEx [1:0] bit value(1) I/O AC characteristics(1) Symbol Parameter fmax(IO)out Maximum frequency(2) 10 tf(IO)out Output high to low level fall time tr(IO)out Output low to high level rise time fmax(IO)out Maximum frequency(2) 01 tf(IO)out Output high to low level fall time tr(IO)out Output low to high level rise time Fmax(IO)out Maximum 11 tf(IO)out tr(IO)out - tEXTIpw Frequency(2) Output high to low level fall time Output low to high level rise time Conditions CL = 50 pF, VDD = 2 V to 3.6 V Max Unit 2 MHz 125(3) CL = 50 pF, VDD = 2 V to 3.6 V ns (3) 125 CL= 50 pF, VDD = 2 V to 3.6 V 10 MHz 25(3) CL= 50 pF, VDD = 2 V to 3.6 V ns 25(3) CL= 30 pF, VDD = 2.7 V to 3.6 V 50 MHz CL = 50 pF, VDD = 2.7 V to 3.6 V 30 MHz CL = 50 pF, VDD = 2 V to 2.7 V 20 MHz CL = 30 pF, VDD = 2.7 V to 3.6 V 5(3) CL = 50 pF, VDD = 2.7 V to 3.6 V 8(3) CL = 50 pF, VDD = 2 V to 2.7 V 12(3) CL = 30 pF, VDD = 2.7 V to 3.6 V 5(3) CL = 50 pF, VDD = 2.7 V to 3.6 V 8(3) CL = 50 pF, VDD = 2 V to 2.7 V 12(3) Pulse width of external signals detected by the EXTI controller 10 ns ns 1. The I/O speed is configured using the MODEx[1:0] bits. Refer to the STM32F10xxx reference manual for a description of GPIO Port configuration register. 2. The maximum frequency is defined in Figure 43. 3. Guaranteed by design, not tested in production. 84/112 Doc ID 14610 Rev 8 STM32F101xC, STM32F101xD, STM32F101xE Electrical characteristics Figure 43. I/O AC characteristics definition 90% 10% 50% 50% 90% 10% EXT ERNAL OUTPUT ON 50pF tr(I O)out tr(I O)out T Maximum frequency is achieved if (tr + tf) ≤ 2/3)T and if the duty cycle is (45-55%) when loaded by 50pF ai14131 5.3.15 NRST pin characteristics The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, RPU (see Table 46). Unless otherwise specified, the parameters given in Table 49 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 10. Table 49. NRST pin characteristics Symbol Parameter Conditions Min Typ Max VIL(NRST)(1) NRST Input low level voltage –0.5 0.8 VIH(NRST)(1) NRST Input high level voltage 2 VDD+0.5 Vhys(NRST) NRST Schmitt trigger voltage hysteresis VF(NRST) V Weak pull-up equivalent resistor(2) RPU (1) Unit 200 VIN = VSS 30 40 NRST Input filtered pulse VNF(NRST)(1) NRST Input not filtered pulse mV 50 kΩ 100 ns 300 ns 1. Guaranteed by design, not tested in production. 2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance must be minimum (~10% order). Figure 44. Recommended NRST pin protection 6$$ %XTERNAL RESETCIRCUIT .234 205 )NTERNAL2ESET &ILTER & 34-&XXX AIC 1. The reset network protects the device against parasitic resets. 2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in Table 49. Otherwise the reset will not be taken into account by the device. Doc ID 14610 Rev 8 85/112 Electrical characteristics 5.3.16 STM32F101xC, STM32F101xD, STM32F101xE TIM timer characteristics The parameters given in Table 50 are guaranteed by design. Refer to Section 5.3.13: I/O current injection characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output). Table 50. Symbol tres(TIM) fEXT ResTIM tCOUNTER TIMx(1) characteristics Parameter Conditions Min Max 1 tTIMxCLK 27.8 ns Timer resolution time fTIMxCLK = 36 MHz Timer external clock frequency on CH1 to CH4 fTIMxCLK = 36 MHz 0 fTIMxCLK/2 MHz 0 18 MHz 16 bit 65536 tTIMxCLK 1820 µs 65536 × 65536 tTIMxCLK 119.2 s Timer resolution 16-bit counter clock period when internal clock is selected tMAX_COUNT Maximum possible count Unit 1 fTIMxCLK = 36 MHz 0.0278 fTIMxCLK = 36 MHz 1. TIMx is used as a general term to refer to the TIM1, TIM2, TIM3 and TIM4 timers. 5.3.17 Communications interfaces I2C interface characteristics Unless otherwise specified, the parameters given in Table 51 are derived from tests performed under ambient temperature, fPCLK1 frequency and VDD supply voltage conditions summarized in Table 10. The STM32F101xC, STM32F101xD and STM32F101xE access line I2C interface meets the requirements of the standard I2C communication protocol with the following restrictions: the I/O pins SDA and SCL are mapped to are not “true” open-drain. When configured as opendrain, the PMOS connected between the I/O pin and VDD is disabled, but is still present. The I2C characteristics are described in Table 51. Refer also to Section 5.3.13: I/O current injection characteristics for more details on the input/output alternate function characteristics (SDA and SCL). 86/112 Doc ID 14610 Rev 8 STM32F101xC, STM32F101xD, STM32F101xE Table 51. Electrical characteristics I2C characteristics Standard mode I2C(1) Fast mode I2C(1)(2) Symbol Parameter Unit Min Max Min Max tw(SCLL) SCL clock low time 4.7 1.3 tw(SCLH) SCL clock high time 4.0 0.6 tsu(SDA) SDA setup time 250 100 (3) 0(4) 900(3) 20+0.1Cb 300 µs th(SDA) SDA data hold time tr(SDA) tr(SCL) SDA and SCL rise time 1000 tf(SDA) tf(SCL) SDA and SCL fall time 300 th(STA) Start condition hold time 4.0 0.6 tsu(STA) Repeated Start condition setup time 4.7 0.6 tsu(STO) Stop condition setup time 4.0 0.6 µs tw(STO:STA) Stop to Start condition time (bus free) 4.7 1.3 µs Cb Capacitive load for each bus line 0 ns 300 µs 400 400 pF 1. Guaranteed by design, not tested in production. 2. fPCLK1 must be higher than 2 MHz to achieve standard mode I2C frequencies. It must be higher than 4 MHz to achieve the fast mode I2C frequencies and it must be a multiple of 10 MHz in order to reach the I2C fast mode maximum clock speed of 400 kHz. 3. The maximum hold time of the Start condition has only to be met if the interface does not stretch the low period of SCL signal. 4. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL. Doc ID 14610 Rev 8 87/112 Electrical characteristics STM32F101xC, STM32F101xD, STM32F101xE Figure 45. I2C bus AC waveforms and measurement circuit(1) 6$$ 6$$ K½ K½ ½ 34-&XXX 3$! )£#BUS ½ 3#, 3 4!242%0%!4%$ 3 4!24 3 4!24 TSU34! 3$! TF3$! TR3$! TH34! 3#, TW3#,( TSU3$! TW3#,, TR3#, TSU34/34! 3 4/0 TH3$! TSU34/ TF3#, AIC 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD. Table 52. SCL frequency (fPCLK1= 36 MHz, VDD = 3.3 V)(1)(2) fSCL I2C_CCR value (kHz) RP = 4.7 kΩ 400 0x801E 300 0x8028 200 0x803C 100 0x00B4 50 0x0168 20 0x0384 1. RP = External pull-up resistance, fSCL = I2C speed, 2. For speeds around 200 kHz, the tolerance on the achieved speed is of ±5%. For other speed ranges, the tolerance on the achieved speed ±2%. These variations depend on the accuracy of the external components used to design the application. 88/112 Doc ID 14610 Rev 8 STM32F101xC, STM32F101xD, STM32F101xE Electrical characteristics SPI interface characteristics Unless otherwise specified, the parameters given in Table 53Table 54 are derived from tests performed under ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 10. Refer to Section 5.3.13: I/O current injection characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO). Table 53. STM32F10xxx SPI characteristics Symbol Parameter fSCK 1/tc(SCK) SPI clock frequency tr(SCK) tf(SCK) tsu(NSS)(1) th(NSS) (1) Slave mode 10 4tPCLK NSS hold time Slave mode 73 Master mode, fPCLK = 36 MHz, presc = 4 50 Master mode - SPI1 3 Master mode - SPI2 5 Slave mode 4 Master mode - SPI1 4 Data input hold time Master mode - SPI2 6 Data output access time 8 Slave mode 5 Slave mode, fPCLK = 36 MHz, presc = 4 0 Slave mode, fPCLK = 20 MHz Data output disable time Slave mode tv(SO) (1) Data output valid time Slave mode (after enable edge) tv(MO)(1) Data output valid time Master mode (after enable edge) tdis(SO)(1)(3) th(SO)(1) th(MO) (1) Data output hold time Unit MHz Slave mode th(SI)(1) ta(SO)(1)(2) 10 NSS setup time Data input setup time Max Master mode Capacitive load: C = 30 pF tw(SCKH) SCK high and low tw(SCKL)(1) time th(MI) (1) Min SPI clock rise and fall time (1) tsu(MI) (1) tsu(SI)(1) Conditions Slave mode (after enable edge) Master mode (after enable edge) 60 ns 55 4tPCLK 10 25 6 25 6 1. Based on characterization, not tested in production. 2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data. 3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z Doc ID 14610 Rev 8 89/112 Electrical characteristics Table 54. Symbol fSCK 1/tc(SCK) tr(SCK) tf(SCK) DuCy(SCK) tsu(NSS)(1) th(NSS) (1) STM32F101xC, STM32F101xD, STM32F101xE SPI characteristics Parameter tsu(MI) (1) tsu(SI)(1) th(MI) SPI clock rise and fall time Max 18 Slave mode 18 Capacitive load: C = 30 pF 8 ns 70 % MHz 30 NSS setup time Slave mode 4tPCLK NSS hold time Slave mode 2tPCLK SCK high and low time Master mode, fPCLK = 36 MHz, presc = 4 50 Master mode 5 Slave mode 5 Master mode 5 Slave mode 4 60 Data input setup time Data input hold time ns ta(SO)(1)(2) Data output access time Slave mode, fPCLK = 20 MHz 0 3tPCLK tdis(SO)(1)(3) 2 10 Data output disable time Slave mode tv(SO) (1)(1) Data output valid time Slave mode (after enable edge) 25 tv(MO) (1)(1) Data output valid time Master mode (after enable edge) 5 th(SO)(1) th(MO)(1) Unit Master mode SPI slave input clock duty Slave mode cycle (1) th(SI)(1) Min SPI clock frequency (1) tw(SCKH) tw(SCKL)(1) Conditions Slave mode (after enable edge) 15 Master mode (after enable edge) 2 Data output hold time 1. Based on characterization, not tested in production. 2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data. 3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z 90/112 Doc ID 14610 Rev 8 STM32F101xC, STM32F101xD, STM32F101xE Electrical characteristics Figure 46. SPI timing diagram - slave mode and CPHA=0 NSS input tc(SCK) th(NSS) SCK Input tSU(NSS) CPHA= 0 CPOL=0 tw(SCKH) tw(SCKL) CPHA= 0 CPOL=1 tv(SO) ta(SO) MISO OUT P UT tr(SCK) tf(SCK) th(SO) MS B O UT BI T6 OUT tdis(SO) LSB OUT tsu(SI) MOSI I NPUT B I T1 IN M SB IN LSB IN th(SI) ai14134c Figure 47. SPI timing diagram - slave mode and CPHA=1(1) NSS input SCK Input tSU(NSS) CPHA=1 CPOL=0 CPHA=1 CPOL=1 tc(SCK) tw(SCKH) tw(SCKL) tv(SO) ta(SO) MISO OUT P UT MS B O UT tsu(SI) MOSI I NPUT th(NSS) th(SO) BI T6 OUT tr(SCK) tf(SCK) tdis(SO) LSB OUT th(SI) B I T1 IN M SB IN LSB IN ai14135 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD. Doc ID 14610 Rev 8 91/112 Electrical characteristics STM32F101xC, STM32F101xD, STM32F101xE Figure 48. SPI timing diagram - master mode(1) High NSS input SCK Input CPHA= 0 CPOL=0 SCK Input tc(SCK) CPHA=1 CPOL=0 CPHA= 0 CPOL=1 CPHA=1 CPOL=1 tsu(MI) MISO INP UT tw(SCKH) tw(SCKL) tr(SCK) tf(SCK) MS BIN BI T6 IN LSB IN th(MI) MOSI OUTUT B I T1 OUT M SB OUT tv(MO) LSB OUT th(MO) ai14136 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD. 5.3.18 12-bit ADC characteristics Unless otherwise specified, the parameters given in Table 55 are derived from tests performed under ambient temperature, fPCLK2 frequency and VDDA supply voltage conditions summarized in Table 10. Note: 92/112 It is recommended to perform a calibration after each power-up. Doc ID 14610 Rev 8 STM32F101xC, STM32F101xD, STM32F101xE Table 55. Symbol Electrical characteristics ADC characteristics Parameter Conditions Min Typ Max Unit VDDA Power supply 2.4 3.6 V VREF+ Positive reference voltage 2.4 VDDA V IVREF Current on the VREF input pin 220(1) µA fADC ADC clock frequency 0.6 14 MHz fS(2) Sampling rate 0.05 1 MHz 823 kHz 17 1/fADC VREF+ V 50 kΩ 1 kΩ 8 pF fTRIG(2) VAIN RAIN(2) External trigger frequency 160(1) fADC = 14 MHz 0 (VSSA or VREFtied to ground) Conversion voltage range(3) External input impedance See Equation 1 and Table 56 for details RADC(2) Sampling switch resistance CADC(2) Internal sample and hold capacitor tCAL(2) Calibration time fADC = 14 MHz tlat(2) Injection trigger conversion latency fADC = 14 MHz tlatr(2) Regular trigger conversion latency fADC = 14 MHz tS(2) Sampling time Power-up time tCONV(2) Total conversion time (including sampling time) µs 83 1/fADC 0.214 (4) 3 fADC = 14 MHz tSTAB(2) 5.9 1/fADC 0.143 µs 2(4) 1/fADC 0.107 17.1 µs 1.5 239.5 1/fADC 1 µs 18 µs 0 fADC = 14 MHz µs 0 1 14 to 252 (tS for sampling +12.5 for 1/fADC successive approximation) 1. Based on characterization, not tested in production. 2. Guaranteed by design, not tested in production. 3. VREF+ can be internally connected to VDDA and VREF- can be internally connected to VSSA, depending on the package. Refer to Section 3: Pinouts and pin descriptions for further details. 4. For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 55. Equation 1: RAIN max formula: TS R AIN < ------------------------------------------------------------- – R ADC N+2 f ADC × C ADC × ln ( 2 ) Doc ID 14610 Rev 8 93/112 Electrical characteristics STM32F101xC, STM32F101xD, STM32F101xE The formula above (Equation 1) is used to determine the maximum external impedance allowed for an error below 1/4 of LSB. Here N = 12 (from 12-bit resolution). Table 56. RAIN max for fADC = 14 MHz(1) Ts (cycles) tS (µs) RAIN max (kΩ) 1.5 0.11 0.4 7.5 0.54 5.9 13.5 0.96 11.4 28.5 2.04 25.2 41.5 2.96 37.2 55.5 3.96 50 71.5 5.11 NA 239.5 17.1 NA 1. Guaranteed by design, not tested in production. Table 57. Symbol ADC accuracy - limited test conditions(1)(2) Parameter ET Total unadjusted error EO Offset error EG Gain error ED Differential linearity error EL Integral linearity error Test conditions Typ Max(3) fPCLK2 = 28 MHz, fADC = 14 MHz, RAIN < 10 kΩ, VDDA = 3 V to 3.6 V, TA = 25 °C Measurements made after ADC calibration VREF+ = VDDA ±1.3 ±2 ±1 ±1.5 ±0.5 ±1.5 ±0.7 ±1 ±0.8 ±1.5 Unit LSB 1. ADC DC accuracy values are measured after internal calibration. 2. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any of the standard (nonrobust) analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject negative current. Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 5.3.13 does not affect the ADC accuracy. 3. Based on characterisation, not tested in production. 94/112 Doc ID 14610 Rev 8 STM32F101xC, STM32F101xD, STM32F101xE ADC accuracy(1) (2)(3) Table 58. Symbol ET Electrical characteristics Parameter Test conditions Total unadjusted error EO Offset error EG Gain error ED Differential linearity error EL Integral linearity error fPCLK2 = 28 MHz, fADC = 14 MHz, RAIN < 10 kΩ, VDDA = 2.4 V to 3.6 V Measurements made after ADC calibration Typ Max(4) ±2 ±5 ±1.5 ±2.5 ±1.5 ±3 ±1 ±2 ±1.5 ±3 Unit LSB 1. ADC DC accuracy values are measured after internal calibration. 2. Better performance could be achieved in restricted VDD, frequency, VREF and temperature ranges. 3. ADC accuracy vs. negative injection current: Injecting negative current on any of the standard (non-robust) analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject negative current. Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 5.3.13 does not affect the ADC accuracy. 4. Based on characterisation, not tested in production. Figure 49. ADC accuracy characteristics V V [1LSBIDEAL = REF+ (or DDA depending on package)] 4096 4096 EG 4095 4094 (1) Example of an actual transfer curve (2) The ideal transfer curve (3) End point correlation line 4093 (2) ET (3) 7 (1) 6 5 4 EO EL 3 ED 2 ET=Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves. EO=Offset Error: deviation between the first actual transition and the first ideal one. EG=Gain Error: deviation between the last ideal transition and the last actual one. ED=Differential Linearity Error: maximum deviation between actual steps and the ideal one. EL=Integral Linearity Error: maximum deviation between any actual transition and the end point correlation line. 1 LSBIDEAL 1 0 1 VSSA 2 3 4 5 6 7 4093 4094 4095 4096 VDDA Doc ID 14610 Rev 8 ai14395b 95/112 Electrical characteristics STM32F101xC, STM32F101xD, STM32F101xE Figure 50. Typical connection diagram using the ADC STM32F10xxx VDD RAIN(1) Sample and hold ADC converter VT 0.6 V RADC(1) AINx VT 0.6 V VAIN Cparasitic IL±1 µA 12-bit converter CADC(1) ai14139d 1. Refer to Table 55 for the values of RAIN, RADC and CADC. 2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy this, fADC should be reduced. General PCB design guidelines Power supply decoupling should be performed as shown in Figure 51 or Figure 52, depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be ceramic (good quality). They should be placed them as close as possible to the chip. Figure 51. Power supply and reference decoupling (VREF+ not connected to VDDA) STM32F10xxx V REF+ 1 µF // 10 nF V DDA 1 µF // 10 nF V SSA/V REF- ai14380b 1. VREF+ and VREF- inputs are available only on 100-pin packages. 96/112 Doc ID 14610 Rev 8 STM32F101xC, STM32F101xD, STM32F101xE Electrical characteristics Figure 52. Power supply and reference decoupling (VREF+ connected to VDDA) STM32F10xxx VREF+/VDDA 1 µF // 10 nF VREF–/VSSA ai14381b 1. VREF+ and VREF- inputs are available only on 100-pin packages. 5.3.19 DAC electrical specifications Table 59. DAC characteristics Symbol Parameter Min Max(1) Typ Unit Comments VDDA Analog supply voltage 2.4 3.6 V VREF+ Reference supply voltage 2.4 3.6 V VSSA Ground 0 0 V RLOAD(2) Resistive load with buffer ON 5 RO(2) Impedance output with buffer OFF 15 kΩ When the buffer is OFF, the minimum resistive load between DAC_OUT and VSS to have a 1% accuracy is 1.5 MΩ CLOAD(2) Capacitive load 50 pF Maximum capacitive load at DAC_OUT pin (when the buffer is ON). DAC_OUT min(2) Lower DAC_OUT voltage with buffer ON DAC_OUT max(2) Higher DAC_OUT voltage with buffer ON DAC_OUT min(2) Lower DAC_OUT voltage with buffer OFF DAC_OUT max(2) Higher DAC_OUT voltage with buffer OFF VREF+ must always be below VDDA kΩ 0.2 V VDDA – 0.2 0.5 V It gives the maximum output excursion of the DAC. It corresponds to 12-bit input code (0x0E0) to (0xF1C) at VREF+ = 3.6 V and (0x155) and (0xEAB) at VREF+ = 2.4 V. mV It gives the maximum output excursion of the DAC. VREF+ – 1LSB V Doc ID 14610 Rev 8 97/112 Electrical characteristics Table 59. DAC characteristics (continued) Symbol IDDVREF+ IDDA DNL(1) INL(1) Offset(1) STM32F101xC, STM32F101xD, STM32F101xE Parameter Min DAC DC current consumption in quiescent mode (Standby mode) DAC DC current consumption in quiescent mode (Standby mode) Differential non linearity Difference between two consecutive code-1LSB) Integral non linearity (difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 1023) Offset error (difference between measured value at Code (0x800) and the ideal value = VREF+/2) Gain error(1) Gain error tSETTLING(1) Settling time (full scale: for a 10-bit input code transition between the lowest and the highest input codes when DAC_OUT reaches final value ±1LSB Max(1) Typ 3 Max frequency for a correct DAC_OUT change when small Update rate(1) variation in the input code (from code i to i+1LSB) Unit Comments 220 µA With no load, worst code (0xF1C) at VREF+ = 3.6 V in terms of DC consumption on the inputs. 380 µA With no load, middle code (0x800) on the inputs. 480 µA With no load, worst code (0xF1C) at VREF+ = 3.6 V in terms of DC consumption on the inputs. ±0.5 LSB Given for the DAC in 10-bit configuration. ±2 LSB Given for the DAC in 12-bit configuration. ±1 LSB Given for the DAC in 10-bit configuration. ±4 LSB Given for the DAC in 12-bit configuration. ±10 mV Given for the DAC in 12-bit configuration. ±3 LSB Given for the DAC in 10-bit at VREF+ = 3.6 V. ±12 LSB Given for the DAC in 12-bit at VREF+ = 3.6 V. ±0.5 % Given for the DAC in 12bit configuration. 4 µs CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ 1 MS/s CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ tWAKEUP(1) Wakeup time from off state (Setting the ENx bit in the DAC Control register) 6.5 10 µs CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ input code between lowest and highest possible ones. PSRR+ (2) Power supply rejection ratio (to VDDA) (static DC measurement –67 –40 dB No RLOAD, CLOAD = 50 pF 1. Based on characterization, not tested in production. 2. Guaranteed by design, not tested in production. 98/112 Doc ID 14610 Rev 8 STM32F101xC, STM32F101xD, STM32F101xE Electrical characteristics Figure 53. 12-bit buffered /non-buffered DAC Buffered/Non-buffered DAC Buffer(1) R LOAD 12-bit digital to analog converter DACx_OUT C LOAD ai17157 1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the DAC_CR register. 5.3.20 Temperature sensor characteristics Table 60. TS characteristics Symbol TL(1) Parameter Min VSENSE linearity with temperature Typ Max Unit ±1 ±2 °C Avg_Slope(1) Average slope 4.0 4.3 4.6 mV/°C V25(1) Voltage at 25°C 1.34 1.43 1.52 V tSTART(2) Startup time 10 µs TS_temp(3)(2) ADC sampling time when reading the temperature 17.1 µs 4 1. 2. Guaranteed by design, not tested in production. 3. Shortest sampling time can be determined in the application by multiple iterations. Doc ID 14610 Rev 8 99/112 Package characteristics STM32F101xC, STM32F101xD, STM32F101xE 6 Package characteristics 6.1 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 100/112 Doc ID 14610 Rev 8 STM32F101xC, STM32F101xD, STM32F101xE Package characteristics Figure 54. LQFP144, 20 x 20 mm, 144-pin thin quad flat package outline(1) Figure 55. Recommended footprint(1)(2) Seating plane C A A2 A1 c b ccc 0.25 mm gage plane C D k 108 109 1.35 73 72 0.35 D1 A1 D3 0.5 L 73 108 L1 17.85 19.9 72 109 144 E1 22.6 37 E 1 E3 36 19.9 22.6 ai149 144 Pin 1 identification 37 36 1 e ME_1A 1. Drawing is not to scale. 2. Dimensions are in millimeters. Table 61. LQFP144, 20 x 20 mm, 144-pin thin quad flat package mechanical data inches(1) millimeters Symbol Min Typ A Max Min Typ 1.60 A1 0.050 A2 1.350 b 0.170 c 0.090 D 21.800 D1 Max 0.0630 0.15 0.0020 1.400 1.45 0.0531 0.0551 0.0571 0.220 0.27 0.0067 0.0087 0.0106 0.20 0.0035 22.000 22.20 0.8583 0.8661 0.874 19.800 20.000 20.20 0.7795 0.7874 0.7953 E 21.800 22.000 22.20 0.8583 0.8661 0.874 E1 19.800 20.000 20.20 0.7795 0.7874 0.7953 D3 17.500 0.0059 0.0079 0.689 E3 17.500 0.689 e 0.500 0.0197 L 0.450 L1 k ccc 0.600 0.75 0.0177 1.000 0° 3.5° 0.0236 0.0295 0.0394 7° 0.080 0° 3.5° 7° 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Doc ID 14610 Rev 8 101/112 Package characteristics STM32F101xC, STM32F101xD, STM32F101xE Figure 56. LQFP100 – 14 x 14 mm, 100-pin low-profile Figure 57. Recommended footprint(1)(2) quad flat package outline(1) 0.25 mm 0.10 inch GAGE PLANE k 75 51 D L D1 76 L1 D3 51 75 50 0.5 C 76 0.3 50 16.7 14.3 b E3 E1 E 100 26 1.2 1 100 26 Pin 1 1 identification 25 12.3 25 C ccc 16.7 ai14906b e A1 A2 A SEATING PLANE C 1L_ME 1. Drawing is not to scale. 2. Dimensions are in millimeters. Table 62. LQPF100 – 14 x 14 mm, 100-pin low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ A Max Min Typ 1.600 A1 0.050 A2 1.350 b 0.170 c 0.090 D 15.800 D1 13.800 D3 Max 0.0630 0.150 0.0020 1.400 1.450 0.0531 0.0551 0.0571 0.220 0.270 0.0067 0.0087 0.0106 0.200 0.0035 16.000 16.200 0.622 0.6299 0.6378 14.000 14.200 0.5433 0.5512 0.5591 12.000 0.0059 0.0079 0.4724 E 15.800 16.000 16.200 0.622 0.6299 0.6378 E1 13.800 14.000 14.200 0.5433 0.5512 0.5591 E3 12.000 e L 0.500 0.450 L1 k ccc 0.4724 0.600 0.0197 0.750 1.000 0° 3.5° 0.0236 0.0295 0.0394 7° 0.08 0° 3.5° 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. 102/112 0.0177 Doc ID 14610 Rev 8 7° STM32F101xC, STM32F101xD, STM32F101xE Package characteristics Figure 58. LQFP64 – 10 x 10 mm, 64 pin low-profile quad Figure 59. Recommended flat package outline(1) footprint(1)(2) D 48 ccc C D1 33 48 33 A A2 D3 0.3 49 32 0.5 32 49 12.7 b 10.3 L1 10.3 E3 E1 E 64 17 1.2 L A1 K 1 16 7.8 64 17 Pin 1 identification 12.7 16 1 c ai14909 5W_ME 1. Drawing is not to scale. 2. Dimensions are in millimeters. Table 63. LQFP64 – 10 x 10 mm, 64 pin low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ A Max Min Typ 1.600 A1 0.050 A2 1.350 b 0.170 c 0.090 D 11.800 D1 9.800 D. Max 0.0630 0.150 0.0020 0.0059 1.400 1.450 0.0531 0.0551 0.0571 0.220 0.270 0.0067 0.0087 0.0106 0.200 0.0035 12.000 12.200 0.4646 0.4724 0.4803 10.000 10.200 0.3858 0.3937 0.4016 0.0079 7.500 E 11.800 12.000 12.200 0.4646 0.4724 0.4803 E1 9.800 10.00 10.200 0.3858 0.3937 0.4016 e 0.500 0.0197 k 0° 3.5° 7° 0° 3.5° 7° L 0.450 0.600 0.75 0.0177 0.0236 0.0295 L1 1.000 0.0394 ccc 0.080 0.0031 Number of pins N 64 1. Values in inches are converted from mm and rounded to 4 decimal digits. Doc ID 14610 Rev 8 103/112 Package characteristics 6.2 STM32F101xC, STM32F101xD, STM32F101xE Thermal characteristics The maximum chip junction temperature (TJmax) must never exceed the values given in Table 10: General operating conditions on page 38. The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated using the following equation: TJ max = TA max + (PD max × ΘJA) Where: ● TA max is the maximum ambient temperature in °C, ● ΘJA is the package junction-to-ambient thermal resistance, in °C/W, ● PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax), ● PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip internal power. PI/O max represents the maximum power dissipation on output pins where: PI/O max = Σ (VOL × IOL) + Σ((VDD – VOH) × IOH), taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the application. Table 64. Package thermal characteristics Symbol ΘJA 6.2.1 Parameter Value Thermal resistance junction-ambient LQFP144 - 20 x 20 mm / 0.5 mm pitch 30 Thermal resistance junction-ambient LQFP100 - 14 x 14 mm / 0.5 mm pitch 46 Thermal resistance junction-ambient LQFP64 - 10 x 10 mm / 0.5 mm pitch 45 Unit °C/W Reference document JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air). Available from www.jedec.org. 104/112 Doc ID 14610 Rev 8 STM32F101xC, STM32F101xD, STM32F101xE Evaluating the maximum junction temperature for an application When ordering the microcontroller, the temperature range is specified in the ordering information scheme shown in Table 65: Ordering information scheme. Each temperature range suffix corresponds to a specific guaranteed ambient temperature at maximum dissipation and, to a specific maximum junction temperature. Here, only temperature range 6 is available (–40 to 85 °C). The following example shows how to calculate the temperature range needed for a given application, making it possible to check whether the required temperature range is compatible with the STM32F10xxx junction temperature range. Example: High-performance application Assuming the following application conditions: Maximum ambient temperature TAmax = 82 °C (measured according to JESD51-2), IDDmax = 50 mA, VDD = 3.5 V, maximum 20 I/Os used at the same time in output at low level with IOL = 8 mA, VOL= 0.4 V and maximum 8 I/Os used at the same time in output mode at low level with IOL = 20 mA, VOL= 1.3 V PINTmax = 50 mA × 3.5 V= 175 mW PIOmax = 20 × 8 mA × 0.4 V + 8 × 20 mA × 1.3 V = 272 mW This gives: PINTmax = 175 mW and PIOmax = 272 mW PDmax = 175 + 272 = 447 mW Thus: PDmax = 447 mW Using the values obtained in Table 65 TJmax is calculated as follows: – For LQFP64, 45 °C/W TJmax = 82 °C + (45 °C/W × 447 mW) = 82 °C + 20.1 °C = 102.1 °C This is within the junction temperature range of the STM32F10xxx (–40 < TJ < 105 °C). Figure 60. LQFP64 PD max vs. TA 700 600 PD (mW) 6.2.2 Package characteristics 500 400 Suffix 6 300 200 100 0 65 75 85 95 105 115 TA (°C) Doc ID 14610 Rev 8 105/112 Part numbering 7 STM32F101xC, STM32F101xD, STM32F101xE Part numbering Table 65. Ordering information scheme Example: STM32 F 101 R C T 6 xxx Device family STM32 = ARM-based 32-bit microcontroller Product type F = general-purpose Device subfamily 101 = access line Pin count R = 64 pins V = 100 pins Z = 144 pins Flash memory size C = 256 Kbytes of Flash memory D = 384 Kbytes of Flash memory E = 512 Kbytes of Flash memory Package T = LQFP Temperature range 6 = Industrial temperature range, –40 to 85 °C. Options xxx = programmed parts TR = tape and real For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST sales office. 106/112 Doc ID 14610 Rev 8 STM32F101xC, STM32F101xD, STM32F101xE 8 Revision history Revision history Table 66. Document revision history Date Revision 07-Apr-2008 1 Initial release. 2 Document status promoted from Target Specification to Preliminary Data. Section 1: Introduction and Section 2.2: Full compatibility throughout the family modified. Small text changes. Note 1 added in Table 2: STM32F101xC, STM32F101xD and STM32F101xE features and peripheral counts on page 11. LQPF100/BGA100 column added to Table 6: FSMC pin definition on page 31. Values added to Maximum current consumption on page 40 (see Table 14, Table 15, Table 16 and Table 17). Values added to Typical current consumption on page 46 (see Table 18, Table 19 and Table 20 and see Figure 11, Figure 12, Figure 14, Figure 15 and Figure 16). Table 19: Typical current consumption in Standby mode removed. Figure 55: Recommended footprint(1) on page 101 corrected. Equation 1 corrected. Section 6.2.2: Evaluating the maximum junction temperature for an application on page 105 added. 3 Document status promoted from Preliminary Data to full datasheet. FSMC (flexible static memory controller) on page 15 modified. Power supply supervisor on page 17 modified and VDDA added to Table 10: General operating conditions on page 38. Table notes revised in Section 5: Electrical characteristics. Capacitance modified in Figure 9: Power supply scheme on page 35. Table 52: SCL frequency (fPCLK1= 36 MHz, VDD = 3.3 V) updated. Table 54: SPI characteristics modified, th(NSS) modified in Figure 46: SPI timing diagram - slave mode and CPHA=0 on page 91. Minimum SDA and SCL fall time value for Fast mode removed from Table 51: I2C characteristics on page 87, note 1 modified. IDD_VBAT values added to Table 17: Typical and maximum current consumptions in Stop and Standby modes on page 43. Table 30: Flash memory endurance and data retention on page 57 updated. fHCLK corrected in Table 41: EMS characteristics. tsu(NSS) modified in Table 54: SPI characteristics. EO corrected in Table 58: ADC accuracy on page 95. fPCLK2 corrected in Table 57: ADC accuracy - limited test conditions and Table 58: ADC accuracy. Figure 50: Typical connection diagram using the ADC on page 96 and note below corrected. Typical TS_temp value removed from Table 60: TS characteristics on page 99. Section 6.1: Package mechanical data on page 100 updated. Small text changes. 22-May-2008 21-Jul-2008 Changes Doc ID 14610 Rev 8 107/112 Revision history STM32F101xC, STM32F101xD, STM32F101xE Table 66. Document revision history (continued) Date 12-Dec-2008 108/112 Revision Changes 4 General-purpose timers (TIMx) on page 19 updated. Table 3: STM32F101xx family updated to show the low-density family. Table 4: Timer feature comparison added Figure 1: STM32F101xC, STM32F101xD and STM32F101xE access line block diagram updated. Note 9 added, main function after reset and Note 5 updated in Table 5: High-density STM32F101xx pin definitions. Note 2 modified below Table 7: Voltage characteristics on page 36, |ΔVDDx| min and |ΔVDDx| min removed. Measurement conditions specified in Section 5.3.5: Supply current characteristics on page 40. General input/output characteristics on page 80 modified. Max values at TA = 85 °C updated in Table 17: Typical and maximum current consumptions in Stop and Standby modes on page 43. Section 5.3.10: FSMC characteristics on page 57 revised. Values added to Table 42: EMI characteristics on page 78. IVREF added to Table 55: ADC characteristics on page 93. Table 64: Package thermal characteristics on page 104 updated. Small text changes. Doc ID 14610 Rev 8 STM32F101xC, STM32F101xD, STM32F101xE Table 66. Revision history Document revision history (continued) Date 30-Mar-2009 Revision Changes 5 I/O information clarified on cover page. Number of ADC peripherals corrected in Table 2: STM32F101xC, STM32F101xD and STM32F101xE features and peripheral counts. In Table 5: High-density STM32F101xx pin definitions: – I/O level of pins PF11, PF12, PF13, PF14, PF15, G0, G1 and G15 updated – PB4, PB13, PB14, PB15, PB3/TRACESWO moved from Default column to Remap column. PG14 pin description modified in Table 6: FSMC pin definition. Figure 6: Memory map on page 33 modified. Note modified in Table 14: Maximum current consumption in Run mode, code with data processing running from Flash and Table 16: Maximum current consumption in Sleep mode, code running from Flash or RAM. Figure 14, Figure 15 and Figure 16 show typical curves (titles changed). Table 21: High-speed external user clock characteristics and Table 22: Low-speed user external clock characteristics modified. ACCHSI max values modified in Table 25: HSI oscillator characteristics FSMC configuration modified for Asynchronous waveforms and timings. Notes modified below Figure 21: Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms and Figure 22: Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms. tw(NADV) values modified in Table 31: Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings and Table 34: Asynchronous multiplexed NOR/PSRAM write timings. th(Data_NWE) modified in Table 32: Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings. In Table 36: Synchronous multiplexed PSRAM write timings and Table 38: Synchronous non-multiplexed PSRAM write timings: – tv(Data-CLK) renamed as td(CLKL-Data) – td(CLKL-Data) min value removed and max value added – th(CLKL-DV) / th(CLKL-ADV) removed Figure 25: Synchronous multiplexed NOR/PSRAM read timings, Figure 26: Synchronous multiplexed PSRAM write timings and Figure 28: Synchronous non-multiplexed PSRAM write timings modified. Small text changes. Doc ID 14610 Rev 8 109/112 Revision history STM32F101xC, STM32F101xD, STM32F101xE Table 66. Document revision history (continued) Date 21-Jul-2009 110/112 Revision Changes 6 Figure 1: STM32F101xC, STM32F101xD and STM32F101xE access line block diagram modified. Note 5 updated and Note 4 added in Table 5: High-density STM32F101xx pin definitions. VRERINT and TCoeff added to Table 13: Embedded internal reference voltage. fHSE_ext min modified in Table 21: High-speed external user clock characteristics. Table 23: HSE 4-16 MHz oscillator characteristics modified. Note 1 modified below Figure 19: Typical application with an 8 MHz crystal. Figure 44: Recommended NRST pin protection modified. CL1 and CL2 replaced by C in Table 23: HSE 4-16 MHz oscillator characteristics and Table 24: LSE oscillator characteristics (fLSE = 32.768 kHz), notes modified and moved below the tables. Table 25: HSI oscillator characteristics modified. Conditions removed from Table 27: Low-power mode wakeup timings. Jitter added to Table 28: PLL characteristics. In Table 31: Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings: th(BL_NOE) and th(A_NOE) modified. In Table 32: Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings: th(A_NWE) and th(Data_NWE) modified. In Table 33: Asynchronous multiplexed NOR/PSRAM read timings: th(AD_NADV) and th(A_NOE) modified. In Table 34: Asynchronous multiplexed NOR/PSRAM write timings: th(A_NWE) modified. In Table 35: Synchronous multiplexed NOR/PSRAM read timings: th(CLKH-NWAITV) modified. In Table 40: Switching characteristics for NAND Flash read and write cycles: th(NOE-D) modified. Table 54: SPI characteristics modified. CADC and RAIN parameters modified in Table 55: ADC characteristics. RAIN max values modified in Table 56: RAIN max for fADC = 14 MHz. Table 59: DAC characteristics modified. Figure 53: 12-bit buffered /nonbuffered DAC added. Doc ID 14610 Rev 8 STM32F101xC, STM32F101xD, STM32F101xE Table 66. Revision history Document revision history (continued) Date 24-Sep-2009 19-Apr-2011 Revision Changes 7 Number of DACs corrected in Table 3: STM32F101xx family. IDD_VBAT updated in Table 17: Typical and maximum current consumptions in Stop and Standby modes. Figure 13: Typical current consumption on VBAT with RTC on vs. temperature at different VBAT values added. IEC 1000 standard updated to IEC 61000 and SAE J1752/3 updated to IEC 61967-2 in Section 5.3.11: EMC characteristics on page 77. Table 59: DAC characteristics modified. Small text changes. 8 Updated footnotes below Table 7: Voltage characteristics on page 36 and Table 8: Current characteristics on page 37 Updated tw min in Table 21: High-speed external user clock characteristics on page 50 Updated startup time in Table 24: LSE oscillator characteristics (fLSE = 32.768 kHz) on page 53 Updated Table 31: Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings on page 58 Updated FSMC sync data latency in Figure 25 thru Figure 28 Updated Figure 38: NAND controller waveforms for common memory write access and Table 40: Switching characteristics for NAND Flash read and write cycles on page 76 Updated Figure 44: Recommended NRST pin protection Added Section 5.3.13: I/O current injection characteristics Updated Section 5.3.13: I/O current injection characteristics Updated note 2 in Table 51: I2C characteristics on page 87 Updated Figure 45: I2C bus AC waveforms and measurement circuit(1) Doc ID 14610 Rev 8 111/112 STM32F101xC, STM32F101xD, STM32F101xE Please Read Carefully: Information in this document is provided solely in connection with ST products. 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The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. © 2011 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 112/112 Doc ID 14610 Rev 8