FREESCALE MC68HC908QY4CDTE

深圳市南天星电子科技有限公司
专业代理飞思卡尔
(Freescale)
飞思卡尔主要产品
8 位微控制器
16 位微控制器
数字信号处理器与控制器
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基于 ARM®技术的 Kinetis MCU
32/64 位微控制器与处理器
模拟与电源管理器件
射频器件（LDMOS，收发器）
传感器（压力，加速度，磁场，
触摸，电池）
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深圳市南天星电子科技有限公司
电话：0755－83040796
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MC68HC908QY4
MC68HC908QT4
MC68HC908QY2
MC68HC908QT2
MC68HC908QY1
MC68HC908QT1
Data Sheet
M68HC08
Microcontrollers
MC68HC908QY4/D
Rev. 4
11/2004
freescale.com
深圳市南天星电子科技有限公司
专业代理飞思卡尔
(Freescale)
飞思卡尔主要产品
8 位微控制器
16 位微控制器
数字信号处理器与控制器
i.MX 应用处理器
基于 ARM®技术的 Kinetis MCU
32/64 位微控制器与处理器
模拟与电源管理器件
射频器件（LDMOS，收发器）
传感器（压力，加速度，磁场，
触摸，电池）
飞思卡尔产品主要应用
汽车电子
数据连接
消费电子
工业控制
医疗保健
电机控制
网络
智能能源
深圳市南天星电子科技有限公司
电话：0755－83040796
传真：0755－83040790
邮箱：[email protected]
网址：www.soustar.com.cn
地址：深圳市福田区福明路雷圳大厦 2306 室
MC68HC908QY4
MC68HC908QT4
MC68HC908QY2
MC68HC908QT2
MC68HC908QY1
MC68HC908QT1
Data Sheet
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This product incorporates SuperFlash® technology licensed from SST.
© Freescale Semiconductor, Inc., 2004. All rights reserved.
MC68HC908QY/QT Family Data Sheet, Rev. 4
Freescale Semiconductor
3
Revision History
The following revision history table summarizes changes contained in this document. For your
convenience, the page number designators have been linked to the appropriate location.
Revision History (Sheet 1 of 3)
Date
Revision
Level
September,
2002
N/A
December,
2002
January,
2003
0.1
0.2
Page
Number(s)
Description
Initial release
N/A
1.2 Features — Added 8-pin dual flat no lead (DFN) packages to features list.
19
Figure 1-2. MCU Pin Assignments — Figure updated to include DFN packages.
21
Figure 2-1. Memory Map — Clarified illegal address and unimplemented
memory.
27
Figure 2-2. Control, Status, and Data Registers — Corrected bit definitions for
Port A Data Register (PTA) and Data Direction Register A (DDRA).
27
Table 13-3. Interrupt Sources — Corrected vector addresses for keyboard
interrupt and ADC conversion complete interrupt.
118
Chapter 13 System Integration Module (SIM) — Removed reference to break
status register as it is duplicated in break module.
113
11.3.1 Internal Oscillator and 11.3.1.1 Internal Oscillator Trimming — Clarified
oscillator trim option ordering information and what to expect with untrimmed
device.
92
Figure 11-5. Oscillator Trim Register (OSCTRIM) — Bit 1 designation corrected.
98
Figure 15-13. Monitor Mode Circuit (Internal Clock, No High Voltage) —
Diagram updated for clarity.
150
Figure 12-1. I/O Port Register Summary — Corrected bit definitions for PTA7,
DDRA7, and DDRA6.
99
Figure 12-2. Port A Data Register (PTA) — Corrected bit definition for PTA7.
100
Figure 12-3. Data Direction Register A (DDRA) — Corrected bit definitions for
DDRA7 and DDRA6.
101
Figure 12-6. Port B Data Register (PTB) — Corrected bit definition for PTB1
103
Chapter 9 Keyboard Interrupt Module (KBI) — Section reworked after deletion
of auto wakeup for clarity.
83
Chapter 4 Auto Wakeup Module (AWU) — New section added for clarity.
49
Figure 10-1. LVI Module Block Diagram — Corrected LVI stop representation.
87
Chapter 16 Electrical Specifications — Extensive changes made to electrical
specifications.
169
17.5 8-Pin Dual Flat No Lead (DFN) Package (Case #1452) — Added case
outline drawing for DFN package.
177
Chapter 17 Ordering Information and Mechanical Specifications — Added
ordering information for DFN package.
185
4.2 Features — Corrected third bulleted item.
49
MC68HC908QY/QT Family Data Sheet, Rev. 4
4
Freescale Semiconductor
Revision History (Sheet 2 of 3)
Date
August,
2003
Revision
Level
1.0
Description
Reformatted to meet latest M68HC08 documentation standards
N/A
Figure 1-1. Block Diagram — Diagram redrawn to include keyboard interrupt
module and TCLK pin designator.
20
Figure 1-2. MCU Pin Assignments — Added TCLK pin designator.
21
Table 1-2. Pin Functions — Added TCLK pin description.
22
Table 1-3. Function Priority in Shared Pins — Revised table for clarity and to
add TCLK.
23
Figure 2-1. Memory Map — Corrected names for the IRQ status and control
register (INTSCR) bits 3–0.
26
3.7.3 ADC Input Clock Register — Clarified bit description for the ADC clock
prescaler bits.
47
4.3 Functional Description — Updated periodic wakeup request values.
51
Figure 6-1. COP Block Diagram — Reworked for clarity
59
Chapter 8 External Interrupt (IRQ) — Corrected bit names for MODE, IRQF,
ACK, and IMASK
Chapter 14 Timer Interface Module (TIM) — Added TCLK function.
15.3 Monitor Module (MON) — Updated with additional data.
Chapter 16 Electrical Specifications — Updated with additional data.
October,
2003
January,
2004
2.0
3.0
Page
Number(s)
77–79
131–139
147
169–173
Figure 2-2. Control, Status, and Data Registers — Deleted unimplemented
areas from $FFB0–$FFBD and $FFC2–$FFCF as they are actually available.
Also corrected $FFBF designation from unimplemented to reserved.
27
Figure 6-1. COP Block Diagram — Reworked for clarity
59
6.3.2 STOP Instruction — Added subsection
60
13.4.2 Active Resets from Internal Sources — Reworked notes for clarity.
111
Table 13-2. Reset Recovery Timing — Replaced previous table with new
information.
112
Chapter 14 Timer Interface Module (TIM) — Updated with additional data.
131
Figure 15-3. Break I/O Register Summary — Corrected bit designators for the
BRKAR register
143
15.3 Monitor Module (MON) — Clarified seventh bullet.
147
Table 17-1. MC Order Numbers — Corrected temperature and package
designators.
175
Figure 2-2. Control, Status, and Data Registers — Corrected reset state for the
FLASH Block Protect Register at address location $FFBE and the Internal
Oscillator Trim Value at $FFC0.
32
Figure 2-5. FLASH Block Protect Register (FLBPR) — Restated reset state for
clarity.
38
MC68HC908QY/QT Family Data Sheet, Rev. 4
Freescale Semiconductor
5
Revision History
Revision History (Sheet 3 of 3)
Date
Revision
Level
Page
Number(s)
Description
Reformatted to meet current documentation standards
November,
2004
4.0
Throughout
6.3.1 BUSCLKX4 — Clarified description of BUSCLKX4
60
Chapter 7 Central Processor Unit (CPU) — In 7.7 Instruction Set Summary:
Reworked definitions for STOP instruction
Added WAIT instruction
72
73
13.8.1 SIM Reset Status Register — Clarified SRSR flag setting
122
14.9.1 TIM Status and Control Register — Added information to TSTOP note
134
16.8 5-V Oscillator Characteristics — Added values for deviation from trimmed
inernal oscillator
165
16.12 3-V Oscillator Characteristics — Added values for deviation from trimmed
inernal oscillator
168
MC68HC908QY/QT Family Data Sheet, Rev. 4
6
Freescale Semiconductor
List of Chapters
Chapter 1 General Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Chapter 2 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Chapter 3 Analog-to-Digital Converter (ADC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Chapter 4 Auto Wakeup Module (AWU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Chapter 5 Configuration Register (CONFIG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Chapter 6 Computer Operating Properly (COP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Chapter 7 Central Processor Unit (CPU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Chapter 8 External Interrupt (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Chapter 9 Keyboard Interrupt Module (KBI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Chapter 10 Low-Voltage Inhibit (LVI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Chapter 11 Oscillator Module (OSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Chapter 12 Input/Output Ports (PORTS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Chapter 13 System Integration Module (SIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Chapter 14 Timer Interface Module (TIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Chapter 15 Development Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Chapter 16 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Chapter 17 Ordering Information and Mechanical Specifications . . . . . . . . . . . . . . . . . . 175
MC68HC908QY/QT Family Data Sheet, Rev. 4
Freescale Semiconductor
7
List of Chapters
MC68HC908QY/QT Family Data Sheet, Rev. 4
8
Freescale Semiconductor
Table of Contents
Chapter 1
General Description
1.1
1.2
1.3
1.4
1.5
1.6
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Function Priority. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17
17
19
19
22
23
Chapter 2
Memory
2.1
2.2
2.3
2.4
2.5
2.6
2.6.1
2.6.2
2.6.3
2.6.4
2.6.5
2.6.6
2.6.7
2.6.8
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Unimplemented Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reserved Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input/Output (I/O) Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Random-Access Memory (RAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FLASH Memory (FLASH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FLASH Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FLASH Page Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FLASH Mass Erase Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FLASH Program Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FLASH Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FLASH Block Protect Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25
25
25
27
32
33
33
34
35
35
36
38
39
39
Chapter 3
Analog-to-Digital Converter (ADC)
3.1
3.2
3.3
3.3.1
3.3.2
3.3.3
3.3.4
3.3.5
3.4
3.5
3.5.1
3.5.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADC Port I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Accuracy and Precision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
41
41
43
44
44
44
44
44
44
45
45
45
MC68HC908QY/QT Family Data Sheet, Rev. 4
Freescale Semiconductor
9
Table of Contents
3.6
3.7
3.7.1
3.7.2
3.7.3
Input/Output Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input/Output Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADC Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADC Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADC Input Clock Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
45
45
45
47
47
Chapter 4
Auto Wakeup Module (AWU)
4.1
4.2
4.3
4.4
4.5
4.6
4.6.1
4.6.2
4.6.3
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input/Output Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port A I/O Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Keyboard Status and Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Keyboard Interrupt Enable Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
49
49
49
51
51
51
51
52
52
Chapter 5
Configuration Register (CONFIG)
5.1
5.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Chapter 6
Computer Operating Properly (COP)
6.1
6.2
6.3
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
6.3.6
6.3.7
6.4
6.5
6.6
6.7
6.7.1
6.7.2
6.8
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BUSCLKX4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
STOP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
COPCTL Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Internal Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
COPD (COP Disable). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
COPRS (COP Rate Select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
COP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
COP Module During Break Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
59
59
60
60
60
60
60
60
60
61
61
61
61
61
61
61
61
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Freescale Semiconductor
Chapter 7
Central Processor Unit (CPU)
7.1
7.2
7.3
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
7.4
7.5
7.5.1
7.5.2
7.6
7.7
7.8
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
63
63
63
64
64
65
65
66
67
67
67
67
67
68
73
Chapter 8
External Interrupt (IRQ)
8.1
8.2
8.3
8.4
8.5
8.6
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IRQ Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IRQ Module During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IRQ Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
75
75
75
78
78
79
Chapter 9
Keyboard Interrupt Module (KBI)
9.1
9.2
9.3
9.3.1
9.3.2
9.4
9.5
9.6
9.7
9.7.1
9.7.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Keyboard Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Keyboard Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Keyboard Module During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input/Output Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Keyboard Status and Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Keyboard Interrupt Enable Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
81
81
83
83
84
85
85
85
85
85
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11
Table of Contents
Chapter 10
Low-Voltage Inhibit (LVI)
10.1
10.2
10.3
10.3.1
10.3.2
10.3.3
10.3.4
10.4
10.5
10.6
10.6.1
10.6.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Polled LVI Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Forced Reset Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage Hysteresis Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LVI Trip Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LVI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LVI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
87
87
87
88
88
88
88
89
89
89
89
89
Chapter 11
Oscillator Module (OSC)
11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.3.1
Internal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.3.1.1
Internal Oscillator Trimming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.3.1.2
Internal to External Clock Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.3.2
External Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.3.3
XTAL Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.3.4
RC Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.4 Oscillator Module Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.4.1
Crystal Amplifier Input Pin (OSC1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.4.2
Crystal Amplifier Output Pin (OSC2/PTA4/BUSCLKX4) . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.4.3
Oscillator Enable Signal (SIMOSCEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.4.4
XTAL Oscillator Clock (XTALCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.4.5
RC Oscillator Clock (RCCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.4.6
Internal Oscillator Clock (INTCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.4.7
Oscillator Out 2 (BUSCLKX4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.4.8
Oscillator Out (BUSCLKX2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.5.1
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.5.2
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.6 Oscillator During Break Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.7 CONFIG2 Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.8 Input/Output (I/O) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.8.1
Oscillator Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.8.2
Oscillator Trim Register (OSCTRIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
91
91
91
92
93
93
93
94
95
95
95
96
96
96
96
96
96
96
97
97
97
97
97
97
98
98
MC68HC908QY/QT Family Data Sheet, Rev. 4
12
Freescale Semiconductor
Chapter 12
Input/Output Ports (PORTS)
12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
12.2 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
12.2.1
Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
12.2.2
Data Direction Register A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
12.2.3
Port A Input Pullup Enable Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
12.3 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
12.3.1
Port B Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
12.3.2
Data Direction Register B. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
12.3.3
Port B Input Pullup Enable Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Chapter 13
System Integration Module (SIM)
13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.2 RST and IRQ Pins Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.3 SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.3.1
Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.3.2
Clock Start-Up from POR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.3.3
Clocks in Stop Mode and Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.4 Reset and System Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.4.1
External Pin Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.4.2
Active Resets from Internal Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.4.2.1
Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.4.2.2
Computer Operating Properly (COP) Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.4.2.3
Illegal Opcode Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.4.2.4
Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.4.2.5
Low-Voltage Inhibit (LVI) Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.5 SIM Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.5.1
SIM Counter During Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.5.2
SIM Counter During Stop Mode Recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.5.3
SIM Counter and Reset States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.6 Exception Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.6.1
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.6.1.1
Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.6.1.2
SWI Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.6.2
Interrupt Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.6.2.1
Interrupt Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.6.2.2
Interrupt Status Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.6.2.3
Interrupt Status Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.6.3
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.6.4
Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.6.5
Status Flag Protection in Break Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.7.1
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.7.2
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
107
110
110
110
110
110
111
111
111
112
113
113
113
113
114
114
114
114
114
114
116
117
117
118
118
119
119
119
119
119
120
121
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13
Table of Contents
13.8 SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
13.8.1
SIM Reset Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
13.8.2
Break Flag Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Chapter 14
Timer Interface Module (TIM)
14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.3 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.4.1
TIM Counter Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.4.2
Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.4.3
Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.4.3.1
Unbuffered Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.4.3.2
Buffered Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.4.4
Pulse Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.4.4.1
Unbuffered PWM Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.4.4.2
Buffered PWM Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.4.4.3
PWM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.6 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.7 TIM During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.8 Input/Output Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.8.1
TIM Clock Pin (PTA2/TCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.8.2
TIM Channel I/O Pins (PTA0/TCH0 and PTA1/TCH1). . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.9 Input/Output Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.9.1
TIM Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.9.2
TIM Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.9.3
TIM Counter Modulo Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.9.4
TIM Channel Status and Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.9.5
TIM Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
125
125
125
127
129
129
129
129
129
130
131
131
132
132
133
133
133
133
133
133
134
135
136
136
139
Chapter 15
Development Support
15.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15.2 Break Module (BRK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15.2.1
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15.2.1.1
Flag Protection During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15.2.1.2
TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15.2.1.3
COP During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15.2.2
Break Module Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15.2.2.1
Break Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15.2.2.2
Break Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15.2.2.3
Break Auxiliary Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15.2.2.4
Break Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15.2.2.5
Break Flag Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15.2.3
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
141
141
141
144
144
144
144
145
145
146
146
147
147
MC68HC908QY/QT Family Data Sheet, Rev. 4
14
Freescale Semiconductor
15.3 Monitor Module (MON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15.3.1
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15.3.1.1
Normal Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15.3.1.2
Forced Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15.3.1.3
Monitor Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15.3.1.4
Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15.3.1.5
Break Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15.3.1.6
Baud Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15.3.1.7
Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15.3.2
Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
147
148
151
152
152
153
153
153
154
157
Chapter 16
Electrical Specifications
16.1
16.2
16.3
16.4
16.5
16.6
16.7
16.8
16.9
16.10
16.11
16.12
16.13
16.14
16.15
16.16
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-V DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Typical 5-V Output Drive Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-V Oscillator Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-V DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Typical 3.0-V Output Drive Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-V Oscillator Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supply Current Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog-to-Digital Converter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer Interface Module Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
159
159
160
160
161
162
163
164
165
166
167
168
169
171
172
173
Chapter 17
Ordering Information and Mechanical Specifications
17.1
17.2
17.3
17.4
17.5
17.6
17.7
17.8
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8-Pin Plastic Dual In-Line Package (Case #626) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8-Pin Small Outline Integrated Circuit Package (Case #968) . . . . . . . . . . . . . . . . . . . . . . . . .
8-Pin Dual Flat No Lead (DFN) Package (Case #1452) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16-Pin Plastic Dual In-Line Package (Case #648D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16-Pin Small Outline Integrated Circuit Package (Case #751G) . . . . . . . . . . . . . . . . . . . . . . .
16-Pin Thin Shrink Small Outline Package (Case #948F) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
175
175
176
176
177
178
178
179
MC68HC908QY/QT Family Data Sheet, Rev. 4
Freescale Semiconductor
15
Table of Contents
MC68HC908QY/QT Family Data Sheet, Rev. 4
16
Freescale Semiconductor
Chapter 1
General Description
1.1 Introduction
The MC68HC908QY4 is a member of the low-cost, high-performance M68HC08 Family of 8-bit
microcontroller units (MCUs). The M68HC08 Family is a Complex Instruction Set Computer (CISC) with
a Von Neumann architecture. All MCUs in the family use the enhanced M68HC08 central processor unit
(CPU08) and are available with a variety of modules, memory sizes and types, and package types.
0.4
Table 1-1. Summary of Device Variations
Device
FLASH
Memory Size
Analog-to-Digital
Converter
Pin
Count
MC68HC908QT1
1536 bytes
—
8 pins
MC68HC908QT2
1536 bytes
4 ch, 8 bit
8 pins
MC68HC908QT4
4096 bytes
4 ch, 8 bit
8 pins
MC68HC908QY1
1536 bytes
—
16 pins
MC68HC908QY2
1536 bytes
4 ch, 8 bit
16 pins
MC68HC908QY4
4096 bytes
4 ch, 8 bit
16 pins
1.2 Features
Features include:
• High-performance M68HC08 CPU core
• Fully upward-compatible object code with M68HC05 Family
• 5-V and 3-V operating voltages (VDD)
• 8-MHz internal bus operation at 5 V, 4-MHz at 3 V
• Trimmable internal oscillator
– 3.2 MHz internal bus operation
– 8-bit trim capability allows 0.4% accuracy(1)
– ± 25% untrimmed
• Auto wakeup from STOP capability
• Configuration (CONFIG) register for MCU configuration options, including:
– Low-voltage inhibit (LVI) trip point
• In-system FLASH programming
• FLASH security(2)
1. The oscillator frequency is guaranteed to ±5% over temperature and voltage range after trimming.
2. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for
unauthorized users.
MC68HC908QY/QT Family Data Sheet, Rev. 4
Freescale Semiconductor
17
General Description
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
On-chip in-application programmable FLASH memory (with internal program/erase voltage
generation)
– MC68HC908QY4 and MC68HC908QT4 — 4096 bytes
– MC68HC908QY2, MC68HC908QY1, MC68HC908QT2, and MC68HC908QT1 — 1536 bytes
128 bytes of on-chip random-access memory (RAM)
2-channel, 16-bit timer interface module (TIM)
4-channel, 8-bit analog-to-digital converter (ADC) on MC68HC908QY2, MC68HC908QY4,
MC68HC908QT2, and MC68HC908QT4
5 or 13 bidirectional input/output (I/O) lines and one input only:
– Six shared with keyboard interrupt function and ADC
– Two shared with timer channels
– One shared with external interrupt (IRQ)
– Eight extra I/O lines on 16-pin package only
– High current sink/source capability on all port pins
– Selectable pullups on all ports, selectable on an individual bit basis
– Three-state ability on all port pins
6-bit keyboard interrupt with wakeup feature (KBI)
Low-voltage inhibit (LVI) module features:
– Software selectable trip point in CONFIG register
System protection features:
– Computer operating properly (COP) watchdog
– Low-voltage detection with reset
– Illegal opcode detection with reset
– Illegal address detection with reset
External asynchronous interrupt pin with internal pullup (IRQ) shared with general-purpose input
pin
Master asynchronous reset pin (RST) shared with general-purpose input/output (I/O) pin
Power-on reset
Internal pullups on IRQ and RST to reduce external components
Memory mapped I/O registers
Power saving stop and wait modes
MC68HC908QY4, MC68HC908QY2, and MC68HC908QY1 are available in these packages:
– 16-pin plastic dual in-line package (PDIP)
– 16-pin small outline integrated circuit (SOIC) package
– 16-pin thin shrink small outline package (TSSOP)
MC68HC908QT4, MC68HC908QT2, and MC68HC908QT1 are available in these packages:
– 8-pin PDIP
– 8-pin SOIC
– 8-pin dual flat no lead (DFN) package
MC68HC908QY/QT Family Data Sheet, Rev. 4
18
Freescale Semiconductor
MCU Block Diagram
Features of the CPU08 include the following:
• Enhanced HC05 programming model
• Extensive loop control functions
• 16 addressing modes (eight more than the HC05)
• 16-bit index register and stack pointer
• Memory-to-memory data transfers
• Fast 8 × 8 multiply instruction
• Fast 16/8 divide instruction
• Binary-coded decimal (BCD) instructions
• Optimization for controller applications
• Efficient C language support
1.3 MCU Block Diagram
Figure 1-1 shows the structure of the MC68HC908QY4.
1.4 Pin Assignments
The MC68HC908QT4, MC68HC908QT2, and MC68HC908QT1 are available in 8-pin packages and the
MC68HC908QY4, MC68HC908QY2, and MC68HC908QY1 in 16-pin packages. Figure 1-2 shows the pin
assignment for these packages.
MC68HC908QY/QT Family Data Sheet, Rev. 4
Freescale Semiconductor
19
General Description
PTA0/AD0/TCH0/KBI0
CLOCK
GENERATOR
(OSCILLATOR)
PTA
PTA2/IRQ/KBI2/TCLK
PTA3/RST/KBI3
DDRA
PTA1/AD1/TCH1/KBI1
SYSTEM INTEGRATION
MODULE
PTA4/OSC2/AD2/KBI4
PTA5/OSC1/AD3/KBI5
M68HC08 CPU
SINGLE INTERRUPT
MODULE
BREAK
MODULE
DDRB
PTB
PTB0
PTB1
PTB2
PTB3
PTB4
PTB5
PTB6
PTB7
POWER-ON RESET
MODULE
8-BIT ADC
128 BYTES RAM
MC68HC908QY4 AND MC68HC908QT4
4096 BYTES
MC68HC908QY2, MC68HC908QY1,
MC68HC908QT2, AND MC68HC908QT1:
1536 BYTES
USER FLASH
KEYBOARD INTERRUPT
MODULE
16-BIT TIMER
MODULE
COP
MODULE
VDD
POWER SUPPLY
MONITOR ROM
VSS
RST, IRQ: Pins have internal (about 30K Ohms) pull up
PTA[0:5]: High current sink and source capability
PTA[0:5]: Pins have programmable keyboard interrupt and pull up
PTB[0:7]: Not available on 8-pin devices – MC68HC908QT1, MC68HC908QT2, and MC68HC908QT4
ADC: Not available on the MC68HC908QY1 and MC68HC908QT1
Figure 1-1. Block Diagram
MC68HC908QY/QT Family Data Sheet, Rev. 4
20
Freescale Semiconductor
Pin Assignments
VDD
1
8
VSS
PTA0/TCH0/KBI0
PTA5/OSC1/AD3/KBI5
2
7
PTA0/AD0/TCH0/KBI0
6
PTA1/TCH1/KBI1
PTA4/OSC2/AD2/KBI4
3
6
PTA1/AD1/TCH1/KBI1
5
PTA2/IRQ/KBI2/TCLK
PTA3/RST/KBI3
4
5
PTA2/IRQ/KBI2/TCLK
VDD
1
8
VSS
PTA5/OSC1/KBI5
2
7
PTA4/OSC2/KBI4
3
PTA3/RST/KBI3
4
8-PIN ASSIGNMENT
MC68HC908QT1 PDIP/SOIC
8-PIN ASSIGNMENT
MC68HC908QT2 AND MC68HC908QT4 PDIP/SOIC
VDD
1
16
VSS
PTB0
PTB7
2
15
PTB0
14
PTB1
PTB6
3
14
PTB1
4
13
PTA0/TCH0/KBI0
PTA5/OSC1/AD3/KBI5
4
13
PTA0/AD0/TCH0/KBI0
PTA4/OSC2/KBI4
5
12
PTA1/TCH1/KBI1
PTA4/OSC2/AD2/KBI4
5
12
PTA1/AD1/TCH1/KBI1
PTB5
6
11
PTB2
PTB5
6
11
PTB2
PTB4
7
10
PTB3
PTB4
7
10
PTB3
PTA3/RST/KBI3
8
9
PTA3/RST/KBI3
8
9
VDD
1
16
VSS
PTB7
2
15
PTB6
3
PTA5/OSC1/KBI5
PTA2/IRQ/KBI2/TCLK
16-PIN ASSIGNMENT
MC68HC908QY2 AND MC68HC908QY4 PDIP/SOIC
16-PIN ASSIGNMENT
MC68HC908QY1 PDIP/SOIC
PTA0/TCH0/KBI0
PTB1
PTB0
VSS
VDD
PTB7
PTB6
PTA5/OSC1/KBI5
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
PTA1/TCH1/KBI1
PTB2
PTB3
PTA2/IRQ/KBI2/TCLK
PTA3/RST/KBI3
PTB4
PTB5
PTA4/OSC2/KBI4
16-PIN ASSIGNMENT
MC68HC908QY1 TSSOP
PTA0/TCH0/KBI0 1
PTA2/IRQ/KBI2/TCLK
PTA0/AD0/TCH0/KBI0
PTB1
PTB0
VSS
VDD
PTB7
PTB6
PTA5/OSC1/AD3/KBI5
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
PTA1/AD1/TCH1/KBI1
PTB2
PTB3
PTA2/IRQ/KBI2/TCLK
PTA3/RST/KBI3
PTB4
PTB5
PTA4/OSC2/AD2/KBI4
16-PIN ASSIGNMENT
MC68HC908QY2 AND MC68HC908QY4 TSSOP
8 PTA1/TCH1/KBI1
PTA0/AD0/TCH0/KBI0 1
8 PTA1/AD1/TCH1/KBI1
VSS 2
7 PTA2/IRQ/KBI2/TCLK
VSS 2
7 PTA2/IRQ/KBI2/TCLK
VDD 3
6 PTA3/RST/KBI3
VDD 3
6 PTA3/RST/KBI3
PTA5/OSC1/KB15 4
5 PTA4/OSC2/KBI4
8-PIN ASSIGNMENT
MC68HC908QT1 DFN
PTA5//OSC1/AD3/KB15 4
5 PTA4/OSC2/AD2/KBI4
8-PIN ASSIGNMENT
MC68HC908QT2 AND MC68HC908QT4 DFN
Figure 1-2. MCU Pin Assignments
MC68HC908QY/QT Family Data Sheet, Rev. 4
Freescale Semiconductor
21
General Description
1.5 Pin Functions
Table 1-2 provides a description of the pin functions.
Table 1-2. Pin Functions
Pin
Name
Description
Input/Output
VDD
Power supply
Power
VSS
Power supply ground
Power
PTA0 — General purpose I/O port
AD0 — A/D channel 0 input
Input/Output
Input
PTA0
TCH0 — Timer Channel 0 I/O
Input/Output
KBI0 — Keyboard interrupt input 0
Input
PTA1 — General purpose I/O port
Input/Output
AD1 — A/D channel 1 input
Input
PTA1
TCH1 — Timer Channel 1 I/O
Input/Output
KBI1 — Keyboard interrupt input 1
Input
PTA2 — General purpose input-only port
Input
IRQ — External interrupt with programmable pullup and Schmitt trigger input
Input
KBI2 — Keyboard interrupt input 2
Input
TCLK — Timer clock input
Input
PTA2
PTA3 — General purpose I/O port
PTA3
PTA4
Input/Output
RST — Reset input, active low with internal pullup and Schmitt trigger
Input
KBI3 — Keyboard interrupt input 3
Input
PTA4 — General purpose I/O port
Input/Output
OSC2 —XTAL oscillator output (XTAL option only)
RC or internal oscillator output (OSC2EN = 1 in PTAPUE register)
Output
Output
AD2 — A/D channel 2 input
Input
KBI4 — Keyboard interrupt input 4
Input
PTA5 — General purpose I/O port
Input/Output
OSC1 — XTAL, RC, or external oscillator input
Input
AD3 — A/D channel 3 input
Input
KBI5 — Keyboard interrupt input 5
Input
PTA5
PTB[0:7](1)
8 general-purpose I/O ports
Input/Output
1. The PTB pins are not available on the 8-pin packages.
MC68HC908QY/QT Family Data Sheet, Rev. 4
22
Freescale Semiconductor
Pin Function Priority
1.6 Pin Function Priority
Table 1-3 is meant to resolve the priority if multiple functions are enabled on a single pin.
NOTE
Upon reset all pins come up as input ports regardless of the priority table.
Table 1-3. Function Priority in Shared Pins
Pin Name
Highest-to-Lowest Priority Sequence
PTA0
AD0 → TCH0 → KBI0 → PTA0
PTA1
AD1 →TCH1 → KBI1 → PTA1
PTA2
IRQ → KBI2 → TCLK → PTA2
PTA3
RST → KBI3 → PTA3
PTA4
OSC2 → AD2 → KBI4 → PTA4
PTA5
OSC1 → AD3 → KBI5 → PTA5
MC68HC908QY/QT Family Data Sheet, Rev. 4
Freescale Semiconductor
23
General Description
MC68HC908QY/QT Family Data Sheet, Rev. 4
24
Freescale Semiconductor
Chapter 2
Memory
2.1 Introduction
The central processor unit (CPU08) can address 64 Kbytes of memory space. The memory map, shown
in Figure 2-1, includes:
• 4096 bytes of user FLASH for MC68HC908QT4 and MC68HC908QY4
• 1536 bytes of user FLASH for MC68HC908QT2, MC68HC908QT1, MC68HC908QY2, and
MC68HC908QY1
• 128 bytes of random access memory (RAM)
• 48 bytes of user-defined vectors, located in FLASH
• 416 bytes of monitor read-only memory (ROM)
• 1536 bytes of FLASH program and erase routines, located in ROM
2.2 Unimplemented Memory Locations
Accessing an unimplemented location can have unpredictable effects on MCU operation. In Figure 2-1
and in register figures in this document, unimplemented locations are shaded.
2.3 Reserved Memory Locations
Accessing a reserved location can have unpredictable effects on MCU operation. In Figure 2-1 and in
register figures in this document, reserved locations are marked with the word Reserved or with the
letter R.
MC68HC908QY/QT Family Data Sheet, Rev. 4
Freescale Semiconductor
25
Memory
$0000
↓
$003F
I/O REGISTERS
64 BYTES
$0040
↓
$007F
RESERVED(1)
64 BYTES
$0080
↓
$00FF
RAM
128 BYTES
$0100
↓
$27FF
UNIMPLEMENTED(1)
9984 BYTES
$2800
↓
$2DFF
AUXILIARY ROM
1536 BYTES
$2E00
↓
$EDFF
UNIMPLEMENTED(1)
49152 BYTES
$EE00
↓
$FDFF
FLASH MEMORY
MC68HC908QT4 AND MC68HC908QY4
4096 BYTES
Note 1.
Attempts to execute code from addresses in this
range will generate an illegal address reset.
$2E00
UNIMPLEMENTED
51712 BYTES
↓
$F7FF
$FE00
BREAK STATUS REGISTER (BSR)
$FE01
RESET STATUS REGISTER (SRSR)
$FE02
BREAK AUXILIARY REGISTER (BRKAR)
$FE03
BREAK FLAG CONTROL REGISTER (BFCR)
$FE04
INTERRUPT STATUS REGISTER 1 (INT1)
$FE05
INTERRUPT STATUS REGISTER 2 (INT2)
$FE06
INTERRUPT STATUS REGISTER 3 (INT3)
$FE07
RESERVED FOR FLASH TEST CONTROL REGISTER (FLTCR)
$FE08
FLASH CONTROL REGISTER (FLCR)
$FE09
BREAK ADDRESS HIGH REGISTER (BRKH)
$FE0A
BREAK ADDRESS LOW REGISTER (BRKL)
$FE0B
BREAK STATUS AND CONTROL REGISTER (BRKSCR)
$FE0C
LVISR
$FE0D
↓
$FE0F
RESERVED FOR FLASH TEST
3 BYTES
$FE10
↓
$FFAF
MONITOR ROM 416 BYTES
$FFB0
↓
$FFBD
FLASH
14 BYTES
$FFBE
FLASH BLOCK PROTECT REGISTER (FLBPR)
$FFBF
RESERVED FLASH
$FFC0
INTERNAL OSCILLATOR TRIM VALUE
$FFC1
RESERVED FLASH
$FFC2
↓
$FFCF
FLASH
14 BYTES
$FFD0
↓
$FFFF
USER VECTORS
48 BYTES
FLASH MEMORY
1536 BYTES
$F800
↓
$FDFF
MC68HC908QT1, MC68HC908QT2,
MC68HC908QY1, and MC68HC908QY2
Memory Map
Figure 2-1. Memory Map
MC68HC908QY/QT Family Data Sheet, Rev. 4
26
Freescale Semiconductor
Input/Output (I/O) Section
2.4 Input/Output (I/O) Section
Addresses $0000–$003F, shown in Figure 2-2, contain most of the control, status, and data registers.
Additional I/O registers have these addresses:
• $FE00 — Break status register, BSR
• $FE01 — Reset status register, SRSR
• $FE02 — Break auxiliary register, BRKAR
• $FE03 — Break flag control register, BFCR
• $FE04 — Interrupt status register 1, INT1
• $FE05 — Interrupt status register 2, INT2
• $FE06 — Interrupt status register 3, INT3
• $FE07 — Reserved
• $FE08 — FLASH control register, FLCR
• $FE09 — Break address register high, BRKH
• $FE0A — Break address register low, BRKL
• $FE0B — Break status and control register, BRKSCR
• $FE0C — LVI status register, LVISR
• $FE0D — Reserved
• $FFBE — FLASH block protect register, FLBPR
• $FFC0 — Internal OSC trim value — Optional
• $FFFF — COP control register, COPCTL
Addr.
$0000
Register Name
Bit 7
Port A Data Register Read:
(PTA) Write:
See page 100. Reset:
Read:
$0001
Port B Data Register
(PTB) Write:
See page 103. Reset:
$0002
Unimplemented
$0003
Unimplemented
$0004
Data Direction Register A Read:
(DDRA) Write:
See page 101. Reset:
Read:
$0005
Data Direction Register B
(DDRB) Write:
See page 103. Reset:
R
6
AWUL
5
4
3
PTA5
PTA4
PTA3
2
PTA2
1
Bit 0
PTA1
PTA0
PTB1
PTB0
DDRA1
DDRA0
Unaffected by reset
PTB7
PTB6
PTB5
PTB4
PTB3
PTB2
Unaffected by reset
0
R
R
DDRA5
DDRA4
DDRA3
0
0
0
0
0
0
0
0
DDRB7
DDRB6
DDRB5
DDRB4
DDRB3
DDRB2
DDRB1
DDRB0
0
0
0
0
0
0
0
0
R
= Reserved
= Unimplemented
U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 1 of 5)
MC68HC908QY/QT Family Data Sheet, Rev. 4
Freescale Semiconductor
27
Memory
Addr.
$0006
↓
$000A
$000B
$000C
Register Name
Bit 7
Port A Input Pullup Enable Read: OSC2EN
Register (PTAPUE) Write:
See page 102. Reset:
0
Port B Input Pullup Enable Read: PTBPUE7
Register (PTBPUE) Write:
See page 104. Reset:
0
Unimplemented
Keyboard Status and Read:
Control Register (KBSCR) Write:
See page 85. Reset:
0
$001A
Read:
0
$001C
$001D
Keyboard Interrupt
Enable Register (KBIER) Write:
See page 86. Reset:
4
3
2
1
Bit 0
PTAPUE5
PTAPUE4
PTAPUE3
PTAPUE2
PTAPUE1
PTAPUE0
0
0
0
0
0
0
0
PTBPUE6
PTBPUE5
PTBPUE4
PTBPUE3
PTBPUE2
PTBPUE1
PTBPUE0
0
0
0
0
0
0
0
0
0
0
KEYF
IMASKK
MODEK
0
0
ACKK
0
0
0
0
0
0
0
0
AWUIE
KBIE5
KBIE4
KBIE3
KBIE2
KBIE1
KBIE0
0
0
0
0
0
0
0
0
0
0
0
0
IRQF
IMASK
MODE
0
0
0
R
R
RSTEN
0
0
0
0(2)
Unimplemented
IRQ Status and Control Read:
Register (INTSCR) Write:
See page 79. Reset:
Read:
$001E
5
Unimplemented
$000D
↓
$0019
$001B
6
Unimplemented
Configuration Register 2
(CONFIG2)(1) Write:
See page 55. Reset:
0
ACK
0
0
0
IRQPUD
IRQEN
R
0
0
0
0
0
OSCOPT1 OSCOPT0
0
1. One-time writable register after each reset.
2. RSTEN reset to 0 by a power-on reset (POR) only.
$001F
Configuration Register 1 Read:
(CONFIG1)(1) Write:
See page 56. Reset:
COPRS
LVISTOP
LVIRSTD
LVIPWRD
LVI5OR3
SSREC
STOP
COPD
0
0
0
0
0(2)
0
0
0
PS2
PS1
PS0
1. One-time writable register after each reset.
2. LVI5OR3 reset to 0 by a power-on reset (POR) only.
$0020
$0021
TIM Status and Control Read:
Register (TSC) Write:
See page 134. Reset:
TOF
TIM Counter Register High Read:
(TCNTH) Write:
See page 135. Reset:
0
0
TOIE
TSTOP
0
0
1
0
0
0
0
0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
0
0
0
0
0
0
0
= Unimplemented
TRST
0
0
R
= Reserved
U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 2 of 5)
MC68HC908QY/QT Family Data Sheet, Rev. 4
28
Freescale Semiconductor
Input/Output (I/O) Section
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
1
1
1
1
1
1
1
1
TIM Counter Modulo
Register Low (TMODL) Write:
See page 136. Reset:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
1
1
1
1
1
1
TIM Channel 0 Status and Read:
Control Register (TSC0) Write:
See page 137. Reset:
CH0F
CH0IE
MS0B
MS0A
ELS0B
ELS0A
TOV0
CH0MAX
0
0
0
0
0
0
0
0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 2
Bit 1
Bit 0
Read:
$0022
$0023
TIM Counter Register Low
(TCNTL) Write:
See page 135. Reset:
TIM Counter Modulo Read:
Register High (TMODH) Write:
See page 136. Reset:
Read:
$0024
$0025
Read:
$0026
$0027
TIM Channel 0
Register High (TCH0H) Write:
See page 139. Reset:
TIM Channel 0 Read:
Register Low (TCH0L) Write:
See page 139. Reset:
Read:
$0028
$0029
TIM Channel 1 Status and
Control Register (TSC1) Write:
See page 137. Reset:
TIM Channel 1 Read:
Register High (TCH1H) Write:
See page 139. Reset:
Read:
$002A
TIM Channel 1
Register Low (TCH1L) Write:
See page 139. Reset:
$002B
↓
$0035
Unimplemented
$0036
Oscillator Status Register Read:
(OSCSTAT) Write:
See page 98. Reset:
$0037
$0038
Unimplemented
Read:
Oscillator Trim Register
(OSCTRIM)
See page 98.
Read:
Write:
Reset:
0
Indeterminate after reset
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Indeterminate after reset
CH1F
0
0
CH1IE
MS1A
ELS1B
ELS1A
TOV1
CH1MAX
0
0
0
0
0
0
0
0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 2
Bit 1
Bit 0
Indeterminate after reset
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Indeterminate after reset
ECGST
R
R
R
R
R
R
ECGON
0
0
0
0
0
0
0
0
TRIM7
TRIM6
TRIM5
TRIM4
TRIM3
TRIM2
TRIM1
TRIM0
1
0
0
0
0
0
0
0
R
= Reserved
= Unimplemented
U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 3 of 5)
MC68HC908QY/QT Family Data Sheet, Rev. 4
Freescale Semiconductor
29
Memory
Addr.
Register Name
Bit 7
$0039
↓
$003B
Unimplemented
$003C
ADC Status and Control Read:
Register (ADSCR) Write:
See page 45. Reset:
$003D
Unimplemented
$003E
$003F
ADC Data Register Read:
(ADR) Write:
See page 47. Reset:
ADC Input Clock Register Read:
(ADICLK) Write:
See page 47. Reset:
Read:
$FE00
Break Status Register
(BSR) Write:
See page 146. Reset:
6
5
4
3
2
1
Bit 0
AIEN
ADCO
CH4
CH3
CH2
CH1
CH0
0
0
0
1
1
1
1
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
COCO
R
Indeterminate after reset
ADIV2
ADIV1
ADIV0
0
0
0
R
R
R
0
0
0
0
0
0
R
R
SBSW
R
See note 1
R
0
1. Writing a 0 clears SBSW.
$FE01
$FE02
$FE03
SIM Reset Status Register
(SRSR)
See page 122.
Read:
POR
PIN
COP
ILOP
ILAD
MODRST
LVI
0
POR:
1
0
0
0
0
0
0
0
Read:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BCFE
R
R
R
R
R
R
R
0
IF5
IF4
IF3
0
IF1
0
0
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
Write:
Break Auxiliary
Register (BRKAR) Write:
See page 146. Reset:
Break Flag Control Read:
Register (BFCR) Write:
See page 147. Reset:
Read:
$FE04
$FE05
Interrupt Status Register 1
(INT1) Write:
See page 79. Reset:
Interrupt Status Register 2 Read:
(INT2) Write:
See page 79. Reset:
Read:
$FE06
$FE07
Interrupt Status Register 3
(INT3) Write:
See page 79. Reset:
Reserved
BDCOP
0
IF14
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IF15
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
R
= Reserved
= Unimplemented
U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 4 of 5)
MC68HC908QY/QT Family Data Sheet, Rev. 4
30
Freescale Semiconductor
Input/Output (I/O) Section
Addr.
Register Name
Read:
$FE08
$FE09
FLASH Control Register
(FLCR) Write:
See page 33. Reset:
Break Address High Read:
Register (BRKH) Write:
See page 145. Reset:
Read:
$FE0A
$FE0B
Break Address low
Register (BRKL) Write:
See page 145. Reset:
Break Status and Control Read:
Register (BRKSCR) Write:
See page 145. Reset:
Read:
$FE0C
$FE0D
↓
$FE0F
$FFBE
LVI Status Register
(LVISR) Write:
See page 89. Reset:
Reserved for FLASH Test
FLASH Block Protect Read:
Register (FLBPR) Write:
See page 38. Reset:
$FFBF
Reserved
$FFC0
Internal Oscillator Trim
Value (Optional)
Read:
Write:
Bit 7
6
5
4
0
0
0
0
3
2
1
Bit 0
HVEN
MASS
ERASE
PGM
0
0
0
0
0
0
0
0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
0
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
BRKE
BRKA
0
0
0
0
0
0
0
0
0
0
0
0
0
0
LVIOUT
0
0
0
0
0
0
R
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
BPR7
BPR6
BPR5
BPR4
BPR3
BPR2
BPR1
BPR0
R
R
R
R
R
R
R
R
TRIM7
TRIM6
TRIM5
TRIM4
TRIM3
TRIM2
TRIM1
TRIM0
R
R
R
Unaffected by reset
Reset:
$FFC1
$FFFF
Reserved
COP Control Register Read:
(COPCTL) Write:
See page 61. Reset:
Unaffected by reset
R
R
R
R
R
LOW BYTE OF RESET VECTOR
WRITING CLEARS COP COUNTER (ANY VALUE)
Unaffected by reset
= Unimplemented
R
= Reserved
U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 5 of 5)
MC68HC908QY/QT Family Data Sheet, Rev. 4
Freescale Semiconductor
31
Memory
.
Table 2-1. Vector Addresses
Vector Priority
Lowest
Vector
IF15
IF14
IF13
↓
IF6
IF5
IF4
IF3
IF2
IF1
—
Highest
—
Address
Vector
$FFDE
ADC conversion complete vector (high)
$FFDF
ADC conversion complete vector (low)
$FFE0
Keyboard vector (high)
$FFE1
Keyboard vector (low)
—
Not used
$FFF2
TIM overflow vector (high)
$FFF3
TIM overflow vector (low)
$FFF4
TIM Channel 1 vector (high)
$FFF5
TIM Channel 1 vector (low)
$FFF6
TIM Channel 0 vector (high)
$FFF7
TIM Channel 0 vector (low)
—
Not used
$FFFA
IRQ vector (high)
$FFFB
IRQ vector (low)
$FFFC
SWI vector (high)
$FFFD
SWI vector (low)
$FFFE
Reset vector (high)
$FFFF
Reset vector (low)
2.5 Random-Access Memory (RAM)
Addresses $0080–$00FF are RAM locations. The location of the stack RAM is programmable. The 16-bit
stack pointer allows the stack to be anywhere in the 64-Kbyte memory space.
NOTE
For correct operation, the stack pointer must point only to RAM locations.
Before processing an interrupt, the central processor unit (CPU) uses five bytes of the stack to save the
contents of the CPU registers.
NOTE
For M6805, M146805, and M68HC05 compatibility, the H register is not
stacked.
During a subroutine call, the CPU uses two bytes of the stack to store the return address. The stack
pointer decrements during pushes and increments during pulls.
NOTE
Be careful when using nested subroutines. The CPU may overwrite data in
the RAM during a subroutine or during the interrupt stacking operation.
MC68HC908QY/QT Family Data Sheet, Rev. 4
32
Freescale Semiconductor
FLASH Memory (FLASH)
2.6 FLASH Memory (FLASH)
This subsection describes the operation of the embedded FLASH memory. The FLASH memory can be
read, programmed, and erased from a single external supply. The program and erase operations are
enabled through the use of an internal charge pump.
The FLASH memory consists of an array of 4096 or 1536 bytes with an additional 48 bytes for user
vectors. The minimum size of FLASH memory that can be erased is 64 bytes; and the maximum size of
FLASH memory that can be programmed in a program cycle is 32 bytes (a row). Program and erase
operations are facilitated through control bits in the FLASH control register (FLCR). Details for these
operations appear later in this section. The address ranges for the user memory and vectors are:
• $EE00 – $FDFF; user memory, 4096 bytes: MC68HC908QY4 and MC68HC908QT4
• $F800 – $FDFF; user memory, 1536 bytes: MC68HC908QY2, MC68HC908QT2,
MC68HC908QY1 and MC68HC908QT1
• $FFD0 – $FFFF; user interrupt vectors, 48 bytes.
NOTE
An erased bit reads as a 1 and a programmed bit reads as a 0.
A security feature prevents viewing of the FLASH contents.(1)
2.6.1 FLASH Control Register
The FLASH control register (FLCR) controls FLASH program and erase operations.
Address:
Read:
$FE08
Bit 7
6
5
4
0
0
0
0
0
0
0
0
Write:
Reset:
3
2
1
Bit 0
HVEN
MASS
ERASE
PGM
0
0
0
0
= Unimplemented
Figure 2-3. FLASH Control Register (FLCR)
HVEN — High Voltage Enable Bit
This read/write bit enables high voltage from the charge pump to the memory for either program or
erase operation. It can only be set if either PGM =1 or ERASE =1 and the proper sequence for
program or erase is followed.
1 = High voltage enabled to array and charge pump on
0 = High voltage disabled to array and charge pump off
MASS — Mass Erase Control Bit
This read/write bit configures the memory for mass erase operation.
1 = Mass erase operation selected
0 = Mass erase operation unselected
1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult
for unauthorized users.
MC68HC908QY/QT Family Data Sheet, Rev. 4
Freescale Semiconductor
33
Memory
ERASE — Erase Control Bit
This read/write bit configures the memory for erase operation. ERASE is interlocked with the PGM bit
such that both bits cannot be equal to 1 or set to 1 at the same time.
1 = Erase operation selected
0 = Erase operation unselected
PGM — Program Control Bit
This read/write bit configures the memory for program operation. PGM is interlocked with the ERASE
bit such that both bits cannot be equal to 1 or set to 1 at the same time.
1 = Program operation selected
0 = Program operation unselected
2.6.2 FLASH Page Erase Operation
Use the following procedure to erase a page of FLASH memory. A page consists of 64 consecutive bytes
starting from addresses $XX00, $XX40, $XX80, or $XXC0. The 48-byte user interrupt vectors area also
forms a page. Any FLASH memory page can be erased alone.
1. Set the ERASE bit and clear the MASS bit in the FLASH control register.
2. Read the FLASH block protect register.
3. Write any data to any FLASH location within the address range of the block to be erased.
4. Wait for a time, tNVS (minimum 10 µs).
5. Set the HVEN bit.
6. Wait for a time, tErase (minimum 1 ms or 4 ms).
7. Clear the ERASE bit.
8. Wait for a time, tNVH (minimum 5 µs).
9. Clear the HVEN bit.
10. After time, tRCV (typical 1 µs), the memory can be accessed in read mode again.
NOTE
Programming and erasing of FLASH locations cannot be performed by
code being executed from the FLASH memory. While these operations
must be performed in the order as shown, but other unrelated operations
may occur between the steps.
CAUTION
A page erase of the vector page will erase the internal oscillator trim value
at $FFC0.
In applications that require more than 1000 program/erase cycles, use the 4 ms page erase specification
to get improved long-term reliability. Any application can use this 4 ms page erase specification. However,
in applications where a FLASH location will be erased and reprogrammed less than 1000 times, and
speed is important, use the 1 ms page erase specification to get a shorter cycle time.
MC68HC908QY/QT Family Data Sheet, Rev. 4
34
Freescale Semiconductor
FLASH Memory (FLASH)
2.6.3 FLASH Mass Erase Operation
Use the following procedure to erase the entire FLASH memory to read as a 1:
1. Set both the ERASE bit and the MASS bit in the FLASH control register.
2. Read the FLASH block protect register.
3. Write any data to any FLASH address(1) within the FLASH memory address range.
4. Wait for a time, tNVS (minimum 10 µs).
5. Set the HVEN bit.
6. Wait for a time, tMErase (minimum 4 ms).
7. Clear the ERASE and MASS bits.
NOTE
Mass erase is disabled whenever any block is protected (FLBPR does not
equal $FF).
8. Wait for a time, tNVHL (minimum 100 µs).
9. Clear the HVEN bit.
10. After time, tRCV (typical 1 µs), the memory can be accessed in read mode again.
NOTE
Programming and erasing of FLASH locations cannot be performed by
code being executed from the FLASH memory. While these operations
must be performed in the order as shown, but other unrelated operations
may occur between the steps.
CAUTION
A mass erase will erase the internal oscillator trim value at $FFC0.
2.6.4 FLASH Program Operation
Programming of the FLASH memory is done on a row basis. A row consists of 32 consecutive bytes
starting from addresses $XX00, $XX20, $XX40, $XX60, $XX80, $XXA0, $XXC0, or $XXE0. Use the
following step-by-step procedure to program a row of FLASH memory
Figure 2-4 shows a flowchart of the programming algorithm.
NOTE
Only bytes which are currently $FF may be programmed.
1. Set the PGM bit. This configures the memory for program operation and enables the latching of
address and data for programming.
2. Read the FLASH block protect register.
3. Write any data to any FLASH location within the address range desired.
4. Wait for a time, tNVS (minimum 10 µs).
5. Set the HVEN bit.
6. Wait for a time, tPGS (minimum 5 µs).
7. Write data to the FLASH address being programmed(2).
1. When in monitor mode, with security sequence failed (see 15.3.2 Security), write to the FLASH block protect register
instead of any FLASH address.
2. The time between each FLASH address change, or the time between the last FLASH address programmed to clearing
PGM bit, must not exceed the maximum programming time, tPROG maximum.
MC68HC908QY/QT Family Data Sheet, Rev. 4
Freescale Semiconductor
35
Memory
8.
9.
10.
11.
12.
13.
Wait for time, tPROG (minimum 30 µs).
Repeat step 7 and 8 until all desired bytes within the row are programmed.
Clear the PGM bit(1).
Wait for time, tNVH (minimum 5 µs).
Clear the HVEN bit.
After time, tRCV (typical 1 µs), the memory can be accessed in read mode again.
NOTE
The COP register at location $FFFF should not be written between
steps 5–12, when the HVEN bit is set. Since this register is located at a
valid FLASH address, unpredictable behavior may occur if this location is
written while HVEN is set.
This program sequence is repeated throughout the memory until all data is programmed.
NOTE
Programming and erasing of FLASH locations cannot be performed by
code being executed from the FLASH memory. While these operations
must be performed in the order shown, other unrelated operations may
occur between the steps. Do not exceed tPROG maximum, see 16.16
Memory Characteristics.
2.6.5 FLASH Protection
Due to the ability of the on-board charge pump to erase and program the FLASH memory in the target
application, provision is made to protect blocks of memory from unintentional erase or program operations
due to system malfunction. This protection is done by use of a FLASH block protect register (FLBPR).
The FLBPR determines the range of the FLASH memory which is to be protected. The range of the
protected area starts from a location defined by FLBPR and ends to the bottom of the FLASH memory
($FFFF). When the memory is protected, the HVEN bit cannot be set in either ERASE or PROGRAM
operations.
NOTE
In performing a program or erase operation, the FLASH block protect
register must be read after setting the PGM or ERASE bit and before
asserting the HVEN bit.
When the FLBPR is programmed with all 0 s, the entire memory is protected from being programmed and
erased. When all the bits are erased (all 1’s), the entire memory is accessible for program and erase.
When bits within the FLBPR are programmed, they lock a block of memory. The address ranges are
shown in 2.6.6 FLASH Block Protect Register. Once the FLBPR is programmed with a value other than
$FF, any erase or program of the FLBPR or the protected block of FLASH memory is prohibited. Mass
erase is disabled whenever any block is protected (FLBPR does not equal $FF). The FLBPR itself can be
erased or programmed only with an external voltage, VTST, present on the IRQ pin. This voltage also
allows entry from reset into the monitor mode.
MC68HC908QY/QT Family Data Sheet, Rev. 4
36
Freescale Semiconductor
FLASH Memory (FLASH)
Algorithm for Programming
a Row (32 Bytes) of FLASH Memory
1
SET PGM BIT
2 READ THE FLASH BLOCK PROTECT REGISTER
3
WRITE ANY DATA TO ANY FLASH ADDRESS
WITHIN THE ROW ADDRESS RANGE DESIRED
4
WAIT FOR A TIME, tNVS
5
SET HVEN BIT
6
WAIT FOR A TIME, tPGS
7
WRITE DATA TO THE FLASH ADDRESS
TO BE PROGRAMMED
8
WAIT FOR A TIME, tPROG
9
COMPLETED
PROGRAMMING
THIS ROW?
Y
N
10
11
12
NOTES:
The time between each FLASH address change (step 7 to step 7),
or the time between the last FLASH address programmed
to clearing PGM bit (step 7 to step 10)
must not exceed the maximum programming
time, tPROG max.
13
This row program algorithm assumes the row/s
to be programmed are initially erased.
CLEAR PGM BIT
WAIT FOR A TIME, tNVH
CLEAR HVEN BIT
WAIT FOR A TIME, tRCV
END OF PROGRAMMING
Figure 2-4. FLASH Programming Flowchart
MC68HC908QY/QT Family Data Sheet, Rev. 4
Freescale Semiconductor
37
Memory
2.6.6 FLASH Block Protect Register
The FLASH block protect register is implemented as a byte within the FLASH memory, and therefore can
only be written during a programming sequence of the FLASH memory. The value in this register
determines the starting address of the protected range within the FLASH memory.
Address:
Read:
Write:
$FFBE
Bit 7
6
5
4
3
2
1
Bit 0
BPR7
BPR6
BPR5
BPR4
BPR3
BPR2
BPR1
BPR0
Reset:
Unaffected by reset. Initial value from factory is 1.
Write to this register is by a programming sequence to the FLASH memory.
Figure 2-5. FLASH Block Protect Register (FLBPR)
BPR[7:0] — FLASH Protection Register Bits [7:0]
These eight bits in FLBPR represent bits [13:6] of a 16-bit memory address. Bits [15:14] are 1s and
bits [5:0] are 0s.
The resultant 16-bit address is used for specifying the start address of the FLASH memory for block
protection. The FLASH is protected from this start address to the end of FLASH memory, at $FFFF.
With this mechanism, the protect start address can be XX00, XX40, XX80, or XXC0 within the FLASH
memory. See Figure 2-6 and Table 2-2.
16-BIT MEMORY ADDRESS
START ADDRESS OF
FLASH BLOCK PROTECT
1
1
FLBPR VALUE
0
0
0
0
0
0
Figure 2-6. FLASH Block Protect Start Address
Table 2-2. Examples of Protect Start Address
BPR[7:0]
Start of Address of Protect Range
$00–$B8
The entire FLASH memory is protected.
$B9 (1011 1001)
$EE40 (1110 1110 0100 0000)
$BA (1011 1010)
$EE80 (1110 1110 1000 0000)
$BB (1011 1011)
$EEC0 (1110 1110 1100 0000)
$BC (1011 1100)
$EF00 (1110 1111 0000 0000)
and so on...
$DE (1101 1110)
$F780 (1111 0111 1000 0000)
$DF (1101 1111)
$F7C0 (1111 0111 1100 0000)
$FE (1111 1110)
$FF80 (1111 1111 1000 0000)
FLBPR, OSCTRIM, and vectors are protected
$FF
The entire FLASH memory is not protected.
MC68HC908QY/QT Family Data Sheet, Rev. 4
38
Freescale Semiconductor
FLASH Memory (FLASH)
2.6.7 Wait Mode
Putting the MCU into wait mode while the FLASH is in read mode does not affect the operation of the
FLASH memory directly, but there will not be any memory activity since the CPU is inactive.
The WAIT instruction should not be executed while performing a program or erase operation on the
FLASH, or the operation will discontinue and the FLASH will be on standby mode.
2.6.8 Stop Mode
Putting the MCU into stop mode while the FLASH is in read mode does not affect the operation of the
FLASH memory directly, but there will not be any memory activity since the CPU is inactive.
The STOP instruction should not be executed while performing a program or erase operation on the
FLASH, or the operation will discontinue and the FLASH will be on standby mode
NOTE
Standby mode is the power-saving mode of the FLASH module in which all
internal control signals to the FLASH are inactive and the current
consumption of the FLASH is at a minimum.
MC68HC908QY/QT Family Data Sheet, Rev. 4
Freescale Semiconductor
39
Memory
MC68HC908QY/QT Family Data Sheet, Rev. 4
40
Freescale Semiconductor
Chapter 3
Analog-to-Digital Converter (ADC)
3.1 Introduction
This section describes the analog-to-digital converter (ADC). The ADC is an 8-bit, 4-channel analog-todigital converter. The ADC module is only available on the MC68HC908QY2, MC68HC908QT2,
MC68HC908QY4, and MC68HC908QT4.
3.2 Features
Features of the ADC module include:
• 4 channels with multiplexed input
• Linear successive approximation with monotonicity
• 8-bit resolution
• Single or continuous conversion
• Conversion complete flag or conversion complete interrupt
• Selectable ADC clock frequency
Figure 3-1 provides a summary of the input/output (I/O) registers.
Addr.
$003C
Register Name
ADC Status and Control
Register (ADSCR)
See page 45.
$003D
Unimplemented
$003E
ADC Data Register
(ADR)
See page 47.
$003F
ADC Input Clock Register
(ADICLK)
See page 47.
Bit 7
6
5
4
3
2
1
Bit 0
AIEN
ADCO
CH4
CH3
CH2
CH1
CH0
Read:
COCO
Write:
R
Reset:
0
0
0
1
1
1
1
1
Read:
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
Write:
Reset:
Read:
Write:
Reset:
Indeterminate after reset
ADIV2
ADIV1
ADIV0
0
0
0
R
= Reserved
0
0
0
0
0
0
0
0
0
0
= Unimplemented
Figure 3-1. ADC I/O Register Summary
MC68HC908QY/QT Family Data Sheet, Rev. 4
Freescale Semiconductor
41
Analog-to-Digital Converter (ADC)
PTA0/AD0/TCH0/KBI0
CLOCK
GENERATOR
(OSCILLATOR)
PTA
PTA2/IRQ/KBI2/TCLK
PTA3/RST/KBI3
DDRA
PTA1/AD1/TCH1/KBI1
SYSTEM INTEGRATION
MODULE
PTA4/OSC2/AD2/KBI4
PTA5/OSC1/AD3/KBI5
M68HC08 CPU
SINGLE INTERRUPT
MODULE
BREAK
MODULE
DDRB
PTB
PTB0
PTB1
PTB2
PTB3
PTB4
PTB5
PTB6
PTB7
POWER-ON RESET
MODULE
8-BIT ADC
128 BYTES RAM
MC68HC908QY4 AND MC68HC908QT4
4096 BYTES
MC68HC908QY2, MC68HC908QY1,
MC68HC908QT2, AND MC68HC908QT1:
1536 BYTES
USER FLASH
KEYBOARD INTERRUPT
MODULE
16-BIT TIMER
MODULE
COP
MODULE
VDD
POWER SUPPLY
MONITOR ROM
VSS
RST, IRQ: Pins have internal (about 30K Ohms) pull up
PTA[0:5]: High current sink and source capability
PTA[0:5]: Pins have programmable keyboard interrupt and pull up
PTB[0:7]: Not available on 8-pin devices – MC68HC908QT1, MC68HC908QT2, and MC68HC908QT4
ADC: Not available on the MC68HC908QY1 and MC68HC908QT1
Figure 3-2. Block Diagram Highlighting ADC Block and Pins
MC68HC908QY/QT Family Data Sheet, Rev. 4
42
Freescale Semiconductor
Functional Description
3.3 Functional Description
Four ADC channels are available for sampling external sources at pins PTA0, PTA1, PTA4, and PTA5.
An analog multiplexer allows the single ADC converter to select one of the four ADC channels as an ADC
voltage input (ADCVIN). ADCVIN is converted by the successive approximation register-based counters.
The ADC resolution is eight bits. When the conversion is completed, ADC puts the result in the ADC data
register and sets a flag or generates an interrupt.
Figure 3-3 shows a block diagram of the ADC.
INTERNAL
DATA BUS
READ DDRA
DISABLE
WRITE DDRA
DDRAx
RESET
WRITE PTA
ADCx
PTAx
READ PTA
DISABLE
ADC CHANNEL x
ADC DATA REGISTER
INTERRUPT
LOGIC
AIEN
CONVERSION
COMPLETE
COCO
BUS CLOCK
ADC VOLTAGE IN
ADCVIN
ADC
CHANNEL
SELECT
(1 OF 4 CHANNELS)
CH[4:0]
ADC CLOCK
CLOCK
GENERATOR
ADIV[2:0]
Figure 3-3. ADC Block Diagram
MC68HC908QY/QT Family Data Sheet, Rev. 4
Freescale Semiconductor
43
Analog-to-Digital Converter (ADC)
3.3.1 ADC Port I/O Pins
PTA0, PTA1, PTA4, and PTA5 are general-purpose I/O pins that are shared with the ADC channels. The
channel select bits (ADC status and control register (ADSCR), $003C), define which ADC channel/port
pin will be used as the input signal. The ADC overrides the port I/O logic by forcing that pin as input to the
ADC. The remaining ADC channels/port pins are controlled by the port I/O logic and can be used as
general-purpose I/O. Writes to the port register or data direction register (DDR) will not have any affect
on the port pin that is selected by the ADC. Read of a port pin which is in use by the ADC will return a 0
if the corresponding DDR bit is at 0. If the DDR bit is at 1, the value in the port data latch is read.
3.3.2 Voltage Conversion
When the input voltage to the ADC equals VDD, the ADC converts the signal to $FF (full scale). If the input
voltage equals VSS, the ADC converts it to $00. Input voltages between VDD and VSS are a straight-line
linear conversion. All other input voltages will result in $FF if greater than VDD and $00 if less than VSS.
NOTE
Input voltage should not exceed the analog supply voltages.
3.3.3 Conversion Time
Sixteen ADC internal clocks are required to perform one conversion. The ADC starts a conversion on the
first rising edge of the ADC internal clock immediately following a write to the ADSCR. If the ADC internal
clock is selected to run at 1 MHz, then one conversion will take 16 µs to complete. With a 1-MHz ADC
internal clock the maximum sample rate is 62.5 kHz.
Conversion Time =
16 ADC Clock Cycles
ADC Clock Frequency
Number of Bus Cycles = Conversion Time × Bus Frequency
3.3.4 Continuous Conversion
In the continuous conversion mode (ADCO = 1), the ADC continuously converts the selected channel
filling the ADC data register (ADR) with new data after each conversion. Data from the previous
conversion will be overwritten whether that data has been read or not. Conversions will continue until the
ADCO bit is cleared. The COCO bit (ADSCR, $003C) is set after each conversion and will stay set until
the next read of the ADC data register.
When a conversion is in process and the ADSCR is written, the current conversion data should be
discarded to prevent an incorrect reading.
3.3.5 Accuracy and Precision
The conversion process is monotonic and has no missing codes.
3.4 Interrupts
When the AIEN bit is set, the ADC module is capable of generating a central processor unit (CPU)
interrupt after each ADC conversion. A CPU interrupt is generated if the COCO bit is at 0. The COCO bit
is not used as a conversion complete flag when interrupts are enabled.
MC68HC908QY/QT Family Data Sheet, Rev. 4
44
Freescale Semiconductor
Low-Power Modes
3.5 Low-Power Modes
The following subsections describe the ADC in low-power modes.
3.5.1 Wait Mode
The ADC continues normal operation during wait mode. Any enabled CPU interrupt request from the ADC
can bring the microcontroller unit (MCU) out of wait mode. If the ADC is not required to bring the MCU out
of wait mode, power down the ADC by setting the CH[4:0] bits in ADSCR to 1s before executing the WAIT
instruction.
3.5.2 Stop Mode
The ADC module is inactive after the execution of a STOP instruction. Any pending conversion is aborted.
ADC conversions resume when the MCU exits stop mode. Allow one conversion cycle to stabilize the
analog circuitry before using ADC data after exiting stop mode.
3.6 Input/Output Signals
The ADC module has four channels that are shared with I/O port A.
ADC voltage in (ADCVIN) is the input voltage signal from one of the four ADC channels to the ADC
module.
3.7 Input/Output Registers
These I/O registers control and monitor ADC operation:
• ADC status and control register (ADSCR)
• ADC data register (ADR)
• ADC clock register (ADICLK)
3.7.1 ADC Status and Control Register
The following paragraphs describe the function of the ADC status and control register (ADSCR). When a
conversion is in process and the ADSCR is written, the current conversion data should be discarded to
prevent an incorrect reading.
Address: $003C
Bit 7
6
5
4
3
2
1
Bit 0
AIEN
ADCO
CH4
CH3
CH2
CH1
CH0
0
1
1
1
1
1
Read:
COCO
Write:
R
Reset:
0
0
R
= Reserved
Figure 3-4. ADC Status and Control Register (ADSCR)
COCO — Conversions Complete Bit
In non-interrupt mode (AIEN = 0), COCO is a read-only bit that is set at the end of each conversion.
COCO will stay set until cleared by a read of the ADC data register. Reset clears this bit.
MC68HC908QY/QT Family Data Sheet, Rev. 4
Freescale Semiconductor
45
Analog-to-Digital Converter (ADC)
In interrupt mode (AIEN = 1), COCO is a read-only bit that is not set at the end of a conversion. It
always reads as a 0.
1 = Conversion completed (AIEN = 0)
0 = Conversion not completed (AIEN = 0) or CPU interrupt enabled (AIEN = 1)
NOTE
The write function of the COCO bit is reserved. When writing to the ADSCR
register, always have a 0 in the COCO bit position.
AIEN — ADC Interrupt Enable Bit
When this bit is set, an interrupt is generated at the end of an ADC conversion. The interrupt signal is
cleared when ADR is read or ADSCR is written. Reset clears the AIEN bit.
1 = ADC interrupt enabled
0 = ADC interrupt disabled
ADCO — ADC Continuous Conversion Bit
When set, the ADC will convert samples continuously and update ADR at the end of each conversion.
Only one conversion is allowed when this bit is cleared. Reset clears the ADCO bit.
1 = Continuous ADC conversion
0 = One ADC conversion
CH[4:0] — ADC Channel Select Bits
CH4, CH3, CH2, CH1, and CH0 form a 5-bit field which is used to select one of the four ADC channels.
The five select bits are detailed in Table 3-1. Care should be taken when using a port pin as both an
analog and a digital input simultaneously to prevent switching noise from corrupting the analog signal.
The ADC subsystem is turned off when the channel select bits are all set to 1. This feature allows for
reduced power consumption for the MCU when the ADC is not used. Reset sets all of these bits to 1.
NOTE
Recovery from the disabled state requires one conversion cycle to stabilize.
Table 3-1. MUX Channel Select
CH4
CH3
CH2
CH1
CH0
ADC
Channel
Input Select
0
0
0
0
0
ADC0
PTA0
0
0
0
0
1
ADC1
PTA1
0
0
0
1
0
ADC2
PTA4
0
0
0
1
1
ADC3
PTA5
0
0
1
0
0
—
↓
↓
↓
↓
↓
—
1
1
0
1
0
—
Unused(1)
1
1
0
1
1
—
Reserved
1
1
1
0
0
—
Unused
1
1
1
0
1
—
VDDA(2)
1
1
1
1
0
—
VSSA(2)
1
1
1
1
1
—
ADC power off
1. If any unused channels are selected, the resulting ADC conversion will be
unknown.
2. The voltage levels supplied from internal reference nodes, as specified in the
table, are used to verify the operation of the ADC converter both in production test and for user applications.
MC68HC908QY/QT Family Data Sheet, Rev. 4
46
Freescale Semiconductor
Input/Output Registers
3.7.2 ADC Data Register
One 8-bit result register is provided. This register is updated each time an ADC conversion completes.
Address: $003E
Read:
Bit 7
6
5
4
3
2
1
Bit 0
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
Write:
Reset:
Indeterminate after reset
= Unimplemented
Figure 3-5. ADC Data Register (ADR)
3.7.3 ADC Input Clock Register
This register selects the clock frequency for the ADC.
Address: $003F
Bit 7
Read:
Write:
Reset:
6
5
ADIV2
ADIV1
ADIV0
0
0
0
4
3
2
1
Bit 0
0
0
0
0
0
0
0
0
0
0
= Unimplemented
Figure 3-6. ADC Input Clock Register (ADICLK)
ADIV2–ADIV0 — ADC Clock Prescaler Bits
ADIV2, ADIV1, and ADIV0 form a 3-bit field which selects the divide ratio used by the ADC to generate
the internal ADC clock. Table 3-2 shows the available clock configurations. The ADC clock frequency
should be set between fADIC(MIN) and fADIC(MAX). The analog input level should remain stable for the
entire conversion time (maximum = 17 ADC clock cycles).
Table 3-2. ADC Clock Divide Ratio
ADIV2
ADIV1
ADIV0
ADC Clock Rate
0
0
0
Bus clock ÷ 1
0
0
1
Bus clock ÷ 2
0
1
0
Bus clock ÷ 4
0
1
1
Bus clock ÷ 8
1
X
X
Bus clock ÷ 16
X = don’t care
MC68HC908QY/QT Family Data Sheet, Rev. 4
Freescale Semiconductor
47
Analog-to-Digital Converter (ADC)
MC68HC908QY/QT Family Data Sheet, Rev. 4
48
Freescale Semiconductor
Chapter 4
Auto Wakeup Module (AWU)
4.1 Introduction
This section describes the auto wakeup module (AWU). The AWU generates a periodic interrupt during
stop mode to wake the part up without requiring an external signal. Figure 4-2 is a block diagram of the
AWU.
4.2 Features
Features of the auto wakeup module include:
• One internal interrupt with separate interrupt enable bit, sharing the same keyboard interrupt vector
and keyboard interrupt mask bit
• Exit from low-power stop mode without external signals
• Selectable timeout periods
• Dedicated low-power internal oscillator separate from the main system clock sources
Figure 4-1 provides a summary of the input/output (I/O) registers used in conjuction with the AWU.
Addr.
$0000
$001A
$001B
Register Name
Bit 7
6
Port A Data Register Read:
(PTA) Write:
See page 51. Reset:
0
AWUL
Keyboard Status Read:
and Control Register Write:
(KBSCR)
See page 52. Reset:
0
Keyboard Interrupt Enable Read:
Register (KBIER) Write:
See page 52. Reset:
0
5
4
3
PTA5
PTA4
PTA3
2
PTA2
1
Bit 0
PTA1
PTA0
IMASKK
MODEK
Unaffected by reset
0
0
0
KEYF
0
ACKK
0
0
0
0
0
0
0
0
0
AWUIE
KBIE5
KBIE4
KBIE3
KBIE2
KBIE1
KBIE0
0
0
0
0
0
0
0
= Unimplemented
Figure 4-1. AWU Register Summary
4.3 Functional Description
The function of the auto wakeup logic is to generate periodic wakeup requests to bring the microcontroller
unit (MCU) out of stop mode. The wakeup requests are treated as regular keyboard interrupt requests,
with the difference that instead of a pin, the interrupt signal is generated by an internal logic.
MC68HC908QY/QT Family Data Sheet, Rev. 4
Freescale Semiconductor
49
Auto Wakeup Module (AWU)
Writing the AWUIE bit in the keyboard interrupt enable register enables or disables the auto wakeup
interrupt input (see Figure 4-2). A logic 1 applied to the AWUIREQ input with auto wakeup interrupt
request enabled, latches an auto wakeup interrupt request.
Auto wakeup latch, AWUL, can be read directly from the bit 6 position of port A data register (PTA). This
is a read-only bit which is occupying an empty bit position on PTA. No PTA associated registers, such as
PTA6 data direction or PTA6 pullup exist for this bit.
Entering stop mode will enable the auto wakeup generation logic. An internal RC oscillator (exclusive for
the auto wakeup feature) drives the wakeup request generator. Once the overflow count is reached in the
generator counter, a wakeup request, AWUIREQ, is latched and sent to the KBI logic. See Figure 4-1.
Wakeup interrupt requests will only be serviced if the associated interrupt enable bit, AWUIE, in KBIER
is set. The AWU shares the keyboard interrupt vector.
COPRS (FROM CONFIG1)
VDD
AUTOWUGEN
TO PTA READ, BIT 6
1 = DIV 29
SHORT 0 = DIV 214
OVERFLOW
INT RC OSC
EN
D
32 kHz
CLK
E
RST
AWUL
Q
AWUIREQ
R
TO KBI INTERRUPT LOGIC (SEE
Figure 9-3. Keyboard Interrupt
Block Diagram)
CLRLOGIC
RESET
CLEAR
ACKK
(CGMXCLK)
BUSCLKX4
CLK
RST
RESET
ISTOP
RESET
AWUIE
Figure 4-2. Auto Wakeup Interrupt Request Generation Logic
The overflow count can be selected from two options defined by the COPRS bit in CONFIG1. This bit was
“borrowed” from the computer operating properly (COP) using the fact that the COP feature is idle (no
MCU clock available) in stop mode. The typical values of the periodic wakeup request are (at room
temperature):
• COPRS = 0: 650 ms @ 5 V, 875 ms @ 3 V
• COPRS = 1: 16 ms @ 5 V, 22 ms @ 3 V
The auto wakeup RC oscillator is highly dependent on operating voltage and temperature. This feature is
not recommended for use as a time-keeping function.
The wakeup request is latched to allow the interrupt source identification. The latched value, AWUL, can
be read directly from the bit 6 position of PTA data register. This is a read-only bit which is occupying an
empty bit position on PTA. No PTA associated registers, such as PTA6 data, PTA6 direction, and PTA6
MC68HC908QY/QT Family Data Sheet, Rev. 4
50
Freescale Semiconductor
Wait Mode
pullup exist for this bit. The latch can be cleared by writing to the ACKK bit in the KBSCR register. Reset
also clears the latch. AWUIE bit in KBI interrupt enable register (see Figure 4-2) has no effect on AWUL
reading.
The AWU oscillator and counters are inactive in normal operating mode and become active only upon
entering stop mode.
4.4 Wait Mode
The AWU module remains inactive in wait mode.
4.5 Stop Mode
When the AWU module is enabled (AWUIE = 1 in the keyboard interrupt enable register) it is activated
automatically upon entering stop mode. Clearing the IMASKK bit in the keyboard status and control
register enables keyboard interrupt requests to bring the MCU out of stop mode. The AWU counters start
from ‘0’ each time stop mode is entered.
4.6 Input/Output Registers
The AWU shares registers with the keyboard interrupt (KBI) module and the port A I/O module. The
following I/O registers control and monitor operation of the AWU:
• Port A data register (PTA)
• Keyboard interrupt status and control register (KBSCR)
• Keyboard interrupt enable register (KBIER)
4.6.1 Port A I/O Register
The port A data register (PTA) contains a data latch for the state of the AWU interrupt request, in addition
to the data latches for port A.
Address: $0000
Read:
Bit 7
6
0
AWUL
0
0
Write:
Reset:
5
4
3
PTA5
PTA4
PTA3
2
PTA2
1
Bit 0
PTA1
PTA0
Unaffected by reset
= Unimplemented
Figure 4-3. Port A Data Register (PTA)
AWUL — Auto Wakeup Latch
This is a read-only bit which has the value of the auto wakeup interrupt request latch. The wakeup
request signal is generated internally. There is no PTA6 port or any of the associated bits such as
PTA6 data direction or pullup bits.
1 = Auto wakeup interrupt request is pending
0 = Auto wakeup interrupt request is not pending
NOTE
PTA5–PTA0 bits are not used in conjuction with the auto wakeup feature.
To see a description of these bits, see 12.2.1 Port A Data Register.
MC68HC908QY/QT Family Data Sheet, Rev. 4
Freescale Semiconductor
51
Auto Wakeup Module (AWU)
4.6.2 Keyboard Status and Control Register
The keyboard status and control register (KBSCR):
• Flags keyboard/auto wakeup interrupt requests
• Acknowledges keyboard/auto wakeup interrupt requests
• Masks keyboard/auto wakeup interrupt requests
Address: $001A
Read:
Bit 7
6
5
4
3
2
0
0
0
0
KEYF
0
Write:
Reset:
ACKK
0
0
0
0
0
0
1
Bit 0
IMASKK
MODEK
0
0
= Unimplemented
Figure 4-4. Keyboard Status and Control Register (KBSCR)
Bits 7–4 — Not used
These read-only bits always read as 0s.
KEYF — Keyboard Flag Bit
This read-only bit is set when a keyboard interrupt is pending on port A or auto wakeup. Reset clears
the KEYF bit.
1 = Keyboard/auto wakeup interrupt pending
0 = No keyboard/auto wakeup interrupt pending
ACKK — Keyboard Acknowledge Bit
Writing a 1 to this write-only bit clears the keyboard/auto wakeup interrupt request on port A and auto
wakeup logic. ACKK always reads as 0.Reset clears ACKK.
IMASKK— Keyboard Interrupt Mask Bit
Writing a 1 to this read/write bit prevents the output of the keyboard interrupt mask from generating
interrupt requests on port A or auto wakeup. Reset clears the IMASKK bit.
1 = Keyboard/auto wakeup interrupt requests masked
0 = Keyboard/auto wakeup interrupt requests not masked
NOTE
MODEK is not used in conjuction with the auto wakeup feature. To see a
description of this bit, see 9.7.1 Keyboard Status and Control Register.
4.6.3 Keyboard Interrupt Enable Register
The keyboard interrupt enable register (KBIER) enables or disables the auto wakeup to operate as a
keyboard/auto wakeup interrupt input.
Address: $001B
Bit 7
Read:
0
Write:
Reset:
0
6
5
4
3
2
1
Bit 0
AWUIE
KBIE5
KBIE4
KBIE3
KBIE2
KBIE1
KBIE0
0
0
0
0
0
0
0
= Unimplemented
Figure 4-5. Keyboard Interrupt Enable Register (KBIER)
MC68HC908QY/QT Family Data Sheet, Rev. 4
52
Freescale Semiconductor
Input/Output Registers
AWUIE — Auto Wakeup Interrupt Enable Bit
This read/write bit enables the auto wakeup interrupt input to latch interrupt requests. Reset clears
AWUIE.
1 = Auto wakeup enabled as interrupt input
0 = Auto wakeup not enabled as interrupt input
NOTE
KBIE5–KBIE0 bits are not used in conjuction with the auto wakeup feature.
To see a description of these bits, see 9.7.2 Keyboard Interrupt Enable
Register.
MC68HC908QY/QT Family Data Sheet, Rev. 4
Freescale Semiconductor
53
Auto Wakeup Module (AWU)
MC68HC908QY/QT Family Data Sheet, Rev. 4
54
Freescale Semiconductor
Chapter 5
Configuration Register (CONFIG)
5.1 Introduction
This section describes the configuration registers (CONFIG1 and CONFIG2). The configuration registers
enable or disable the following options:
• Stop mode recovery time (32 × BUSCLKX4 cycles or
4096 × BUSCLKX4 cycles)
• STOP instruction
• Computer operating properly module (COP)
• COP reset period (COPRS): (8176) × BUSCLKX4 or (262,128) × BUSCLKX4
• Low-voltage inhibit (LVI) enable and trip voltage selection
• OSC option selection
• IRQ pin
• RST pin
• Auto wakeup timeout period
5.2 Functional Description
The configuration registers are used in the initialization of various options. The configuration registers can
be written once after each reset. Most of the configuration register bits are cleared during reset. Since the
various options affect the operation of the microcontroller unit (MCU) it is recommended that this register
be written immediately after reset. The configuration registers are located at $001E and $001F, and may
be read at anytime.
NOTE
The CONFIG registers are one-time writable by the user after each reset.
Upon a reset, the CONFIG registers default to predetermined settings as
shown in Figure 5-1 and Figure 5-2.
Address: $001E
Bit 7
6
5
4
3
2
1
Bit 0
IRQPUD
IRQEN
R
OSCOPT1
OSCOPT0
R
R
RSTEN
Reset:
0
0
0
0
0
0
0
U
POR:
0
0
0
0
0
0
0
0
R
= Reserved
Read:
Write:
U = Unaffected
Figure 5-1. Configuration Register 2 (CONFIG2)
MC68HC908QY/QT Family Data Sheet, Rev. 4
Freescale Semiconductor
55
Configuration Register (CONFIG)
IRQPUD — IRQ Pin Pullup Control Bit
1 = Internal pullup is disconnected
0 = Internal pullup is connected between IRQ pin and VDD
IRQEN — IRQ Pin Function Selection Bit
1 = Interrupt request function active in pin
0 = Interrupt request function inactive in pin
OSCOPT1 and OSCOPT0 — Selection Bits for Oscillator Option
(0, 0) Internal oscillator
(0, 1) External oscillator
(1, 0) External RC oscillator
(1, 1) External XTAL oscillator
RSTEN — RST Pin Function Selection
1 = Reset function active in pin
0 = Reset function inactive in pin
NOTE
The RSTEN bit is cleared by a power-on reset (POR) only. Other resets will
leave this bit unaffected.
Address: $001F
Read:
Write:
Reset:
POR:
Bit 7
6
5
4
3
2
1
Bit 0
COPRS
LVISTOP
LVIRSTD
LVIPWRD
LVI5OR3
SSREC
STOP
COPD
0
0
0
0
U
0
0
0
0
0
0
0
0
0
0
0
U = Unaffected
Figure 5-2. Configuration Register 1 (CONFIG1)
COPRS (Out of STOP Mode) — COP Reset Period Selection Bit
1 = COP reset short cycle = (8176) × BUSCLKX4
0 = COP reset long cycle = (262,128) × BUSCLKX4
COPRS (In STOP Mode) — Auto Wakeup Period Selection Bit
1 = Auto wakeup short cycle = (29) × INTRCOSC
0 = Auto wakeup long cycle = (214) × INTRCOSC
LVISTOP — LVI Enable in Stop Mode Bit
When the LVIPWRD bit is clear, setting the LVISTOP bit enables the LVI to operate during stop mode.
Reset clears LVISTOP.
1 = LVI enabled during stop mode
0 = LVI disabled during stop mode
LVIRSTD — LVI Reset Disable Bit
LVIRSTD disables the reset signal from the LVI module.
1 = LVI module resets disabled
0 = LVI module resets enabled
MC68HC908QY/QT Family Data Sheet, Rev. 4
56
Freescale Semiconductor
Functional Description
LVIPWRD — LVI Power Disable Bit
LVIPWRD disables the LVI module.
1 = LVI module power disabled
0 = LVI module power enabled
LVI5OR3 — LVI 5-V or 3-V Operating Mode Bit
LVI5OR3 selects the voltage operating mode of the LVI module. The voltage mode selected for the
LVI should match the operating VDD for the LVI’s voltage trip points for each of the modes.
1 = LVI operates in 5-V mode
0 = LVI operates in 3-V mode
NOTE
The LVI5OR3 bit is cleared by a power-on reset (POR) only. Other resets
will leave this bit unaffected.
SSREC — Short Stop Recovery Bit
SSREC enables the CPU to exit stop mode with a delay of 32 BUSCLKX4 cycles instead of a 4096
BUSCLKX4 cycle delay.
1 = Stop mode recovery after 32 BUSCLKX4 cycles
0 = Stop mode recovery after 4096 BUSCLKX4 cycles
NOTE
Exiting stop mode by an LVI reset will result in the long stop recovery.
The system stabilization time for power-on reset and long stop recovery (both 4096 BUSCLKX4
cycles) gives a delay longer than the LVI enable time for these startup scenarios. There is no period
where the MCU is not protected from a low-power condition. However, when using the short stop
recovery configuration option, the 32 BUSCLKX4 delay must be greater than the LVI’s turn on time to
avoid a period in startup where the LVI is not protecting the MCU.
STOP — STOP Instruction Enable Bit
STOP enables the STOP instruction.
1 = STOP instruction enabled
0 = STOP instruction treated as illegal opcode
COPD — COP Disable Bit
COPD disables the COP module.
1 = COP module disabled
0 = COP module enabled
MC68HC908QY/QT Family Data Sheet, Rev. 4
Freescale Semiconductor
57
Configuration Register (CONFIG)
MC68HC908QY/QT Family Data Sheet, Rev. 4
58
Freescale Semiconductor
Chapter 6
Computer Operating Properly (COP)
6.1 Introduction
The computer operating properly (COP) module contains a free-running counter that generates a reset if
allowed to overflow. The COP module helps software recover from runaway code. Prevent a COP reset
by clearing the COP counter periodically. The COP module can be disabled through the COPD bit in the
configuration 1 (CONFIG1) register.
6.2 Functional Description
INTERNAL RESET SOURCES
RESET STATUS REGISTER
COP TIMEOUT
CLEAR STAGES 5–12
STOP INSTRUCTION
RESET CIRCUIT
12-BIT SIM COUNTER
CLEAR ALL STAGES
BUSCLKX4
COPCTL WRITE
COP CLOCK
COPEN (FROM SIM)
COP DISABLE (COPD FROM CONFIG1)
RESET
COPCTL WRITE
6-BIT COP COUNTER
CLEAR
COP COUNTER
COP RATE SELECT
(COPRS FROM CONFIG1)
Figure 6-1. COP Block Diagram
MC68HC908QY/QT Family Data Sheet, Rev. 4
Freescale Semiconductor
59
Computer Operating Properly (COP)
The COP counter is a free-running 6-bit counter preceded by the 12-bit system integration module (SIM)
counter. If not cleared by software, the COP counter overflows and generates an asynchronous reset after
262,128 or 8176 BUSCLKX4 cycles; depending on the state of the COP rate select bit, COPRS, in
configuration register 1. With a 262,128 BUSCLKX4 cycle overflow option, the internal 12.8-MHz
oscillator gives a COP timeout period of 20.48 ms. Writing any value to location $FFFF before an overflow
occurs prevents a COP reset by clearing the COP counter and stages 12–5 of the SIM counter.
NOTE
Service the COP immediately after reset and before entering or after exiting
stop mode to guarantee the maximum time before the first COP counter
overflow.
A COP reset pulls the RST pin low (if the RSTEN bit is set in the CONFIG1 register) for 32 × BUSCLKX4
cycles and sets the COP bit in the reset status register (RSR). See 13.8.1 SIM Reset Status Register.
NOTE
Place COP clearing instructions in the main program and not in an interrupt
subroutine. Such an interrupt subroutine could keep the COP from
generating a reset even while the main program is not working properly.
6.3 I/O Signals
The following paragraphs describe the signals shown in Figure 6-1.
6.3.1 BUSCLKX4
BUSCLKX4 is the oscillator output signal. BUSCLKX4 frequency is equal to the internal oscillator
frequency, the crystal frequency, or the RC-oscillator frequency.
6.3.2 STOP Instruction
The STOP instruction clears the SIM counter.
6.3.3 COPCTL Write
Writing any value to the COP control register (COPCTL) (see 6.4 COP Control Register) clears the COP
counter and clears stages 12–5 of the SIM counter. Reading the COP control register returns the low byte
of the reset vector.
6.3.4 Power-On Reset
The power-on reset (POR) circuit in the SIM clears the SIM counter 4096 × BUSCLKX4 cycles after
power up.
6.3.5 Internal Reset
An internal reset clears the SIM counter and the COP counter.
6.3.6 COPD (COP Disable)
The COPD signal reflects the state of the COP disable bit (COPD) in the configuration register 1
(CONFIG1). See Chapter 5 Configuration Register (CONFIG).
MC68HC908QY/QT Family Data Sheet, Rev. 4
60
Freescale Semiconductor
COP Control Register
6.3.7 COPRS (COP Rate Select)
The COPRS signal reflects the state of the COP rate select bit (COPRS) in the configuration register 1
(CONFIG1). See Chapter 5 Configuration Register (CONFIG).
6.4 COP Control Register
The COP control register (COPCTL) is located at address $FFFF and overlaps the reset vector. Writing
any value to $FFFF clears the COP counter and starts a new timeout period. Reading location $FFFF
returns the low byte of the reset vector.
Address: $FFFF
Bit 7
6
5
4
3
Read:
LOW BYTE OF RESET VECTOR
Write:
CLEAR COP COUNTER
Reset:
Unaffected by reset
2
1
Bit 0
Figure 6-2. COP Control Register (COPCTL)
6.5 Interrupts
The COP does not generate CPU interrupt requests.
6.6 Monitor Mode
The COP is disabled in monitor mode when VTST is present on the IRQ pin.
6.7 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption standby modes.
6.7.1 Wait Mode
The COP continues to operate during wait mode. To prevent a COP reset during wait mode, periodically
clear the COP counter.
6.7.2 Stop Mode
Stop mode turns off the BUSCLKX4 input to the COP and clears the SIM counter. Service the COP
immediately before entering or after exiting stop mode to ensure a full COP timeout period after entering
or exiting stop mode.
6.8 COP Module During Break Mode
The COP is disabled during a break interrupt with monitor mode when BDCOP bit is set in break auxiliary
register (BRKAR).
MC68HC908QY/QT Family Data Sheet, Rev. 4
Freescale Semiconductor
61
Computer Operating Properly (COP)
MC68HC908QY/QT Family Data Sheet, Rev. 4
62
Freescale Semiconductor
Chapter 7
Central Processor Unit (CPU)
7.1 Introduction
The M68HC08 CPU (central processor unit) is an enhanced and fully object-code-compatible version of
the M68HC05 CPU. The CPU08 Reference Manual (document order number CPU08RM/AD) contains a
description of the CPU instruction set, addressing modes, and architecture.
7.2 Features
Features of the CPU include:
• Object code fully upward-compatible with M68HC05 Family
• 16-bit stack pointer with stack manipulation instructions
• 16-bit index register with x-register manipulation instructions
• 8-MHz CPU internal bus frequency
• 64-Kbyte program/data memory space
• 16 addressing modes
• Memory-to-memory data moves without using accumulator
• Fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions
• Enhanced binary-coded decimal (BCD) data handling
• Modular architecture with expandable internal bus definition for extension of addressing range
beyond 64 Kbytes
• Low-power stop and wait modes
7.3 CPU Registers
Figure 7-1 shows the five CPU registers. CPU registers are not part of the memory map.
MC68HC908QY/QT Family Data Sheet, Rev. 4
Freescale Semiconductor
63
Central Processor Unit (CPU)
0
7
ACCUMULATOR (A)
0
15
H
X
INDEX REGISTER (H:X)
15
0
STACK POINTER (SP)
15
0
PROGRAM COUNTER (PC)
7
0
V 1 1 H I N Z C
CONDITION CODE REGISTER (CCR)
CARRY/BORROW FLAG
ZERO FLAG
NEGATIVE FLAG
INTERRUPT MASK
HALF-CARRY FLAG
TWO’S COMPLEMENT OVERFLOW FLAG
Figure 7-1. CPU Registers
7.3.1 Accumulator
The accumulator is a general-purpose 8-bit register. The CPU uses the accumulator to hold operands and
the results of arithmetic/logic operations.
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
Unaffected by reset
Figure 7-2. Accumulator (A)
7.3.2 Index Register
The 16-bit index register allows indexed addressing of a 64-Kbyte memory space. H is the upper byte of
the index register, and X is the lower byte. H:X is the concatenated 16-bit index register.
In the indexed addressing modes, the CPU uses the contents of the index register to determine the
conditional address of the operand.
The index register can serve also as a temporary data storage location.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Bit
0
0
0
0
0
0
0
0
0
X
X
X
X
X
X
X
X
Read:
Write:
Reset:
X = Indeterminate
Figure 7-3. Index Register (H:X)
MC68HC908QY/QT Family Data Sheet, Rev. 4
64
Freescale Semiconductor
CPU Registers
7.3.3 Stack Pointer
The stack pointer is a 16-bit register that contains the address of the next location on the stack. During a
reset, the stack pointer is preset to $00FF. The reset stack pointer (RSP) instruction sets the least
significant byte to $FF and does not affect the most significant byte. The stack pointer decrements as data
is pushed onto the stack and increments as data is pulled from the stack.
In the stack pointer 8-bit offset and 16-bit offset addressing modes, the stack pointer can function as an
index register to access data on the stack. The CPU uses the contents of the stack pointer to determine
the conditional address of the operand.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Bit
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Read:
Write:
Reset:
Figure 7-4. Stack Pointer (SP)
NOTE
The location of the stack is arbitrary and may be relocated anywhere in
random-access memory (RAM). Moving the SP out of page 0 ($0000 to
$00FF) frees direct address (page 0) space. For correct operation, the
stack pointer must point only to RAM locations.
7.3.4 Program Counter
The program counter is a 16-bit register that contains the address of the next instruction or operand to be
fetched.
Normally, the program counter automatically increments to the next sequential memory location every
time an instruction or operand is fetched. Jump, branch, and interrupt operations load the program
counter with an address other than that of the next sequential location.
During reset, the program counter is loaded with the reset vector address located at $FFFE and $FFFF.
The vector address is the address of the first instruction to be executed after exiting the reset state.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Bit
0
Read:
Write:
Reset:
Loaded with vector from $FFFE and $FFFF
Figure 7-5. Program Counter (PC)
MC68HC908QY/QT Family Data Sheet, Rev. 4
Freescale Semiconductor
65
Central Processor Unit (CPU)
7.3.5 Condition Code Register
The 8-bit condition code register contains the interrupt mask and five flags that indicate the results of the
instruction just executed. Bits 6 and 5 are set permanently to 1. The following paragraphs describe the
functions of the condition code register.
Read:
Write:
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
V
1
1
H
I
N
Z
C
X
1
1
X
1
X
X
X
X = Indeterminate
Figure 7-6. Condition Code Register (CCR)
V — Overflow Flag
The CPU sets the overflow flag when a two's complement overflow occurs. The signed branch
instructions BGT, BGE, BLE, and BLT use the overflow flag.
1 = Overflow
0 = No overflow
H — Half-Carry Flag
The CPU sets the half-carry flag when a carry occurs between accumulator bits 3 and 4 during an
add-without-carry (ADD) or add-with-carry (ADC) operation. The half-carry flag is required for
binary-coded decimal (BCD) arithmetic operations. The DAA instruction uses the states of the H and
C flags to determine the appropriate correction factor.
1 = Carry between bits 3 and 4
0 = No carry between bits 3 and 4
I — Interrupt Mask
When the interrupt mask is set, all maskable CPU interrupts are disabled. CPU interrupts are enabled
when the interrupt mask is cleared. When a CPU interrupt occurs, the interrupt mask is set
automatically after the CPU registers are saved on the stack, but before the interrupt vector is fetched.
1 = Interrupts disabled
0 = Interrupts enabled
NOTE
To maintain M6805 Family compatibility, the upper byte of the index
register (H) is not stacked automatically. If the interrupt service routine
modifies H, then the user must stack and unstack H using the PSHH and
PULH instructions.
After the I bit is cleared, the highest-priority interrupt request is serviced first.
A return-from-interrupt (RTI) instruction pulls the CPU registers from the stack and restores the
interrupt mask from the stack. After any reset, the interrupt mask is set and can be cleared only by the
clear interrupt mask software instruction (CLI).
N — Negative Flag
The CPU sets the negative flag when an arithmetic operation, logic operation, or data manipulation
produces a negative result, setting bit 7 of the result.
1 = Negative result
0 = Non-negative result
MC68HC908QY/QT Family Data Sheet, Rev. 4
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Freescale Semiconductor
Arithmetic/Logic Unit (ALU)
Z — Zero Flag
The CPU sets the zero flag when an arithmetic operation, logic operation, or data manipulation
produces a result of $00.
1 = Zero result
0 = Non-zero result
C — Carry/Borrow Flag
The CPU sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the
accumulator or when a subtraction operation requires a borrow. Some instructions — such as bit test
and branch, shift, and rotate — also clear or set the carry/borrow flag.
1 = Carry out of bit 7
0 = No carry out of bit 7
7.4 Arithmetic/Logic Unit (ALU)
The ALU performs the arithmetic and logic operations defined by the instruction set.
Refer to the CPU08 Reference Manual (document order number CPU08RM/AD) for a description of the
instructions and addressing modes and more detail about the architecture of the CPU.
7.5 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption standby modes.
7.5.1 Wait Mode
The WAIT instruction:
• Clears the interrupt mask (I bit) in the condition code register, enabling interrupts. After exit from
wait mode by interrupt, the I bit remains clear. After exit by reset, the I bit is set.
• Disables the CPU clock
7.5.2 Stop Mode
The STOP instruction:
• Clears the interrupt mask (I bit) in the condition code register, enabling external interrupts. After
exit from stop mode by external interrupt, the I bit remains clear. After exit by reset, the I bit is set.
• Disables the CPU clock
After exiting stop mode, the CPU clock begins running after the oscillator stabilization delay.
7.6 CPU During Break Interrupts
If a break module is present on the MCU, the CPU starts a break interrupt by:
• Loading the instruction register with the SWI instruction
• Loading the program counter with $FFFC:$FFFD or with $FEFC:$FEFD in monitor mode
The break interrupt begins after completion of the CPU instruction in progress. If the break address
register match occurs on the last cycle of a CPU instruction, the break interrupt begins immediately.
A return-from-interrupt instruction (RTI) in the break routine ends the break interrupt and returns the MCU
to normal operation if the break interrupt has been deasserted.
MC68HC908QY/QT Family Data Sheet, Rev. 4
Freescale Semiconductor
67
Central Processor Unit (CPU)
7.7 Instruction Set Summary
Table 7-1 provides a summary of the M68HC08 instruction set.
ADC #opr
ADC opr
ADC opr
ADC opr,X
ADC opr,X
ADC ,X
ADC opr,SP
ADC opr,SP
ADD #opr
ADD opr
ADD opr
ADD opr,X
ADD opr,X
ADD ,X
ADD opr,SP
ADD opr,SP
V H I N Z C
A ← (A) + (M) + (C)
Add with Carry
A ← (A) + (M)
Add without Carry
IMM
DIR
EXT
IX2
– IX1
IX
SP1
SP2
A9
B9
C9
D9
E9
F9
9EE9
9ED9
ii
dd
hh ll
ee ff
ff
IMM
DIR
EXT
– IX2
IX1
IX
SP1
SP2
AB
BB
CB
DB
EB
FB
9EEB
9EDB
ii
dd
hh ll
ee ff
ff
ff
ee ff
ff
ee ff
Cycles
Effect
on CCR
Description
Operand
Operation
Opcode
Source
Form
Address
Mode
Table 7-1. Instruction Set Summary (Sheet 1 of 6)
2
3
4
4
3
2
4
5
2
3
4
4
3
2
4
5
AIS #opr
Add Immediate Value (Signed) to SP
SP ← (SP) + (16 « M)
– – – – – – IMM
A7
ii
2
AIX #opr
Add Immediate Value (Signed) to H:X
H:X ← (H:X) + (16 « M)
– – – – – – IMM
AF
ii
2
A ← (A) & (M)
IMM
DIR
EXT
IX2
0 – – – IX1
IX
SP1
SP2
A4
B4
C4
D4
E4
F4
9EE4
9ED4
ii
dd
hh ll
ee ff
ff
2
3
4
4
3
2
4
5
0
DIR
INH
INH
– – IX1
IX
SP1
38 dd
48
58
68 ff
78
9E68 ff
4
1
1
4
3
5
C
DIR
INH
– – INH
IX1
IX
SP1
37 dd
47
57
67 ff
77
9E67 ff
4
1
1
4
3
5
AND #opr
AND opr
AND opr
AND opr,X
AND opr,X
AND ,X
AND opr,SP
AND opr,SP
ASL opr
ASLA
ASLX
ASL opr,X
ASL ,X
ASL opr,SP
Logical AND
Arithmetic Shift Left
(Same as LSL)
C
b7
ASR opr
ASRA
ASRX
ASR opr,X
ASR opr,X
ASR opr,SP
Arithmetic Shift Right
BCC rel
Branch if Carry Bit Clear
b0
b7
BCLR n, opr
Clear Bit n in M
b0
PC ← (PC) + 2 + rel ? (C) = 0
Mn ← 0
ff
ee ff
– – – – – – REL
24
rr
3
DIR (b0)
DIR (b1)
DIR (b2)
– – – – – – DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
11
13
15
17
19
1B
1D
1F
dd
dd
dd
dd
dd
dd
dd
dd
4
4
4
4
4
4
4
4
BCS rel
Branch if Carry Bit Set (Same as BLO)
PC ← (PC) + 2 + rel ? (C) = 1
– – – – – – REL
25
rr
3
BEQ rel
Branch if Equal
PC ← (PC) + 2 + rel ? (Z) = 1
– – – – – – REL
27
rr
3
BGE opr
Branch if Greater Than or Equal To
(Signed Operands)
PC ← (PC) + 2 + rel ? (N ⊕ V) = 0
– – – – – – REL
90
rr
3
BGT opr
Branch if Greater Than (Signed
Operands)
PC ← (PC) + 2 + rel ? (Z) | (N ⊕ V) = 0 – – – – – – REL
92
rr
3
BHCC rel
Branch if Half Carry Bit Clear
PC ← (PC) + 2 + rel ? (H) = 0
– – – – – – REL
28
rr
BHCS rel
Branch if Half Carry Bit Set
PC ← (PC) + 2 + rel ? (H) = 1
– – – – – – REL
29
rr
BHI rel
Branch if Higher
PC ← (PC) + 2 + rel ? (C) | (Z) = 0
– – – – – – REL
22
rr
3
3
3
MC68HC908QY/QT Family Data Sheet, Rev. 4
68
Freescale Semiconductor
Instruction Set Summary
V H I N Z C
Cycles
Effect
on CCR
Description
Operand
Operation
Opcode
Source
Form
Address
Mode
Table 7-1. Instruction Set Summary (Sheet 2 of 6)
BHS rel
Branch if Higher or Same
(Same as BCC)
PC ← (PC) + 2 + rel ? (C) = 0
– – – – – – REL
BIH rel
Branch if IRQ Pin High
PC ← (PC) + 2 + rel ? IRQ = 1
– – – – – – REL
2F
rr
3
BIL rel
Branch if IRQ Pin Low
PC ← (PC) + 2 + rel ? IRQ = 0
– – – – – – REL
2E
rr
3
(A) & (M)
IMM
DIR
EXT
0 – – – IX2
IX1
IX
SP1
SP2
A5
B5
C5
D5
E5
F5
9EE5
9ED5
ii
dd
hh ll
ee ff
ff
ff
ee ff
2
3
4
4
3
2
4
5
rr
3
BIT #opr
BIT opr
BIT opr
BIT opr,X
BIT opr,X
BIT ,X
BIT opr,SP
BIT opr,SP
Bit Test
BLE opr
Branch if Less Than or Equal To
(Signed Operands)
PC ← (PC) + 2 + rel ? (Z) | (N ⊕ V) = 1 – – – – – – REL
24
93
rr
3
BLO rel
Branch if Lower (Same as BCS)
PC ← (PC) + 2 + rel ? (C) = 1
– – – – – – REL
25
rr
3
BLS rel
Branch if Lower or Same
PC ← (PC) + 2 + rel ? (C) | (Z) = 1
– – – – – – REL
23
rr
3
BLT opr
Branch if Less Than (Signed Operands)
PC ← (PC) + 2 + rel ? (N ⊕ V) =1
– – – – – – REL
91
rr
3
BMC rel
Branch if Interrupt Mask Clear
PC ← (PC) + 2 + rel ? (I) = 0
– – – – – – REL
2C
rr
3
BMI rel
Branch if Minus
PC ← (PC) + 2 + rel ? (N) = 1
– – – – – – REL
2B
rr
3
BMS rel
Branch if Interrupt Mask Set
PC ← (PC) + 2 + rel ? (I) = 1
– – – – – – REL
2D
rr
3
BNE rel
Branch if Not Equal
PC ← (PC) + 2 + rel ? (Z) = 0
– – – – – – REL
26
rr
3
BPL rel
Branch if Plus
PC ← (PC) + 2 + rel ? (N) = 0
– – – – – – REL
2A
rr
3
BRA rel
Branch Always
PC ← (PC) + 2 + rel
– – – – – – REL
20
rr
3
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
– – – – – DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
01
03
05
07
09
0B
0D
0F
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
5
5
5
5
5
5
5
5
– – – – – – REL
21
rr
3
PC ← (PC) + 3 + rel ? (Mn) = 1
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
– – – – – DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
00
02
04
06
08
0A
0C
0E
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
5
5
5
5
5
5
5
5
Mn ← 1
DIR (b0)
DIR (b1)
DIR (b2)
– – – – – – DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
10
12
14
16
18
1A
1C
1E
dd
dd
dd
dd
dd
dd
dd
dd
4
4
4
4
4
4
4
4
PC ← (PC) + 2; push (PCL)
SP ← (SP) – 1; push (PCH)
SP ← (SP) – 1
PC ← (PC) + rel
– – – – – – REL
AD
rr
4
PC ← (PC) + 3 + rel ? (A) – (M) = $00
PC ← (PC) + 3 + rel ? (A) – (M) = $00
PC ← (PC) + 3 + rel ? (X) – (M) = $00
PC ← (PC) + 3 + rel ? (A) – (M) = $00
PC ← (PC) + 2 + rel ? (A) – (M) = $00
PC ← (PC) + 4 + rel ? (A) – (M) = $00
DIR
IMM
– – – – – – IMM
IX1+
IX+
SP1
31
41
51
61
71
9E61
dd rr
ii rr
ii rr
ff rr
rr
ff rr
5
4
4
5
4
6
PC ← (PC) + 3 + rel ? (Mn) = 0
BRCLR n,opr,rel Branch if Bit n in M Clear
BRN rel
PC ← (PC) + 2
Branch Never
BRSET n,opr,rel Branch if Bit n in M Set
BSET n,opr
Set Bit n in M
BSR rel
Branch to Subroutine
CBEQ opr,rel
CBEQA #opr,rel
CBEQX #opr,rel Compare and Branch if Equal
CBEQ opr,X+,rel
CBEQ X+,rel
CBEQ opr,SP,rel
CLC
Clear Carry Bit
C←0
– – – – – 0 INH
98
1
CLI
Clear Interrupt Mask
I←0
– – 0 – – – INH
9A
2
MC68HC908QY/QT Family Data Sheet, Rev. 4
Freescale Semiconductor
69
Central Processor Unit (CPU)
CLR opr
CLRA
CLRX
CLRH
CLR opr,X
CLR ,X
CLR opr,SP
CMP #opr
CMP opr
CMP opr
CMP opr,X
CMP opr,X
CMP ,X
CMP opr,SP
CMP opr,SP
Clear
Compare A with M
Complement (One’s Complement)
CPHX #opr
CPHX opr
Compare H:X with M
CPX #opr
CPX opr
CPX opr
CPX ,X
CPX opr,X
CPX opr,X
CPX opr,SP
CPX opr,SP
Compare X with M
DAA
Decimal Adjust A
Decrement
DIV
Divide
INC opr
INCA
INCX
INC opr,X
INC ,X
INC opr,SP
Exclusive OR M with A
Increment
DIR
INH
INH
0 – – 0 1 – INH
IX1
IX
SP1
3F dd
4F
5F
8C
6F ff
7F
9E6F ff
(A) – (M)
IMM
DIR
EXT
IX2
– – IX1
IX
SP1
SP2
A1
B1
C1
D1
E1
F1
9EE1
9ED1
DIR
INH
INH
0 – – 1
IX1
IX
SP1
33 dd
43
53
63 ff
73
9E63 ff
M ← (M) = $FF – (M)
A ← (A) = $FF – (M)
X ← (X) = $FF – (M)
M ← (M) = $FF – (M)
M ← (M) = $FF – (M)
M ← (M) = $FF – (M)
(H:X) – (M:M + 1)
(X) – (M)
(A)10
DBNZ opr,rel
DBNZA rel
DBNZX rel
Decrement and Branch if Not Zero
DBNZ opr,X,rel
DBNZ X,rel
DBNZ opr,SP,rel
DEC opr
DECA
DECX
DEC opr,X
DEC ,X
DEC opr,SP
M ← $00
A ← $00
X ← $00
H ← $00
M ← $00
M ← $00
M ← $00
ff
ee ff
2
3
4
4
3
2
4
5
4
1
1
4
3
5
ii ii+1
dd
3
4
IMM
DIR
EXT
IX2
– – IX1
IX
SP1
SP2
A3
B3
C3
D3
E3
F3
9EE3
9ED3
ii
dd
hh ll
ee ff
ff
2
3
4
4
3
2
4
5
U – – INH
72
A ← (A) – 1 or M ← (M) – 1 or X ← (X) – 1
PC ← (PC) + 3 + rel ? (result) ≠ 0
DIR
PC ← (PC) + 2 + rel ? (result) ≠ 0
INH
PC ← (PC) + 2 + rel ? (result) ≠ 0
– – – – – – INH
PC ← (PC) + 3 + rel ? (result) ≠ 0
IX1
PC ← (PC) + 2 + rel ? (result) ≠ 0
IX
PC ← (PC) + 4 + rel ? (result) ≠ 0
SP1
3B
4B
5B
6B
7B
9E6B
ff
ee ff
2
dd rr
rr
rr
ff rr
rr
ff rr
M ← (M) – 1
A ← (A) – 1
X ← (X) – 1
M ← (M) – 1
M ← (M) – 1
M ← (M) – 1
DIR
INH
INH
– – –
IX1
IX
SP1
A ← (H:A)/(X)
H ← Remainder
– – – – INH
52
A ← (A ⊕ M)
IMM
DIR
EXT
0 – – – IX2
IX1
IX
SP1
SP2
A8
B8
C8
D8
E8
F8
9EE8
9ED8
DIR
INH
– – – INH
IX1
IX
SP1
3C dd
4C
5C
6C ff
7C
9E6C ff
M ← (M) + 1
A ← (A) + 1
X ← (X) + 1
M ← (M) + 1
M ← (M) + 1
M ← (M) + 1
3
1
1
1
3
2
4
65
75
– – IMM
DIR
ii
dd
hh ll
ee ff
ff
Cycles
V H I N Z C
COM opr
COMA
COMX
COM opr,X
COM ,X
COM opr,SP
EOR #opr
EOR opr
EOR opr
EOR opr,X
EOR opr,X
EOR ,X
EOR opr,SP
EOR opr,SP
Effect
on CCR
Description
Operand
Operation
Opcode
Source
Form
Address
Mode
Table 7-1. Instruction Set Summary (Sheet 3 of 6)
3A dd
4A
5A
6A ff
7A
9E6A ff
5
3
3
5
4
6
4
1
1
4
3
5
7
ii
dd
hh ll
ee ff
ff
ff
ee ff
2
3
4
4
3
2
4
5
4
1
1
4
3
5
MC68HC908QY/QT Family Data Sheet, Rev. 4
70
Freescale Semiconductor
Instruction Set Summary
JSR opr
JSR opr
JSR opr,X
JSR opr,X
JSR ,X
Jump to Subroutine
LDHX #opr
LDHX opr
Load H:X from M
2
3
4
3
2
PC ← (PC) + n (n = 1, 2, or 3)
Push (PCL); SP ← (SP) – 1
Push (PCH); SP ← (SP) – 1
PC ← Unconditional Address
DIR
EXT
– – – – – – IX2
IX1
IX
BD
CD
DD
ED
FD
dd
hh ll
ee ff
ff
4
5
6
5
4
A ← (M)
IMM
DIR
EXT
IX2
0 – – – IX1
IX
SP1
SP2
A6
B6
C6
D6
E6
F6
9EE6
9ED6
ii
dd
hh ll
ee ff
ff
ff
ee ff
2
3
4
4
3
2
4
5
ii jj
dd
3
4
ii
dd
hh ll
ee ff
ff
2
3
4
4
3
2
4
5
H:X ← (M:M + 1)
MOV opr,opr
MOV opr,X+
MOV #opr,opr
MOV X+,opr
Move
MUL
Unsigned multiply
C
b7
b7
0
DIR
INH
INH
– – IX1
IX
SP1
38 dd
48
58
68 ff
78
9E68 ff
4
1
1
4
3
5
C
DIR
INH
– – 0 INH
IX1
IX
SP1
34 dd
44
54
64 ff
74
9E64 ff
4
1
1
4
3
5
b0
H:X ← (H:X) + 1 (IX+D, DIX+)
DD
DIX+
0 – – – IMD
IX+D
X:A ← (X) × (A)
– 0 – – – 0 INH
M ← –(M) = $00 – (M)
A ← –(A) = $00 – (A)
X ← –(X) = $00 – (X)
M ← –(M) = $00 – (M)
M ← –(M) = $00 – (M)
DIR
INH
INH
– – IX1
IX
SP1
(M)Destination ← (M)Source
Negate (Two’s Complement)
45
55
AE
BE
CE
DE
EE
FE
9EEE
9EDE
b0
0
IMM
DIR
IMM
DIR
EXT
IX2
0 – – – IX1
IX
SP1
SP2
X ← (M)
Logical Shift Left
(Same as ASL)
Logical Shift Right
0 – – –
4E
5E
6E
7E
dd dd
dd
ii dd
dd
42
No Operation
None
– – – – – – INH
9D
NSA
Nibble Swap A
A ← (A[3:0]:A[7:4])
– – – – – – INH
62
A ← (A) | (M)
IMM
DIR
EXT
IX2
0 – – –
IX1
IX
SP1
SP2
AA
BA
CA
DA
EA
FA
9EEA
9EDA
Inclusive OR A and M
ff
ee ff
5
4
4
4
5
30 dd
40
50
60 ff
70
9E60 ff
NOP
ORA #opr
ORA opr
ORA opr
ORA opr,X
ORA opr,X
ORA ,X
ORA opr,SP
ORA opr,SP
Cycles
dd
hh ll
ee ff
ff
Load X from M
LSR opr
LSRA
LSRX
LSR opr,X
LSR ,X
LSR opr,SP
NEG opr
NEGA
NEGX
NEG opr,X
NEG ,X
NEG opr,SP
BC
CC
DC
EC
FC
Jump
Load A from M
LSL opr
LSLA
LSLX
LSL opr,X
LSL ,X
LSL opr,SP
PC ← Jump Address
DIR
EXT
– – – – – – IX2
IX1
IX
Effect
on CCR
Description
V H I N Z C
LDA #opr
LDA opr
LDA opr
LDA opr,X
LDA opr,X
LDA ,X
LDA opr,SP
LDA opr,SP
LDX #opr
LDX opr
LDX opr
LDX opr,X
LDX opr,X
LDX ,X
LDX opr,SP
LDX opr,SP
Operand
JMP opr
JMP opr
JMP opr,X
JMP opr,X
JMP ,X
Operation
Address
Mode
Source
Form
Opcode
Table 7-1. Instruction Set Summary (Sheet 4 of 6)
4
1
1
4
3
5
1
3
ii
dd
hh ll
ee ff
ff
ff
ee ff
2
3
4
4
3
2
4
5
PSHA
Push A onto Stack
Push (A); SP ← (SP) – 1
– – – – – – INH
87
2
PSHH
Push H onto Stack
Push (H); SP ← (SP) – 1
– – – – – – INH
8B
2
PSHX
Push X onto Stack
Push (X); SP ← (SP) – 1
– – – – – – INH
89
2
MC68HC908QY/QT Family Data Sheet, Rev. 4
Freescale Semiconductor
71
Central Processor Unit (CPU)
V H I N Z C
Cycles
Effect
on CCR
Description
Operand
Operation
Opcode
Source
Form
Address
Mode
Table 7-1. Instruction Set Summary (Sheet 5 of 6)
PULA
Pull A from Stack
SP ← (SP + 1); Pull (A)
– – – – – – INH
86
2
PULH
Pull H from Stack
SP ← (SP + 1); Pull (H)
– – – – – – INH
8A
2
PULX
Pull X from Stack
SP ← (SP + 1); Pull (X)
– – – – – – INH
C
DIR
INH
INH
– – IX1
IX
SP1
39 dd
49
59
69 ff
79
9E69 ff
4
1
1
4
3
5
DIR
INH
– – INH
IX1
IX
SP1
36 dd
46
56
66 ff
76
9E66 ff
4
1
1
4
3
5
ROL opr
ROLA
ROLX
ROL opr,X
ROL ,X
ROL opr,SP
Rotate Left through Carry
b7
b0
88
2
ROR opr
RORA
RORX
ROR opr,X
ROR ,X
ROR opr,SP
Rotate Right through Carry
RSP
Reset Stack Pointer
SP ← $FF
– – – – – – INH
9C
1
RTI
Return from Interrupt
SP ← (SP) + 1; Pull (CCR)
SP ← (SP) + 1; Pull (A)
SP ← (SP) + 1; Pull (X)
SP ← (SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCL)
INH
80
7
RTS
Return from Subroutine
SP ← SP + 1; Pull (PCH)
SP ← SP + 1; Pull (PCL)
– – – – – – INH
81
4
A ← (A) – (M) – (C)
IMM
DIR
EXT
– – IX2
IX1
IX
SP1
SP2
A2
B2
C2
D2
E2
F2
9EE2
9ED2
SBC #opr
SBC opr
SBC opr
SBC opr,X
SBC opr,X
SBC ,X
SBC opr,SP
SBC opr,SP
C
b7
Subtract with Carry
b0
ii
dd
hh ll
ee ff
ff
ff
ee ff
2
3
4
4
3
2
4
5
SEC
Set Carry Bit
C←1
– – – – – 1 INH
99
1
SEI
Set Interrupt Mask
I←1
– – 1 – – – INH
9B
2
M ← (A)
DIR
EXT
IX2
0 – – – IX1
IX
SP1
SP2
B7
C7
D7
E7
F7
9EE7
9ED7
(M:M + 1) ← (H:X)
0 – – – DIR
35
I ← 0; Stop Processing
– – 0 – – – INH
8E
M ← (X)
DIR
EXT
IX2
0 – – – IX1
IX
SP1
SP2
BF
CF
DF
EF
FF
9EEF
9EDF
dd
hh ll
ee ff
ff
IMM
DIR
EXT
– – IX2
IX1
IX
SP1
SP2
A0
B0
C0
D0
E0
F0
9EE0
9ED0
ii
dd
hh ll
ee ff
ff
STA opr
STA opr
STA opr,X
STA opr,X
STA ,X
STA opr,SP
STA opr,SP
Store A in M
STHX opr
Store H:X in M
STOP
Enable Interrupts, Stop Processing,
Refer to MCU Documentation
STX opr
STX opr
STX opr,X
STX opr,X
STX ,X
STX opr,SP
STX opr,SP
SUB #opr
SUB opr
SUB opr
SUB opr,X
SUB opr,X
SUB ,X
SUB opr,SP
SUB opr,SP
Store X in M
Subtract
A ← (A) – (M)
dd
hh ll
ee ff
ff
ff
ee ff
3
4
4
3
2
4
5
dd
4
1
ff
ee ff
ff
ee ff
3
4
4
3
2
4
5
2
3
4
4
3
2
4
5
MC68HC908QY/QT Family Data Sheet, Rev. 4
72
Freescale Semiconductor
Opcode Map
V H I N Z C
Cycles
Effect
on CCR
Description
Operand
Operation
Opcode
Source
Form
Address
Mode
Table 7-1. Instruction Set Summary (Sheet 6 of 6)
SWI
Software Interrupt
PC ← (PC) + 1; Push (PCL)
SP ← (SP) – 1; Push (PCH)
SP ← (SP) – 1; Push (X)
SP ← (SP) – 1; Push (A)
SP ← (SP) – 1; Push (CCR)
SP ← (SP) – 1; I ← 1
PCH ← Interrupt Vector High Byte
PCL ← Interrupt Vector Low Byte
CCR ← (A)
INH
84
2
X ← (A)
– – – – – – INH
97
1
A ← (CCR)
– – – – – – INH
(A) – $00 or (X) – $00 or (M) – $00
DIR
INH
INH
0 – – –
IX1
IX
SP1
TAP
Transfer A to CCR
TAX
Transfer A to X
TPA
Transfer CCR to A
TST opr
TSTA
TSTX
TST opr,X
TST ,X
TST opr,SP
Test for Negative or Zero
TSX
Transfer SP to H:X
TXA
Transfer X to A
TXS
Transfer H:X to SP
WAIT
A
C
CCR
dd
dd rr
DD
DIR
DIX+
ee ff
EXT
ff
H
H
hh ll
I
ii
IMD
IMM
INH
IX
IX+
IX+D
IX1
IX1+
IX2
M
N
Enable Interrupts; Wait for Interrupt
– – 1 – – – INH
83
85
3D dd
4D
5D
6D ff
7D
9E6D ff
9
1
3
1
1
3
2
4
H:X ← (SP) + 1
– – – – – – INH
95
2
A ← (X)
– – – – – – INH
9F
1
(SP) ← (H:X) – 1
– – – – – – INH
94
2
I bit ← 0; Inhibit CPU clocking
until interrupted
– – 0 – – – INH
8F
1
Accumulator
Carry/borrow bit
Condition code register
Direct address of operand
Direct address of operand and relative offset of branch instruction
Direct to direct addressing mode
Direct addressing mode
Direct to indexed with post increment addressing mode
High and low bytes of offset in indexed, 16-bit offset addressing
Extended addressing mode
Offset byte in indexed, 8-bit offset addressing
Half-carry bit
Index register high byte
High and low bytes of operand address in extended addressing
Interrupt mask
Immediate operand byte
Immediate source to direct destination addressing mode
Immediate addressing mode
Inherent addressing mode
Indexed, no offset addressing mode
Indexed, no offset, post increment addressing mode
Indexed with post increment to direct addressing mode
Indexed, 8-bit offset addressing mode
Indexed, 8-bit offset, post increment addressing mode
Indexed, 16-bit offset addressing mode
Memory location
Negative bit
n
opr
PC
PCH
PCL
REL
rel
rr
SP1
SP2
SP
U
V
X
Z
&
|
⊕
()
–( )
#
«
←
?
:
—
Any bit
Operand (one or two bytes)
Program counter
Program counter high byte
Program counter low byte
Relative addressing mode
Relative program counter offset byte
Relative program counter offset byte
Stack pointer, 8-bit offset addressing mode
Stack pointer 16-bit offset addressing mode
Stack pointer
Undefined
Overflow bit
Index register low byte
Zero bit
Logical AND
Logical OR
Logical EXCLUSIVE OR
Contents of
Negation (two’s complement)
Immediate value
Sign extend
Loaded with
If
Concatenated with
Set or cleared
Not affected
7.8 Opcode Map
See Table 7-2.
MC68HC908QY/QT Family Data Sheet, Rev. 4
Freescale Semiconductor
73
MSB
Branch
REL
DIR
INH
3
4
0
1
2
5
BRSET0
3 DIR
5
BRCLR0
3 DIR
5
BRSET1
3 DIR
5
BRCLR1
3 DIR
5
BRSET2
3 DIR
5
BRCLR2
3 DIR
5
BRSET3
3 DIR
5
BRCLR3
3 DIR
5
BRSET4
3 DIR
5
BRCLR4
3 DIR
5
BRSET5
3 DIR
5
BRCLR5
3 DIR
5
BRSET6
3 DIR
5
BRCLR6
3 DIR
5
BRSET7
3 DIR
5
BRCLR7
3 DIR
4
BSET0
2 DIR
4
BCLR0
2 DIR
4
BSET1
2 DIR
4
BCLR1
2 DIR
4
BSET2
2 DIR
4
BCLR2
2 DIR
4
BSET3
2 DIR
4
BCLR3
2 DIR
4
BSET4
2 DIR
4
BCLR4
2 DIR
4
BSET5
2 DIR
4
BCLR5
2 DIR
4
BSET6
2 DIR
4
BCLR6
2 DIR
4
BSET7
2 DIR
4
BCLR7
2 DIR
3
BRA
2 REL
3
BRN
2 REL
3
BHI
2 REL
3
BLS
2 REL
3
BCC
2 REL
3
BCS
2 REL
3
BNE
2 REL
3
BEQ
2 REL
3
BHCC
2 REL
3
BHCS
2 REL
3
BPL
2 REL
3
BMI
2 REL
3
BMC
2 REL
3
BMS
2 REL
3
BIL
2 REL
3
BIH
2 REL
Read-Modify-Write
INH
IX1
5
6
1
NEGX
1 INH
4
CBEQX
3 IMM
7
DIV
1 INH
1
COMX
1 INH
1
LSRX
1 INH
4
LDHX
2 DIR
1
RORX
1 INH
1
ASRX
1 INH
1
LSLX
1 INH
1
ROLX
1 INH
1
DECX
1 INH
3
DBNZX
2 INH
1
INCX
1 INH
1
TSTX
1 INH
4
MOV
2 DIX+
1
CLRX
1 INH
4
NEG
2
IX1
5
CBEQ
3 IX1+
3
NSA
1 INH
4
COM
2 IX1
4
LSR
2 IX1
3
CPHX
3 IMM
4
ROR
2 IX1
4
ASR
2 IX1
4
LSL
2 IX1
4
ROL
2 IX1
4
DEC
2 IX1
5
DBNZ
3 IX1
4
INC
2 IX1
3
TST
2 IX1
4
MOV
3 IMD
3
CLR
2 IX1
SP1
IX
9E6
7
Control
INH
INH
8
9
Register/Memory
IX2
SP2
IMM
DIR
EXT
A
B
C
D
9ED
4
SUB
3 EXT
4
CMP
3 EXT
4
SBC
3 EXT
4
CPX
3 EXT
4
AND
3 EXT
4
BIT
3 EXT
4
LDA
3 EXT
4
STA
3 EXT
4
EOR
3 EXT
4
ADC
3 EXT
4
ORA
3 EXT
4
ADD
3 EXT
3
JMP
3 EXT
5
JSR
3 EXT
4
LDX
3 EXT
4
STX
3 EXT
4
SUB
3 IX2
4
CMP
3 IX2
4
SBC
3 IX2
4
CPX
3 IX2
4
AND
3 IX2
4
BIT
3 IX2
4
LDA
3 IX2
4
STA
3 IX2
4
EOR
3 IX2
4
ADC
3 IX2
4
ORA
3 IX2
4
ADD
3 IX2
4
JMP
3 IX2
6
JSR
3 IX2
4
LDX
3 IX2
4
STX
3 IX2
5
SUB
4 SP2
5
CMP
4 SP2
5
SBC
4 SP2
5
CPX
4 SP2
5
AND
4 SP2
5
BIT
4 SP2
5
LDA
4 SP2
5
STA
4 SP2
5
EOR
4 SP2
5
ADC
4 SP2
5
ORA
4 SP2
5
ADD
4 SP2
IX1
SP1
IX
E
9EE
F
LSB
0
1
2
3
MC68HC908QY/QT Family Data Sheet, Rev. 4
4
5
6
7
8
9
A
B
C
D
E
Freescale Semiconductor
F
4
1
NEG
NEGA
2 DIR 1 INH
5
4
CBEQ CBEQA
3 DIR 3 IMM
5
MUL
1 INH
4
1
COM
COMA
2 DIR 1 INH
4
1
LSR
LSRA
2 DIR 1 INH
4
3
STHX
LDHX
2 DIR 3 IMM
4
1
ROR
RORA
2 DIR 1 INH
4
1
ASR
ASRA
2 DIR 1 INH
4
1
LSL
LSLA
2 DIR 1 INH
4
1
ROL
ROLA
2 DIR 1 INH
4
1
DEC
DECA
2 DIR 1 INH
5
3
DBNZ DBNZA
3 DIR 2 INH
4
1
INC
INCA
2 DIR 1 INH
3
1
TST
TSTA
2 DIR 1 INH
5
MOV
3 DD
3
1
CLR
CLRA
2 DIR 1 INH
INH Inherent
REL Relative
IMM Immediate
IX
Indexed, No Offset
DIR Direct
IX1 Indexed, 8-Bit Offset
EXT Extended
IX2 Indexed, 16-Bit Offset
DD Direct-Direct
IMD Immediate-Direct
IX+D Indexed-Direct DIX+ Direct-Indexed
*Pre-byte for stack pointer indexed instructions
5
3
NEG
NEG
3 SP1 1 IX
6
4
CBEQ
CBEQ
4 SP1 2 IX+
2
DAA
1 INH
5
3
COM
COM
3 SP1 1 IX
5
3
LSR
LSR
3 SP1 1 IX
4
CPHX
2 DIR
5
3
ROR
ROR
3 SP1 1 IX
5
3
ASR
ASR
3 SP1 1 IX
5
3
LSL
LSL
3 SP1 1 IX
5
3
ROL
ROL
3 SP1 1 IX
5
3
DEC
DEC
3 SP1 1 IX
6
4
DBNZ
DBNZ
4 SP1 2 IX
5
3
INC
INC
3 SP1 1 IX
4
2
TST
TST
3 SP1 1 IX
4
MOV
2 IX+D
4
2
CLR
CLR
3 SP1 1 IX
SP1 Stack Pointer, 8-Bit Offset
SP2 Stack Pointer, 16-Bit Offset
IX+ Indexed, No Offset with
Post Increment
IX1+ Indexed, 1-Byte Offset with
Post Increment
7
3
RTI
BGE
1 INH 2 REL
4
3
RTS
BLT
1 INH 2 REL
3
BGT
2 REL
9
3
SWI
BLE
1 INH 2 REL
2
2
TAP
TXS
1 INH 1 INH
1
2
TPA
TSX
1 INH 1 INH
2
PULA
1 INH
2
1
PSHA
TAX
1 INH 1 INH
2
1
PULX
CLC
1 INH 1 INH
2
1
PSHX
SEC
1 INH 1 INH
2
2
PULH
CLI
1 INH 1 INH
2
2
PSHH
SEI
1 INH 1 INH
1
1
CLRH
RSP
1 INH 1 INH
1
NOP
1 INH
1
STOP
*
1 INH
1
1
WAIT
TXA
1 INH 1 INH
2
SUB
2 IMM
2
CMP
2 IMM
2
SBC
2 IMM
2
CPX
2 IMM
2
AND
2 IMM
2
BIT
2 IMM
2
LDA
2 IMM
2
AIS
2 IMM
2
EOR
2 IMM
2
ADC
2 IMM
2
ORA
2 IMM
2
ADD
2 IMM
3
SUB
2 DIR
3
CMP
2 DIR
3
SBC
2 DIR
3
CPX
2 DIR
3
AND
2 DIR
3
BIT
2 DIR
3
LDA
2 DIR
3
STA
2 DIR
3
EOR
2 DIR
3
ADC
2 DIR
3
ORA
2 DIR
3
ADD
2 DIR
2
JMP
2 DIR
4
4
BSR
JSR
2 REL 2 DIR
2
3
LDX
LDX
2 IMM 2 DIR
2
3
AIX
STX
2 IMM 2 DIR
MSB
0
3
SUB
2 IX1
3
CMP
2 IX1
3
SBC
2 IX1
3
CPX
2 IX1
3
AND
2 IX1
3
BIT
2 IX1
3
LDA
2 IX1
3
STA
2 IX1
3
EOR
2 IX1
3
ADC
2 IX1
3
ORA
2 IX1
3
ADD
2 IX1
3
JMP
2 IX1
5
JSR
2 IX1
5
3
LDX
LDX
4 SP2 2 IX1
5
3
STX
STX
4 SP2 2 IX1
4
SUB
3 SP1
4
CMP
3 SP1
4
SBC
3 SP1
4
CPX
3 SP1
4
AND
3 SP1
4
BIT
3 SP1
4
LDA
3 SP1
4
STA
3 SP1
4
EOR
3 SP1
4
ADC
3 SP1
4
ORA
3 SP1
4
ADD
3 SP1
2
SUB
1 IX
2
CMP
1 IX
2
SBC
1 IX
2
CPX
1 IX
2
AND
1 IX
2
BIT
1 IX
2
LDA
1 IX
2
STA
1 IX
2
EOR
1 IX
2
ADC
1 IX
2
ORA
1 IX
2
ADD
1 IX
2
JMP
1 IX
4
JSR
1 IX
4
2
LDX
LDX
3 SP1 1 IX
4
2
STX
STX
3 SP1 1 IX
High Byte of Opcode in Hexadecimal
LSB
Low Byte of Opcode in Hexadecimal
0
5
Cycles
BRSET0 Opcode Mnemonic
3 DIR Number of Bytes / Addressing Mode
Central Processor Unit (CPU)
74
Table 7-2. Opcode Map
Bit Manipulation
DIR
DIR
Chapter 8
External Interrupt (IRQ)
8.1 Introduction
The IRQ pin (external interrupt), shared with PTA2 (general purpose input) and keyboard interrupt (KBI),
provides a maskable interrupt input
8.2 Features
Features of the IRQ module include the following:
•
•
External interrupt pin, IRQ
IRQ interrupt control bits
•
Hysteresis buffer
•
Programmable edge-only or edge and level interrupt sensitivity
•
•
Automatic interrupt acknowledge
Selectable internal pullup resistor
8.3 Functional Description
IRQ pin functionality is enabled by setting configuration register 2 (CONFIG2) IRQEN bit accordingly. A
zero disables the IRQ function and IRQ will assume the other shared functionalities. A one enables the
IRQ function.
A falling edge on the external interrupt pin can latch a central processor unit (CPU) interrupt request.
Figure 8-2 shows the structure of the IRQ module.
Interrupt signals on the IRQ pin are latched into the IRQ latch. An interrupt latch remains set until one of
the following actions occurs:
•
Vector fetch — A vector fetch automatically generates an interrupt acknowledge signal that clears
the IRQ latch.
•
Software clear — Software can clear the interrupt latch by writing to the acknowledge bit in the
interrupt status and control register (INTSCR). Writing a 1 to the ACK bit clears the IRQ latch.
•
Reset — A reset automatically clears the interrupt latch.
The external interrupt pin is falling-edge-triggered out of reset and is software- configurable to be either
falling-edge or falling-edge and low-level triggered. The MODE bit in the INTSCR controls the triggering
sensitivity of the IRQ pin.
When the interrupt pin is edge-triggered only (MODE = 0), the CPU interrupt request remains set until a
vector fetch, software clear, or reset occurs.
MC68HC908QY/QT Family Data Sheet, Rev. 4
Freescale Semiconductor
75
External Interrupt (IRQ)
PTA0/AD0/TCH0/KBI0
CLOCK
GENERATOR
(OSCILLATOR)
PTA
PTA2/IRQ/KBI2/TCLK
PTA3/RST/KBI3
DDRA
PTA1/AD1/TCH1/KBI1
SYSTEM INTEGRATION
MODULE
PTA4/OSC2/AD2/KBI4
PTA5/OSC1/AD3/KBI5
M68HC08 CPU
SINGLE INTERRUPT
MODULE
BREAK
MODULE
DDRB
PTB
PTB0
PTB1
PTB2
PTB3
PTB4
PTB5
PTB6
PTB7
POWER-ON RESET
MODULE
8-BIT ADC
128 BYTES RAM
MC68HC908QY4 AND MC68HC908QT4
4096 BYTES
MC68HC908QY2, MC68HC908QY1,
MC68HC908QT2, AND MC68HC908QT1:
1536 BYTES
USER FLASH
KEYBOARD INTERRUPT
MODULE
16-BIT TIMER
MODULE
COP
MODULE
VDD
POWER SUPPLY
MONITOR ROM
VSS
RST, IRQ: Pins have internal (about 30K Ohms) pull up
PTA[0:5]: High current sink and source capability
PTA[0:5]: Pins have programmable keyboard interrupt and pull up
PTB[0:7]: Not available on 8-pin devices – MC68HC908QT1, MC68HC908QT2, and MC68HC908QT4
ADC: Not available on the MC68HC908QY1 and MC68HC908QT1
Figure 8-1. Block Diagram Highlighting IRQ Block and Pins
MC68HC908QY/QT Family Data Sheet, Rev. 4
76
Freescale Semiconductor
Functional Description
ACK
INTERNAL ADDRESS BUS
RESET
TO CPU FOR
BIL/BIH
INSTRUCTIONS
VECTOR
FETCH
DECODER
VDD
IRQPUD
INTERNAL
PULLUP
DEVICE
VDD
IRQF
D
CLR
Q
CK
IRQ
SYNCHRONIZER
IRQ
INTERRUPT
REQUEST
HIGH
VOLTAGE
DETECT
TO MODE
SELECT
LOGIC
IRQ
FF
IMASK
MODE
Figure 8-2. IRQ Module Block Diagram
When the interrupt pin is both falling-edge and low-level triggered (MODE = 1), the CPU interrupt request
remains set until both of the following occur:
•
Vector fetch or software clear
•
Return of the interrupt pin to logic 1
The vector fetch or software clear may occur before or after the interrupt pin returns to logic 1. As long as
the pin is low, the interrupt request remains pending. A reset will clear the latch and the MODE control bit,
thereby clearing the interrupt even if the pin stays low.
When set, the IMASK bit in the INTSCR mask all external interrupt requests. A latched interrupt request
is not presented to the interrupt priority logic unless the IMASK bit is clear.
NOTE
The interrupt mask (I) in the condition code register (CCR) masks all
interrupt requests, including external interrupt requests. See
13.6 Exception Control.
Figure 8-3 provides a summary of the IRQ I/O register.
Addr.
Register Name
$001D
IRQ Status and Control Read:
Register (INTSCR) Write:
See page 79. Reset:
Bit 7
6
5
4
3
0
0
0
0
IRQF
2
0
ACK
0
0
0
0
0
0
1
Bit 0
IMASK
MODE
0
0
= Unimplemented
Figure 8-3. IRQ I/O Register Summary
MC68HC908QY/QT Family Data Sheet, Rev. 4
Freescale Semiconductor
77
External Interrupt (IRQ)
8.4 IRQ Pin
A falling edge on the IRQ pin can latch an interrupt request into the IRQ latch. A vector fetch, software
clear, or reset clears the IRQ latch.
If the MODE bit is set, the IRQ pin is both falling-edge sensitive and low-level sensitive. With MODE set,
both of the following actions must occur to clear IRQ:
• Vector fetch or software clear — A vector fetch generates an interrupt acknowledge signal to clear
the latch. Software may generate the interrupt acknowledge signal by writing a 1 to the ACK bit in
the interrupt status and control register (INTSCR). The ACK bit is useful in applications that poll the
IRQ pin and require software to clear the IRQ latch. Writing to the ACK bit prior to leaving an
interrupt service routine can also prevent spurious interrupts due to noise. Setting ACK does not
affect subsequent transitions on the IRQ pin. A falling edge that occurs after writing to the ACK bit
latches another interrupt request. If the IRQ mask bit, IMASK, is clear, the CPU loads the program
counter with the vector address at locations $FFFA and $FFFB.
• Return of the IRQ pin to logic 1 — As long as the IRQ pin is at logic 0, IRQ remains active.
The vector fetch or software clear and the return of the IRQ pin to logic 1 may occur in any order. The
interrupt request remains pending as long as the IRQ pin is at logic 0. A reset will clear the latch and the
MODE control bit, thereby clearing the interrupt even if the pin stays low.
If the MODE bit is clear, the IRQ pin is falling-edge sensitive only. With MODE clear, a vector fetch or
software clear immediately clears the IRQ latch.
The IRQF bit in the INTSCR register can be used to check for pending interrupts. The IRQF bit is not
affected by the IMASK bit, which makes it useful in applications where polling is preferred.
NOTE
When the IRQ function is enabled in the CONFIG2 register, the BIH and BIL instructions can be used to
read the logic level on the IRQ pin. If the IRQ function is disabled, these instructions will behave as if the
IRQ pin is a logic 1, regardless of the actual level on the pin. Conversely, when the IRQ function is
enabled, bit 2 of the port A data register will always read a 0.
NOTE
When using the level-sensitive interrupt trigger, avoid false interrupts by
masking interrupt requests in the interrupt routine. An internal pullup
resistor to VDD is connected to the IRQ pin; this can be disabled by setting
the IRQPUD bit in the CONFIG2 register ($001E).
8.5 IRQ Module During Break Interrupts
The system integration module (SIM) controls whether the IRQ latch can be cleared during the break
state. The BCFE bit in the break flag control register (BFCR) enables software to clear the latches during
the break state. See Chapter 13 System Integration Module (SIM).
To allow software to clear the IRQ latch during a break interrupt, write a 1 to the BCFE bit. If a latch is
cleared during the break state, it remains cleared when the MCU exits the break state.
To protect the latches during the break state, write a 0 to the BCFE bit. With BCFE at 0 (its default state),
writing to the ACK bit in the IRQ status and control register during the break state has no effect on the
IRQ latch.
MC68HC908QY/QT Family Data Sheet, Rev. 4
78
Freescale Semiconductor
IRQ Status and Control Register
8.6 IRQ Status and Control Register
The IRQ status and control register (ISCR) controls and monitors operation of the IRQ module, see
Chapter 5 Configuration Register (CONFIG).
The ISCR has the following functions:
• Shows the state of the IRQ flag
• Clears the IRQ latch
• Masks IRQ and interrupt request
• Controls triggering sensitivity of the IRQ interrupt pin
Address: $001D
Read:
Bit 7
6
5
4
3
0
0
0
0
IRQF
Write:
Reset:
2
0
ACK
0
0
0
0
0
0
1
Bit 0
IMASK
MODE
0
0
= Unimplemented
Figure 8-4. IRQ Status and Control Register (INTSCR)
IRQF — IRQ Flag
This read-only status bit is high when the IRQ interrupt is pending.
1 = IRQ interrupt pending
0 = IRQ interrupt not pending
ACK — IRQ Interrupt Request Acknowledge Bit
Writing a 1 to this write-only bit clears the IRQ latch. ACK always reads as 0. Reset clears ACK.
IMASK — IRQ Interrupt Mask Bit
Writing a 1 to this read/write bit disables IRQ interrupt requests. Reset clears IMASK.
1 = IRQ interrupt requests disabled
0 = IRQ interrupt requests enabled
MODE — IRQ Edge/Level Select Bit
This read/write bit controls the triggering sensitivity of the IRQ pin. Reset clears MODE.
1 = IRQ interrupt requests on falling edges and low levels
0 = IRQ interrupt requests on falling edges only
MC68HC908QY/QT Family Data Sheet, Rev. 4
Freescale Semiconductor
79
External Interrupt (IRQ)
MC68HC908QY/QT Family Data Sheet, Rev. 4
80
Freescale Semiconductor
Chapter 9
Keyboard Interrupt Module (KBI)
9.1 Introduction
The keyboard interrupt module (KBI) provides six independently maskable external interrupts, which are
accessible via the PTA0–PTA5 pins.
9.2 Features
Features of the keyboard interrupt module include:
• Six keyboard interrupt pins with separate keyboard interrupt enable bits and one keyboard interrupt
mask
• Software configurable pullup device if input pin is configured as input port bit
• Programmable edge-only or edge and level interrupt sensitivity
• Exit from low-power modes
Figure 9-1 provides a summary of the input/output (I/O) registers
Addr.
Register Name
Bit 7
6
5
4
3
2
Keyboard Status and Control Read:
$001A
Register (KBSCR) Write:
See page 85. Reset:
0
0
0
0
KEYF
0
Keyboard Interrupt Enable Read:
Register (KBIER) Write:
See page 86. Reset:
0
$001B
ACKK
0
0
1
Bit 0
IMASKK
MODEK
0
0
0
0
0
0
0
AWUIE
KBIE5
KBIE4
KBIE3
KBIE2
KBIE1
KBIE0
0
0
0
0
0
0
0
= Unimplemented
Figure 9-1. KBI I/O Register Summary
MC68HC908QY/QT Family Data Sheet, Rev. 4
Freescale Semiconductor
81
Keyboard Interrupt Module (KBI)
PTA0/AD0/TCH0/KBI0
CLOCK
GENERATOR
(OSCILLATOR)
PTA
PTA2/IRQ/KBI2/TCLK
PTA3/RST/KBI3
DDRA
PTA1/AD1/TCH1/KBI1
SYSTEM INTEGRATION
MODULE
PTA4/OSC2/AD2/KBI4
PTA5/OSC1/AD3/KBI5
M68HC08 CPU
SINGLE INTERRUPT
MODULE
BREAK
MODULE
DDRB
PTB
PTB0
PTB1
PTB2
PTB3
PTB4
PTB5
PTB6
PTB7
POWER-ON RESET
MODULE
8-BIT ADC
128 BYTES RAM
MC68HC908QY4 AND MC68HC908QT4
4096 BYTES
MC68HC908QY2, MC68HC908QY1,
MC68HC908QT2, AND MC68HC908QT1:
1536 BYTES
USER FLASH
KEYBOARD INTERRUPT
MODULE
16-BIT TIMER
MODULE
COP
MODULE
VDD
POWER SUPPLY
MONITOR ROM
VSS
RST, IRQ: Pins have internal (about 30K Ohms) pull up
PTA[0:5]: High current sink and source capability
PTA[0:5]: Pins have programmable keyboard interrupt and pull up
PTB[0:7]: Not available on 8-pin devices – MC68HLC908QT1, MC68HLC908QT2, and MC68HLC908QT4
ADC: Not available on the MC68HC908QY1 and MC68HC908QT1
Figure 9-2. Block Diagram Highlighting KBI Block and Pins
MC68HC908QY/QT Family Data Sheet, Rev. 4
82
Freescale Semiconductor
Functional Description
9.3 Functional Description
The keyboard interrupt module controls the enabling/disabling of interrupt functions on the six port A pins.
These six pins can be enabled/disabled independently of each other.
INTERNAL BUS
VECTOR FETCH
DECODER
ACKK
KBI0
VDD
KBIE0
TO PULLUP ENABLE
.
.
.
RESET
D
CLR
KEYF
Q
SYNCHRONIZER
CK
KBI5
KEYBOARD
INTERRUPT FF
IMASKK
KEYBOARD
INTERRUPT
REQUEST
MODEK
KBIE5
TO PULLUP ENABLE
AWUIREQ(1)
1. For AWUGEN logic refer to Figure 4-2. Auto Wakeup Interrupt Request Generation Logic.
Figure 9-3. Keyboard Interrupt Block Diagram
9.3.1 Keyboard Operation
Writing to the KBIE0–KBIE5 bits in the keyboard interrupt enable register (KBIER) independently enables
or disables each port A pin as a keyboard interrupt pin. Enabling a keyboard interrupt pin in port A also
enables its internal pullup device irrespective of PTAPUEx bits in the port A input pullup enable register
(see 12.2.3 Port A Input Pullup Enable Register). A logic 0 applied to an enabled keyboard interrupt pin
latches a keyboard interrupt request.
A keyboard interrupt is latched when one or more keyboard interrupt inputs goes low after all were high.
The MODEK bit in the keyboard status and control register controls the triggering mode of the keyboard
interrupt.
• If the keyboard interrupt is edge-sensitive only, a falling edge on a keyboard interrupt input does
not latch an interrupt request if another keyboard pin is already low. To prevent losing an interrupt
request on one input because another input is still low, software can disable the latter input while
it is low.
• If the keyboard interrupt is falling edge and low-level sensitive, an interrupt request is present as
long as any keyboard interrupt input is low.
If the MODEK bit is set, the keyboard interrupt inputs are both falling edge and low-level sensitive, and
both of the following actions must occur to clear a keyboard interrupt request:
• Vector fetch or software clear — A vector fetch generates an interrupt acknowledge signal to clear
the interrupt request. Software may generate the interrupt acknowledge signal by writing a 1 to the
ACKK bit in the keyboard status and control register (KBSCR). The ACKK bit is useful in
MC68HC908QY/QT Family Data Sheet, Rev. 4
Freescale Semiconductor
83
Keyboard Interrupt Module (KBI)
•
applications that poll the keyboard interrupt inputs and require software to clear the keyboard
interrupt request. Writing to the ACKK bit prior to leaving an interrupt service routine can also
prevent spurious interrupts due to noise. Setting ACKK does not affect subsequent transitions on
the keyboard interrupt inputs. A falling edge that occurs after writing to the ACKK bit latches
another interrupt request. If the keyboard interrupt mask bit, IMASKK, is clear, the central
processor unit (CPU) loads the program counter with the vector address at locations $FFE0 and
$FFE1.
Return of all enabled keyboard interrupt inputs to logic 1 — As long as any enabled keyboard
interrupt pin is at logic 0, the keyboard interrupt remains set. The auto wakeup interrupt input,
AWUIREQ, will be cleared only by writing to ACKK bit in KBSCR or reset.
The vector fetch or software clear and the return of all enabled keyboard interrupt pins to logic 1 may occur
in any order.
If the MODEK bit is clear, the keyboard interrupt pin is falling-edge sensitive only. With MODEK clear, a
vector fetch or software clear immediately clears the keyboard interrupt request.
Reset clears the keyboard interrupt request and the MODEK bit, clearing the interrupt request even if a
keyboard interrupt input stays at logic 0.
The keyboard flag bit (KEYF) in the keyboard status and control register can be used to see if a pending
interrupt exists. The KEYF bit is not affected by the keyboard interrupt mask bit (IMASKK) which makes
it useful in applications where polling is preferred.
To determine the logic level on a keyboard interrupt pin, use the data direction register to configure the
pin as an input and then read the data register.
NOTE
Setting a keyboard interrupt enable bit (KBIEx) forces the corresponding
keyboard interrupt pin to be an input, overriding the data direction register.
However, the data direction register bit must be a 0 for software to read the
pin.
9.3.2 Keyboard Initialization
When a keyboard interrupt pin is enabled, it takes time for the internal pullup to reach a logic 1. Therefore
a false interrupt can occur as soon as the pin is enabled.
To prevent a false interrupt on keyboard initialization:
1. Mask keyboard interrupts by setting the IMASKK bit in the keyboard status and control register.
2. Enable the KBI pins by setting the appropriate KBIEx bits in the keyboard interrupt enable register.
3. Write to the ACKK bit in the keyboard status and control register to clear any false interrupts.
4. Clear the IMASKK bit.
An interrupt signal on an edge-triggered pin can be acknowledged immediately after enabling the pin. An
interrupt signal on an edge- and level-triggered interrupt pin must be acknowledged after a delay that
depends on the external load.
Another way to avoid a false interrupt:
1. Configure the keyboard pins as outputs by setting the appropriate DDRA bits in the data direction
register A.
2. Write 1s to the appropriate port A data register bits.
3. Enable the KBI pins by setting the appropriate KBIEx bits in the keyboard interrupt enable register.
MC68HC908QY/QT Family Data Sheet, Rev. 4
84
Freescale Semiconductor
Wait Mode
9.4 Wait Mode
The keyboard module remains active in wait mode. Clearing the IMASKK bit in the keyboard status and
control register enables keyboard interrupt requests to bring the MCU out of wait mode.
9.5 Stop Mode
The keyboard module remains active in stop mode. Clearing the IMASKK bit in the keyboard status and
control register enables keyboard interrupt requests to bring the MCU out of stop mode.
9.6 Keyboard Module During Break Interrupts
The system integration module (SIM) controls whether the keyboard interrupt latch can be cleared during
the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear status
bits during the break state.
To allow software to clear the keyboard interrupt latch during a break interrupt, write a 1 to the BCFE bit.
If a latch is cleared during the break state, it remains cleared when the MCU exits the break state.
To protect the latch during the break state, write a 0 to the BCFE bit. With BCFE at 0 (its default state),
writing to the keyboard acknowledge bit (ACKK) in the keyboard status and control register during the
break state has no effect.
9.7 Input/Output Registers
The following I/O registers control and monitor operation of the keyboard interrupt module:
• Keyboard interrupt status and control register (KBSCR)
• Keyboard interrupt enable register (KBIER)
9.7.1 Keyboard Status and Control Register
The keyboard status and control register (KBSCR):
• Flags keyboard interrupt requests
• Acknowledges keyboard interrupt requests
• Masks keyboard interrupt requests
• Controls keyboard interrupt triggering sensitivity
Address: $001A
Read:
Bit 7
6
5
4
3
2
0
0
0
0
KEYF
0
Write:
ACKK
Reset:
0
0
0
0
0
0
1
Bit 0
IMASKK
MODEK
0
0
= Unimplemented
Figure 9-4. Keyboard Status and Control Register (KBSCR)
Bits 7–4 — Not used
These read-only bits always read as 0s.
MC68HC908QY/QT Family Data Sheet, Rev. 4
Freescale Semiconductor
85
Keyboard Interrupt Module (KBI)
KEYF — Keyboard Flag Bit
This read-only bit is set when a keyboard interrupt is pending on port A or auto wakeup. Reset clears
the KEYF bit.
1 = Keyboard interrupt pending
0 = No keyboard interrupt pending
ACKK — Keyboard Acknowledge Bit
Writing a 1 to this write-only bit clears the keyboard interrupt request on port A and auto wakeup logic.
ACKK always reads as 0. Reset clears ACKK.
IMASKK— Keyboard Interrupt Mask Bit
Writing a 1 to this read/write bit prevents the output of the keyboard interrupt mask from generating
interrupt requests on port A or auto wakeup. Reset clears the IMASKK bit.
1 = Keyboard interrupt requests masked
0 = Keyboard interrupt requests not masked
MODEK — Keyboard Triggering Sensitivity Bit
This read/write bit controls the triggering sensitivity of the keyboard interrupt pins on port A and auto
wakeup. Reset clears MODEK.
1 = Keyboard interrupt requests on falling edges and low levels
0 = Keyboard interrupt requests on falling edges only
9.7.2 Keyboard Interrupt Enable Register
The port A keyboard interrupt enable register (KBIER) enables or disables each port A pin or auto wakeup
to operate as a keyboard interrupt input.
Address: $001B
Bit 7
Read:
0
Write:
Reset:
0
6
5
4
3
2
1
Bit 0
AWUIE
KBIE5
KBIE4
KBIE3
KBIE2
KBIE1
KBIE0
0
0
0
0
0
0
0
= Unimplemented
Figure 9-5. Keyboard Interrupt Enable Register (KBIER)
KBIE5–KBIE0 — Port A Keyboard Interrupt Enable Bits
Each of these read/write bits enables the corresponding keyboard interrupt pin on port A to latch
interrupt requests. Reset clears the keyboard interrupt enable register.
1 = KBIx pin enabled as keyboard interrupt pin
0 = KBIx pin not enabled as keyboard interrupt pin
NOTE
AWUIE bit is not used in conjunction with the keyboard interrupt feature. To
see a description of this bit, see Chapter 4 Auto Wakeup Module (AWU).
MC68HC908QY/QT Family Data Sheet, Rev. 4
86
Freescale Semiconductor
Chapter 10
Low-Voltage Inhibit (LVI)
10.1 Introduction
This section describes the low-voltage inhibit (LVI) module, which monitors the voltage on the VDD pin
and can force a reset when the VDD voltage falls below the LVI trip falling voltage, VTRIPF.
10.2 Features
Features of the LVI module include:
• Programmable LVI reset
• Programmable power consumption
• Selectable LVI trip voltage
• Programmable stop mode operation
10.3 Functional Description
Figure 10-1 shows the structure of the LVI module. LVISTOP, LVIPWRD, LVI5OR3, and LVIRSTD are
user selectable options found in the configuration register (CONFIG1). See Chapter 5 Configuration
Register (CONFIG).
VDD
STOP INSTRUCTION
LVISTOP
FROM CONFIG
FROM CONFIG
LVIRSTD
LVIPWRD
FROM CONFIG
LOW VDD
DETECTOR
VDD > LVITRIP = 0
LVI RESET
VDD ≤ LVITRIP = 1
LVIOUT
LVI5OR3
FROM CONFIG
Figure 10-1. LVI Module Block Diagram
The LVI is enabled out of reset. The LVI module contains a bandgap reference circuit and comparator.
Clearing the LVI power disable bit, LVIPWRD, enables the LVI to monitor VDD voltage. Clearing the LVI
reset disable bit, LVIRSTD, enables the LVI module to generate a reset when VDD falls below a voltage,
MC68HC908QY/QT Family Data Sheet, Rev. 4
Freescale Semiconductor
87
Low-Voltage Inhibit (LVI)
VTRIPF. Setting the LVI enable in stop mode bit, LVISTOP, enables the LVI to operate in stop mode.
Setting the LVI 5-V or 3-V trip point bit, LVI5OR3, enables the trip point voltage, VTRIPF, to be configured
for 5-V operation. Clearing the LVI5OR3 bit enables the trip point voltage, VTRIPF, to be configured for 3-V
operation. The actual trip thresholds are specified in 16.5 5-V DC Electrical Characteristics and 16.9 3-V
DC Electrical Characteristics.
NOTE
After a power-on reset, the LVI’s default mode of operation is 3 volts. If a
5-V system is used, the user must set the LVI5OR3 bit to raise the trip point
to 5-V operation.
If the user requires 5-V mode and sets the LVI5OR3 bit after power-on reset
while the VDD supply is not above the VTRIPR for 5-V mode, the
microcontroller unit (MCU) will immediately go into reset. The next time the
LVI releases the reset, the supply will be above the VTRIPR for 5-V mode.
Once an LVI reset occurs, the MCU remains in reset until VDD rises above a voltage, VTRIPR, which
causes the MCU to exit reset. See Chapter 13 System Integration Module (SIM) for the reset recovery
sequence.
The output of the comparator controls the state of the LVIOUT flag in the LVI status register (LVISR) and
can be used for polling LVI operation when the LVI reset is disabled.
10.3.1 Polled LVI Operation
In applications that can operate at VDD levels below the VTRIPF level, software can monitor VDD by polling
the LVIOUT bit. In the configuration register, the LVIPWRD bit must be cleared to enable the LVI module,
and the LVIRSTD bit must be at set to disable LVI resets.
10.3.2 Forced Reset Operation
In applications that require VDD to remain above the VTRIPF level, enabling LVI resets allows the LVI
module to reset the MCU when VDD falls below the VTRIPF level. In the configuration register, the
LVIPWRD and LVIRSTD bits must be cleared to enable the LVI module and to enable LVI resets.
10.3.3 Voltage Hysteresis Protection
Once the LVI has triggered (by having VDD fall below VTRIPF), the LVI will maintain a reset condition until
VDD rises above the rising trip point voltage, VTRIPR. This prevents a condition in which the MCU is
continually entering and exiting reset if VDD is approximately equal to VTRIPF. VTRIPR is greater than
VTRIPF by the hysteresis voltage, VHYS.
10.3.4 LVI Trip Selection
The LVI5OR3 bit in the configuration register selects whether the LVI is configured for 5-V or 3-V
protection.
NOTE
The microcontroller is guaranteed to operate at a minimum supply voltage.
The trip point (VTRIPF [5 V] or VTRIPF [3 V]) may be lower than this.
See 16.5 5-V DC Electrical Characteristics and 16.9 3-V DC Electrical
Characteristics for the actual trip point voltages.
MC68HC908QY/QT Family Data Sheet, Rev. 4
88
Freescale Semiconductor
LVI Status Register
10.4 LVI Status Register
The LVI status register (LVISR) indicates if the VDD voltage was detected below the VTRIPF level while
LVI resets have been disabled.
Address: $FE0C
Read:
Bit 7
6
5
4
3
2
1
Bit 0
LVIOUT
0
0
0
0
0
0
R
0
0
0
0
0
0
0
0
R
= Reserved
Write:
Reset:
= Unimplemented
Figure 10-2. LVI Status Register (LVISR)
LVIOUT — LVI Output Bit
This read-only flag becomes set when the VDD voltage falls below the VTRIPF trip voltage and is cleared
when VDD voltage rises above VTRIPR. The difference in these threshold levels results in a hysteresis
that prevents oscillation into and out of reset (see Table 10-1). Reset clears the LVIOUT bit.
Table 10-1. LVIOUT Bit Indication
VDD
LVIOUT
VDD > VTRIPR
0
VDD < VTRIPF
1
VTRIPF < VDD < VTRIPR
Previous value
10.5 LVI Interrupts
The LVI module does not generate interrupt requests.
10.6 Low-Power Modes
The STOP and WAIT instructions put the MCU in low power-consumption standby modes.
10.6.1 Wait Mode
If enabled, the LVI module remains active in wait mode. If enabled to generate resets, the LVI module can
generate a reset and bring the MCU out of wait mode.
10.6.2 Stop Mode
When the LVIPWRD bit in the configuration register is cleared and the LVISTOP bit in the configuration
register is set, the LVI module remains active in stop mode. If enabled to generate resets, the LVI module
can generate a reset and bring the MCU out of stop mode.
MC68HC908QY/QT Family Data Sheet, Rev. 4
Freescale Semiconductor
89
Low-Voltage Inhibit (LVI)
MC68HC908QY/QT Family Data Sheet, Rev. 4
90
Freescale Semiconductor
Chapter 11
Oscillator Module (OSC)
11.1 Introduction
The oscillator module is used to provide a stable clock source for the microcontroller system and bus. The
oscillator module generates two output clocks, BUSCLKX2 and BUSCLKX4. The BUSCLKX4 clock is
used by the system integration module (SIM) and the computer operating properly module (COP). The
BUSCLKX2 clock is divided by two in the SIM to be used as the bus clock for the microcontroller.
Therefore the bus frequency will be one fourth of the BUSCLKX4 frequency.
11.2 Features
The oscillator has these four clock source options available:
1. Internal oscillator: An internally generated, fixed frequency clock, trimmable to ±5%.This is the
default option out of reset.
2. External oscillator: An external clock that can be driven directly into OSC1.
3. External RC: A built-in oscillator module (RC oscillator) that requires an external R connection only.
The capacitor is internal to the chip.
4. External crystal: A built-in oscillator module (XTAL oscillator) that requires an external crystal or
ceramic-resonator.
11.3 Functional Description
The oscillator contains these major subsystems:
• Internal oscillator circuit
• Internal or external clock switch control
• External clock circuit
• External crystal circuit
• External RC clock circuit
MC68HC908QY/QT Family Data Sheet, Rev. 4
Freescale Semiconductor
91
Oscillator Module (OSC)
PTA0/AD0/TCH0/KBI0
CLOCK
GENERATOR
(OSCILLATOR)
PTA
PTA2/IRQ/KBI2/TCLK
PTA3/RST/KBI3
DDRA
PTA1/AD1/TCH1/KBI1
SYSTEM INTEGRATION
MODULE
PTA4/OSC2/AD2/KBI4
PTA5/OSC1/AD3/KBI5
M68HC08 CPU
SINGLE INTERRUPT
MODULE
BREAK
MODULE
DDRB
PTB
PTB0
PTB1
PTB2
PTB3
PTB4
PTB5
PTB6
PTB7
POWER-ON RESET
MODULE
8-BIT ADC
128 BYTES RAM
MC68HC908QY4 AND MC68HC908QT4
4096 BYTES
MC68HC908QY2, MC68HC908QY1,
MC68HC908QT2, AND MC68HC908QT1:
1536 BYTES
USER FLASH
KEYBOARD INTERRUPT
MODULE
16-BIT TIMER
MODULE
COP
MODULE
VDD
POWER SUPPLY
MONITOR ROM
VSS
RST, IRQ: Pins have internal (about 30K Ohms) pull up
PTA[0:5]: High current sink and source capability
PTA[0:5]: Pins have programmable keyboard interrupt and pull up
PTB[0:7]: Not available on 8-pin devices – MC68HC908QT1, MC68HC908QT2, and MC68HC908QT4
ADC: Not available on the MC68HC908QY1 and MC68HC908QT1
Figure 11-1. Block Diagram Highlighting OSC Block and Pins
11.3.1 Internal Oscillator
The internal oscillator circuit is designed for use with no external components to provide a clock source
with tolerance less than ±25% untrimmed.An 8-bit trimming register allows adjustment to a tolerance of
less than ±5%.
The internal oscillator will generate a clock of 12.8 MHz typical (INTCLK) resulting in a bus speed (internal
clock ÷ 4) of 3.2 MHz. 3.2 MHz came from the maximum bus speed guaranteed at 3 V which is 4
MHz.Since the internal oscillator will have a ±25% tolerance (pre-trim), then the +25% case should not
allow a frequency higher than 4 MHz:
3.2 MHz + 25% = 4 MHz
Figure 11-3 shows how BUSCLKX4 is derived from INTCLK and, like the RC oscillator, OSC2 can output
BUSCLKX4 by setting OSC2EN in PTAPUE register.See Chapter 12 Input/Output Ports (PORTS)
MC68HC908QY/QT Family Data Sheet, Rev. 4
92
Freescale Semiconductor
Functional Description
11.3.1.1 Internal Oscillator Trimming
The 8-bit trimming register, OSCTRIM, allows a clock period adjust of +127 and –128 steps. Increasing
OSCTRIM value increases the clock period. Trimming allows the internal clock frequency to be set to
12.8 MHz ± 5%.
All devices are programmed with a trim value in a reserved FLASH location, $FFC0. This value can be
copied from the FLASH to the OSCTRIM register ($0038) during reset initialization.
Reset loads OSCTRIM with a default value of $80.
WARNING
Bulk FLASH erasure will set location $FFC0 to $FF and the factory
programmed value will be lost.
11.3.1.2 Internal to External Clock Switching
When external clock source (external OSC, RC, or XTAL) is desired, the user must perform the following
steps:
1. For external crystal circuits only, OSCOPT[1:0] = 1:1: To help precharge an external crystal
oscillator, set PTA4 (OSC2) as an output and drive high for several cycles. This may help the
crystal circuit start more robustly.
2. Set CONFIG2 bits OSCOPT[1:0] according to . The oscillator module control logic will then set
OSC1 as an external clock input and, if the external crystal option is selected, OSC2 will also be
set as the clock output.
3. Create a software delay to wait the stabilization time needed for the selected clock source (crystal,
resonator, RC) as recommended by the component manufacturer. A good rule of thumb for crystal
oscillators is to wait 4096 cycles of the crystal frequency, i.e., for a 4-MHz crystal, wait
approximately 1 msec.
4. After the manufacturer’s recommended delay has elapsed, the ECGON bit in the OSC status
register (OSCSTAT) needs to be set by the user software.
5. After ECGON set is detected, the OSC module checks for oscillator activity by waiting two external
clock rising edges.
6. The OSC module then switches to the external clock. Logic provides a glitch free transition.
7. The OSC module first sets the ECGST bit in the OSCSTAT register and then stops the internal
oscillator.
NOTE
Once transition to the external clock is done, the internal oscillator will only
be reactivated with reset. No post-switch clock monitor feature is
implemented (clock does not switch back to internal if external clock dies).
11.3.2 External Oscillator
The external clock option is designed for use when a clock signal is available in the application to provide
a clock source to the microcontroller. The OSC1 pin is enabled as an input by the oscillator module. The
clock signal is used directly to create BUSCLKX4 and also divided by two to create BUSCLKX2.
In this configuration, the OSC2 pin cannot output BUSCLKX4.So the OSC2EN bit in the port A pullup
enable register will be clear to enable PTA4 I/O functions on the pin
MC68HC908QY/QT Family Data Sheet, Rev. 4
Freescale Semiconductor
93
Oscillator Module (OSC)
11.3.3 XTAL Oscillator
The XTAL oscillator circuit is designed for use with an external crystal or ceramic resonator to provide an
accurate clock source. In this configuration, the OSC2 pin is dedicated to the external crystal circuit. The
OSC2EN bit in the port A pullup enable register has no effect when this clock mode is selected.
In its typical configuration, the XTAL oscillator is connected in a Pierce oscillator configuration, as shown
in Figure 11-2. This figure shows only the logical representation of the internal components and may not
represent actual circuitry. The oscillator configuration uses five components:
• Crystal, X1
• Fixed capacitor, C1
• Tuning capacitor, C2 (can also be a fixed capacitor)
• Feedback resistor, RB
• Series resistor, RS (optional)
NOTE
The series resistor (RS) is included in the diagram to follow strict Pierce
oscillator guidelines and may not be required for all ranges of operation,
especially with high frequency crystals. Refer to the crystal manufacturer’s
data for more information.
FROM SIM
TO SIM
BUSCLKX4
XTALCLK
TO SIM
BUSCLKX2
÷2
SIMOSCEN
MCU
OSC1
OSC2
RS(1)
RB
X1
C1
C2
Note 1.
RS can be zero (shorted) when used with higher-frequency crystals. Refer to manufacturer’s
data. See Chapter 16 Electrical Specifications for component value recommendations.
Figure 11-2. XTAL Oscillator External Connections
MC68HC908QY/QT Family Data Sheet, Rev. 4
94
Freescale Semiconductor
Oscillator Module Signals
11.3.4 RC Oscillator
The RC oscillator circuit is designed for use with external R to provide a clock source with tolerance less
than 25%.
In its typical configuration, the RC oscillator requires two external components, one R and one C. In the
MC68HC908QY4, the capacitor is internal to the chip. The R value should have a tolerance of 1% or less,
to obtain a clock source with less than 25% tolerance. The oscillator configuration uses one component,
REXT.
In this configuration, the OSC2 pin can be left in the reset state as PTA4. Or, the OSC2EN bit in the port
A pullup enable register can be set to enable the OSC2 output function on the pin. Enabling the OSC2
output slightly increases the external RC oscillator frequency, fRCCLK.
See Figure 11-3
OSCRCOPT
FROM SIM
TO SIM
TO SIM
INTCLK
0
BUSCLKX4
BUSCLKX2
1
SIMOSCEN
EXTERNAL RC
EN
OSCILLATOR
RCCLK
÷2
1
0
PTA4
I/O
PTA4
OSC2EN
MCU
OSC1
PTA4/BUSCLKX4 (OSC2)
VDD
REXT
See Chapter 16 Electrical Specifications for component value requirements.
Figure 11-3. RC Oscillator External Connections
11.4 Oscillator Module Signals
The following paragraphs describe the signals that are inputs to and outputs from the oscillator module.
11.4.1 Crystal Amplifier Input Pin (OSC1)
The OSC1 pin is either an input to the crystal oscillator amplifier, an input to the RC oscillator circuit, or
an external clock source.
For the internal oscillator configuration, the OSC1 pin can assume other functions according to Table 1-3.
Function Priority in Shared Pins.
MC68HC908QY/QT Family Data Sheet, Rev. 4
Freescale Semiconductor
95
Oscillator Module (OSC)
11.4.2 Crystal Amplifier Output Pin (OSC2/PTA4/BUSCLKX4)
For the XTAL oscillator device, the OSC2 pin is the crystal oscillator inverting amplifier output.
For the external clock option, the OSC2 pin is dedicated to the PTA4 I/O function. The OSC2EN bit has
no effect.
For the internal oscillator or RC oscillator options, the OSC2 pin can assume other functions according to
Table 1-3. Function Priority in Shared Pins, or the output of the oscillator clock (BUSCLKX4).
Table 11-1. OSC2 Pin Function
Option
OSC2 Pin Function
XTAL oscillator
Inverting OSC1
External clock
PTA4 I/O
Internal oscillator
or
RC oscillator
Controlled by OSC2EN bit in PTAPUE register
OSC2EN = 0: PTA4 I/O
OSC2EN = 1: BUSCLKX4 output
11.4.3 Oscillator Enable Signal (SIMOSCEN)
The SIMOSCEN signal comes from the system integration module (SIM) and enables/disables either the
XTAL oscillator circuit, the RC oscillator, or the internal oscillator.
11.4.4 XTAL Oscillator Clock (XTALCLK)
XTALCLK is the XTAL oscillator output signal. It runs at the full speed of the crystal (fXCLK) and comes
directly from the crystal oscillator circuit. Figure 11-2 shows only the logical relation of XTALCLK to OSC1
and OSC2 and may not represent the actual circuitry. The duty cycle of XTALCLK is unknown and may
depend on the crystal and other external factors. Also, the frequency and amplitude of XTALCLK can be
unstable at start up.
11.4.5 RC Oscillator Clock (RCCLK)
RCCLK is the RC oscillator output signal. Its frequency is directly proportional to the time constant of
external R and internal C. Figure 11-3 shows only the logical relation of RCCLK to OSC1 and may not
represent the actual circuitry.
11.4.6 Internal Oscillator Clock (INTCLK)
INTCLK is the internal oscillator output signal. Its nominal frequency is fixed to 12.8 MHz, but it can be
also trimmed using the oscillator trimming feature of the OSCTRIM register (see 11.3.1.1 Internal
Oscillator Trimming).
11.4.7 Oscillator Out 2 (BUSCLKX4)
BUSCLKX4 is the same as the input clock (XTALCLK, RCCLK, or INTCLK). This signal is driven to the
SIM module and is used to determine the COP cycles.
11.4.8 Oscillator Out (BUSCLKX2)
The frequency of this signal is equal to half of the BUSCLKX4, this signal is driven to the SIM for
generation of the bus clocks used by the CPU and other modules on the MCU. BUSCLKX2 will be divided
MC68HC908QY/QT Family Data Sheet, Rev. 4
96
Freescale Semiconductor
Low Power Modes
again in the SIM and results in the internal bus frequency being one fourth of either the XTALCLK,
RCCLK, or INTCLK frequency.
11.5 Low Power Modes
The WAIT and STOP instructions put the MCU in low-power consumption standby modes.
11.5.1 Wait Mode
The WAIT instruction has no effect on the oscillator logic. BUSCLKX2 and BUSCLKX4 continue to drive
to the SIM module.
11.5.2 Stop Mode
The STOP instruction disables either the XTALCLK, the RCCLK, or INTCLK output, hence BUSCLKX2
and BUSCLKX4.
11.6 Oscillator During Break Mode
The oscillator continues to drive BUSCLKX2 and BUSCLKX4 when the device enters the break state.
11.7 CONFIG2 Options
Two CONFIG2 register options affect the operation of the oscillator module: OSCOPT1 and OSCOPT0.
All CONFIG2 register bits will have a default configuration. Refer to Chapter 5 Configuration Register
(CONFIG) for more information on how the CONFIG2 register is used.
Table 11-2 shows how the OSCOPT bits are used to select the oscillator clock source.
.
Table 11-2. Oscillator Modes
OSCOPT1
OSCOPT0
Oscillator Modes
0
0
Internal oscillator
0
1
External oscillator
1
0
External RC
1
1
External crystal
11.8 Input/Output (I/O) Registers
The oscillator module contains these two registers:
1. Oscillator status register (OSCSTAT)
2. Oscillator trim register (OSCTRIM)
MC68HC908QY/QT Family Data Sheet, Rev. 4
Freescale Semiconductor
97
Oscillator Module (OSC)
11.8.1 Oscillator Status Register
The oscillator status register (OSCSTAT) contains the bits for switching from internal to external clock
sources.
Address: $0036
Read:
Write:
Reset:
Bit 7
6
5
4
3
2
1
R
R
R
R
R
R
ECGON
0
0
0
0
0
0
0
R
= Reserved
Bit 0
ECGST
0
= Unimplemented
Figure 11-4. Oscillator Status Register (OSCSTAT)
ECGON — External Clock Generator On Bit
This read/write bit enables external clock generator, so that the switching process can be initiated. This
bit is forced low during reset. This bit is ignored in monitor mode with the internal oscillator bypassed,
PTM or CTM mode.
1 = External clock generator enabled
0 = External clock generator disabled
ECGST — External Clock Status Bit
This read-only bit indicates whether or not an external clock source is engaged to drive the system
clock.
1 = An external clock source engaged
0 = An external clock source disengaged
11.8.2 Oscillator Trim Register (OSCTRIM)
Address: $0038
Read:
Write:
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
TRIM7
TRIM6
TRIM5
TRIM4
TRIM3
TRIM2
TRIM1
TRIM0
1
0
0
0
0
0
0
0
Figure 11-5. Oscillator Trim Register (OSCTRIM)
TRIM7–TRIM0 — Internal Oscillator Trim Factor Bits
These read/write bits change the size of the internal capacitor used by the internal oscillator. By
measuring the period of the internal clock and adjusting this factor accordingly, the frequency of the
internal clock can be fine tuned. Increasing (decreasing) this factor by one increases (decreases) the
period by approximately 0.2% of the untrimmed period (the period for TRIM = $80). The trimmed
frequency is guaranteed not to vary by more than ±5% over the full specified range of temperature and
voltage. The reset value is $80, which sets the frequency to 12.8 MHz (3.2 MHz bus speed) ±25%.
MC68HC908QY/QT Family Data Sheet, Rev. 4
98
Freescale Semiconductor
Chapter 12
Input/Output Ports (PORTS)
12.1 Introduction
The MC68HC908QT1, MC68HC908QT2, and MC68HC908QT4 have five bidirectional input-output (I/O)
pins and one input only pin. The MC68HC908QY1, MC68HC908QY2, and MC68HC908QY4 have
thirteen bidirectional pins and one input only pin. All I/O pins are programmable as inputs or outputs.
NOTE
Connect any unused I/O pins to an appropriate logic level, either VDD or VSS.
Although the I/O ports do not require termination for proper operation,
termination reduces excess current consumption and the possibility of
electrostatic damage.
Figure 12-1 provides a summary of the I/O registers.
Addr.
$0000
$0001
$0004
$0005
$000B
$000C
Register Name
Port A Data Register
(PTA)
See page 100.
Port B Data Register
(PTB)
See page 103.
Data Direction Register A
(DDRA)
See page 101.
Data Direction Register B
(DDRB)
See page 103.
Port A Input Pullup Enable
Register (PTAPUE)
See page 102.
Port B Input Pullup Enable
Register (PTBPUE)
See page 104.
Bit 7
Read:
Write:
R
6
AWUL
5
4
3
PTA5
PTA4
PTA3
Reset:
Read:
Write:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
PTA2
1
Bit 0
PTA1
PTA0
PTB1
PTB0
DDRA1
DDRA0
Unaffected by reset
PTB7
PTB6
PTB5
Reset:
Read:
2
PTB4
PTB3
PTB2
Unaffected by reset
0
R
R
DDRA5
DDRA4
DDRA3
0
0
0
0
0
0
0
0
DDRB7
DDRB6
DDRB5
DDRB4
DDRB3
DDRB2
DDRB1
DDRB0
0
0
0
0
0
0
0
0
PTAPUE5
PTAPUE4
PTAPUE3
PTAPUE2
PTAPUE1
PTAPUE0
OSC2EN
0
0
0
0
0
0
0
0
PTBPUE7
PTBPUE6
PTBPUE5
PTBPUE4
PTBPUE3
PTBPUE2
PTBPUE1
PTBPUE0
0
0
0
0
0
0
0
0
R
= Reserved
= Unimplemented
Figure 12-1. I/O Port Register Summary
MC68HC908QY/QT Family Data Sheet, Rev. 4
Freescale Semiconductor
99
Input/Output Ports (PORTS)
12.2 Port A
Port A is a 6-bit special function port that shares all six of its pins with the keyboard interrupt (KBI) module
(see Chapter 9 Keyboard Interrupt Module (KBI)). Each port A pin also has a software configurable pullup
device if the corresponding port pin is configured as an input port.
NOTE
PTA2 is input only.
When the IRQ function is enabled in the configuration register 2
(CONFIG2), bit 2 of the port A data register (PTA) will always read a 0. In
this case, the BIH and BIL instructions can be used to read the logic level
on the PTA2 pin. When the IRQ function is disabled, these instructions will
behave as if the PTA2 pin is a logic 1. However, reading bit 2 of PTA will
read the actual logic level on the pin.
12.2.1 Port A Data Register
The port A data register (PTA) contains a data latch for each of the six port A pins.
Address: $0000
Bit 7
Read:
Write:
R
6
AWUL
5
4
3
PTA5
PTA4
PTA3
Reset:
2
PTA2
1
Bit 0
PTA1
PTA0
KBI1
KBI0
Unaffected by reset
KBI5
Additional Functions:
R
= Reserved
KBI4
KBI3
KBI2
= Unimplemented
Figure 12-2. Port A Data Register (PTA)
PTA[5:0] — Port A Data Bits
These read/write bits are software programmable. Data direction of each port A pin is under the control
of the corresponding bit in data direction register A. Reset has no effect on port A data.
AWUL — Auto Wakeup Latch Data Bit
This is a read-only bit which has the value of the auto wakeup interrupt request latch. The wakeup
request signal is generated internally (see Chapter 4 Auto Wakeup Module (AWU)). There is no PTA6
port nor any of the associated bits such as PTA6 data register, pullup enable or direction.
KBI[5:0] — Port A Keyboard Interrupts
The keyboard interrupt enable bits, KBIE5–KBIE0, in the keyboard interrupt control enable register
(KBIER) enable the port A pins as external interrupt pins (see Chapter 9 Keyboard Interrupt Module
(KBI)).
MC68HC908QY/QT Family Data Sheet, Rev. 4
100
Freescale Semiconductor
Port A
12.2.2 Data Direction Register A
Data direction register A (DDRA) determines whether each port A pin is an input or an output. Writing a 1
to a DDRA bit enables the output buffer for the corresponding port A pin; a 0 disables the output buffer.
Address: $0004
Read:
Write:
Reset:
Bit 7
6
5
4
3
R
R
DDRA5
DDRA4
DDRA3
0
0
0
0
0
R
= Reserved
2
0
1
Bit 0
DDRA1
DDRA0
0
0
0
= Unimplemented
Figure 12-3. Data Direction Register A (DDRA)
DDRA[5:0] — Data Direction Register A Bits
These read/write bits control port A data direction. Reset clears DDRA[5:0], configuring all port A pins
as inputs.
1 = Corresponding port A pin configured as output
0 = Corresponding port A pin configured as input
NOTE
Avoid glitches on port A pins by writing to the port A data register before
changing data direction register A bits from 0 to 1.
Figure 12-4 shows the port A I/O logic.
READ DDRA ($0004)
PTAPUEx
INTERNAL DATA BUS
WRITE DDRA ($0004)
RESET
DDRAx
30 k
WRITE PTA ($0000)
PTAx
PTAx
READ PTA ($0000)
TO KEYBOARD INTERRUPT CIRCUIT
Figure 12-4. Port A I/O Circuit
NOTE
Figure 12-4 does not apply to PTA2
When DDRAx is a 1, reading address $0000 reads the PTAx data latch. When DDRAx is a 0, reading
address $0000 reads the voltage level on the pin. The data latch can always be written, regardless of the
state of its data direction bit.
MC68HC908QY/QT Family Data Sheet, Rev. 4
Freescale Semiconductor
101
Input/Output Ports (PORTS)
12.2.3 Port A Input Pullup Enable Register
The port A input pullup enable register (PTAPUE) contains a software configurable pullup device for each
if the six port A pins. Each bit is individually configurable and requires the corresponding data direction
register, DDRAx, to be configured as input. Each pullup device is automatically and dynamically disabled
when its corresponding DDRAx bit is configured as output.
Address: $000B
Bit 7
Read:
Write:
Reset:
6
OSC2EN
0
5
4
3
2
1
Bit 0
PTAPUE5
PTAPUE4
PTAPUE3
PTAPUE2
PTAPUE1
PTAPUE0
0
0
0
0
0
0
0
= Unimplemented
Figure 12-5. Port A Input Pullup Enable Register (PTAPUE)
OSC2EN — Enable PTA4 on OSC2 Pin
This read/write bit configures the OSC2 pin function when internal oscillator or RC oscillator option is
selected. This bit has no effect for the XTAL or external oscillator options.
1 = OSC2 pin outputs the internal or RC oscillator clock (BUSCLKX4)
0 = OSC2 pin configured for PTA4 I/O, having all the interrupt and pullup functions
PTAPUE[5:0] — Port A Input Pullup Enable Bits
These read/write bits are software programmable to enable pullup devices on port A pins.
1 = Corresponding port A pin configured to have internal pull if its DDRA bit is set to 0
0 = Pullup device is disconnected on the corresponding port A pin regardless of the state of its
DDRA bit
Table 12-1 summarizes the operation of the port A pins.
Table 12-1. Port A Pin Functions
PTAPUE
Bit
DDRA
Bit
PTA
Bit
1
0
X(1)
0
0
X
1
Accesses to DDRA
I/O Pin
Mode
Accesses to PTA
Read/Write
Read
Write
(2)
DDRA5–DDRA0
Pin
PTA5–PTA0(3)
X
Input, Hi-Z(4)
DDRA5–DDRA0
Pin
PTA5–PTA0(3)
X
Output
DDRA5–DDRA0
PTA5–PTA0
PTA5–PTA0(5)
Input, VDD
1. X = don’t care
2. I/O pin pulled to VDD by internal pullup.
3. Writing affects data register, but does not affect input.
4. Hi-Z = high impedance
5. Output does not apply to PTA2
MC68HC908QY/QT Family Data Sheet, Rev. 4
102
Freescale Semiconductor
Port B
12.3 Port B
Port B is an 8-bit general purpose I/O port. Port B is only available on the MC68HC908QY1,
MC68HC908QY2, and MC68HC908QY4.
12.3.1 Port B Data Register
The port B data register (PTB) contains a data latch for each of the eight port B pins.
Address: $0001
Read:
Write:
Bit 7
6
5
4
3
2
1
Bit 0
PTB7
PTB6
PTB5
PTB4
PTB3
PTB2
PTB1
PTB0
Reset:
Unaffected by reset
Figure 12-6. Port B Data Register (PTB)
PTB[7:0] — Port B Data Bits
These read/write bits are software programmable. Data direction of each port B pin is under the control
of the corresponding bit in data direction register B. Reset has no effect on port B data.
12.3.2 Data Direction Register B
Data direction register B (DDRB) determines whether each port B pin is an input or an output. Writing a 1
to a DDRB bit enables the output buffer for the corresponding port B pin; a 0 disables the output buffer.
Address: $0005
Read:
Write:
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
DDRB7
DDRB6
DDRB5
DDRB4
DDRB3
DDRB2
DDRB1
DDRB0
0
0
0
0
0
0
0
0
Figure 12-7. Data Direction Register B (DDRB)
DDRB[7:0] — Data Direction Register B Bits
These read/write bits control port B data direction. Reset clears DDRB[7:0], configuring all port B pins
as inputs.
1 = Corresponding port B pin configured as output
0 = Corresponding port B pin configured as input
NOTE
Avoid glitches on port B pins by writing to the port B data register before
changing data direction register B bits from 0 to 1. Figure 12-8 shows the
port B I/O logic.
MC68HC908QY/QT Family Data Sheet, Rev. 4
Freescale Semiconductor
103
Input/Output Ports (PORTS)
READ DDRB ($0005)
PTBPUEx
INTERNAL DATA BUS
WRITE DDRB ($0005)
DDRBx
RESET
30 k
WRITE PTB ($0001)
PTBx
PTBx
READ PTB ($0001)
Figure 12-8. Port B I/O Circuit
When DDRBx is a 1, reading address $0001 reads the PTBx data latch. When DDRBx is a 0, reading
address $0001 reads the voltage level on the pin. The data latch can always be written, regardless of the
state of its data direction bit. Table 12-2 summarizes the operation of the port B pins.
Table 12-2. Port B Pin Functions
DDRB
Bit
PTB
Bit
I/O Pin
Mode
Accesses to DDRB
Accesses to PTB
Read/Write
Read
Write
0
X(1)
Input, Hi-Z(2)
DDRB7–DDRB0
Pin
PTB7–PTB0(3)
1
X
Output
DDRB7–DDRB0
Pin
PTB7–PTB0
1. X = don’t care
2. Hi-Z = high impedance
3. Writing affects data register, but does not affect the input.
12.3.3 Port B Input Pullup Enable Register
The port B input pullup enable register (PTBPUE) contains a software configurable pullup device for each
of the eight port B pins. Each bit is individually configurable and requires the corresponding data direction
register, DDRBx, be configured as input. Each pullup device is automatically and dynamically disabled
when its corresponding DDRBx bit is configured as output.
Address: $000C
Read:
Write:
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
PTBPUE7
PTBPUE6
PTBPUE5
PTBPUE4
PTBPUE3
PTBPUE2
PTBPUE2
PTBPUE0
0
0
0
0
0
0
0
0
Figure 12-9. Port B Input Pullup Enable Register (PTBPUE)
PTBPUE[7:0] — Port B Input Pullup Enable Bits
These read/write bits are software programmable to enable pullup devices on port B pins
1 = Corresponding port B pin configured to have internal pull if its DDRB bit is set to 0
0 = Pullup device is disconnected on the corresponding port B pin regardless of the state of its
DDRB bit.
MC68HC908QY/QT Family Data Sheet, Rev. 4
104
Freescale Semiconductor
Port B
Table 12-3 summarizes the operation of the port B pins.
Table 12-3. Port B Pin Functions
PTBPUE
Bit
DDRB
Bit
PTB
Bit
I/O Pin
Mode
Accesses to DDRB
Read/Write
Read
Write
1
0
X(1)
Input, VDD(2)
DDRB7–DDRB0
Pin
PTB7–PTB0(3)
0
0
X
Input, Hi-Z(4)
DDRB7–DDRB0
Pin
PTB7–PTB0(3)
X
1
X
Output
DDRB7–DDRB0
PTB7–PTB0
PTB7–PTB0
1.
2.
3.
4.
Accesses to PTB
X = don’t care
I/O pin pulled to VDD by internal pullup.
Writing affects data register, but does not affect input.
Hi-Z = high impedance
MC68HC908QY/QT Family Data Sheet, Rev. 4
Freescale Semiconductor
105
Input/Output Ports (PORTS)
MC68HC908QY/QT Family Data Sheet, Rev. 4
106
Freescale Semiconductor
Chapter 13
System Integration Module (SIM)
13.1 Introduction
This section describes the system integration module (SIM), which supports up to 24 external and/or
internal interrupts. Together with the central processor unit (CPU), the SIM controls all microcontroller unit
(MCU) activities. A block diagram of the SIM is shown in Figure 13-1. Figure 13-2 is a summary of the
SIM I/O registers. The SIM is a system state controller that coordinates CPU and exception timing.
The SIM is responsible for:
• Bus clock generation and control for CPU and peripherals
– Stop/wait/reset/break entry and recovery
– Internal clock control
• Master reset control, including power-on reset (POR) and computer operating properly (COP)
timeout
• Interrupt control:
– Acknowledge timing
– Arbitration control timing
– Vector address generation
• CPU enable/disable timing
Table 13-1. Signal Name Conventions
Signal Name
Description
BUSCLKX4
Buffered clock from the internal, RC or XTAL oscillator circuit.
BUSCLKX2
The BUSCLKX4 frequency divided by two. This signal is again divided by two in the SIM to
generate the internal bus clocks (bus clock = BUSCLKX4 ÷ 4).
Address bus
Internal address bus
Data bus
Internal data bus
PORRST
Signal from the power-on reset module to the SIM
IRST
Internal reset signal
R/W
Read/write signal
MC68HC908QY/QT Family Data Sheet, Rev. 4
Freescale Semiconductor
107
System Integration Module (SIM)
MODULE STOP
MODULE WAIT
CPU STOP (FROM CPU)
CPU WAIT (FROM CPU)
STOP/WAIT
CONTROL
SIMOSCEN (TO OSCILLATOR)
SIM
COUNTER
COP CLOCK
BUSCLKX4 (FROM OSCILLATOR)
BUSCLKX2 (FROM OSCILLATOR)
÷2
VDD
INTERNAL
PULL-UP
RESET
PIN LOGIC
CLOCK
CONTROL
CLOCK GENERATORS
POR CONTROL
MASTER
RESET
CONTROL
RESET PIN CONTROL
SIM RESET STATUS REGISTER
INTERNAL CLOCKS
ILLEGAL OPCODE (FROM CPU)
ILLEGAL ADDRESS (FROM ADDRESS
MAP DECODERS)
COP TIMEOUT (FROM COP MODULE)
LVI RESET (FROM LVI MODULE)
FORCED MON MODE ENTRY (FROM MENRST MODULE)
RESET
INTERRUPT CONTROL
AND PRIORITY DECODE
INTERRUPT SOURCES
CPU INTERFACE
Figure 13-1. SIM Block Diagram
MC68HC908QY/QT Family Data Sheet, Rev. 4
108
Freescale Semiconductor
Introduction
Addr.
Register Name
$FE00
Break Status Register
(BSR)
See page 146.
Bit 7
6
5
4
3
2
R
R
R
R
R
R
Read:
Bit 0
SBSW
Write:
Reset:
1
R
Note 1
0
0
0
0
0
0
0
0
1. Writing a 0 clears SBSW.
$FE01
$FE02
SIM Reset Status
Register (SRSR)
See page 122.
$FE05
$FE06
Interrupt Status
Register 1 (INT1)
See page 118.
Interrupt Status
Register 2 (INT2)
See page 118.
Interrupt Status
Register 3 (INT3)
See page 119.
POR
PIN
COP
ILOP
ILAD
MODRST
LVI
0
1
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
BCFE
R
R
R
R
R
R
R
Write:
POR:
Reserved
Break Flag Control Register
$FE03
(BFCR)
See page 123.
$FE04
Read:
Read:
Write:
Reset:
0
Read:
0
IF5
IF4
IF3
0
IF1
0
0
Write:
R
R
R
R
R
R
R
R
Reset:
0
0
0
0
0
0
0
0
Read:
IF14
0
0
0
0
0
0
0
Write:
R
R
R
R
R
R
R
R
Reset:
0
0
0
0
0
0
0
0
Read:
0
0
0
0
0
0
0
IF15
Write:
R
R
R
R
R
R
R
R
Reset:
0
0
0
0
0
0
0
0
R
= Reserved
= Unimplemented
Figure 13-2. SIM I/O Register Summary
MC68HC908QY/QT Family Data Sheet, Rev. 4
Freescale Semiconductor
109
System Integration Module (SIM)
13.2 RST and IRQ Pins Initialization
RST and IRQ pins come out of reset as PTA3 and PTA2 respectively. RST and IRQ functions can be
activated by programing CONFIG2 accordingly. Refer to Chapter 5 Configuration Register (CONFIG).
13.3 SIM Bus Clock Control and Generation
The bus clock generator provides system clock signals for the CPU and peripherals on the MCU. The
system clocks are generated from an incoming clock, BUSCLKX2, as shown in Figure 13-3.
FROM
OSCILLATOR
BUSCLKX4
FROM
OSCILLATOR
BUSCLKX2
SIM COUNTER
÷2
BUS CLOCK
GENERATORS
SIM
Figure 13-3. SIM Clock Signals
13.3.1 Bus Timing
In user mode, the internal bus frequency is the oscillator frequency (BUSCLKX4) divided by four.
13.3.2 Clock Start-Up from POR
When the power-on reset module generates a reset, the clocks to the CPU and peripherals are inactive
and held in an inactive phase until after the 4096 BUSCLKX4 cycle POR time out has completed. The
IBUS clocks start upon completion of the time out.
13.3.3 Clocks in Stop Mode and Wait Mode
Upon exit from stop mode by an interrupt or reset, the SIM allows BUSCLKX4 to clock the SIM counter.
The CPU and peripheral clocks do not become active until after the stop delay time out. This time out is
selectable as 4096 or 32 BUSCLKX4 cycles. See 13.7.2 Stop Mode.
In wait mode, the CPU clocks are inactive. The SIM also produces two sets of clocks for other modules.
Refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode.
Some modules can be programmed to be active in wait mode.
MC68HC908QY/QT Family Data Sheet, Rev. 4
110
Freescale Semiconductor
Reset and System Initialization
13.4 Reset and System Initialization
The MCU has these reset sources:
• Power-on reset module (POR)
• External reset pin (RST)
• Computer operating properly module (COP)
• Low-voltage inhibit module (LVI)
• Illegal opcode
• Illegal address
All of these resets produce the vector $FFFE–FFFF ($FEFE–FEFF in monitor mode) and assert the
internal reset signal (IRST). IRST causes all registers to be returned to their default values and all
modules to be returned to their reset states.
An internal reset clears the SIM counter (see 13.5 SIM Counter), but an external reset does not. Each of
the resets sets a corresponding bit in the SIM reset status register (SRSR). See 13.8 SIM Registers.
13.4.1 External Pin Reset
The RST pin circuits include an internal pullup device. Pulling the asynchronous RST pin low halts all
processing. The PIN bit of the SIM reset status register (SRSR) is set as long as RST is held low for at
least the minimum tRL time. Figure 13-4 shows the relative timing. The RST pin function is only available
if the RSTEN bit is set in the CONFIG1 register.
BUSCLKX2
RST
ADDRESS BUS
VECT H
PC
VECT L
Figure 13-4. External Reset Timing
13.4.2 Active Resets from Internal Sources
The RST pin is initially setup as a general-purpose input after a POR. Setting the RSTEN bit in the
CONFIG1 register enables the pin for the reset function. This section assumes the RSTEN bit is set when
describing activity on the RST pin.
NOTE
For POR and LVI resets, the SIM cycles through 4096 BUSCLKX4 cycles
during which the SIM forces the RST pin low. The internal reset signal then
follows the sequence from the falling edge of RST shown in Figure 13-5.
The COP reset is asynchronous to the bus clock.
The active reset feature allows the part to issue a reset to peripherals and other chips within a system
built around the MCU.
MC68HC908QY/QT Family Data Sheet, Rev. 4
Freescale Semiconductor
111
System Integration Module (SIM)
All internal reset sources actively pull the RST pin low for 32 BUSCLKX4 cycles to allow resetting of
external peripherals. The internal reset signal IRST continues to be asserted for an additional 32 cycles
(see Figure 13-5). An internal reset can be caused by an illegal address, illegal opcode, COP time out,
LVI, or POR (see Figure 13-6).
IRST
RST PULLED LOW BY MCU
RST
32 CYCLES
32 CYCLES
BUSCLKX4
ADDRESS
BUS
VECTOR HIGH
Figure 13-5. Internal Reset Timing
ILLEGAL ADDRESS RST
ILLEGAL OPCODE RST
COPRST
POR
LVI
INTERNAL RESET
Figure 13-6. Sources of Internal Reset
Table 13-2. Reset Recovery Timing
Reset Recovery Type
Actual Number of Cycles
POR/LVI
4163 (4096 + 64 + 3)
All others
67 (64 + 3)
13.4.2.1 Power-On Reset
When power is first applied to the MCU, the power-on reset module (POR) generates a pulse to indicate
that power on has occurred. The SIM counter counts out 4096 BUSCLKX4 cycles. Sixty-four BUSCLKX4
cycles later, the CPU and memories are released from reset to allow the reset vector sequence to occur.
• At power on, the following events occur:
• A POR pulse is generated.
• The internal reset signal is asserted.
• The SIM enables the oscillator to drive BUSCLKX4.
• Internal clocks to the CPU and modules are held inactive for 4096 BUSCLKX4 cycles to allow
stabilization of the oscillator.
• The POR bit of the SIM reset status register (SRSR) is set
See Figure 13-7.
MC68HC908QY/QT Family Data Sheet, Rev. 4
112
Freescale Semiconductor
Reset and System Initialization
OSC1
PORRST
4096
CYCLES
32
CYCLES
32
CYCLES
BUSCLKX4
BUSCLKX2
RST
ADDRESS BUS
$FFFE
$FFFF
Figure 13-7. POR Recovery
13.4.2.2 Computer Operating Properly (COP) Reset
An input to the SIM is reserved for the COP reset signal. The overflow of the COP counter causes an
internal reset and sets the COP bit in the SIM reset status register (SRSR). The SIM actively pulls down
the RST pin for all internal reset sources.
To prevent a COP module time out, write any value to location $FFFF. Writing to location $FFFF clears
the COP counter and stages 12–5 of the SIM counter. The SIM counter output, which occurs at least
every (212 – 24) BUSCLKX4 cycles, drives the COP counter. The COP should be serviced as soon as
possible out of reset to guarantee the maximum amount of time before the first time out.
The COP module is disabled during a break interrupt with monitor mode when BDCOP bit is set in break
auxiliary register (BRKAR).
13.4.2.3 Illegal Opcode Reset
The SIM decodes signals from the CPU to detect illegal instructions. An illegal instruction sets the ILOP
bit in the SIM reset status register (SRSR) and causes a reset.
If the stop enable bit, STOP, in the mask option register is 0, the SIM treats the STOP instruction as an
illegal opcode and causes an illegal opcode reset. The SIM actively pulls down the RST pin for all internal
reset sources.
13.4.2.4 Illegal Address Reset
An opcode fetch from an unmapped address generates an illegal address reset. The SIM verifies that the
CPU is fetching an opcode prior to asserting the ILAD bit in the SIM reset status register (SRSR) and
resetting the MCU. A data fetch from an unmapped address does not generate a reset. The SIM actively
pulls down the RST pin for all internal reset sources. See Figure 2-1. Memory Map for memory ranges.
13.4.2.5 Low-Voltage Inhibit (LVI) Reset
The LVI asserts its output to the SIM when the VDD voltage falls to the LVI trip voltage VTRIPF. The LVI
bit in the SIM reset status register (SRSR) is set, and the external reset pin (RST) is held low while the
MC68HC908QY/QT Family Data Sheet, Rev. 4
Freescale Semiconductor
113
System Integration Module (SIM)
SIM counter counts out 4096 BUSCLKX4 cycles after VDD rises above VTRIPR. Sixty-four BUSCLKX4
cycles later, the CPU and memories are released from reset to allow the reset vector sequence to occur.
The SIM actively pulls down the (RST) pin for all internal reset sources.
13.5 SIM Counter
The SIM counter is used by the power-on reset module (POR) and in stop mode recovery to allow the
oscillator time to stabilize before enabling the internal bus (IBUS) clocks. The SIM counter also serves as
a prescaler for the computer operating properly module (COP). The SIM counter uses 12 stages for
counting, followed by a 13th stage that triggers a reset of SIM counters and supplies the clock for the COP
module. The SIM counter is clocked by the falling edge of BUSCLKX4.
13.5.1 SIM Counter During Power-On Reset
The power-on reset module (POR) detects power applied to the MCU. At power-on, the POR circuit
asserts the signal PORRST. Once the SIM is initialized, it enables the oscillator to drive the bus clock
state machine.
13.5.2 SIM Counter During Stop Mode Recovery
The SIM counter also is used for stop mode recovery. The STOP instruction clears the SIM counter. After
an interrupt, break, or reset, the SIM senses the state of the short stop recovery bit, SSREC, in the
configuration register 1 (CONFIG1). If the SSREC bit is a 1, then the stop recovery is reduced from the
normal delay of 4096 BUSCLKX4 cycles down to 32 BUSCLKX4 cycles. This is ideal for applications
using canned oscillators that do not require long start-up times from stop mode. External crystal
applications should use the full stop recovery time, that is, with SSREC cleared in the configuration
register 1 (CONFIG1).
13.5.3 SIM Counter and Reset States
External reset has no effect on the SIM counter (see 13.7.2 Stop Mode for details.) The SIM counter is
free-running after all reset states. See 13.4.2 Active Resets from Internal Sources for counter control and
internal reset recovery sequences.
13.6 Exception Control
Normal sequential program execution can be changed in three different ways:
1. Interrupts
a. Maskable hardware CPU interrupts
b. Non-maskable software interrupt instruction (SWI)
2. Reset
3. Break interrupts
13.6.1 Interrupts
An interrupt temporarily changes the sequence of program execution to respond to a particular event.
Figure 13-8 flow charts the handling of system interrupts.
MC68HC908QY/QT Family Data Sheet, Rev. 4
114
Freescale Semiconductor
Exception Control
FROM RESET
BREAK
INTERRUPT?
I BIT
SET?
YES
NO
YES
I BIT SET?
NO
IRQ
INTERRUPT?
YES
NO
TIMER
INTERRUPT?
YES
NO
STACK CPU REGISTERS
SET I BIT
LOAD PC WITH INTERRUPT VECTOR
(AS MANY INTERRUPTS AS EXIST ON CHIP)
FETCH NEXT
INSTRUCTION
SWI
INSTRUCTION?
YES
NO
RTI
INSTRUCTION?
YES
UNSTACK CPU REGISTERS
NO
EXECUTE INSTRUCTION
Figure 13-8. Interrupt Processing
MC68HC908QY/QT Family Data Sheet, Rev. 4
Freescale Semiconductor
115
System Integration Module (SIM)
Interrupts are latched, and arbitration is performed in the SIM at the start of interrupt processing. The
arbitration result is a constant that the CPU uses to determine which vector to fetch. Once an interrupt is
latched by the SIM, no other interrupt can take precedence, regardless of priority, until the latched
interrupt is serviced (or the I bit is cleared).
At the beginning of an interrupt, the CPU saves the CPU register contents on the stack and sets the
interrupt mask (I bit) to prevent additional interrupts. At the end of an interrupt, the RTI instruction recovers
the CPU register contents from the stack so that normal processing can resume. Figure 13-9 shows
interrupt entry timing. Figure 13-10 shows interrupt recovery timing.
MODULE
INTERRUPT
I BIT
ADDRESS BUS
DATA BUS
SP
DUMMY
DUMMY
SP – 1
SP – 2
PC – 1[7:0] PC – 1[15:8]
SP – 3
X
SP – 4
A
VECT H
CCR
VECT L
V DATA H
START ADDR
V DATA L
OPCODE
R/W
Figure 13-9. Interrupt Entry
MODULE
INTERRUPT
I BIT
ADDRESS BUS
SP – 4
DATA BUS
SP – 3
CCR
SP – 2
A
SP – 1
X
SP
PC
PC + 1
PC – 1[7:0] PC – 1[15:8] OPCODE
OPERAND
R/W
Figure 13-10. Interrupt Recovery
13.6.1.1 Hardware Interrupts
A hardware interrupt does not stop the current instruction. Processing of a hardware interrupt begins after
completion of the current instruction. When the current instruction is complete, the SIM checks all pending
hardware interrupts. If interrupts are not masked (I bit clear in the condition code register), and if the
corresponding interrupt enable bit is set, the SIM proceeds with interrupt processing; otherwise, the next
instruction is fetched and executed.
If more than one interrupt is pending at the end of an instruction execution, the highest priority interrupt is
serviced first. Figure 13-11 demonstrates what happens when two interrupts are pending. If an interrupt
is pending upon exit from the original interrupt service routine, the pending interrupt is serviced before the
LDA instruction is executed.
MC68HC908QY/QT Family Data Sheet, Rev. 4
116
Freescale Semiconductor
Exception Control
The LDA opcode is prefetched by both the INT1 and INT2 return-from-interrupt (RTI) instructions.
However, in the case of the INT1 RTI prefetch, this is a redundant operation.
NOTE
To maintain compatibility with the M6805 Family, the H register is not
pushed on the stack during interrupt entry. If the interrupt service routine
modifies the H register or uses the indexed addressing mode, software
should save the H register and then restore it prior to exiting the routine.
CLI
LDA #$FF
INT1
BACKGROUND ROUTINE
PSHH
INT1 INTERRUPT SERVICE ROUTINE
PULH
RTI
INT2
PSHH
INT2 INTERRUPT SERVICE ROUTINE
PULH
RTI
Figure 13-11. Interrupt Recognition Example
13.6.1.2 SWI Instruction
The SWI instruction is a non-maskable instruction that causes an interrupt regardless of the state of the
interrupt mask (I bit) in the condition code register.
NOTE
A software interrupt pushes PC onto the stack. A software interrupt does
not push PC – 1, as a hardware interrupt does.
13.6.2 Interrupt Status Registers
The flags in the interrupt status registers identify maskable interrupt sources. Table 13-3 summarizes the
interrupt sources and the interrupt status register flags that they set. The interrupt status registers can be
useful for debugging.
MC68HC908QY/QT Family Data Sheet, Rev. 4
Freescale Semiconductor
117
System Integration Module (SIM)
Table 13-3. Interrupt Sources
Flag
Mask(1)
INT
Register
Flag
Reset
—
—
—
$FFFE–$FFFF
SWI instruction
—
—
—
$FFFC–$FFFD
IRQ pin
IRQF
IMASK
IF1
$FFFA–$FFFB
Timer channel 0 interrupt
CH0F
CH0IE
IF3
$FFF6–$FFF7
Timer channel 1 interrupt
CH1F
CH1IE
IF4
$FFF4–$FFF5
TOF
TOIE
IF5
$FFF2–$FFF3
Keyboard interrupt
KEYF
IMASKK
IF14
$FFE0–$FFE1
ADC conversion complete interrupt
COCO
AIEN
IF15
$FFDE–$FFDF
Priority
Highest
Source
Timer overflow interrupt
Lowest
Vector
Address
1. The I bit in the condition code register is a global mask for all interrupt sources except the SWI
instruction.
13.6.2.1 Interrupt Status Register 1
Address: $FE04
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
IF5
IF4
IF3
0
IF1
0
0
Write:
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
R
= Reserved
Reset:
Figure 13-12. Interrupt Status Register 1 (INT1)
IF1 and IF3–IF5 — Interrupt Flags
These flags indicate the presence of interrupt requests from the sources shown in Table 13-3.
1 = Interrupt request present
0 = No interrupt request present
Bit 0, 1, 3, and 7 — Always read 0
13.6.2.2 Interrupt Status Register 2
Address: $FE05
Bit 7
6
5
4
3
2
1
Bit 0
Read:
IF14
0
0
0
0
0
0
0
Write:
R
R
R
R
R
R
R
R
Reset:
0
0
0
0
0
0
0
0
R
= Reserved
Figure 13-13. Interrupt Status Register 2 (INT2)
IF14 — Interrupt Flags
This flag indicates the presence of interrupt requests from the sources shown in Table 13-3.
1 = Interrupt request present
0 = No interrupt request present
Bit 0–6 — Always read 0
MC68HC908QY/QT Family Data Sheet, Rev. 4
118
Freescale Semiconductor
Low-Power Modes
13.6.2.3 Interrupt Status Register 3
Address: $FE06
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
0
0
0
0
0
0
IF15
Write:
R
R
R
R
R
R
R
R
Reset:
0
0
0
0
0
0
0
0
R
= Reserved
Figure 13-14. Interrupt Status Register 3 (INT3)
IF15 — Interrupt Flags
These flags indicate the presence of interrupt requests from the sources shown in Table 13-3.
1 = Interrupt request present
0 = No interrupt request present
Bit 1–7 — Always read 0
13.6.3 Reset
All reset sources always have equal and highest priority and cannot be arbitrated.
13.6.4 Break Interrupts
The break module can stop normal program flow at a software programmable break point by asserting its
break interrupt output. (See Chapter 15 Development Support.) The SIM puts the CPU into the break
state by forcing it to the SWI vector location. Refer to the break interrupt subsection of each module to
see how each module is affected by the break state.
13.6.5 Status Flag Protection in Break Mode
The SIM controls whether status flags contained in other modules can be cleared during break mode. The
user can select whether flags are protected from being cleared by properly initializing the break clear flag
enable bit (BCFE) in the break flag control register (BFCR).
Protecting flags in break mode ensures that set flags will not be cleared while in break mode. This
protection allows registers to be freely read and written during break mode without losing status flag
information.
Setting the BCFE bit enables the clearing mechanisms. Once cleared in break mode, a flag remains
cleared even when break mode is exited. Status flags with a two-step clearing mechanism — for example,
a read of one register followed by the read or write of another — are protected, even when the first step
is accomplished prior to entering break mode. Upon leaving break mode, execution of the second step
will clear the flag as normal.
13.7 Low-Power Modes
Executing the WAIT or STOP instruction puts the MCU in a low power- consumption mode for standby
situations. The SIM holds the CPU in a non-clocked state. The operation of each of these modes is
described below. Both STOP and WAIT clear the interrupt mask (I) in the condition code register, allowing
interrupts to occur.
MC68HC908QY/QT Family Data Sheet, Rev. 4
Freescale Semiconductor
119
System Integration Module (SIM)
13.7.1 Wait Mode
In wait mode, the CPU clocks are inactive while the peripheral clocks continue to run. Figure 13-15 shows
the timing for wait mode entry.
ADDRESS BUS
WAIT ADDR
DATA BUS
WAIT ADDR + 1
PREVIOUS DATA
SAME
SAME
NEXT OPCODE
SAME
SAME
R/W
NOTE: Previous data can be operand data or the WAIT opcode, depending on the last instruction.
Figure 13-15. Wait Mode Entry Timing
A module that is active during wait mode can wake up the CPU with an interrupt if the interrupt is enabled.
Stacking for the interrupt begins one cycle after the WAIT instruction during which the interrupt occurred.
In wait mode, the CPU clocks are inactive. Refer to the wait mode subsection of each module to see if the
module is active or inactive in wait mode. Some modules can be programmed to be active in wait mode.
Wait mode can also be exited by a reset (or break in emulation mode). A break interrupt during wait mode
sets the SIM break stop/wait bit, SBSW, in the break status register (BSR). If the COP disable bit, COPD,
in the configuration register is 0, then the computer operating properly module (COP) is enabled and
remains active in wait mode.
Figure 13-16 and Figure 13-17 show the timing for wait recovery.
ADDRESS BUS
DATA BUS
$6E0B
$A6
$A6
$6E0C
$A6
$01
$00FF
$0B
$00FE
$00FD
$00FC
$6E
EXITSTOPWAIT
NOTE: EXITSTOPWAIT = RST pin OR CPU interrupt OR break interrupt
Figure 13-16. Wait Recovery from Interrupt
32
CYCLES
$6E0B
ADDRESS BUS
DATA BUS
$A6
$A6
32
CYCLES
RSTVCT H
RSTVCT L
$A6
RST
BUSCLKX4
Figure 13-17. Wait Recovery from Internal Reset
MC68HC908QY/QT Family Data Sheet, Rev. 4
120
Freescale Semiconductor
Low-Power Modes
13.7.2 Stop Mode
In stop mode, the SIM counter is reset and the system clocks are disabled. An interrupt request from a
module can cause an exit from stop mode. Stacking for interrupts begins after the selected stop recovery
time has elapsed. Reset or break also causes an exit from stop mode.
The SIM disables the oscillator signals (BUSCLKX2 and BUSCLKX4) in stop mode, stopping the CPU
and peripherals. Stop recovery time is selectable using the SSREC bit in the configuration register 1
(CONFIG1). If SSREC is set, stop recovery is reduced from the normal delay of 4096 BUSCLKX4 cycles
down to 32. This is ideal for the internal oscillator, RC oscillator, and external oscillator options which do
not require long start-up times from stop mode.
NOTE
External crystal applications should use the full stop recovery time by
clearing the SSREC bit.
The SIM counter is held in reset from the execution of the STOP instruction until the beginning of stop
recovery. It is then used to time the recovery period.
Figure 13-18 shows stop mode entry timing and Figure 13-19 shows the stop mode recovery time from
interrupt or break.
NOTE
To minimize stop current, all pins configured as inputs should be driven to
a logic 1 or logic 0.
CPUSTOP
ADDRESS BUS
DATA BUS
STOP ADDR
STOP ADDR + 1
PREVIOUS DATA
SAME
NEXT OPCODE
SAME
SAME
SAME
R/W
NOTE: Previous data can be operand data or the STOP opcode, depending on the last instruction.
Figure 13-18. Stop Mode Entry Timing
STOP RECOVERY PERIOD
BUSCLKX4
INTERRUPT
ADDRESS BUS
STOP +1
STOP + 2
STOP + 2
SP
SP – 1
SP – 2
SP – 3
Figure 13-19. Stop Mode Recovery from Interrupt
MC68HC908QY/QT Family Data Sheet, Rev. 4
Freescale Semiconductor
121
System Integration Module (SIM)
13.8 SIM Registers
The SIM has three memory mapped registers. Table 13-4 shows the mapping of these registers.
Table 13-4. SIM Registers
Address
Register
Access Mode
$FE00
BSR
User
$FE01
SRSR
User
$FE03
BFCR
User
13.8.1 SIM Reset Status Register
The SRSR register contains flags that show the source of the last reset. The status register will
automatically clear after reading SRSR. A power-on reset sets the POR bit and clears all other bits in the
register. All other reset sources set the individual flag bits but do not clear the register. More than one
reset source can be flagged at any time depending on the conditions at the time of the internal or external
reset. For example, the POR and LVI bit can both be set if the power supply has a slow rise time.
Address: $FE01
Read:
Bit 7
6
5
4
3
2
1
Bit 0
POR
PIN
COP
ILOP
ILAD
MODRST
LVI
0
1
0
0
0
0
0
0
0
Write:
POR:
= Unimplemented
Figure 13-20. SIM Reset Status Register (SRSR)
POR — Power-On Reset Bit
1 = Last reset caused by POR circuit
0 = Read of SRSR
PIN — External Reset Bit
1 = Last reset caused by external reset pin (RST)
0 = POR or read of SRSR
COP — Computer Operating Properly Reset Bit
1 = Last reset caused by COP counter
0 = POR or read of SRSR
ILOP — Illegal Opcode Reset Bit
1 = Last reset caused by an illegal opcode
0 = POR or read of SRSR
ILAD — Illegal Address Reset Bit (illegal attempt to fetch an opcode from an unimplemented
address)
1 = Last reset caused by an opcode fetch from an illegal address
0 = POR or read of SRSR
MC68HC908QY/QT Family Data Sheet, Rev. 4
122
Freescale Semiconductor
SIM Registers
MODRST — Monitor Mode Entry Module Reset Bit
1 = Last reset caused by monitor mode entry when vector locations $FFFE and $FFFF are $FF after
POR while IRQ ≠ VTST
0 = POR or read of SRSR
LVI — Low Voltage Inhibit Reset Bit
1 = Last reset caused by LVI circuit
0 = POR or read of SRSR
13.8.2 Break Flag Control Register
The break control register (BFCR) contains a bit that enables software to clear status bits while the MCU
is in a break state.
Address: $FE03
Read:
Write:
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
BCFE
R
R
R
R
R
R
R
0
R
= Reserved
Figure 13-21. Break Flag Control Register (BFCR)
BCFE — Break Clear Flag Enable Bit
This read/write bit enables software to clear status bits by accessing status registers while the MCU is
in a break state. To clear status bits during the break state, the BCFE bit must be set.
1 = Status bits clearable during break
0 = Status bits not clearable during break
MC68HC908QY/QT Family Data Sheet, Rev. 4
Freescale Semiconductor
123
System Integration Module (SIM)
MC68HC908QY/QT Family Data Sheet, Rev. 4
124
Freescale Semiconductor
Chapter 14
Timer Interface Module (TIM)
14.1 Introduction
This section describes the timer interface module (TIM). The TIM is a two-channel timer that provides a
timing reference with input capture, output compare, and pulse-width-modulation functions. Figure 14-2
is a block diagram of the TIM.
14.2 Features
Features of the TIM include the following:
• Two input capture/output compare channels
– Rising-edge, falling-edge, or any-edge input capture trigger
– Set, clear, or toggle output compare action
• Buffered and unbuffered pulse width modulation (PWM) signal generation
• Programmable TIM clock input
– 7-frequency internal bus clock prescaler selection
– External TIM clock input
• Free-running or modulo up-count operation
• Toggle any channel pin on overflow
• TIM counter stop and reset bits
14.3 Pin Name Conventions
The TIM shares two input/output (I/O) pins with two port A I/O pins. The full names of the TIM I/O pins are
listed in Table 14-1. The generic pin name appear in the text that follows.
Table 14-1. Pin Name Conventions
TIM Generic Pin Names:
Full TIM Pin Names:
TCH0
TCH1
TCLK
PTA0/TCH0
PTA1/TCH1
PTA2/TCLK
MC68HC908QY/QT Family Data Sheet, Rev. 4
Freescale Semiconductor
125
Timer Interface Module (TIM)
PTA0/AD0/TCH0/KBI0
CLOCK
GENERATOR
(OSCILLATOR)
PTA
PTA2/IRQ/KBI2/TCLK
PTA3/RST/KBI3
DDRA
PTA1/AD1/TCH1/KBI1
SYSTEM INTEGRATION
MODULE
PTA4/OSC2/AD2/KBI4
PTA5/OSC1/AD3/KBI5
M68HC08 CPU
PTB
SINGLE INTERRUPT
MODULE
BREAK
MODULE
DDRB
PTB0
PTB1
PTB2
PTB3
PTB4
PTB5
PTB6
PTB7
POWER-ON RESET
MODULE
MC68HC908QY4 AND MC68HC908QT4
4096 BYTES
MC68HC908QY2, MC68HC908QY1,
MC68HC908QT2, AND MC68HC908QT1:
1536 BYTES
USER FLASH
8-BIT ADC
128 BYTES RAM
KEYBOARD INTERRUPT
MODULE
16-BIT TIMER
MODULE
COP
MODULE
VDD
POWER SUPPLY
VSS
MONITOR ROM
RST, IRQ: Pins have internal (about 30K Ohms) pull up
PTA[0:5]: High current sink and source capability
PTA[0:5]: Pins have programmable keyboard interrupt and pull up
PTB[0:7]: Not available on 8-pin devices – MC68HC908QT1, MC68HC908QT2, and MC68HC908QT4
ADC: Not available on the MC68HC908QY1 and MC68HC908QT1
Figure 14-1. Block Diagram Highlighting TIM Block and Pins
MC68HC908QY/QT Family Data Sheet, Rev. 4
126
Freescale Semiconductor
Functional Description
14.4 Functional Description
Figure 14-2 shows the structure of the TIM. The central component of the TIM is the 16-bit TIM counter
that can operate as a free-running counter or a modulo up-counter. The TIM counter provides the timing
reference for the input capture and output compare functions. The TIM counter modulo registers,
TMODH:TMODL, control the modulo value of the TIM counter. Software can read the TIM counter value
at any time without affecting the counting sequence.
The two TIM channels are programmable independently as input capture or output compare channels.
PTA2/IRQ/KBI2/TCLK
PRESCALER SELECT
INTERNAL
BUS CLOCK
PRESCALER
TSTOP
PS2
TRST
PS1
PS0
16-BIT COUNTER
TOF
TOIE
INTERRUPT
LOGIC
16-BIT COMPARATOR
TMODH:TMODL
TOV0
CHANNEL 0
ELS0B
ELS0A
CH0MAX
16-BIT COMPARATOR
TCH0H:TCH0L
PORT
LOGIC
TCH0
CH0F
16-BIT LATCH
CH0IE
MS0A
INTERRUPT
LOGIC
MS0B
INTERNAL BUS
TOV1
CHANNEL 1
ELS1B
ELS1A
CH1MAX
PORT
LOGIC
TCH1
16-BIT COMPARATOR
TCH1H:TCH1L
CH1F
16-BIT LATCH
MS1A
CH1IE
INTERRUPT
LOGIC
Figure 14-2. TIM Block Diagram
MC68HC908QY/QT Family Data Sheet, Rev. 4
Freescale Semiconductor
127
Timer Interface Module (TIM)
Addr.
$0020
$0021
$0022
$0023
$0024
$0025
$0026
$0027
$0028
$0029
$002A
Register Name
TIM Status and Control
Register (TSC)
See page 134.
TIM Counter Register High
(TCNTH)
See page 135.
TIM Counter Register Low
(TCNTL)
See page 135.
TIM Counter Modulo Register
High (TMODH)
See page 136.
TIM Counter Modulo Register
Low (TMODL)
See page 136.
TIM Channel 0 Status and
Control Register (TSC0)
See page 137.
TIM Channel 0 Register High
(TCH0H)
See page 139.
TIM Channel 0 Register Low
(TCH0L)
See page 139.
TIM Channel 1 Status and
Control Register (TSC1)
See page 137.
TIM Channel 1 Register High
(TCH1H)
See page 139.
TIM Channel 1 Register Low
(TCH1L)
See page 139.
Bit 7
Read:
TOF
Write:
0
Reset:
Read:
6
5
4
3
0
0
2
1
Bit 0
PS2
PS1
PS0
TOIE
TSTOP
0
0
1
0
0
0
0
0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Reset:
0
0
0
0
0
0
0
0
Read:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
1
1
1
1
1
1
1
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset:
1
1
1
1
1
1
1
1
Read:
CH0F
Write:
0
CH0IE
MS0B
MS0A
ELS0B
ELS0A
TOV0
CH0MAX
Reset:
0
0
0
0
0
0
0
0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 2
Bit 1
Bit 0
TRST
Write:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Read:
Write:
Reset:
Read:
Write:
Indeterminate after reset
Bit 7
Bit 6
Bit 5
Reset:
CH1F
Write:
0
Reset:
0
0
Bit 15
Bit 14
Write:
CH1IE
0
MS1A
ELS1B
ELS1A
TOV1
CH1MAX
0
0
0
0
0
0
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 2
Bit 1
Bit 0
Reset:
Read:
Write:
Bit 3
Indeterminate after reset
Read:
Read:
Bit 4
Indeterminate after reset
Bit 7
Bit 6
Bit 5
Reset:
Bit 4
Bit 3
Indeterminate after reset
= Unimplemented
Figure 14-3. TIM I/O Register Summary
MC68HC908QY/QT Family Data Sheet, Rev. 4
128
Freescale Semiconductor
Functional Description
14.4.1 TIM Counter Prescaler
The TIM clock source is one of the seven prescaler outputs or the TIM clock pin, TCLK. The prescaler
generates seven clock rates from the internal bus clock. The prescaler select bits, PS[2:0], in the TIM
status and control register (TSC) select the TIM clock source.
14.4.2 Input Capture
With the input capture function, the TIM can capture the time at which an external event occurs. When an
active edge occurs on the pin of an input capture channel, the TIM latches the contents of the TIM counter
into the TIM channel registers, TCHxH:TCHxL. The polarity of the active edge is programmable. Input
captures can generate TIM central processor unit (CPU) interrupt requests.
14.4.3 Output Compare
With the output compare function, the TIM can generate a periodic pulse with a programmable polarity,
duration, and frequency. When the counter reaches the value in the registers of an output compare
channel, the TIM can set, clear, or toggle the channel pin. Output compares can generate TIM CPU
interrupt requests.
14.4.3.1 Unbuffered Output Compare
Any output compare channel can generate unbuffered output compare pulses as described in 14.4.3
Output Compare. The pulses are unbuffered because changing the output compare value requires writing
the new value over the old value currently in the TIM channel registers.
An unsynchronized write to the TIM channel registers to change an output compare value could cause
incorrect operation for up to two counter overflow periods. For example, writing a new value before the
counter reaches the old value but after the counter reaches the new value prevents any compare during
that counter overflow period. Also, using a TIM overflow interrupt routine to write a new, smaller output
compare value may cause the compare to be missed. The TIM may pass the new value before it is written.
Use the following methods to synchronize unbuffered changes in the output compare value on channel x:
• When changing to a smaller value, enable channel x output compare interrupts and write the new
value in the output compare interrupt routine. The output compare interrupt occurs at the end of
the current output compare pulse. The interrupt routine has until the end of the counter overflow
period to write the new value.
• When changing to a larger output compare value, enable TIM overflow interrupts and write the new
value in the TIM overflow interrupt routine. The TIM overflow interrupt occurs at the end of the
current counter overflow period. Writing a larger value in an output compare interrupt routine (at
the end of the current pulse) could cause two output compares to occur in the same counter
overflow period.
14.4.3.2 Buffered Output Compare
Channels 0 and 1 can be linked to form a buffered output compare channel whose output appears on the
TCH0 pin. The TIM channel registers of the linked pair alternately control the output.
Setting the MS0B bit in TIM channel 0 status and control register (TSC0) links channel 0 and channel 1.
The output compare value in the TIM channel 0 registers initially controls the output on the TCH0 pin.
Writing to the TIM channel 1 registers enables the TIM channel 1 registers to synchronously control the
output after the TIM overflows. At each subsequent overflow, the TIM channel registers (0 or 1) that
MC68HC908QY/QT Family Data Sheet, Rev. 4
Freescale Semiconductor
129
Timer Interface Module (TIM)
control the output are the ones written to last. TSC0 controls and monitors the buffered output compare
function, and TIM channel 1 status and control register (TSC1) is unused. While the MS0B bit is set, the
channel 1 pin, TCH1, is available as a general-purpose I/O pin.
NOTE
In buffered output compare operation, do not write new output compare
values to the currently active channel registers. User software should track
the currently active channel to prevent writing a new value to the active
channel. Writing to the active channel registers is the same as generating
unbuffered output compares.
14.4.4 Pulse Width Modulation (PWM)
By using the toggle-on-overflow feature with an output compare channel, the TIM can generate a PWM
signal. The value in the TIM counter modulo registers determines the period of the PWM signal. The
channel pin toggles when the counter reaches the value in the TIM counter modulo registers. The time
between overflows is the period of the PWM signal
As Figure 14-4 shows, the output compare value in the TIM channel registers determines the pulse width
of the PWM signal. The time between overflow and output compare is the pulse width. Program the TIM
to clear the channel pin on output compare if the state of the PWM pulse is logic 1 (ELSxA = 0). Program
the TIM to set the pin if the state of the PWM pulse is logic 0 (ELSxA = 1).
The value in the TIM counter modulo registers and the selected prescaler output determines the
frequency of the PWM output The frequency of an 8-bit PWM signal is variable in 256 increments. Writing
$00FF (255) to the TIM counter modulo registers produces a PWM period of 256 times the internal bus
clock period if the prescaler select value is 000. See 14.9.1 TIM Status and Control Register.
The value in the TIM channel registers determines the pulse width of the PWM output. The pulse width of
an 8-bit PWM signal is variable in 256 increments. Writing $0080 (128) to the TIM channel registers
produces a duty cycle of 128/256 or 50%.
OVERFLOW
OVERFLOW
OVERFLOW
PERIOD
POLARITY = 1
(ELSxA = 0)
TCHx
PULSE
WIDTH
POLARITY = 0
(ELSxA = 1)
TCHx
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
Figure 14-4. PWM Period and Pulse Width
MC68HC908QY/QT Family Data Sheet, Rev. 4
130
Freescale Semiconductor
Functional Description
14.4.4.1 Unbuffered PWM Signal Generation
Any output compare channel can generate unbuffered PWM pulses as described in 14.4.4 Pulse Width
Modulation (PWM). The pulses are unbuffered because changing the pulse width requires writing the new
pulse width value over the old value currently in the TIM channel registers.
An unsynchronized write to the TIM channel registers to change a pulse width value could cause incorrect
operation for up to two PWM periods. For example, writing a new value before the counter reaches the
old value but after the counter reaches the new value prevents any compare during that PWM period.
Also, using a TIM overflow interrupt routine to write a new, smaller pulse width value may cause the
compare to be missed. The TIM may pass the new value before it is written.
Use the following methods to synchronize unbuffered changes in the PWM pulse width on channel x:
• When changing to a shorter pulse width, enable channel x output compare interrupts and write the
new value in the output compare interrupt routine. The output compare interrupt occurs at the end
of the current pulse. The interrupt routine has until the end of the PWM period to write the new
value.
• When changing to a longer pulse width, enable TIM overflow interrupts and write the new value in
the TIM overflow interrupt routine. The TIM overflow interrupt occurs at the end of the current PWM
period. Writing a larger value in an output compare interrupt routine (at the end of the current pulse)
could cause two output compares to occur in the same PWM period.
NOTE
In PWM signal generation, do not program the PWM channel to toggle on
output compare. Toggling on output compare prevents reliable 0% duty
cycle generation and removes the ability of the channel to self-correct in the
event of software error or noise. Toggling on output compare also can
cause incorrect PWM signal generation when changing the PWM pulse
width to a new, much larger value.
14.4.4.2 Buffered PWM Signal Generation
Channels 0 and 1 can be linked to form a buffered PWM channel whose output appears on the TCH0 pin.
The TIM channel registers of the linked pair alternately control the pulse width of the output.
Setting the MS0B bit in TIM channel 0 status and control register (TSC0) links channel 0 and channel 1.
The TIM channel 0 registers initially control the pulse width on the TCH0 pin. Writing to the TIM channel
1 registers enables the TIM channel 1 registers to synchronously control the pulse width at the beginning
of the next PWM period. At each subsequent overflow, the TIM channel registers (0 or 1) that control the
pulse width are the ones written to last. TSC0 controls and monitors the buffered PWM function, and TIM
channel 1 status and control register (TSC1) is unused. While the MS0B bit is set, the channel 1 pin,
TCH1, is available as a general-purpose I/O pin.
NOTE
In buffered PWM signal generation, do not write new pulse width values to
the currently active channel registers. User software should track the
currently active channel to prevent writing a new value to the active
channel. Writing to the active channel registers is the same as generating
unbuffered PWM signals.
MC68HC908QY/QT Family Data Sheet, Rev. 4
Freescale Semiconductor
131
Timer Interface Module (TIM)
14.4.4.3 PWM Initialization
To ensure correct operation when generating unbuffered or buffered PWM signals, use the following
initialization procedure:
1. In the TIM status and control register (TSC):
a. Stop the TIM counter by setting the TIM stop bit, TSTOP.
b. Reset the TIM counter and prescaler by setting the TIM reset bit, TRST.
2. In the TIM counter modulo registers (TMODH:TMODL), write the value for the required PWM
period.
3. In the TIM channel x registers (TCHxH:TCHxL), write the value for the required pulse width.
4. In TIM channel x status and control register (TSCx):
a. Write 0:1 (for unbuffered output compare or PWM signals) or 1:0 (for buffered output compare
or PWM signals) to the mode select bits, MSxB:MSxA. See Table 14-3.
b. Write 1 to the toggle-on-overflow bit, TOVx.
c. Write 1:0 (polarity 1 — to clear output on compare) or 1:1 (polarity 0 — to set output on
compare) to the edge/level select bits, ELSxB:ELSxA. The output action on compare must
force the output to the complement of the pulse width level. See Table 14-3.
NOTE
In PWM signal generation, do not program the PWM channel to toggle on
output compare. Toggling on output compare prevents reliable 0% duty
cycle generation and removes the ability of the channel to self-correct in the
event of software error or noise. Toggling on output compare can also
cause incorrect PWM signal generation when changing the PWM pulse
width to a new, much larger value.
5. In the TIM status control register (TSC), clear the TIM stop bit, TSTOP.
Setting MS0B links channels 0 and 1 and configures them for buffered PWM operation. The TIM channel
0 registers (TCH0H:TCH0L) initially control the buffered PWM output. TIM status control register 0
(TSCR0) controls and monitors the PWM signal from the linked channels. MS0B takes priority over MS0A.
Clearing the toggle-on-overflow bit, TOVx, inhibits output toggles on TIM overflows. Subsequent output
compares try to force the output to a state it is already in and have no effect. The result is a 0% duty cycle
output.
Setting the channel x maximum duty cycle bit (CHxMAX) and setting the TOVx bit generates a 100% duty
cycle output. See 14.9.4 TIM Channel Status and Control Registers.
14.5 Interrupts
The following TIM sources can generate interrupt requests:
• TIM overflow flag (TOF) — The TOF bit is set when the TIM counter reaches the modulo value
programmed in the TIM counter modulo registers. The TIM overflow interrupt enable bit, TOIE,
enables TIM overflow CPU interrupt requests. TOF and TOIE are in the TIM status and control
register.
• TIM channel flags (CH1F:CH0F) — The CHxF bit is set when an input capture or output compare
occurs on channel x. Channel x TIM CPU interrupt requests are controlled by the channel x
interrupt enable bit, CHxIE. Channel x TIM CPU interrupt requests are enabled when CHxIE =1.
CHxF and CHxIE are in the TIM channel x status and control register.
MC68HC908QY/QT Family Data Sheet, Rev. 4
132
Freescale Semiconductor
Wait Mode
14.6 Wait Mode
The WAIT instruction puts the MCU in low power-consumption standby mode.
The TIM remains active after the execution of a WAIT instruction. In wait mode the TIM registers are not
accessible by the CPU. Any enabled CPU interrupt request from the TIM can bring the MCU out of wait
mode.
If TIM functions are not required during wait mode, reduce power consumption by stopping the TIM before
executing the WAIT instruction.
14.7 TIM During Break Interrupts
A break interrupt stops the TIM counter.
The system integration module (SIM) controls whether status bits in other modules can be cleared during
the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear status
bits during the break state. See 13.8.2 Break Flag Control Register.
To allow software to clear status bits during a break interrupt, write a 1 to the BCFE bit. If a status bit is
cleared during the break state, it remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a 0 to the BCFE bit. With BCFE at 0 (its default state),
software can read and write I/O registers during the break state without affecting status bits. Some status
bits have a two-step read/write clearing procedure. If software does the first step on such a bit before the
break, the bit cannot change during the break state as long as BCFE is at 0. After the break, doing the
second step clears the status bit.
14.8 Input/Output Signals
Port A shares three of its pins with the TIM. Two TIM channel I/O pins are PTA0/TCH0 and PTA1/TCH1
and an alternate clock source is PTA2/TCLK.
14.8.1 TIM Clock Pin (PTA2/TCLK)
PTA2/TCLK is an external clock input that can be the clock source for the TIM counter instead of the
prescaled internal bus clock. Select the PTA2/TCLK input by writing 1s to the three prescaler select bits,
PS[2–0]. (See 14.9.1 TIM Status and Control Register.) When the PTA2/TCLK pin is the TIM clock input,
it is an input regardless of port pin initialization.
14.8.2 TIM Channel I/O Pins (PTA0/TCH0 and PTA1/TCH1)
Each channel I/O pin is programmable independently as an input capture pin or an output compare pin.
PTA0/TCH0 can be configured as a buffered output compare or buffered PWM pin.
14.9 Input/Output Registers
The following I/O registers control and monitor operation of the TIM:
• TIM status and control register (TSC)
• TIM counter registers (TCNTH:TCNTL)
• TIM counter modulo registers (TMODH:TMODL)
• TIM channel status and control registers (TSC0 and TSC1)
• TIM channel registers (TCH0H:TCH0L and TCH1H:TCH1L)
MC68HC908QY/QT Family Data Sheet, Rev. 4
Freescale Semiconductor
133
Timer Interface Module (TIM)
14.9.1 TIM Status and Control Register
The TIM status and control register (TSC) does the following:
• Enables TIM overflow interrupts
• Flags TIM overflows
• Stops the TIM counter
• Resets the TIM counter
• Prescales the TIM counter clock
Address: $0020
Bit 7
Read:
TOF
Write:
0
Reset:
0
6
5
TOIE
TSTOP
0
1
4
3
0
0
TRST
0
0
2
1
Bit 0
PS2
PS1
PS0
0
0
0
= Unimplemented
Figure 14-5. TIM Status and Control Register (TSC)
TOF — TIM Overflow Flag Bit
This read/write flag is set when the TIM counter reaches the modulo value programmed in the TIM
counter modulo registers. Clear TOF by reading the TIM status and control register when TOF is set
and then writing a 0 to TOF. If another TIM overflow occurs before the clearing sequence is complete,
then writing 0 to TOF has no effect. Therefore, a TOF interrupt request cannot be lost due to
inadvertent clearing of TOF. Reset clears the TOF bit. Writing a 1 to TOF has no effect.
1 = TIM counter has reached modulo value
0 = TIM counter has not reached modulo value
TOIE — TIM Overflow Interrupt Enable Bit
This read/write bit enables TIM overflow interrupts when the TOF bit becomes set. Reset clears the
TOIE bit.
1 = TIM overflow interrupts enabled
0 = TIM overflow interrupts disabled
TSTOP — TIM Stop Bit
This read/write bit stops the TIM counter. Counting resumes when TSTOP is cleared. Reset sets the
TSTOP bit, stopping the TIM counter until software clears the TSTOP bit.
1 = TIM counter stopped
0 = TIM counter active
NOTE
Do not set the TSTOP bit before entering wait mode if the TIM is required
to exit wait mode. When the TSTOP bit is set and the timer is configured for
input capture operation, input captures are inhibited until the TSTOP bit is
cleared.
When using TSTOP to stop the timer counter, see if any timer flags are set.
If a timer flag is set, it must be cleared by clearing TSTOP, then clearing the
flag, then setting TSTOP again.
MC68HC908QY/QT Family Data Sheet, Rev. 4
134
Freescale Semiconductor
Input/Output Registers
TRST — TIM Reset Bit
Setting this write-only bit resets the TIM counter and the TIM prescaler. Setting TRST has no effect on
any other registers. Counting resumes from $0000. TRST is cleared automatically after the TIM
counter is reset and always reads as a 0. Reset clears the TRST bit.
1 = Prescaler and TIM counter cleared
0 = No effect
NOTE
Setting the TSTOP and TRST bits simultaneously stops the TIM counter at
a value of $0000.
PS[2:0] — Prescaler Select Bits
These read/write bits select either the PTA2/TCLK pin or one of the seven prescaler outputs as the
input to the TIM counter as Table 14-2 shows. Reset clears the PS[2:0] bits.
Table 14-2. Prescaler Selection
PS2
0
0
0
0
1
1
1
1
PS1
0
0
1
1
0
0
1
1
PS0
0
1
0
1
0
1
0
1
TIM Clock Source
Internal bus clock ÷ 1
Internal bus clock ÷ 2
Internal bus clock ÷ 4
Internal bus clock ÷ 8
Internal bus clock ÷ 16
Internal bus clock ÷ 32
Internal bus clock ÷ 64
PTA2/TCLK
14.9.2 TIM Counter Registers
The two read-only TIM counter registers contain the high and low bytes of the value in the TIM counter.
Reading the high byte (TCNTH) latches the contents of the low byte (TCNTL) into a buffer. Subsequent
reads of TCNTH do not affect the latched TCNTL value until TCNTL is read. Reset clears the TIM counter
registers. Setting the TIM reset bit (TRST) also clears the TIM counter registers.
NOTE
If you read TCNTH during a break interrupt, be sure to unlatch TCNTL by
reading TCNTL before exiting the break interrupt. Otherwise, TCNTL
retains the value latched during the break.
Address: $0021
Bit 7
Read:
Bit 15
Write:
Reset:
0
TCNTH
6
Bit 14
Address: $0022
Bit 7
Read:
Bit 7
Write:
Reset:
0
TCNTL
0
6
Bit 6
5
Bit 13
4
Bit 12
3
Bit 11
2
Bit 10
1
Bit 9
Bit 0
Bit 8
0
0
0
0
0
0
5
Bit 5
4
Bit 4
3
Bit 3
2
Bit 2
1
Bit 1
Bit 0
Bit 0
0
0
0
0
0
0
0
= Unimplemented
Figure 14-6. TIM Counter Registers (TCNTH:TCNTL)
MC68HC908QY/QT Family Data Sheet, Rev. 4
Freescale Semiconductor
135
Timer Interface Module (TIM)
14.9.3 TIM Counter Modulo Registers
The read/write TIM modulo registers contain the modulo value for the TIM counter. When the TIM counter
reaches the modulo value, the overflow flag (TOF) becomes set, and the TIM counter resumes counting
from $0000 at the next timer clock. Writing to the high byte (TMODH) inhibits the TOF bit and overflow
interrupts until the low byte (TMODL) is written. Reset sets the TIM counter modulo registers.
Address: $0023
Read:
Write:
Reset:
6
5
4
3
2
1
Bit 0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
1
1
1
1
1
1
1
1
Address: $0024
Read:
Write:
Reset:
TMODH
Bit 7
TMODL
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
1
1
1
1
1
1
Figure 14-7. TIM Counter Modulo Registers (TMODH:TMODL)
NOTE
Reset the TIM counter before writing to the TIM counter modulo registers.
14.9.4 TIM Channel Status and Control Registers
Each of the TIM channel status and control registers does the following:
• Flags input captures and output compares
• Enables input capture and output compare interrupts
• Selects input capture, output compare, or PWM operation
• Selects high, low, or toggling output on output compare
• Selects rising edge, falling edge, or any edge as the active input capture trigger
• Selects output toggling on TIM overflow
• Selects 0% and 100% PWM duty cycle
• Selects buffered or unbuffered output compare/PWM operation
MC68HC908QY/QT Family Data Sheet, Rev. 4
136
Freescale Semiconductor
Input/Output Registers
Address: $0025
Bit 7
TSC0
6
5
4
3
2
1
Bit 0
CH0IE
MS0B
MS0A
ELS0B
ELS0A
TOV0
CH0MAX
0
0
0
0
0
0
5
4
3
2
1
Bit 0
MS1A
ELS1B
ELS1A
TOV1
CH1MAX
0
0
0
0
0
Read:
CH0F
Write:
0
Reset:
0
0
Address: $0028
TSC1
Bit 7
Read:
CH1F
Write:
0
Reset:
0
6
CH1IE
0
0
0
= Unimplemented
Figure 14-8. TIM Channel Status and Control
Registers (TSC0:TSC1)
CHxF — Channel x Flag Bit
When channel x is an input capture channel, this read/write bit is set when an active edge occurs on
the channel x pin. When channel x is an output compare channel, CHxF is set when the value in the
TIM counter registers matches the value in the TIM channel x registers.
Clear CHxF by reading the TIM channel x status and control register with CHxF set and then writing
a 0 to CHxF. If another interrupt request occurs before the clearing sequence is complete, then writing
a 0 to CHxF has no effect. Therefore, an interrupt request cannot be lost due to inadvertent clearing
of CHxF.
Reset clears the CHxF bit. Writing a 1 to CHxF has no effect.
1 = Input capture or output compare on channel x
0 = No input capture or output compare on channel x
CHxIE — Channel x Interrupt Enable Bit
This read/write bit enables TIM CPU interrupt service requests on channel x. Reset clears the CHxIE
bit.
1 = Channel x CPU interrupt requests enabled
0 = Channel x CPU interrupt requests disabled
MSxB — Mode Select Bit B
This read/write bit selects buffered output compare/PWM operation. MSxB exists only in the TIM
channel 0 status and control register.
Setting MS0B disables the channel 1 status and control register and reverts TCH1 to general-purpose
I/O.
Reset clears the MSxB bit.
1 = Buffered output compare/PWM operation enabled
0 = Buffered output compare/PWM operation disabled
MSxA — Mode Select Bit A
When ELSxB:A ≠ 00, this read/write bit selects either input capture operation or unbuffered output
compare/PWM operation. See Table 14-3.
1 = Unbuffered output compare/PWM operation
0 = Input capture operation
MC68HC908QY/QT Family Data Sheet, Rev. 4
Freescale Semiconductor
137
Timer Interface Module (TIM)
When ELSxB:A = 00, this read/write bit selects the initial output level of the TCHx pin (see Table 14-3).
Reset clears the MSxA bit.
1 = Initial output level low
0 = Initial output level high
NOTE
Before changing a channel function by writing to the MSxB or MSxA bit, set
the TSTOP and TRST bits in the TIM status and control register (TSC).
Table 14-3. Mode, Edge, and Level Selection
MSxB
MSxA
ELSxB
ELSxA
X
0
0
0
X
1
0
0
Mode
Output preset
Configuration
Pin under port control; initial output level high
Pin under port control; initial output level low
0
0
0
1
0
0
1
0
0
0
1
1
Capture on rising or falling edge
0
1
0
0
Software compare only
0
1
0
1
0
1
1
0
0
1
1
1
1
X
0
1
1
X
1
0
1
X
1
1
Capture on rising edge only
Input capture
Output compare
or PWM
Capture on falling edge only
Toggle output on compare
Clear output on compare
Set output on compare
Buffered output
compare or
buffered PWM
Toggle output on compare
Clear output on compare
Set output on compare
ELSxB and ELSxA — Edge/Level Select Bits
When channel x is an input capture channel, these read/write bits control the active edge-sensing logic
on channel x.
When channel x is an output compare channel, ELSxB and ELSxA control the channel x output
behavior when an output compare occurs.
When ELSxB and ELSxA are both clear, channel x is not connected to an I/O port, and pin TCHx is
available as a general-purpose I/O pin. Table 14-3 shows how ELSxB and ELSxA work. Reset clears
the ELSxB and ELSxA bits.
NOTE
After initially enabling a TIM channel register for input capture operation
and selecting the edge sensitivity, clear CHxF to ignore any erroneous
edge detection flags.
TOVx — Toggle-On-Overflow Bit
When channel x is an output compare channel, this read/write bit controls the behavior of the channel
x output when the TIM counter overflows. When channel x is an input capture channel, TOVx has no
effect Reset clears the TOVx bit.
1 = Channel x pin toggles on TIM counter overflow.
0 = Channel x pin does not toggle on TIM counter overflow.
NOTE
When TOVx is set, a TIM counter overflow takes precedence over a
channel x output compare if both occur at the same time.
MC68HC908QY/QT Family Data Sheet, Rev. 4
138
Freescale Semiconductor
Input/Output Registers
CHxMAX — Channel x Maximum Duty Cycle Bit
When the TOVx bit is at a 1, setting the CHxMAX bit forces the duty cycle of buffered and unbuffered
PWM signals to 100%. As Figure 14-9 shows, the CHxMAX bit takes effect in the cycle after it is set
or cleared. The output stays at the 100% duty cycle level until the cycle after CHxMAX is cleared.
OVERFLOW
OVERFLOW
OVERFLOW
OVERFLOW
OVERFLOW
PERIOD
TCHx
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
CHxMAX
Figure 14-9. CHxMAX Latency
14.9.5 TIM Channel Registers
These read/write registers contain the captured TIM counter value of the input capture function or the
output compare value of the output compare function. The state of the TIM channel registers after reset
is unknown.
In input capture mode (MSxB:MSxA = 0:0), reading the high byte of the TIM channel x registers (TCHxH)
inhibits input captures until the low byte (TCHxL) is read.
In output compare mode (MSxB:MSxA ≠ 0:0), writing to the high byte of the TIM channel x registers
(TCHxH) inhibits output compares until the low byte (TCHxL) is written.
Address: $0026
Bit 7
Read:
Bit 15
Write:
Reset:
TCH0H
6
Address: $0027
Bit 7
Read:
Bit 7
Write:
Reset:
TCH0L
6
Address: $0029
Bit 7
Read:
Bit 15
Write:
Reset:
TCH1H
6
Address: $02A
Bit 7
Read:
Bit 7
Write:
Reset:
TCH1L
6
Bit 14
5
4
3
2
1
Bit 0
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Indeterminate after reset
Bit 6
5
4
3
2
1
Bit 0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Indeterminate after reset
Bit 14
5
4
3
2
1
Bit 0
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Indeterminate after reset
Bit 6
5
4
3
2
1
Bit 0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Indeterminate after reset
Figure 14-10. TIM Channel Registers (TCH0H/L:TCH1H/L)
MC68HC908QY/QT Family Data Sheet, Rev. 4
Freescale Semiconductor
139
Timer Interface Module (TIM)
MC68HC908QY/QT Family Data Sheet, Rev. 4
140
Freescale Semiconductor
Chapter 15
Development Support
15.1 Introduction
This section describes the break module, the monitor read-only memory (MON), and the monitor mode
entry methods.
15.2 Break Module (BRK)
The break module can generate a break interrupt that stops normal program flow at a defined address to
enter a background program.
Features include:
• Accessible input/output (I/O) registers during the break Interrupt
• Central processor unit (CPU) generated break interrupts
• Software-generated break interrupts
• Computer operating properly (COP) disabling during break interrupts
15.2.1 Functional Description
When the internal address bus matches the value written in the break address registers, the break module
issues a breakpoint signal (BKPT) to the system integration module (SIM). The SIM then causes the CPU
to load the instruction register with a software interrupt instruction (SWI). The program counter vectors to
$FFFC and $FFFD ($FEFC and $FEFD in monitor mode).
The following events can cause a break interrupt to occur:
• A CPU generated address (the address in the program counter) matches the contents of the break
address registers.
• Software writes a 1 to the BRKA bit in the break status and control register.
When a CPU generated address matches the contents of the break address registers, the break interrupt
is generated. A return-from-interrupt instruction (RTI) in the break routine ends the break interrupt and
returns the microcontroller unit (MCU) to normal operation.
Figure 15-2 shows the structure of the break module.
Figure 15-3 provides a summary of the I/O registers.
MC68HC908QY/QT Family Data Sheet, Rev. 4
Freescale Semiconductor
141
Development Support
PTA0/AD0/TCH0/KBI0
CLOCK
GENERATOR
(OSCILLATOR)
PTA
PTA2/IRQ/KBI2/TCLK
PTA3/RST/KBI3
DDRA
PTA1/AD1/TCH1/KBI1
SYSTEM INTEGRATION
MODULE
PTA4/OSC2/AD2/KBI4
PTA5/OSC1/AD3/KBI5
M68HC08 CPU
SINGLE INTERRUPT
MODULE
BREAK
MODULE
DDRB
PTB
PTB0
PTB1
PTB2
PTB3
PTB4
PTB5
PTB6
PTB7
POWER-ON RESET
MODULE
8-BIT ADC
128 BYTES RAM
MC68HC908QY4 AND MC68HC908QT4
4096 BYTES
MC68HC908QY2, MC68HC908QY1,
MC68HC908QT2, AND MC68HC908QT1:
1536 BYTES
USER FLASH
KEYBOARD INTERRUPT
MODULE
16-BIT TIMER
MODULE
COP
MODULE
VDD
POWER SUPPLY
MONITOR ROM
VSS
RST, IRQ: Pins have internal (about 30K Ohms) pull up
PTA[0:5]: High current sink and source capability
PTA[0:5]: Pins have programmable keyboard interrupt and pull up
PTB[0:7]: Not available on 8-pin devices – MC68HC908QT1, MC68HC908QT2, and MC68HC908QT4
ADC: Not available on the MC68HC908QY1 and MC68HC908QT1
Figure 15-1. Block Diagram Highlighting BRK and MON Blocks
MC68HC908QY/QT Family Data Sheet, Rev. 4
142
Freescale Semiconductor
Break Module (BRK)
ADDRESS BUS[15:8]
BREAK ADDRESS REGISTER HIGH
8-BIT COMPARATOR
ADDRESS BUS[15:0]
BKPT
(TO SIM)
CONTROL
8-BIT COMPARATOR
BREAK ADDRESS REGISTER LOW
ADDRESS BUS[7:0]
Figure 15-2. Break Module Block Diagram
Addr.
Register Name
$FE00
Break Status Register Read:
(BSR) Write:
See page 146. Reset:
$FE02
Break Auxiliary Register Read:
(BRKAR) Write:
See page 146. Reset:
$FE03
$FE09
Break Flag Control Read:
Register (BFCR) Write:
See page 147. Reset:
Break Address High Read:
Register (BRKH) Write:
See page 145. Reset:
$FE0A
Break Address Low Read:
Register (BRKL) Write:
See page 145. Reset:
$FE0B
Break Status and Control Read:
Register (BRKSCR) Write:
See page 145. Reset:
1. Writing a 0 clears SBSW.
Bit 7
6
5
4
3
2
1
R
R
R
R
R
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BCFE
R
R
R
R
R
R
R
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
0
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
SBSW
Note(1)
Bit 0
R
0
BDCOP
0
BRKE
BRKA
0
0
= Unimplemented
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
= Reserved
Figure 15-3. Break I/O Register Summary
MC68HC908QY/QT Family Data Sheet, Rev. 4
Freescale Semiconductor
143
Development Support
When the internal address bus matches the value written in the break address registers or when software
writes a 1 to the BRKA bit in the break status and control register, the CPU starts a break interrupt by:
• Loading the instruction register with the SWI instruction
• Loading the program counter with $FFFC and $FFFD ($FEFC and $FEFD in monitor mode)
The break interrupt timing is:
• When a break address is placed at the address of the instruction opcode, the instruction is not
executed until after completion of the break interrupt routine.
• When a break address is placed at an address of an instruction operand, the instruction is executed
before the break interrupt.
• When software writes a 1 to the BRKA bit, the break interrupt occurs just before the next instruction
is executed.
By updating a break address and clearing the BRKA bit in a break interrupt routine, a break interrupt can
be generated continuously.
CAUTION
A break address should be placed at the address of the instruction opcode. When software does not
change the break address and clears the BRKA bit in the first break interrupt routine, the next break
interrupt will not be generated after exiting the interrupt routine even when the internal address bus
matches the value written in the break address registers.
15.2.1.1 Flag Protection During Break Interrupts
The system integration module (SIM) controls whether or not module status bits can be cleared during
the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear status
bits during the break state. See 13.8.2 Break Flag Control Register and the Break Interrupts subsection
for each module.
15.2.1.2 TIM During Break Interrupts
A break interrupt stops the timer counter.
15.2.1.3 COP During Break Interrupts
The COP is disabled during a break interrupt with monitor mode when BDCOP bit is set in break auxiliary
register (BRKAR).
15.2.2 Break Module Registers
These registers control and monitor operation of the break module:
• Break status and control register (BRKSCR)
• Break address register high (BRKH)
• Break address register low (BRKL)
• Break status register (BSR)
• Break flag control register (BFCR)
MC68HC908QY/QT Family Data Sheet, Rev. 4
144
Freescale Semiconductor
Break Module (BRK)
15.2.2.1 Break Status and Control Register
The break status and control register (BRKSCR) contains break module enable and status bits.
Address: $FE0B
Read:
Write:
Reset:
Bit 7
6
BRKE
BRKA
0
0
5
4
3
2
1
Bit 0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented
Figure 15-4. Break Status and Control Register (BRKSCR)
BRKE — Break Enable Bit
This read/write bit enables breaks on break address register matches. Clear BRKE by writing a 0 to
bit 7. Reset clears the BRKE bit.
1 = Breaks enabled on 16-bit address match
0 = Breaks disabled
BRKA — Break Active Bit
This read/write status and control bit is set when a break address match occurs. Writing a 1 to BRKA
generates a break interrupt. Clear BRKA by writing a 0 to it before exiting the break routine. Reset
clears the BRKA bit.
1 = Break address match
0 = No break address match
15.2.2.2 Break Address Registers
The break address registers (BRKH and BRKL) contain the high and low bytes of the desired breakpoint
address. Reset clears the break address registers.
Address: $FE09
Read:
Write:
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
0
0
0
0
0
0
0
0
Figure 15-5. Break Address Register High (BRKH)
Address: $FE0A
Read:
Write:
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
Figure 15-6. Break Address Register Low (BRKL)
MC68HC908QY/QT Family Data Sheet, Rev. 4
Freescale Semiconductor
145
Development Support
15.2.2.3 Break Auxiliary Register
The break auxiliary register (BRKAR) contains a bit that enables software to disable the COP while the
MCU is in a state of break interrupt with monitor mode.
Address: $FE02
Read:
Bit 7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Write:
Reset:
Bit 0
BDCOP
0
= Unimplemented
Figure 15-7. Break Auxiliary Register (BRKAR)
BDCOP — Break Disable COP Bit
This read/write bit disables the COP during a break interrupt. Reset clears the BDCOP bit.
1 = COP disabled during break interrupt
0 = COP enabled during break interrupt
15.2.2.4 Break Status Register
The break status register (BSR) contains a flag to indicate that a break caused an exit from wait mode.
This register is only used in emulation mode.
Address: $FE00
Bit 7
Read:
Write:
R
6
R
5
R
4
R
3
R
2
R
Reset:
1
SBSW
Note(1)
Bit 0
R
0
R
= Reserved
1. Writing a 0 clears SBSW.
Figure 15-8. Break Status Register (BSR)
SBSW — SIM Break Stop/Wait
SBSW can be read within the break state SWI routine. The user can modify the return address on the
stack by subtracting one from it.
1 = Wait mode was exited by break interrupt
0 = Wait mode was not exited by break interrupt
MC68HC908QY/QT Family Data Sheet, Rev. 4
146
Freescale Semiconductor
Monitor Module (MON)
15.2.2.5 Break Flag Control Register
The break control register (BFCR) contains a bit that enables software to clear status bits while the MCU
is in a break state.
Address: $FE03
Read:
Write:
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
BCFE
R
R
R
R
R
R
R
0
R
= Reserved
Figure 15-9. Break Flag Control Register (BFCR)
BCFE — Break Clear Flag Enable Bit
This read/write bit enables software to clear status bits by accessing status registers while the MCU is
in a break state. To clear status bits during the break state, the BCFE bit must be set.
1 = Status bits clearable during break
0 = Status bits not clearable during break
15.2.3 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power- consumption standby modes. If enabled,
the break module will remain enabled in wait and stop modes. However, since the internal address bus
does not increment in these modes, a break interrupt will never be triggered.
15.3 Monitor Module (MON)
This subsection describes the monitor module (MON) and the monitor mode entry methods. The monitor
allows debugging and programming of the microcontroller unit (MCU) through a single-wire interface with
a host computer. Monitor mode entry can be achieved without use of the higher test voltage, VTST, as
long as vector addresses $FFFE and $FFFF are blank, thus reducing the hardware requirements for
in-circuit programming.
Features include:
• Normal user-mode pin functionality on most pins
• One pin dedicated to serial communication between MCU and host computer
• Standard non-return-to-zero (NRZ) communication with host computer
• Execution of code in random-access memory (RAM) or FLASH
• FLASH memory security feature(1)
• FLASH memory programming interface
• Use of external 9.8304 MHz oscillator to generate internal frequency of 2.4576 MHz
• Simple internal oscillator mode of operation (no external clock or high voltage)
• Monitor mode entry without high voltage, VTST, if reset vector is blank ($FFFE and $FFFF contain
$FF)
• Standard monitor mode entry if high voltage is applied to IRQ
1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for
unauthorized users.
MC68HC908QY/QT Family Data Sheet, Rev. 4
Freescale Semiconductor
147
Development Support
15.3.1 Functional Description
Figure 15-10 shows a simplified diagram of monitor mode entry.
The monitor module receives and executes commands from a host computer. Figure 15-11, Figure 15-12,
and Figure 15-13 show example circuits used to enter monitor mode and communicate with a host
computer via a standard RS-232 interface.
POR RESET
NO
CONDITIONS
FROM Table 15-1
PTA0 = 1,
RESET VECTOR
BLANK?
IRQ = VTST?
YES
PTA0 = 1,
PTA1 = 1, AND
PTA4 = 0?
NO
NO
YES
YES
FORCED
MONITOR MODE
NORMAL
USER MODE
NORMAL
MONITOR MODE
INVALID
USER MODE
HOST SENDS
8 SECURITY BYTES
IS RESET
POR?
YES
NO
YES
ARE ALL
SECURITY BYTES
CORRECT?
ENABLE FLASH
NO
DISABLE FLASH
MONITOR MODE ENTRY
DEBUGGING
AND FLASH
PROGRAMMING
(IF FLASH
IS ENABLED)
EXECUTE
MONITOR CODE
YES
DOES RESET
OCCUR?
NO
Figure 15-10. Simplified Monitor Mode Entry Flowchart
MC68HC908QY/QT Family Data Sheet, Rev. 4
148
Freescale Semiconductor
Monitor Module (MON)
VDD
VDD
10 kΩ*
VDD
0.1 µF
RST (PTA3)
MAX232
1
1 µF
+
VDD
VTST
15
C1–
1 µF
1 kΩ
1 µF
1 µF
9.1 V
3
7
10
8
9
10 kΩ*
10 kΩ
+
PTA4
74HC125
5
6
DB9
2
IRQ (PTA2)
VDD
V– 6
5 C2–
10 kΩ*
PTA1
V+ 2
C2+
+
VDD
1 µF
+
4
OSC1 (PTA5)
16
C1+
+
3
9.8304 MHz CLOCK
74HC125
3
2
PTA0
4
VSS
1
5
* Value not critical
Figure 15-11. Monitor Mode Circuit (External Clock, with High Voltage)
VDD
N.C.
RST (PTA3)
VDD
0.1 µF
MAX232
1
1 µF
+
16
9.8304 MHz CLOCK
+
3
4
1 µF
C1+
VDD
C1–
C2+
+
5 C2–
1 µF
15
1 µF
+
3
10 kΩ*
V+ 2
VDD
1 µF
10 kΩ
74HC125
5
6
+
7
10
8
9
74HC125
3
2
PTA1
N.C.
PTA4
N.C.
IRQ (PTA2)
V– 6
DB9
2
OSC1 (PTA5)
PTA0
4
VSS
1
5
* Value not critical
Figure 15-12. Monitor Mode Circuit (External Clock, No High Voltage)
MC68HC908QY/QT Family Data Sheet, Rev. 4
Freescale Semiconductor
149
Development Support
VDD
N.C.
RST (PTA3)
VDD
0.1 µF
MAX232
1
1 µF
+
4
C1–
C2+
+
5 C2–
N.C.
1 µF
15
3
5
IRQ (PTA2)
1 µF
+
PTA1
N.C.
PTA4
N.C.
10 kΩ*
V+ 2
VDD
V– 6
1 µF
10 kΩ
74HC125
5
6
+
DB9
2
OSC1 (PTA5)
16
+
3
1 µF
C1+
VDD
7
10
8
9
74HC125
3
2
PTA0
VSS
4
1
* Value not critical
Figure 15-13. Monitor Mode Circuit (Internal Clock, No High Voltage)
Simple monitor commands can access any memory address. In monitor mode, the MCU can execute
code downloaded into RAM by a host computer while most MCU pins retain normal operating mode
functions. All communication between the host computer and the MCU is through the PTA0 pin. A
level-shifting and multiplexing interface is required between PTA0 and the host computer. PTA0 is used
in a wired-OR configuration and requires a pullup resistor.
The monitor code has been updated from previous versions of the monitor code to allow enabling the
internal oscillator to generate the internal clock. This addition, which is enabled when IRQ is held low out
of reset, is intended to support serial communication/programming at 9600 baud in monitor mode by using
the internal oscillator, and the internal oscillator user trim value OSCTRIM (FLASH location $FFC0, if
programmed) to generate the desired internal frequency (3.2 MHz). Since this feature is enabled only
when IRQ is held low out of reset, it cannot be used when the reset vector is programmed (i.e., the value
is not $FFFF) because entry into monitor mode in this case requires VTST on IRQ. The IRQ pin must
remain low during this monitor session in order to maintain communication.
Table 15-1 shows the pin conditions for entering monitor mode. As specified in the table, monitor mode
may be entered after a power-on reset (POR) and will allow communication at 9600 baud provided one
of the following sets of conditions is met:
• If $FFFE and $FFFF do not contain $FF (programmed state):
– The external clock is 9.8304 MHz
– IRQ = VTST
• If $FFFE and $FFFF contain $FF (erased state):
– The external clock is 9.8304 MHz
– IRQ = VDD (this can be implemented through the internal IRQ pullup)
• If $FFFE and $FFFF contain $FF (erased state):
– IRQ = VSS (internal oscillator is selected, no external clock required)
MC68HC908QY/QT Family Data Sheet, Rev. 4
150
Freescale Semiconductor
Monitor Module (MON)
Table 15-1. Monitor Mode Signal Requirements and Options
Mode
Serial
Mode
CommuniSelection
RST
Reset
IRQ
cation
(PTA2) (PTA3) Vector
PTA0
PTA1 PTA4
Communication
Speed
COP
External
Bus
Clock
Frequency
Comments
Baud
Rate
VTST
VDD
X
1
1
0
Disabled
9.8304
MHz
2.4576
MHz
9600
Provide external
clock at OSC1.
VDD
X
$FFFF
(blank)
1
X
X
Disabled
9.8304
MHz
2.4576
MHz
9600
Provide external
clock at OSC1.
VSS
X
$FFFF
(blank)
1
X
X
Disabled
X
3.2 MHz
(Trimmed)
9600
Internal clock
is active.
User
X
X
Not
$FFFF
X
X
X
Enabled
X
X
X
MON08
Function
[Pin No.]
VTST
[6]
RST
[4]
—
COM
[8]
—
OSC1
[13]
—
—
Normal
Monitor
Forced
Monitor
MOD0 MOD1
[12]
[10]
1. PTA0 must have a pullup resistor to VDD in monitor mode.
2. Communication speed in the table is an example to obtain a baud rate of 9600. Baud rate using external oscillator is bus
frequency / 256 and baud rate using internal oscillator is bus frequency / 335.
3. External clock is a 9.8304 MHz oscillator on OSC1.
4. X = don’t care
5. MON08 pin refers to P&E Microcomputer Systems’ MON08-Cyclone 2 by 8-pin connector.
NC
1
2
GND
NC
3
4
RST
NC
5
6
IRQ
NC
7
8
PTA0
NC
9
10
PTA4
NC
11
12
PTA1
OSC1
13
14
NC
VDD
15
16
NC
The rising edge of the internal RST signal latches the monitor mode. Once monitor mode is latched, the
values on PTA1 and PTA4 pins can be changed.
Once out of reset, the MCU waits for the host to send eight security bytes (see 15.3.2 Security). After the
security bytes, the MCU sends a break signal (10 consecutive logic 0s) to the host, indicating that it is
ready to receive a command.
15.3.1.1 Normal Monitor Mode
RST and OSC1 functions will be active on the PTA3 and PTA5 pins respectively as long as VTST is
applied to the IRQ pin. If the IRQ pin is lowered (no longer VTST) then the chip will still be operating in
monitor mode, but the pin functions will be determined by the settings in the configuration registers (see
Chapter 5 Configuration Register (CONFIG)) when VTST was lowered. With VTST lowered, the BIH and
BIL instructions will read the IRQ pin state only if IRQEN is set in the CONFIG2 register.
MC68HC908QY/QT Family Data Sheet, Rev. 4
Freescale Semiconductor
151
Development Support
If monitor mode was entered with VTST on IRQ, then the COP is disabled as long as VTST is applied to
IRQ.
15.3.1.2 Forced Monitor Mode
If entering monitor mode without high voltage on IRQ, then startup port pin requirements and conditions,
(PTA1/PTA4) are not in effect. This is to reduce circuit requirements when performing in-circuit
programming.
NOTE
If the reset vector is blank and monitor mode is entered, the chip will see an
additional reset cycle after the initial power-on reset (POR). Once the reset
vector has been programmed, the traditional method of applying a voltage,
VTST, to IRQ must be used to enter monitor mode.
If monitor mode was entered as a result of the reset vector being blank, the COP is always disabled
regardless of the state of IRQ.
If the voltage applied to the IRQ is less than VTST, the MCU will come out of reset in user mode. Internal
circuitry monitors the reset vector fetches and will assert an internal reset if it detects that the reset vectors
are erased ($FF). When the MCU comes out of reset, it is forced into monitor mode without requiring high
voltage on the IRQ pin. Once out of reset, the monitor code is initially executing with the internal clock at
its default frequency.
If IRQ is held high, all pins will default to regular input port functions except for PTA0 and PTA5 which will
operate as a serial communication port and OSC1 input respectively (refer to Figure 15-11). That will
allow the clock to be driven from an external source through OSC1 pin.
If IRQ is held low, all pins will default to regular input port function except for PTA0 which will operate as
serial communication port. Refer to Figure 15-12.
Regardless of the state of the IRQ pin, it will not function as a port input pin in monitor mode. Bit 2 of the
Port A data register will always read 0. The BIH and BIL instructions will behave as if the IRQ pin is
enabled, regardless of the settings in the configuration register. See Chapter 5 Configuration Register
(CONFIG).
The COP module is disabled in forced monitor mode. Any reset other than a power-on reset (POR) will
automatically force the MCU to come back to the forced monitor mode.
15.3.1.3 Monitor Vectors
In monitor mode, the MCU uses different vectors for reset, SWI (software interrupt), and break interrupt
than those for user mode. The alternate vectors are in the $FE page instead of the $FF page and allow
code execution from the internal monitor firmware instead of user code.
NOTE
Exiting monitor mode after it has been initiated by having a blank reset
vector requires a power-on reset (POR). Pulling RST (when RST pin
available) low will not exit monitor mode in this situation.
MC68HC908QY/QT Family Data Sheet, Rev. 4
152
Freescale Semiconductor
Monitor Module (MON)
Table 15-2 summarizes the differences between user mode and monitor mode regarding vectors.
Table 15-2. Mode Difference
Functions
Modes
Reset
Vector High
Reset
Vector Low
Break
Vector High
Break
Vector Low
SWI
Vector High
SWI
Vector Low
User
$FFFE
$FFFF
$FFFC
$FFFD
$FFFC
$FFFD
Monitor
$FEFE
$FEFF
$FEFC
$FEFD
$FEFC
$FEFD
15.3.1.4 Data Format
Communication with the monitor ROM is in standard non-return-to-zero (NRZ) mark/space data format.
Transmit and receive baud rates must be identical.
START
BIT
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
STOP
BIT
NEXT
START
BIT
Figure 15-14. Monitor Data Format
15.3.1.5 Break Signal
A start bit (logic 0) followed by nine logic 0 bits is a break signal. When the monitor receives a break signal,
it drives the PTA0 pin high for the duration of two bits and then echoes back the break signal.
MISSING STOP BIT
2-STOP BIT DELAY BEFORE ZERO ECHO
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
Figure 15-15. Break Transaction
15.3.1.6 Baud Rate
The monitor communication baud rate is controlled by the frequency of the external or internal oscillator
and the state of the appropriate pins as shown in Table 15-1.
Table 15-1 also lists the bus frequencies to achieve standard baud rates. The effective baud rate is the
bus frequency divided by 256 when using an external oscillator. When using the internal oscillator in
forced monitor mode, the effective baud rate is the bus frequency divided by 335.
MC68HC908QY/QT Family Data Sheet, Rev. 4
Freescale Semiconductor
153
Development Support
15.3.1.7 Commands
The monitor ROM firmware uses these commands:
• READ (read memory)
• WRITE (write memory)
• IREAD (indexed read)
• IWRITE (indexed write)
• READSP (read stack pointer)
• RUN (run user program)
The monitor ROM firmware echoes each received byte back to the PTA0 pin for error checking. An 11-bit
delay at the end of each command allows the host to send a break character to cancel the command. A
delay of two bit times occurs before each echo and before READ, IREAD, or READSP data is returned.
The data returned by a read command appears after the echo of the last byte of the command.
NOTE
Wait one bit time after each echo before sending the next byte.
FROM
HOST
4
ADDRESS
HIGH
READ
READ
4
1
ADDRESS
HIGH
1
ECHO
Notes:
1 = Echo delay, 2 bit times
2 = Data return delay, 2 bit times
ADDRESS
LOW
ADDRESS
LOW
DATA
1
4
3, 2
4
RETURN
3 = Cancel command delay, 11 bit times
4 = Wait 1 bit time before sending next byte.
Figure 15-16. Read Transaction
FROM
HOST
3
ADDRESS
HIGH
WRITE
WRITE
1
3
ADDRESS
HIGH
1
ADDRESS
LOW
3
ADDRESS
LOW
1
DATA
3
DATA
1
2, 3
ECHO
Notes:
1 = Echo delay, 2 bit times
2 = Cancel command delay, 11 bit times
3 = Wait 1 bit time before sending next byte.
Figure 15-17. Write Transaction
A brief description of each monitor mode command is given in Table 15-3 through Table 15-8.
MC68HC908QY/QT Family Data Sheet, Rev. 4
154
Freescale Semiconductor
Monitor Module (MON)
Table 15-3. READ (Read Memory) Command
Description
Read byte from memory
Operand
2-byte address in high-byte:low-byte order
Data Returned
Returns contents of specified address
Opcode
$4A
Command Sequence
SENT TO MONITOR
READ
ADDRESS ADDRESS ADDRESS
HIGH
HIGH
LOW
READ
ADDRESS
LOW
DATA
ECHO
RETURN
Table 15-4. WRITE (Write Memory) Command
Description
Operand
Data Returned
Opcode
Write byte to memory
2-byte address in high-byte:low-byte order; low byte followed by data
byte
None
$49
Command Sequence
FROM HOST
WRITE
WRITE
ADDRESS
HIGH
ADDRESS
HIGH
ADDRESS
LOW
ADDRESS
LOW
DATA
DATA
ECHO
Table 15-5. IREAD (Indexed Read) Command
Description
Operand
Data Returned
Opcode
Read next 2 bytes in memory from last address accessed
None
Returns contents of next two addresses
$1A
Command Sequence
FROM HOST
IREAD
IREAD
DATA
DATA
ECHO
RETURN
MC68HC908QY/QT Family Data Sheet, Rev. 4
Freescale Semiconductor
155
Development Support
Table 15-6. IWRITE (Indexed Write) Command
Description
Operand
Data Returned
Opcode
Write to last address accessed + 1
Single data byte
None
$19
Command Sequence
FROM HOST
IWRITE
IWRITE
DATA
DATA
ECHO
A sequence of IREAD or IWRITE commands can access a block of memory sequentially over the full
64-Kbyte memory map.
Table 15-7. READSP (Read Stack Pointer) Command
Description
Operand
Data Returned
Opcode
Reads stack pointer
None
Returns incremented stack pointer value (SP + 1) in
high-byte:low-byte order
$0C
Command Sequence
FROM HOST
READSP
SP
HIGH
READSP
ECHO
SP
LOW
RETURN
Table 15-8. RUN (Run User Program) Command
Description
Executes PULH and RTI instructions
Operand
None
Data Returned
None
Opcode
$28
Command Sequence
FROM HOST
RUN
RUN
ECHO
MC68HC908QY/QT Family Data Sheet, Rev. 4
156
Freescale Semiconductor
Monitor Module (MON)
The MCU executes the SWI and PSHH instructions when it enters monitor mode. The RUN command
tells the MCU to execute the PULH and RTI instructions. Before sending the RUN command, the host can
modify the stacked CPU registers to prepare to run the host program. The READSP command returns
the incremented stack pointer value, SP + 1. The high and low bytes of the program counter are at
addresses SP + 5 and SP + 6.
SP
HIGH BYTE OF INDEX REGISTER
SP + 1
CONDITION CODE REGISTER
SP + 2
ACCUMULATOR
SP + 3
LOW BYTE OF INDEX REGISTER
SP + 4
HIGH BYTE OF PROGRAM COUNTER
SP + 5
LOW BYTE OF PROGRAM COUNTER
SP + 6
SP + 7
Figure 15-18. Stack Pointer at Monitor Mode Entry
15.3.2 Security
A security feature discourages unauthorized reading of FLASH locations while in monitor mode. The host
can bypass the security feature at monitor mode entry by sending eight security bytes that match the
bytes at locations $FFF6–$FFFD. Locations $FFF6–$FFFD contain user-defined data.
NOTE
Do not leave locations $FFF6–$FFFD blank. For security reasons, program
locations $FFF6–$FFFD even if they are not used for vectors.
During monitor mode entry, the MCU waits after the power-on reset for the host to send the eight security
bytes on pin PTA0. If the received bytes match those at locations $FFF6–$FFFD, the host bypasses the
security feature and can read all FLASH locations and execute code from FLASH. Security remains
bypassed until a power-on reset occurs. If the reset was not a power-on reset, security remains bypassed
and security code entry is not required. See Figure 15-19.
Upon power-on reset, if the received bytes of the security code do not match the data at locations
$FFF6–$FFFD, the host fails to bypass the security feature. The MCU remains in monitor mode, but
reading a FLASH location returns an invalid value and trying to execute code from FLASH causes an
illegal address reset. After receiving the eight security bytes from the host, the MCU transmits a break
character, signifying that it is ready to receive a command.
NOTE
The MCU does not transmit a break character until after the host sends the
eight security bytes.
To determine whether the security code entered is correct, check to see if bit 6 of RAM address $80 is
set. If it is, then the correct security code has been entered and FLASH can be accessed.
If the security sequence fails, the device should be reset by a power-on reset and brought up in monitor
mode to attempt another entry. After failing the security sequence, the FLASH module can also be mass
erased by executing an erase routine that was downloaded into internal RAM. The mass erase operation
clears the security code locations so that all eight security bytes become $FF (blank).
MC68HC908QY/QT Family Data Sheet, Rev. 4
Freescale Semiconductor
157
Development Support
VDD
4096 + 32 CGMXCLK CYCLES
COMMAND
BYTE 8
BYTE 2
BYTE 1
RST
FROM HOST
PA0
4
BREAK
2
1
COMMAND ECHO
1
BYTE 8 ECHO
Notes:
1 = Echo delay, 2 bit times
2 = Data return delay, 2 bit times
4 = Wait 1 bit time before sending next byte.
1
BYTE 2 ECHO
FROM MCU
4
1
BYTE 1 ECHO
256 BUS CYCLES
(MINIMUM)
Figure 15-19. Monitor Mode Entry Timing
MC68HC908QY/QT Family Data Sheet, Rev. 4
158
Freescale Semiconductor
Chapter 16
Electrical Specifications
16.1 Introduction
This section contains electrical and timing specifications.
16.2 Absolute Maximum Ratings
Maximum ratings are the extreme limits to which the microcontroller unit (MCU) can be exposed without
permanently damaging it.
NOTE
This device is not guaranteed to operate properly at the maximum ratings.
Refer to 16.5 5-V DC Electrical Characteristics and 16.9 3-V DC Electrical
Characteristics for guaranteed operating conditions.
Characteristic(1)
Symbol
Value
Unit
Supply voltage
VDD
–0.3 to +6.0
V
Input voltage
VIN
VSS –0.3 to VDD +0.3
V
VTST
VSS –0.3 to +9.1
V
I
±15
mA
IPTA0—IPTA5
±25
mA
Storage temperature
TSTG
–55 to +150
°C
Maximum current out of VSS
IMVSS
100
mA
Maximum current into VDD
IMVDD
100
mA
Mode entry voltage, IRQ pin
Maximum current per pin excluding PTA0–PTA5, VDD, and VSS
Maximum current for pins PTA0–PTA5
1. Voltages references to VSS.
NOTE
This device contains circuitry to protect the inputs against damage due to
high static voltages or electric fields; however, it is advised that normal
precautions be taken to avoid application of any voltage higher than
maximum-rated voltages to this high-impedance circuit. For proper
operation, it is recommended that VIN and VOUT be constrained to the
range VSS ≤ (VIN or VOUT) ≤ VDD. Reliability of operation is enhanced if
unused inputs are connected to an appropriate logic voltage level (for
example, either VSS or VDD.)
MC68HC908QY/QT Family Data Sheet, Rev. 4
Freescale Semiconductor
159
Electrical Specifications
16.3 Functional Operating Range
Characteristic
Operating temperature range
Operating voltage range
Symbol
Value
Unit
Temp.
Code
TA
– 40 to +125
– 40 to +105
– 40 to +85
°C
M
V
C
VDD
2.7 to 5.5
V
—
16.4 Thermal Characteristics
Characteristic
Symbol
Value
Unit
Thermal resistance
8-pin PDIP
8-pin SOIC
8-pin DFN
16-pin PDIP
16-pin SOIC
16-pin TSSOP
θJA
I/O pin power dissipation
PI/O
User determined
W
Power dissipation(1)
PD
PD = (IDD x VDD)
+ PI/O = K/(TJ + 273°C)
W
Constant(2)
K
Average junction temperature
Maximum junction temperature
105
142
173
76
90
133
°C/W
PD x (TA + 273°C)
+ PD2 x θJA
W/°C
TJ
TA + (PD x θJA)
°C
TJM
150
°C
1. Power dissipation is a function of temperature.
2. K constant unique to the device. K can be determined for a known TA and measured PD. With this value of K, PD and TJ
can be determined for any value of TA.
MC68HC908QY/QT Family Data Sheet, Rev. 4
160
Freescale Semiconductor
5-V DC Electrical Characteristics
16.5 5-V DC Electrical Characteristics
Characteristic(1)
Symbol
Min
Typ(2)
Max
VDD –0.4
VDD –1.5
VDD –0.8
—
—
—
—
—
—
—
—
50
—
—
—
—
—
—
0.4
1.5
0.8
Unit
Output high voltage
ILoad = –2.0 mA, all I/O pins
ILoad = –10.0 mA, all I/O pins
ILoad = –15.0 mA, PTA0, PTA1, PTA3–PTA5 only
VOH
Maximum combined IOH (all I/O pins)
IOHT
Output low voltage
ILoad = 1.6 mA, all I/O pins
ILoad = 10.0 mA, all I/O pins
ILoad = 15.0 mA, PTA0, PTA1, PTA3–PTA5 only
VOL
Maximum combined IOL (all I/O pins)
IOLT
—
—
50
mA
Input high voltage
PTA0–PTA5, PTB0–PTB7
VIH
0.7 x VDD
—
VDD
V
Input low voltage
PTA0–PTA5, PTB0–PTB7
VIL
VSS
—
0.3 x VDD
V
VHYS
0.06 x VDD
—
—
V
IINJ
–2
—
+2
mA
IINJTOT
–25
—
+25
mA
IIL
–1
±0.1
+1
µA
Capacitance
Ports (as input)
Ports (as input)
CIN
COUT
—
—
—
—
12
8
pF
POR rearm voltage(3)
VPOR
0
—
100
mV
POR rise time ramp rate(4)
RPOR
0.035
—
—
V/ms
Monitor mode entry voltage
VTST
VDD + 2.5
—
9.1
V
RPU
16
26
36
kΩ
Low-voltage inhibit reset, trip falling voltage
VTRIPF
3.90
4.20
4.50
V
Low-voltage inhibit reset, trip rising voltage
VTRIPR
4.00
4.30
4.60
V
Low-voltage inhibit reset/recover hysteresis
VHYS
—
100
—
mV
Input hysteresis
DC injection current, all ports
Total dc current injection (sum of all I/O)
Ports Hi-Z leakage current
(5)
Pullup resistors
PTA0–PTA5, PTB0–PTB7
V
mA
V
1. VDD = 4.5 to 5.5 Vdc, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted.
2. Typical values reflect average measurements at midpoint of voltage range, 25°C only.
3. Maximum is highest voltage that POR is guaranteed.
4. If minimum VDD is not reached before the internal POR reset is released, the LVI will hold the part in reset until minimum
VDD is reached.
5. RPU is measured at VDD = 5.0 V.
MC68HC908QY/QT Family Data Sheet, Rev. 4
Freescale Semiconductor
161
Electrical Specifications
16.6 Typical 5-V Output Drive Characteristics
2.0
VDD-VOH (V)
1.5
5V PTA
1.0
5V PTB
0.5
0.0
0
-5
-10
-15
-20
-25
-30
-35
IOH (mA)
Figure 16-1. Typical 5-Volt Output High Voltage
versus Output High Current (25°C)
2.0
VOL (V)
1.5
5V PTA
5V PTB
1.0
0.5
0.0
0
5
10
15
20
25
30
35
IOL (mA)
Figure 16-2. Typical 5-Volt Output Low Voltage
versus Output Low Current (25°C)
MC68HC908QY/QT Family Data Sheet, Rev. 4
162
Freescale Semiconductor
5-V Control Timing
16.7 5-V Control Timing
Characteristic(1)
Symbol
Min
Max
Unit
Internal operating frequency
fOP (fBus)
—
8
MHz
Internal clock period (1/fOP)
tcyc
125
—
ns
RST input pulse width low
tRL
100
—
ns
IRQ interrupt pulse width low (edge-triggered)
tILIH
100
—
ns
IRQ interrupt pulse period
tILIL
Note(2)
—
tcyc
1. VDD = 4.5 to 5.5 Vdc, VSS = 0 Vdc, TA = TL to TH; timing shown with respect to 20% VDD and 70% VSS, unless otherwise
noted.
2. The minimum period is the number of cycles it takes to execute the interrupt service routine plus 1 tcyc.
tRL
RST
tILIL
tILIH
IRQ
Figure 16-3. RST and IRQ Timing
MC68HC908QY/QT Family Data Sheet, Rev. 4
Freescale Semiconductor
163
Electrical Specifications
16.8 5-V Oscillator Characteristics
Characteristic
Symbol
Min
Typ
Max
Unit
fINTCLK
—
12.8
—
MHz
—
—
—
± 0.4
±2
—
—
—
±5
fOSCXCLK
1
—
24
MHz
fRCCLK
2
—
12
MHz
fOSCXCLK
dc
—
32
MHz
Crystal load capacitance(5)
CL
—
20
—
pF
Crystal fixed capacitance(3)
C1
—
2 x CL
—
—
Crystal tuning capacitance(3)
C2
—
2 x CL
—
—
Feedback bias resistor
RB
0.5
1
10
MΩ
Internal oscillator
frequency(1)
Deviation from trimmed Internal oscillator
12.8 MHz, fixed voltage, fixed temp
12.8 MHz, VDD ± 10%, 0 to 70°C
12.8 MHz, VDD ± 10%, –40 to 125°C
(2)(3)
ACCINT
Crystal frequency, XTALCLK(1)
External RC oscillator frequency, RCCLK(1)
External clock reference frequency(1) (4)
REXT
RC oscillator external resistor
Crystal series damping resistor
fOSCXCLK = 1 MHz
fOSCXCLK = 4 MHz
fOSCXCLK = > 8 MHz
See Figure 16-4
—
—
—
RS
%
—
20
10
0
—
—
—
kΩ
1. Bus frequency, fOP, is oscillator frequency divided by 4.
2. Deviation values assumes trimming @25°C and midpoint of voltage range.
3. Values are based on characterization results, not tested in production.
4. No more than 10% duty cycle deviation from 50%.
5. Consult crystal vendor data sheet.
14
5 V 25°C
RC FREQUENCY, f RCCLK (MHz)
12
10
8
6
4
2
0
0
10
20
30
40
50
60
R EXT (k Ω)
Figure 16-4. RC versus Frequency (5 Volts @ 25°C)
MC68HC908QY/QT Family Data Sheet, Rev. 4
164
Freescale Semiconductor
3-V DC Electrical Characteristics
16.9 3-V DC Electrical Characteristics
Characteristic(1)
Symbol
Min
Typ(2)
Max
VDD –0.3
VDD –1.0
VDD –0.8
—
—
—
—
—
—
—
—
50
—
—
—
—
—
—
0.3
1.0
0.8
Unit
Output high voltage
ILoad = –0.6 mA, all I/O pins
ILoad = –4.0 mA, all I/O pins
ILoad = –10.0 mA, PTA0, PTA1, PTA3–PTA5 only
VOH
Maximum combined IOH (all I/O pins)
IOHT
Output low voltage
ILoad = 0.5 mA, all I/O pins
ILoad = 6.0 mA, all I/O pins
ILoad = 10.0 mA, PTA0, PTA1, PTA3–PTA5 only
VOL
Maximum combined IOL (all I/O pins)
IOLT
—
—
50
mA
Input high voltage
PTA0–PTA5, PTB0–PTB7
VIH
0.7 x VDD
—
VDD
V
Input low voltage
PTA0–PTA5, PTB0–PTB7
VIL
VSS
—
0.3 x VDD
V
VHYS
0.06 x VDD
—
—
V
IINJ
–2
—
+2
mA
IINJTOT
–25
—
+25
mA
IIL
–1
±0.1
+1
µA
Capacitance
Ports (as input)
Ports (as input)
CIN
COUT
—
—
—
—
12
8
pF
POR rearm voltage(3)
VPOR
0
—
100
mV
POR rise time ramp rate(4)
RPOR
0.035
—
—
V/ms
Monitor mode entry voltage
VTST
VDD + 2.5
—
VDD + 4.0
V
RPU
16
26
36
kΩ
Low-voltage inhibit reset, trip falling voltage
VTRIPF
2.40
2.55
2.70
V
Low-voltage inhibit reset, trip rising voltage
VTRIPR
2.50
2.65
2.80
V
Low-voltage inhibit reset/recover hysteresis
VHYS
—
60
—
mV
Input hysteresis
DC injection current, all ports
Total dc current injection (sum of all I/O)
Ports Hi-Z leakage current
(5)
Pullup resistors
PTA0–PTA5, PTB0–PTB7
V
mA
V
1. VDD = 2.7 to 3.3 Vdc, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted.
2. Typical values reflect average measurements at midpoint of voltage range, 25°C only.
3. Maximum is highest voltage that POR is guaranteed.
4. If minimum VDD is not reached before the internal POR reset is released, the LVI will hold the part in reset until minimum
VDD is reached.
5. RPU are measured at VDD = 3.0 V
MC68HC908QY/QT Family Data Sheet, Rev. 4
Freescale Semiconductor
165
Electrical Specifications
16.10 Typical 3.0-V Output Drive Characteristics
1.5
VDD-VOH (V)
1.0
3V PTA
3V PTB
0.5
0.0
0
-5
-10
-15
-20
IOH (mA)
Figure 16-5. Typical 3-Volt Output High Voltage
versus Output High Current (25°C)
1.5
VOL (V)
1.0
3V PTA
3V PTB
0.5
0.0
0
5
10
15
20
IOL (mA)
Figure 16-6. Typical 3-Volt Output Low Voltage
versus Output Low Current (25°C)
MC68HC908QY/QT Family Data Sheet, Rev. 4
166
Freescale Semiconductor
3-V Control Timing
16.11 3-V Control Timing
Characteristic(1)
Symbol
Min
Max
Unit
Internal operating frequency
fOP (fBus)
—
4
MHz
Internal clock period (1/fOP)
tcyc
250
—
ns
RST input pulse width low
tRL
200
—
ns
IRQ interrupt pulse width low (edge-triggered)
tILIH
200
—
ns
—
tcyc
tILIL
IRQ interrupt pulse period
(2)
Note
1. VDD = 2.7 to 3.3 Vdc, VSS = 0 Vdc, TA = TL to TH; timing shown with respect to 20% VDD and 70% VDD, unless otherwise
noted.
2. The minimum period is the number of cycles it takes to execute the interrupt service routine plus 1 tcyc.
tRL
RST
tILIL
tILIH
IRQ
Figure 16-7. RST and IRQ Timing
MC68HC908QY/QT Family Data Sheet, Rev. 4
Freescale Semiconductor
167
Electrical Specifications
16.12 3-V Oscillator Characteristics
Characteristic
Symbol
Min
Typ
Max
Unit
fINTCLK
—
12.8
—
MHz
—
—
—
± 0.4
±2
—
—
—
±5
fOSCXCLK
1
—
16
MHz
fRCCLK
2
—
10
MHz
fOSCXCLK
dc
—
16
MHz
Crystal load capacitance(5)
CL
—
20
—
pF
Crystal fixed capacitance(3)
C1
—
2 x CL
—
—
Crystal tuning capacitance(3)
C2
—
2 x CL
—
—
Feedback bias resistor
RB
0.5
1
10
MΩ
Internal oscillator
frequency(1)
Deviation from trimmed Internal oscillator
12.8 MHz, fixed voltage, fixed temp
12.8 MHz, VDD ± 10%, 0 to 70°C
12.8 MHz, VDD ± 10%, –40 to 125°C
(2)(3)
ACCINT
Crystal frequency, XTALCLK(1)
External RC oscillator frequency, RCCLK (1)
External clock reference frequency(1) (4)
REXT
RC oscillator external resistor
Crystal series damping resistor
fOSCXCLK = 1 MHz
fOSCXCLK = 4 MHz
fOSCXCLK = > 8 MHz
See Figure 16-8
—
—
—
RS
%
—
10
5
0
—
—
—
kΩ
1. Bus frequency, fOP, is oscillator frequency divided by 4.
2. Deviation values assumes trimming @25°C and midpoint of voltage range.
3. Values are based on characterization results, not tested in production.
4. No more than 10% duty cycle deviation from 50%
5. Consult crystal vendor data sheet
12
3 V 25°C
RC FREQUENCY, f
RCCLK (MHz)
10
8
6
4
2
0
0
10
20
30
40
50
60
R EXT (k Ω)
Figure 16-8. RC versus Frequency (3 Volts @ 25°C)
MC68HC908QY/QT Family Data Sheet, Rev. 4
168
Freescale Semiconductor
Supply Current Characteristics
16.13 Supply Current Characteristics
Voltage
Bus
Frequency
(MHz)
Symbol
Typ(2)
Max
Unit
Run Mode VDD supply current(3)
5.0
3.0
3.2
3.2
RIDD
6.0
2.5
7.0
3.2
mA
Wait Mode VDD supply current(4)
5.0
3.0
3.2
3.2
WIDD
1.0
0.67
1.5
1.0
mA
mA
0.04
—
—
7
125
1.0
2.0
5.0
—
—
0.02
—
—
5
100
0.5
1.0
4.0
—
—
Characteristic(1)
Stop Mode VDD supply current(5)
–40 to 85°C
–40 to 105°C
–40 to 125°C
25°C with auto wakeup enabled
Incremental current with LVI enabled at 25°C
Stop Mode VDD supply current(5)
–40 to 85°C
–40 to 105°C
–40 to 125°C
25°C with auto wakeup enabled
Incremental current with LVI enabled at 25°C
5.0
SIDD
3.0
SIDD
µA
µA
1. VSS = 0 Vdc, TA = TL to TH, unless otherwise noted.
2. Typical values reflect average measurements at 25°C only.
3. Run (operating) IDD measured using trimmed internal oscillator, ADC off, all other modules enabled. All pins configured as
inputs and tied to 0.2 V from rail.
4. Wait IDD measured using trimmed internal oscillator, ADC off, all other modules enabled. All pins configured as inputs and
tied to 0.2 V from rail.
5. Stop IDD measured with all pins tied to 0.2 V or less from rail. No dc loads. On the 8-pin versions, port B is configured as
inputs with pullups enabled.
MC68HC908QY/QT Family Data Sheet, Rev. 4
Freescale Semiconductor
169
Electrical Specifications
14
12
IDD (mA)
10
Crystal w/o ADC
8
Crystal w/ ADC
6
4
Internal Osc w/o
ADC
2
Internal Osc w/
ADC
0
0
1
2
3
4
5
6
7
Bus Frequency (MHz)
Figure 16-9. Typical 5-Volt Run Current
versus Bus Frequency (25°C)
4
3
IDD (mA)
Crystal w/o ADC
2
Crystal w/ ADC
Internal Osc w/o
ADC
1
Internal Osc w/
ADC
0
0
1
2
3
4
5
Bus Frequency (MHz)
Figure 16-10. Typical 3-Volt Run Current
versus Bus Frequency (25°C)
MC68HC908QY/QT Family Data Sheet, Rev. 4
170
Freescale Semiconductor
Analog-to-Digital Converter Characteristics
16.14 Analog-to-Digital Converter Characteristics
Characteristic
Symbol
Min
Max
Unit
Comments
Supply voltage
VDDAD
2.7
(VDD min)
5.5
(VDD max)
V
—
Input voltages
VADIN
VSS
VDD
V
—
Resolution
(1 LSB)
RES
10.5
21.5
mV
—
Absolute accuracy
(Total unadjusted error)
ETUE
—
± 1.5
LSB
Includes quantization
ADC internal clock
fADIC
0.5
1.048
MHz
tADIC = 1/fADIC,
tested only at 1 MHz
Conversion range
VAIN
VSS
VDD
V
—
Power-up time
tADPU
16
—
tADIC cycles
tADIC = 1/fADIC
Conversion time
tADC
16
17
tADIC cycles
tADIC = 1/fADIC
Sample time(1)
tADS
5
—
tADIC cycles
tADIC = 1/fADIC
Zero input reading(2)
ZADI
00
01
Hex
VIN = VSS
Full-scale reading(3)
FADI
FE
FF
Hex
VIN = VDD
Input capacitance
CADI
—
8
pF
Not tested
IIL
—
±1
µA
—
mA
mA
Enabled
Enabled
Input leakage(3)
ADC supply current
VDD = 3 V
VDD = 5 V
IADAD
Typical = 0.45
Typical = 0.65
1. Source impedances greater than 10 kΩ adversely affect internal RC charging time during input sampling.
2. Zero-input/full-scale reading requires sufficient decoupling measures for accurate conversions.
3. The external system error caused by input leakage current is approximately equal to the product of R source and input
current.
MC68HC908QY/QT Family Data Sheet, Rev. 4
Freescale Semiconductor
171
Electrical Specifications
16.15 Timer Interface Module Characteristics
Characteristic
Symbol
Min
Max
Unit
tTH, tTL
2
—
tcyc
tTLTL
Note(1)
—
tcyc
tTCL, tTCH
tcyc + 5
—
ns
Timer input capture pulse width
Timer input capture period
Timer input clock pulse width
1. The minimum period is the number of cycles it takes to execute the interrupt service routine plus 1 tcyc.
tTLTL
tTH
INPUT CAPTURE
RISING EDGE
tTLTL
tTL
INPUT CAPTURE
FALLING EDGE
tTLTL
tTH
tTL
INPUT CAPTURE
BOTH EDGES
tTCH
TCLK
tTCL
Figure 16-11. Timer Input Timing
MC68HC908QY/QT Family Data Sheet, Rev. 4
172
Freescale Semiconductor
Memory Characteristics
16.16 Memory Characteristics
Characteristic
Symbol
Min
Typ
Max
Unit
VRDR
1.3
—
—
V
—
1
—
—
MHz
fRead(1)
0
—
8M
Hz
FLASH page erase time
<1 k cycles
>1 k cycles
tErase
0.9
3.6
1
4
1.1
5.5
ms
FLASH mass erase time
tMErase
4
—
—
ms
FLASH PGM/ERASE to HVEN setup time
tNVS
10
—
—
µs
FLASH high-voltage hold time
tNVH
5
—
—
µs
FLASH high-voltage hold time (mass erase)
tNVHL
100
—
—
µs
FLASH program hold time
tPGS
5
—
—
µs
FLASH program time
tPROG
30
—
40
µs
FLASH return to read time
tRCV(2)
1
—
—
µs
FLASH cumulative program HV period
tHV(3)
—
—
4
ms
FLASH endurance(4)
—
10 k
100 k
—
Cycles
FLASH data retention time(5)
—
15
100
—
Years
RAM data retention voltage
FLASH program bus clock frequency
FLASH read bus clock frequency
1. fRead is defined as the frequency range for which the FLASH memory can be read.
2. tRCV is defined as the time it needs before the FLASH can be read after turning off the high voltage charge pump, by
clearing HVEN to 0.
3. tHV is defined as the cumulative high voltage programming time to the same row before next erase.
tHV must satisfy this condition: tNVS + tNVH + tPGS + (tPROG x 32) ≤ tHV maximum.
4. Typical endurance was evaluated for this product family. For additional information on how Freescale defines Typical
Endurance, please refer to Engineering Bulletin EB619.
5. Typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated
to 25°C using the Arrhenius equation. For additional information on how Freescale defines Typical Data Retention, please
refer to Engineering Bulletin EB618.
MC68HC908QY/QT Family Data Sheet, Rev. 4
Freescale Semiconductor
173
Electrical Specifications
MC68HC908QY/QT Family Data Sheet, Rev. 4
174
Freescale Semiconductor
Chapter 17
Ordering Information and Mechanical Specifications
17.1 Introduction
This section contains order numbers for the MC68HC908QY1, MC68HC908QY2, MC68HC908QY4,
MC68HC908QT1, MC68HC908QT2, and MC69HC908QT4. Dimensions are given for:
• 8-pin plastic dual in-line package (PDIP)
• 8-pin small outline integrated circuit (SOIC) package
• 8-pin dual flat no lead (DFN) package
• 16-pin PDIP
• 16-pin SOIC
• 16-pin thin shrink small outline package (TSSOP)
17.2 MC Order Numbers
Table 17-1. MC Order Numbers
MC Order Number
ADC
FLASH Memory
Package
16-pins
PDIP, SOIC,
and TSSOP
MC908QY1
—
1536 bytes
MC908QY2
Yes
1536 bytes
MC908QY4
Yes
4096 bytes
MC908QT1
—
1536 bytes
MC908QT2
Yes
1536 bytes
MC908QT4
Yes
4096 bytes
8-pins
PDIP, SOIC,
and DFN
Temperature and package designators:
C = –40°C to +85°C
V = –40°C to +105°C
M = –40°C to +125°C
P = Plastic dual in-line package (PDIP)
DW = Small outline integrated circuit package (SOIC)
DT = Thin shrink small outline package (TSSOP)
FQ = Dual flat no lead (DFN)
MC908QY1XXX
FAMILY
PACKAGE DESIGNATOR
TEMPERATURE RANGE
Figure 17-1. Device Numbering System
MC68HC908QY/QT Family Data Sheet, Rev. 4
Freescale Semiconductor
175
Ordering Information and Mechanical Specifications
17.3 8-Pin Plastic Dual In-Line Package (Case #626)
8
NOTES:
1. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
2. PACKAGE CONTOUR OPTIONAL (ROUND OR
SQUARE CORNERS).
3. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
5
-B1
4
DIM
A
B
C
D
F
G
H
J
K
L
M
N
F
-A-
NOTE 2
L
C
J
-TN
SEATING
PLANE
D
K
0.13 (0.005)
M
T A
M
B
INCHES
MIN MAX
0.370 0.400
0.240 0.260
0.155 0.175
0.015 0.020
0.040 0.070
0.100 BSC
0.030 0.050
0.008 0.012
0.115 0.135
0.300 BSC
--10 °
0.030 0.040
STYLE 1:
1.
AC IN
2.
DC + IN
3.
DC - IN
4.
AC IN
5.
GROUND
6.
OUTPUT
7.
AUXILIARY
8.
VCC
M
G
H
MILLIMETERS
MIN
MAX
9.40 10.16
6.10
6.60
3.94
4.45
0.38
0.51
1.02
1.78
2.54 BSC
0.76
1.27
0.20
0.30
2.92
3.43
7.62 BSC
--10 °
0.76
1.01
M
17.4 8-Pin Small Outline Integrated Circuit Package (Case #968)
8
LE
5
Q1
E HE
M×
1
4
L
Z
DETAIL P
D
e
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER
3. DIMENSION D AND E DO NOT INCLUDE MOLD
FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD
FLASH OR PROTRUSIONS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL
CONDITION. DAMBAR CANNOT BE LOCATED
ON THE LOWER RADIUS OR THE FOOT
MINIMUM SPACE BETWEEN PROTRUSIONS
AND ADJACENT LEAD TO BE 0.46 (0.018).
A1
A
P
b
0.13 (0.005)
c
M
0.10 (0.004)
DIM
A
A1
b
c
D
E
e
HE
L
LE
M
Q1
Z
MILLIMETERS
MIN
MAX
--2.05
0.05
0.20
0.35
0.50
0.18
0.27
5.10
5.50
5.10
5.45
1.27 BSC
7.40
8.20
0.50
0.85
1.10
1.50
0°
10°
0.70
0.90
--0.94
INCHES
MIN MAX
--- 0.081
0.002 0.008
0.014 0.020
0.007 0.011
0.201 0.217
0.201 0.215
0.050 BSC
0.291 0.323
0.020 0.033
0.043 0.059
0°
10°
0.028 0.035
--- 0.037
MC68HC908QY/QT Family Data Sheet, Rev. 4
176
Freescale Semiconductor
8-Pin Dual Flat No Lead (DFN) Package (Case #1452)
17.5 8-Pin Dual Flat No Lead (DFN) Package (Case #1452)
0.1 C
4
A
0.1 C
8
2X
0.1 C
5
1.0 1.00
0.8 0.75
2X
0.05 C
4
(0.35)
0.05
0.00
4
(0.8)
C
SEATING PLANE
DETAIL G
VIEW ROTATED 90 o CLOCKWISE
1
4
0.3
0.2
PIN 1
INDEX AREA
B
G
M
0.3
0.2
M
DETAIL M
BACKSIDE PIN 1 INDEX
0.1 C A B
DETAIL M
PIN 1 INDEX
1
3.5
3.4
EXPOSED DIE
ATTACH PAD
4
3.05
2.95
0.1 C A B
2.55
2.45
0.1 C A B
0.4
6X
DETAIL N
N
8X
0.5
0.4
8
5
8X
VIEW M-M
0.35
0.25
0.1
M
C A B
0.05
M
C
0.8
8X
0.065
0.015
NOTES:
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 1994.
3. THE COMPLETE JEDEC DESIGNATOR FOR THIS
PACKAGE IS: HP-VFDFP-N.
4. COPLANARITY APPLIES TO LEADS AND DIE ATTACH
PAD.
MC68HC908QY/QT Family Data Sheet, Rev. 4
Freescale Semiconductor
177
Ordering Information and Mechanical Specifications
17.6 16-Pin Plastic Dual In-Line Package (Case #648D)
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
5. MOLD FLASH OR PROTRUSIONS SHALL NOT
EXCEED 0.25 (0.010).
6. ROUNDED CORNERS OPTIONAL.
-A16
9
-B1
8
F
L
C
S
-T-
SEATING
PLANE
K
H
G
M
J
D 16 PL
0.25 (0.010)
M
T B
S
A
S
DIM
A
B
C
D
F
G
H
J
K
L
M
S
INCHES
MILLIMETERS
MIN
MAX
MIN MAX
0.740 0.760 18.80 19.30
0.245 0.260
6.23
6.60
0.145 0.175
3.69
4.44
0.015 0.021
0.39
0.53
0.050 0.070
1.27
1.77
0.100 BSC
2.54 BSC
0.050 BSC
1.27 BSC
0.008 0.015
0.21
0.38
0.120 0.140
3.05
3.55
0.295 0.305
7.50
7.74
0°
10°
0°
10°
0.015 0.035
0.39
0.88
17.7 16-Pin Small Outline Integrated Circuit Package (Case #751G)
A
D
q
9
1
8
H
h X 45 °
E
0.25
8X
M
B
M
16
16X
M
14X
e
T A
S
B
S
A1
L
A
0.25
B
B
SEATING
PLANE
T
C
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND
TOLERANCES PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INLCUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER
SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 TOTAL IN
EXCESS OF THE B DIMENSION AT MAXIMUM
MATERIAL CONDITION.
MILLIMETERS
DIM MIN
MAX
A
2.35
2.65
A1 0.10
0.25
B
0.35
0.49
C
0.23
0.32
D 10.15 10.45
E
7.40
7.60
e
1.27 BSC
H 10.05 10.55
h
0.25
0.75
L
0.40
1.00
q
0°
7°
MC68HC908QY/QT Family Data Sheet, Rev. 4
178
Freescale Semiconductor
16-Pin Thin Shrink Small Outline Package (Case #948F)
17.8 16-Pin Thin Shrink Small Outline Package (Case #948F)
16X K REF
0.10 (0.004) M T U
0.15 (0.006) T U
V
S
S
S
K
K1
2X
L/2
16
9
J1
B
-U-
L
SECTION N-N
J
PIN 1
IDENT.
8
1
N
0.25 (0.010)
0.15 (0.006) T U
S
A
-V-
M
NOTES:
4. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
5. CONTROLLING DIMENSION: MILLIMETER.
6. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
7. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED
0.25 (0.010) PER SIDE.
8. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL
IN EXCESS OF THE K DIMENSION AT
MAXIMUM MATERIAL CONDITION.
9. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
10. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE -W-.
N
F
DETAIL E
-W-
C
0.10 (0.004)
-T- SEATING
PLANE
H
D
DETAIL E
G
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
4.90
5.10
4.30
4.50
--1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.18
0.28
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0°
8°
INCHES
MIN MAX
0.193 0.200
0.169 0.177
--- 0.047
0.002 0.006
0.020 0.030
0.026 BSC
0.007 0.011
0.004 0.008
0.004 0.006
0.007 0.012
0.007 0.010
0.252 BSC
0°
8°
MC68HC908QY/QT Family Data Sheet, Rev. 4
Freescale Semiconductor
179
Ordering Information and Mechanical Specifications
MC68HC908QY/QT Family Data Sheet, Rev. 4
180
Freescale Semiconductor
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MC68HC908QY4
Rev. 4, 11/2004
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