FREESCALE MC68HC908GP32CBE

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MC68HC908GP32
Data Sheet
M68HC08
Microcontrollers
MC68HC908GP32
Rev. 10
1/2008
freescale.com
深圳市南天星电子科技有限公司
专业代理
Freescale
ON Semi
Atmel
TI
ADI
IR
Microchip
NXP
飞思卡尔
安森美
爱特梅尔
德州仪器
模拟器件
国际整流器
微芯
恩智浦
深圳市南天星电子科技有限公司
电话：0755－83040796 83040795
传真：0755－83040790
邮箱：[email protected]
网址：www.soustar.com.cn
地址：深圳市福田区福明路雷圳大厦 2306 室
MC68HC908GP32
Data Sheet
To provide the most up-to-date information, the revision of our documents on the World Wide Web will be
the most current. Your printed copy may be an earlier revision. To verify you have the latest information
available, refer to:
http://freescale.com
The following revision history table summarizes changes contained in this document. For your
convenience, the page number designators have been linked to the appropriate location.
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc.
This product incorporates SuperFlash® technology licensed from SST.
© Freescale Semiconductor, Inc., 2001, 2006, 2008. All rights reserved.
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
3
Revision History
Revision History
Date
July,
2001
August,
2002
August,
2005
March,
2006
Revision
Level
Page
Number(s)
Description
In Table 15-1, second cell in "Comment" column, corrected PTC to
PTC1.
199
In Figure 21-2, Timebase control register, bit 0 is a reserved bit.
337
Updated crystal oscillator component values in 23.17.1 CGM
Component Specifications.
387
Added appendix A: MC68HC08GP32 — ROM part.
397
Section 22. Timer Interface Module (TIM) — Timer discrepancies
corrected throughout this section.
341
Section 24. Mechanical Specifications — Replaced incorrect 44-pin QFP
drawing, case 824E to case 824A.
393
5
6
6.1
Updated to meet Freescale identity guidelines.
Throughout
3.5 Clock Generator Module (CGM) — Updated description to remove
erroneous information.
46
19.16.1 CGM Component Specifications — Updated to reflect correct
values.
250
7
April,
2007
8
12.5.1 Port D Data Register — Corrected the description of the slave
select (SS) bit.
123
June,
2007
9
Never released. Typos.
N/A
Deleted the Resets and Interrupts Chapter because it was redundant
N/A
Chapter 2 Memory — Removed DMA bit references
N/A
Chapter 2 Memory — Integrated RAM and FLASH sections
N/A
2.6 FLASH Memory — Updated FLASH erase, programming, and block
protect information
38
4.7.1 ADC Status and Control Register — Corrected COCO bit
description
56
9.4 Interrupts — Updated External Interrupt Module information
103
Chapter 10 Keyboard Interrupt (KBI) Module — Updated KBI module
information
105
Chapter 12 Input/Output (I/O) Ports — Added unused pins note
115
Chapter 13 Serial Communications Interface Module (SCI) — Removed
DMA references
131
Figure 13-1. SCI Module Block Diagram — Replaced SCI block diagram
133
Figure 13-4. SCI Transmitter Block Diagram — Replaced SCI
transmitter block diagram
135
January,
2008
10
MC68HC908GP32 Data Sheet, Rev. 10
4
Freescale Semiconductor
Revision History
Date
January,
2008
Revision
Level
Description
Page
Number(s)
Figure 13-5. SCI Receiver Block Diagram — Replaced SCI receiver
block diagram
138
Chapter 14 System Integration Module (SIM) — Corrected Break
interrupt and SBSW bit descriptions
157
14.7.2 SIM Reset Status Register — Updated SIM reset status register
information
172
Chapter 15 Serial Peripheral Interface Module (SPI) — Deleted IIC
reference
175
Chapter 15 Serial Peripheral Interface Module (SPI) — Removed DMA
references
175
Figure 15-2. SPI Module Block Diagram — Replaced SPI module block
diagram
177
Table 17-3. Mode, Edge, and Level Selection — Added software output
compare to mode table
212
Chapter 18 Development Support — Integrated Break module and
monitor mode chapters into Development Support Chapter
215
10
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
5
Revision History
MC68HC908GP32 Data Sheet, Rev. 10
6
Freescale Semiconductor
List of Chapters
Chapter 1 General Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Chapter 2 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Chapter 3 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Chapter 4 Analog-to-Digital Converter (ADC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Chapter 5 Clock Generator Module (CGM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Chapter 6 Configuration Register (CONFIG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
Chapter 7 Computer Operating Properly (COP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
Chapter 8 Central Processor Unit (CPU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
Chapter 9 External Interrupt (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
Chapter 10 Keyboard Interrupt (KBI) Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
Chapter 11 Low-Voltage Inhibit (LVI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
Chapter 12 Input/Output (I/O) Ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
Chapter 13 Serial Communications Interface Module (SCI) . . . . . . . . . . . . . . . . . . . . . . .131
Chapter 14 System Integration Module (SIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157
Chapter 15 Serial Peripheral Interface Module (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175
Chapter 16 Timebase Module (TBM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .195
Chapter 17 Timer Interface Module (TIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199
Chapter 18 Development Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215
Chapter 19 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .233
Chapter 20 Mechanical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .255
Chapter 21 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .263
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
7
List of Chapters
MC68HC908GP32 Data Sheet, Rev. 10
8
Freescale Semiconductor
Table of Contents
Chapter 1
General Description
1.1
1.2
1.2.1
1.2.2
1.3
1.4
1.5
1.5.1
1.5.2
1.5.3
1.5.4
1.5.5
1.5.6
1.5.7
1.5.8
1.5.9
1.5.10
1.5.11
1.5.12
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Standard Features of the MC68HC908GP32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features of the CPU08 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Supply Pins (VDD and VSS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Oscillator Pins (OSC1 and OSC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Reset Pin (RST). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Interrupt Pin (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CGM Power Supply Pins (VDDA and VSSA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Filter Capacitor Pin (CGMXFC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADC Power Supply/Reference Pins (VDDAD/VREFH and VSSAD/VREFL). . . . . . . . . . . . . . . .
Port A Input/Output (I/O) Pins (PTA7/KBD7–PTA0/KBD0) . . . . . . . . . . . . . . . . . . . . . . . . .
Port B I/O Pins (PTB7/AD7–PTB0/AD0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port C I/O Pins (PTC6–PTC0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port D I/O Pins (PTD7/T2CH1–PTD0/SS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port E I/O Pins (PTE1/RxD–PTE0/TxD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21
21
21
22
23
24
26
26
27
27
27
27
27
27
28
28
28
28
28
Chapter 2
Memory
2.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2
Unimplemented Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3
Reserved Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4
Input/Output (I/O) Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5
Random-Access Memory (RAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6
FLASH Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6.1
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6.2
FLASH Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6.3
FLASH Page Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6.4
FLASH Mass Erase Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6.5
FLASH Program Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6.6
FLASH Block Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6.6.1
FLASH Block Protect Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6.7
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6.8
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
29
29
29
29
38
38
38
39
39
40
40
42
44
45
45
MC68HC908GP32 Data Sheet, Rev. 10
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Table of Contents
Chapter 3
Low-Power Modes
3.1
3.1.1
3.1.2
3.2
3.2.1
3.2.2
3.3
3.3.1
3.3.2
3.4
3.4.1
3.4.2
3.5
3.5.1
3.5.2
3.6
3.6.1
3.6.2
3.7
3.7.1
3.7.2
3.8
3.8.1
3.8.2
3.9
3.9.1
3.9.2
3.10
3.10.1
3.10.2
3.11
3.11.1
3.11.2
3.12
3.12.1
3.12.2
3.13
3.13.1
3.13.2
3.14
3.15
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog-to-Digital Converter (ADC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Break Module (BRK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Central Processor Unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Generator Module (CGM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Computer Operating Properly Module (COP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Interrupt Module (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Keyboard Interrupt Module (KBI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Low-Voltage Inhibit Module (LVI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Communications Interface Module (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Peripheral Interface Module (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer Interface Module (TIM1 and TIM2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timebase Module (TBM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Exiting Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Exiting Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
47
47
47
47
47
47
47
47
48
48
48
48
48
48
48
48
48
49
49
49
49
49
49
49
49
49
49
50
50
50
50
50
50
50
50
50
51
51
51
51
52
MC68HC908GP32 Data Sheet, Rev. 10
10
Freescale Semiconductor
Chapter 4
Analog-to-Digital Converter (ADC)
4.1
4.2
4.3
4.3.1
4.3.2
4.3.3
4.3.4
4.3.5
4.4
4.5
4.5.1
4.5.2
4.6
4.6.1
4.6.2
4.6.3
4.7
4.7.1
4.7.2
4.7.3
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADC Port I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Accuracy and Precision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADC Analog Power Pin (VDDAD)/ADC Voltage Reference High Pin (VREFH) . . . . . . . . . . .
ADC Analog Ground Pin (VSSAD)/ADC Voltage Reference Low Pin (VREFL) . . . . . . . . . . .
ADC Voltage In (VADIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADC Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADC Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADC Clock Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
53
53
53
53
53
54
55
55
55
55
55
55
55
55
56
56
56
56
58
58
Chapter 5
Clock Generator Module (CGM)
5.1
5.2
5.3
5.3.1
5.3.2
5.3.3
5.3.4
5.3.5
5.3.6
5.3.7
5.3.8
5.3.9
5.4
5.4.1
5.4.2
5.4.3
5.4.4
5.4.5
5.4.6
5.4.7
5.4.8
5.4.9
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Crystal Oscillator Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Phase-Locked Loop Circuit (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PLL Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Acquisition and Tracking Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Manual and Automatic PLL Bandwidth Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Programming the PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Special Programming Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Base Clock Selector Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CGM External Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Crystal Amplifier Input Pin (OSC1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Crystal Amplifier Output Pin (OSC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Filter Capacitor Pin (CGMXFC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PLL Analog Power Pin (VDDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PLL Analog Ground Pin (VSSA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Oscillator Enable Signal (SIMOSCEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Oscillator Stop Mode Enable Bit (OSCSTOPENB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Crystal Output Frequency Signal (CGMXCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CGM Base Clock Output (CGMOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
61
61
61
63
63
63
64
64
65
68
68
68
69
69
69
69
70
70
70
70
70
70
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
11
Table of Contents
5.4.10
5.5
5.5.1
5.5.2
5.5.3
5.5.4
5.5.5
5.5.6
5.6
5.7
5.7.1
5.7.2
5.7.3
5.8
5.8.1
5.8.2
5.8.3
CGM CPU Interrupt (CGMINT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CGM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PLL Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PLL Bandwidth Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PLL Multiplier Select Register High . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PLL Multiplier Select Register Low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PLL VCO Range Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PLL Reference Divider Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Special Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CGM During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Acquisition/Lock Time Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Acquisition/Lock Time Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Parametric Influences on Reaction Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Choosing a Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
70
71
72
73
74
75
75
76
76
77
77
77
77
78
78
78
79
Chapter 6
Configuration Register (CONFIG)
6.1
6.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Chapter 7
Computer Operating Properly (COP)
7.1
7.2
7.3
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
7.3.6
7.3.7
7.3.8
7.4
7.5
7.6
7.7
7.7.1
7.7.2
7.8
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CGMXCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
STOP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
COPCTL Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Internal Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reset Vector Fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
COPD (COP Disable). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
COPRS (COP Rate Select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
COP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
COP Module During Break Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
85
85
86
86
86
86
86
86
86
87
87
87
87
87
87
87
87
88
MC68HC908GP32 Data Sheet, Rev. 10
12
Freescale Semiconductor
Chapter 8
Central Processor Unit (CPU)
8.1
8.2
8.3
8.3.1
8.3.2
8.3.3
8.3.4
8.3.5
8.4
8.5
8.5.1
8.5.2
8.6
8.7
8.8
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
89
89
89
90
90
91
91
92
93
93
93
93
93
94
99
Chapter 9
External Interrupt (IRQ)
9.1
9.2
9.3
9.3.1
9.3.2
9.4
9.5
9.5.1
9.5.2
9.6
9.7
9.7.1
9.8
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MODE = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MODE = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IRQ Module During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IRQ Input Pins (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
101
101
101
102
102
103
103
103
103
103
103
103
104
Chapter 10
Keyboard Interrupt (KBI) Module
10.1
10.2
10.3
10.4
10.4.1
10.4.2
10.4.3
10.5
10.6
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Keyboard Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MODEK = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MODEK = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Keyboard Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
105
105
105
106
106
106
107
107
107
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10.6.1
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.6.2
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.7 KBI During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.8 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.8.1
KBI Input Pins (KBI7:KBI0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.9 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.9.1
Keyboard Status and Control Register (INTKBSCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.9.2
Keyboard Interrupt Enable Register (INTKBIER). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
107
107
107
108
108
108
108
109
Chapter 11
Low-Voltage Inhibit (LVI)
11.1
11.2
11.3
11.3.1
11.3.2
11.3.3
11.3.4
11.4
11.5
11.6
11.6.1
11.6.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Polled LVI Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Forced Reset Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage Hysteresis Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LVI Trip Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LVI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LVI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
111
111
111
112
112
113
113
113
113
114
114
114
Chapter 12
Input/Output (I/O) Ports
12.1
12.2
12.2.1
12.2.2
12.2.3
12.3
12.3.1
12.3.2
12.4
12.4.1
12.4.2
12.4.3
12.5
12.5.1
12.5.2
12.5.3
12.6
12.6.1
12.6.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Direction Register A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port A Input Pullup Enable Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port B Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Direction Register B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port C Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Direction Register C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port C Input Pullup Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port D Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Direction Register D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port D Input Pullup Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port E Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Direction Register E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
115
118
118
118
119
120
120
120
122
122
122
124
124
124
125
127
127
127
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Chapter 13
Serial Communications Interface Module (SCI)
13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.3 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.4.1
Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.4.2
Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.4.2.1
Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.4.2.2
Character Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.4.2.3
Break Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.4.2.4
Idle Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.4.2.5
Inversion of Transmitted Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.4.2.6
Transmitter Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.4.3
Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.4.3.1
Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.4.3.2
Character Reception. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.4.3.3
Data Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.4.3.4
Framing Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.4.3.5
Baud Rate Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.4.3.6
Receiver Wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.4.3.7
Receiver Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.4.3.8
Error Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.5.1
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.5.2
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.6 SCI During Break Module Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.7.1
PTE0/TxD (Transmit Data). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.7.2
PTE1/RxD (Receive Data) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.8 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.8.1
SCI Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.8.2
SCI Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.8.3
SCI Control Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.8.4
SCI Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.8.5
SCI Status Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.8.6
SCI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.8.7
SCI Baud Rate Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
131
131
131
132
134
135
135
136
136
136
137
137
137
137
137
139
140
140
142
143
143
144
144
144
144
144
144
145
145
145
147
149
150
152
153
153
Chapter 14
System Integration Module (SIM)
14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.2 SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.2.1
Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.2.2
Clock Startup from POR or LVI Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.2.3
Clocks in Stop Mode and Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.3 Reset and System Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
157
159
160
160
160
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14.3.1
External Pin Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.3.2
Active Resets from Internal Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.3.2.1
Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.3.2.2
Computer Operating Properly (COP) Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.3.2.3
Illegal Opcode Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.3.2.4
Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.3.2.5
Low-Voltage Inhibit (LVI) Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.3.2.6
Monitor Mode Entry Module Reset (MODRST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.4 SIM Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.4.1
SIM Counter During Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.4.2
SIM Counter During Stop Mode Recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.4.3
SIM Counter and Reset States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.5 Exception Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.5.1
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.5.1.1
Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.5.1.2
SWI Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.5.1.3
Interrupt Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.5.2
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.5.3
Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.5.4
Status Flag Protection in Break Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.6.1
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.6.2
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.7 SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.7.1
SIM Break Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.7.2
SIM Reset Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.7.3
SIM Break Flag Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
160
161
161
162
162
163
163
163
163
163
163
163
164
164
166
166
167
168
168
169
169
169
170
171
172
172
173
Chapter 15
Serial Peripheral Interface Module (SPI)
15.1
15.2
15.3
15.4
15.4.1
15.4.2
15.5
15.5.1
15.5.2
15.5.3
15.5.4
15.6
15.7
15.7.1
15.7.2
15.8
15.9
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmission Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Phase and Polarity Controls. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmission Format When CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmission Format When CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmission Initiation Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Queuing Transmission Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overflow Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mode Fault Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Resetting the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
175
175
175
176
176
178
178
178
179
180
180
181
182
183
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15.10 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15.10.1
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15.10.2
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15.11 SPI During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15.12 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15.12.1
MISO (Master In/Slave Out). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15.12.2
MOSI (Master Out/Slave In). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15.12.3
SPSCK (Serial Clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15.12.4
SS (Slave Select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15.12.5
CGND (Clock Ground) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15.13 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15.13.1
SPI Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15.13.2
SPI Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15.13.3
SPI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
187
187
187
187
188
188
188
188
189
189
190
190
191
193
Chapter 16
Timebase Module (TBM)
16.1
16.2
16.3
16.4
16.5
16.6
16.6.1
16.6.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timebase Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
195
195
195
196
197
198
198
198
Chapter 17
Timer Interface Module (TIM)
17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.3 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.4.1
TIM Counter Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.4.2
Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.4.3
Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.4.3.1
Unbuffered Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.4.3.2
Buffered Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.4.4
Pulse Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.4.4.1
Unbuffered PWM Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.4.4.2
Buffered PWM Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.4.4.3
PWM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.6.1
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.6.2
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.7 TIM During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
199
199
199
200
203
203
203
203
203
204
205
205
206
207
207
207
207
207
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17.8 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.9 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.9.1
TIM Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.9.2
TIM Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.9.3
TIM Counter Modulo Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.9.4
TIM Channel Status and Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.9.5
TIM Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
208
208
208
209
210
211
213
Chapter 18
Development Support
18.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18.2 Break Module (BRK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18.2.1
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18.2.1.1
Flag Protection During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18.2.1.2
TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18.2.1.3
COP During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18.2.2
Break Module Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18.2.2.1
Break Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18.2.2.2
Break Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18.2.2.3
SIM Break Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18.2.2.4
SIM Break Flag Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18.2.3
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18.3 Monitor Module (MON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18.3.1
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18.3.1.1
Normal Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18.3.1.2
Forced Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18.3.1.3
Monitor Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18.3.1.4
Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18.3.1.5
Break Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18.3.1.6
Baud Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18.3.1.7
Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18.3.2
Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
215
215
215
217
217
217
217
218
218
219
219
219
220
220
225
226
226
227
227
227
227
231
Chapter 19
Electrical Specifications
19.1
19.2
19.3
19.4
19.5
19.6
19.7
19.8
19.9
19.10
19.11
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.0-V DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.0-V DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.0-V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.0-V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output High-Voltage Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Low-Voltage Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Typical Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
233
233
234
234
235
237
239
240
241
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19.12 ADC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.13 5.0-V SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.14 3.0-V SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.15 Timer Interface Module Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.16 Clock Generation Module Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.16.1
CGM Component Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.16.2
CGM Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.17 Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
246
247
248
251
252
252
253
253
Chapter 20
Mechanical Specifications
20.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
Chapter 21
Ordering Information
21.1
21.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
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MC68HC908GP32 Data Sheet, Rev. 10
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Chapter 1
General Description
1.1 Introduction
The MC68HC908GP32 is a member of the low-cost, high-performance M68HC08 Family of 8-bit
microcontroller units (MCUs). All MCUs in the family use the enhanced M68HC08 central processor unit
(CPU08) and are available with a variety of modules, memory sizes and types, and package types.
1.2 Features
For convenience, features have been organized to reflect:
• Standard features of the MC68HC908GP32
• Features of the CPU08
1.2.1 Standard Features of the MC68HC908GP32
•
•
•
•
•
•
•
•
•
•
•
•
•
•
High-performance M68HC08 architecture optimized for C-compilers
Fully upward-compatible object code with M6805, M146805, and M68HC05 Families
8-MHz internal bus frequency
FLASH program memory security(1)
On-chip programming firmware for use with host personal computer which does not require high
voltage for entry
In-system programming
System protection features:
– Optional computer operating properly (COP) reset
– Low-voltage detection with optional reset and selectable trip points for 3.0-V and 5.0-V
operation
– Illegal opcode detection with reset
– Illegal address detection with reset
Low-power design; fully static with stop and wait modes
Standard low-power modes of operation:
– Wait mode
– Stop mode
Master reset pin and power-on reset (POR)
32 Kbytes of on-chip FLASH memory with in-circuit programming capabilities of FLASH program
memory
512 bytes of on-chip random-access memory (RAM)
Serial peripheral interface module (SPI)
Serial communications interface module (SCI)
1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for
unauthorized users.
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General Description
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Two 16-bit, 2-channel timer interface modules (TIM1 and TIM2) with selectable input capture,
output compare, and PWM capability on each channel
8-channel, 8-bit successive approximation analog-to-digital converter (ADC)
BREAK module (BRK) to allow single breakpoint setting during in-circuit debugging
Internal pullups on IRQ and RST to reduce customer system cost
Clock generator module with on-chip 32-kHz crystal compatible PLL (phase-lock loop)
Up to 33 general-purpose input/output (I/O) pins, including:
– 26 shared-function I/O pins
– Five or seven dedicated I/O pins, depending on package choice
Selectable pullups on inputs only on ports A, C, and D. Selection is on an individual port bit basis.
During output mode, pullups are disengaged.
High current 10-mA sink/10-mA source capability on all port pins
Higher current 15-mA sink/source capability on PTC0–PTC4
Timebase module with clock prescaler circuitry for eight user selectable periodic real-time
interrupts with optional active clock source during stop mode for periodic wakeup from stop using
an external 32-kHz crystal
Oscillator stop mode enable bit (OSCSTOPENB) in the CONFIG register to allow user selection of
having the oscillator enabled or disabled during stop mode
8-bit keyboard wakeup port
40-pin plastic dual-in-line package (PDIP), 42-pin shrink dual-in-line package (SDIP), or 44-pin
quad flat pack (QFP)
Specific features of the MC68HC908GP32 in 40-pin PDIP are:
– Port C is only 5 bits: PTC0–PTC4
– Port D is only 6 bits: PTD0–PTD5; single 2-channel TIM module
Specific features of the MC68HC908GP32 in 42-pin SDIP are:
– Port C is only 5 bits: PTC0–PTC4
– Port D is 8 bits: PTD0–PTD7; dual 2-channel TIM modules
Specific features of the MC68HC908GP32 in 44-pin QFP are:
– Port C is 7 bits: PTC0–PTC6
– Port D is 8 bits: PTD0–PTD7; dual 2-channel TIM modules
1.2.2 Features of the CPU08
Features of the CPU08 include:
• Enhanced HC05 programming model
• Extensive loop control functions
• 16 addressing modes (eight more than the HC05)
• 16-bit index register and stack pointer
• Memory-to-memory data transfers
• Fast 8 × 8 multiply instruction
• Fast 16/8 divide instruction
• Binary-coded decimal (BCD) instructions
• Optimization for controller applications
• Efficient C language support
MC68HC908GP32 Data Sheet, Rev. 10
22
Freescale Semiconductor
MCU Block Diagram
1.3 MCU Block Diagram
Figure 1-1 shows the structure of the MC68HC908GP32. Text in parentheses within a module block
indicates the module name. Text in parentheses next to a signal indicates the module which uses the
signal.
INTERNAL BUS
PTC6 †
PTC5 †
PTC4 † ‡
PTC3 † ‡
PTC2 † ‡
PTC1 † ‡
PTC0 † ‡
PTD7/T2CH1 †
PTD6/T2CH0 †
PTD5/T1CH1 †
PTD4/T1CH0 †
PTD3/SPSCK †
PTD2/MOSI †
PTD1/MISO †
PTD0/SS †
PTE1/RxD
PTE0/TxD
DDRA
PORTA
USER RAM — 512 BYTES
DDRB
DUAL VOLTAGE
LOW-VOLTAGE INHIBIT MODULE
PORTB
USER FLASH — 32,256 BYTES
PTB7/AD7
PTB6/AD6
PTB5/AD5
PTB4/AD4
PTB3/AD3
PTB2/AD2
PTB1/AD1
PTB0/AD0
PORTC
SINGLE BREAKPOINT BREAK
MODULE
DDRD
CONTROL AND STATUS REGISTERS — 64 BYTES
PTA7/KBD7–
PTA0/KBD0 †
PORTD
PROGRAMMABLE TIMEBASE
MODULE
DDRE
ARITHMETIC/LOGIC
UNIT (ALU)
CPU
REGISTERS
PORTE
M68HC08 CPU
8-BIT KEYBOARD
INTERRUPT MODULE
MONITOR ROM — 307 BYTES
USER FLASH VECTOR SPACE — 36 BYTES
CLOCK GENERATOR MODULE
OSC1
OSC2
CGMXFC
2-CHANNEL TIMER INTERFACE
MODULE 2
DDRC
2-CHANNEL TIMER INTERFACE
MODULE 1
32-kHz OSCILLATOR
SERIAL COMMUNICATIONS
INTERFACE MODULE
PHASE-LOCKED LOOP
COMPUTER OPERATING
PROPERLY MODULE
* RST
24 INTR SYSTEM INTEGRATION
MODULE
* IRQ
SINGLE EXTERNAL IRQ
MODULE
VDDAD/VREFH
VSSAD/VREFL
MONITOR MODULE
8-BIT ANALOG-TO-DIGITAL
CONVERTER MODULE
POWER-ON RESET
MODULE
VDD
VSS
VDDA
VSSA
SERIAL PERIPHERAL
INTERFACE MODULE
DATA BUS SWITCH
MODULE
MEMORY MAP
MODULE
POWER
SECURITY
MODULE
CONFIGURATION REGISTER 1
MODULE
CONFIGURATION REGISTER 2
MODULE
MONITOR MODE ENTRY
MODULE
† Ports are software configurable with pullup device if input port.
‡ Higher current drive port pins
* Pin contains integrated pullup device
Figure 1-1. MCU Block Diagram
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
23
General Description
1.4 Pin Assignments
VDDA (PLL)
1
40
PTA7/KBD7
VSSA (PLL)
2
39
PTA6/KBD6
CGMXFC (PLL)
3
38
PTA5/KBD5
OSC2
4
37
PTA4/KBD4
OSC1
5
36
PTA3/KBD3
RST
6
35
PTA2/KBD2
PTC0
7
34
PTA1/KBD1
PTC1
8
33
PTA0/KBD0
PTC2
9
32
VSSAD/VREFL (ADC)
PTC3
10
31
VDDAD/VREFH (ADC)
PTC4
11
30
PTB7/AD7
PTE0/TxD
12
29
PTB6/AD6
PTE1/RxD
13
28
PTB5/AD5
IRQ
14
27
PTB4/AD4
PTD0/SS
15
26
PTB3/AD3
PTD1/MISO
16
25
PTB2/AD2
PTD2/MOSI
17
24
PTB1/AD1
PTD3/SPSCK
18
23
PTB0/AD0
VSS
19
22
PTD5/T1CH1
VDD
20
21
PTD4/T1CH0
Pins Not Available
on 40-Pin Package
Internal
Connection
PTC5
Connected to ground
PTC6
Connected to ground
PTD6/T2CH0
Unconnected
PTD7/T2CH1
Unconnected
Figure 1-2. 40-Pin PDIP Pin Assignments
MC68HC908GP32 Data Sheet, Rev. 10
24
Freescale Semiconductor
Pin Assignments
VDDA (PLL)
1
42
PTA7/KBD7
VSSA (PLL)
2
41
PTA6/KBD6
CGMXFC (PLL)
3
40
PTA5/KBD5
OSC2
4
39
PTA4/KBD4
OSC1
5
38
PTA3/KBD3
RST
6
37
PTA2/KBD2
PTC0
7
36
PTA1/KBD1
PTC1
8
35
PTA0/KBD0
PTC2
9
34
VSSAD/VREFL (ADC)
PTC3
10
33
VDDAD/VREFH (ADC)
PTC4
11
32
PTB7/AD7
PTE0/TxD
12
31
PTB6/AD6
PTE1/RxD
13
30
PTB5/AD5
IRQ
14
29
PTB4/AD4
PTD0/SS
15
28
PTB3/AD3
PTD1/MISO
16
27
PTB2/AD2
PTD2/MOSI
17
26
PTB1/AD1
PTD3/SPSCK
18
25
PTB0/AD0
VSS
19
24
PTD7/T2CH1
VDD
20
23
PTD6/T2CH0
PTD4/T1CH0
21
22
PTD5/T1CH1
Pins Not Available
on 42-Pin Package
Internal
Connection
PTC5
Connected to ground
PTC6
Connected to ground
Figure 1-3. 42-Pin SDIP Pin Assignments
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
25
34 PTA2/KBD2
PTA3/KBD3
PTA6/KBD6
38
35
PTA7/KBD7
39
PTA4/KBD4
VDDA
40
36
VSSA
41
PTA5/KBD5
CGMXFC
42
37
OSC2
RST 1
43
44 OSC1
General Description
33 PTA1/KBD1
28
PTB6/AD6
PTC5
7
27
PTB5/AD5
PTC6
8
26
PTB4/AD4
PTE0/TxD
9
25
PTB3/AD3
PTE1/RxD
10
24
PTB2/AD2
23 PTB1/AD1
PTB0/AD0 22
PTD0/SS 12
IRQ 11
21
6
PTD7/T2CH1
PTC4
20
PTB7/AD7
PTD6/T2CH0
29
19
5
PTD5/T1CH1
PTC3
18
VDDAD/VREFH
PTD4/T1CH0
30
17
4
VDD
PTC2
16
VSSAD/VREFL
VSS
31
15
3
PTD3/SPSCK
PTC1
14
PTA0/KBD0
PTD2/MOSI
32
13
2
PTD1/MISO
PTC0
Figure 1-4. 44-Pin QFP Pin Assignments
1.5 Pin Functions
Descriptions of the pin functions are provided here.
1.5.1 Power Supply Pins (VDD and VSS)
VDD and VSS are the power supply and ground pins. The MCU operates from a single power supply.
Fast signal transitions on MCU pins place high, short-duration current demands on the power supply. To
prevent noise problems, take special care to provide power supply bypassing at the MCU as Figure 1-5
shows. Place the C1 bypass capacitor as close to the MCU as possible. Use a high-frequency-response
ceramic capacitor for C1. C2 is an optional bulk current bypass capacitor for use in applications that
require the port pins to source high current levels.
MC68HC908GP32 Data Sheet, Rev. 10
26
Freescale Semiconductor
Pin Functions
MCU
VDD
VSS
C1
0.1 µF
+
C2
VDD
NOTE: Component values shown
represent typical applications.
Figure 1-5. Power Supply Bypassing
1.5.2 Oscillator Pins (OSC1 and OSC2)
The OSC1 and OSC2 pins are the connections for the on-chip oscillator circuit. See Chapter 5 Clock
Generator Module (CGM).
1.5.3 External Reset Pin (RST)
A low on the RST pin forces the MCU to a known startup state. RST is bidirectional, allowing a reset of
the entire system. It is driven low when any internal reset source is asserted. This pin contains an internal
pullup resistor. See Chapter 14 System Integration Module (SIM).
1.5.4 External Interrupt Pin (IRQ)
IRQ is an asynchronous external interrupt pin. This pin contains an internal pullup resistor.
See Chapter 9 External Interrupt (IRQ).
1.5.5 CGM Power Supply Pins (VDDA and VSSA)
VDDA and VSSA are the power supply pins for the analog portion of the clock generator module (CGM).
Connect the VDDA pin to the same voltage potential as VDD, and the VSSA pin to the same voltage
potential as VSS. Decoupling of these pins should be as per the digital supply. See Chapter 5 Clock
Generator Module (CGM)
1.5.6 External Filter Capacitor Pin (CGMXFC)
CGMXFC is an external filter capacitor connection for the CGM. See Chapter 5 Clock Generator Module
(CGM)
1.5.7 ADC Power Supply/Reference Pins (VDDAD/VREFH and VSSAD/VREFL)
VDDAD and VSSAD are the power supply pins for the analog-to-digital converter (ADC). Connect the VDDAD
pin to the same voltage potential as VDD, and the VSSAD pin to the same voltage potential as VSS.
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
27
General Description
Decoupling of these pins should be as per the digital supply. See Chapter 4 Analog-to-Digital Converter
(ADC).
VREFH is the high reference supply for the ADC, and is internally connected to VDDAD. VREFL is the low
reference supply for the ADC, and is internally connected to VSSAD.
1.5.8 Port A Input/Output (I/O) Pins (PTA7/KBD7–PTA0/KBD0)
PTA7–PTA0 are general-purpose, bidirectional I/O port pins. Any or all of the port A pins can be
programmed to serve as keyboard interrupt pins. See Chapter 12 Input/Output (I/O) Ports and Chapter
10 Keyboard Interrupt (KBI) Module.
These port pins also have selectable pullups when configured for input mode. The pullups are disengaged
when configured for output mode. The pullups are selectable on an individual port bit basis.
1.5.9 Port B I/O Pins (PTB7/AD7–PTB0/AD0)
PTB7–PTB0 are general-purpose, bidirectional I/O port pins that can also be used for analog-to-digital
converter (ADC) inputs. See Chapter 12 Input/Output (I/O) Ports and Chapter 4 Analog-to-Digital
Converter (ADC).
1.5.10 Port C I/O Pins (PTC6–PTC0)
PTC6–PTC0 are general-purpose, bidirectional I/O port pins. See Chapter 12 Input/Output (I/O) Ports.
PTC5 and PTC6 are only available on 44-pin QFP package.
These port pins also have selectable pullups when configured for input mode. The pullups are disengaged
when configured for output mode. The pullups are selectable on an individual port bit basis.
1.5.11 Port D I/O Pins (PTD7/T2CH1–PTD0/SS)
PTD7–PTD0 are special-function, bidirectional I/O port pins. PTD0–PTD3 can be programmed to be
serial peripheral interface (SPI) pins, while PTD4–PTD7 can be individually programmed to be timer
interface module (TIM1 and TIM2) pins. See Chapter 17 Timer Interface Module (TIM), Chapter 15 Serial
Peripheral Interface Module (SPI), and Chapter 12 Input/Output (I/O) Ports. PTD6 and PTD7 are only
available on 42-SDIP and 44-pin QFP packages.
These port pins also have selectable pullups when configured for input mode. The pullups are disengaged
when configured for output mode. The pullups are selectable on an individual port bit basis.
1.5.12 Port E I/O Pins (PTE1/RxD–PTE0/TxD)
PTE0–PTE1 are general-purpose, bidirectional I/O port pins. These pins can also be programmed to be
serial communications interface (SCI) pins. See Chapter 13 Serial Communications Interface Module
(SCI) and Chapter 12 Input/Output (I/O) Ports.
MC68HC908GP32 Data Sheet, Rev. 10
28
Freescale Semiconductor
Chapter 2
Memory
2.1 Introduction
The CPU08 can address 64 Kbytes of memory space. The memory map, shown in Figure 2-1, includes:
• 32,256 bytes of user FLASH memory
• 512 bytes of random-access memory (RAM)
• 36 bytes of user-defined vectors
• 307 bytes of monitor ROM
2.2 Unimplemented Memory Locations
Accessing an unimplemented location can cause an illegal address reset. In the memory map (Figure 2-1)
and in register figures in this document, unimplemented locations are shaded.
2.3 Reserved Memory Locations
Accessing a reserved location can have unpredictable effects on MCU operation. In the Figure 2-1 and
in register figures in this document, reserved locations are marked with the word Reserved or with the
letter R.
2.4 Input/Output (I/O) Section
Most of the control, status, and data registers are in the zero page area of $0000–$003F. Additional I/O
registers have these addresses:
• $FE00; SIM break status register, SBSR
• $FE01; SIM reset status register, SRSR
• $FE02; reserved, SUBAR
• $FE03; SIM break flag control register, SBFCR
• $FE04; interrupt status register 1, INT1
• $FE05; interrupt status register 2, INT2
• $FE06; interrupt status register 3, INT3
• $FE07; reserved
• $FE08; FLASH control register, FLCR
• $FE09; break address register high, BRKH
• $FE0A; break address register low, BRKL
• $FE0B; break status and control register, BRKSCR
• $FE0C; LVI status register, LVISR
• $FF7E; FLASH block protect register, FLBPR
• $FFFF; COP control register, COPCTL
Data registers are shown in Figure 2-2. Table 2-1 is a list of vector locations.
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
29
Memory
$0000
↓
$003F
$0040
↓
$023F
$0240
↓
$7FFF
$8000
↓
$FDFF
RAM
512 Bytes
Unimplemented
32,192 Bytes
FLASH Memory
32,256 Bytes
$FE00
SIM Break Status Register (SBSR)
$FE01
SIM Reset Status Register (SRSR)
$FE02
Reserved (SUBAR)
$FE03
SIM Break Flag Control Register (SBFCR)
$FE04
Interrupt Status Register 1 (INT1)
$FE05
Interrupt Status Register 2 (INT2)
$FE06
Interrupt Status Register 3 (INT3)
$FE07
Reserved
$FE08
FLASH Control Register (FLCR)
$FE09
Break Address Register High (BRKH)
$FE0A
Break Address Register Low (BRKL)
$FE0B
Break Status and Control Register (BRKSCR)
$FE0C
LVI Status Register (LVISR)
$FE0D
↓
$FE0F
$FE10
↓
$FE1F
$FE20
↓
$FF52
$FF53
↓
$FF7D
$FF7E
$FF7F
↓
$FFDB
Note: $FFF6–$FFFD
reserved for
8 security bytes
I/O Registers
64 Bytes
$FFDC
↓
$FFFF
Unimplemented
3 Bytes
Unimplemented
16 Bytes
Reserved for Compatibility with Monitor Code
for A-Family Parts
Monitor ROM
307 Bytes
Unimplemented
43 Bytes
FLASH Block Protect Register (FLBPR)
Unimplemented
93 Bytes
FLASH Vectors
36 Bytes
Figure 2-1. Memory Map
MC68HC908GP32 Data Sheet, Rev. 10
30
Freescale Semiconductor
Input/Output (I/O) Section
Addr.
$0000
$0001
$0002
$0003
$0004
$0005
$0006
$0007
$0008
$0009
$000A
$000B
Register Name
Port A Data Register
(PTA)
Port B Data Register
(PTB)
Port C Data Register
(PTC)
Port D Data Register
(PTD)
Data Direction Register A
(DDRA)
Data Direction Register B
(DDRB)
Data Direction Register C
(DDRC)
Data Direction Register D
(DDRD)
Port E Data Register
(PTE)
Unimplemented
Unimplemented
Unimplemented
$000C
Data Direction Register E
(DDRE)
$000D
Port A Input Pullup Enable
Register
(PTAPUE)
Bit 7
Read:
PTA7
Write:
Reset:
Read:
PTB7
Write:
Reset:
Read:
0
Write:
Reset:
Read:
PTD7
Write:
Reset:
Read:
DDRA7
Write:
Reset:
0
Read:
DDRB7
Write:
Reset:
0
Read:
0
Write:
Reset:
0
Read:
DDRD7
Write:
Reset:
0
Read:
0
Write:
Reset:
Read:
Write:
Reset:
0
Read:
Write:
Reset:
0
Read:
Write:
Reset:
0
Read:
0
Write:
Reset:
0
Read:
PTAPUE7
Write:
Reset:
0
6
5
4
3
2
1
Bit 0
PTA6
PTA5
PTA4
PTA3
PTA2
PTA1
PTA0
PTB2
PTB1
PTB0
PTC2
PTC1
PTC0
PTD2
PTD1
PTD0
Unaffected by reset
PTB6
PTB5
PTB4
PTB3
Unaffected by reset
PTC6
PTC5
PTC4
PTC3
Unaffected by reset
PTD6
PTD5
PTD4
PTD3
Unaffected by reset
DDRA6
DDRA5
DDRA4
DDRA3
DDRA2
DDRA1
DDRA0
0
0
0
0
0
0
0
DDRB6
DDRB5
DDRB4
DDRB3
DDRB2
DDRB1
DDRB0
0
0
0
0
0
0
0
DDRC6
DDRC5
DDRC4
DDRC3
DDRC2
DDRC1
DDRC0
0
0
0
0
0
0
0
DDRD6
DDRD5
DDRD4
DDRD3
DDRD2
DDRD1
DDRD0
0
0
0
0
0
0
0
0
0
0
0
0
PTE1
PTE0
Unaffected by reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DDRE1
DDRE0
0
0
0
0
0
0
0
PTAPUE6
PTAPUE5
PTAPUE4
PTAPUE3
PTAPUE2
PTAPUE1
PTAPUE0
0
0
= Unimplemented
0
R = Reserved
0
0
0
U = Unaffected
0
Figure 2-2. Control, Status, and Data Registers (Sheet 1 of 6)
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
31
Memory
Addr.
$000E
$000F
$0010
$0011
$0012
$0013
$0014
$0015
$0016
$0017
$0018
$0019
$001A
$001B
$001C
Register Name
Bit 7
0
Port C Input Pullup Enable Read:
Register Write:
(PTCPUE) Reset:
0
Read:
Port D Input Pullup Enable
PTDPUE7
Register Write:
(PTDPUE) Reset:
0
Read:
SPRIE
SPI Control Register
Write:
(SPCR)
Reset:
0
SPRF
SPI Status and Control Read:
Register Write:
(SPSCR) Reset:
0
Read:
R7
SPI Data Register
Write:
T7
(SPDR)
Reset:
Read:
SCI Control Register 1
Write:
(SCC1)
Reset:
Read:
SCI Control Register 2
Write:
(SCC2)
Reset:
Read:
SCI Control Register 3
Write:
(SCC3)
Reset:
Read:
SCI Status Register 1
Write:
(SCS1)
Reset:
Read:
SCI Status Register 2
Write:
(SCS2)
Reset:
Read:
SCI Data Register
Write:
(SCDR)
Reset:
Read:
SCI Baud Rate Register
Write:
(SCBR)
Reset:
Keyboard Status Read:
and Control Register Write:
(INTKBSCR) Reset:
Keyboard Interrupt Enable Read:
Register Write:
(INTKBIER) Reset:
Time Base Module Control Read:
Register Write:
(TBCR) Reset:
6
5
4
3
2
1
Bit 0
PTCPUE6
PTCPUE5
PTCPUE4
PTCPUE3
PTCPUE2
PTCPUE1
PTCPUE0
0
0
0
0
0
0
0
PTDPUE6
PTDPUE5
PTDPUE4
PTDPUE3
PTDPUE2
PTDPUE1
PTDPUE0
0
0
0
0
0
0
0
R
SPMSTR
CPOL
CPHA
SPWOM
SPE
SPTIE
0
1
OVRF
0
MODF
1
SPTE
0
0
0
MODFEN
SPR1
SPR0
0
R5
T5
0
R4
T4
1
R3
T3
0
R2
T2
0
R1
T1
0
R0
T0
ERRIE
0
R6
T6
Unaffected by reset
LOOPS
ENSCI
TXINV
M
WAKE
ILTY
PEN
PTY
0
0
0
0
0
0
0
0
SCTIE
TCIE
SCRIE
ILIE
TE
RE
RWU
SBK
0
R8
0
0
0
0
0
0
0
T8
R
R
ORIE
NEIE
FEIE
PEIE
U
SCTE
U
TC
0
SCRF
0
IDLE
0
OR
0
NF
0
FE
0
PE
1
1
0
0
0
0
0
BKF
0
RPF
0
R7
T7
0
R6
T6
0
R5
T5
0
R2
T2
0
R1
T1
0
R0
T0
0
0
R4
R3
T4
T3
Unaffected by reset
SCP1
SCP0
R
SCR2
SCR1
SCR0
0
0
IMASKK
MODEK
0
0
0
0
0
0
0
0
0
0
0
KEYF
0
0
0
0
0
0
0
ACKK
0
KBIE7
KBIE6
KBIE5
KBIE4
KBIE3
KBIE2
KBIE1
KBIE0
0
TBIF
0
0
0
0
0
0
TBR2
TBR1
TBR0
0
0
TACK
0
TBIE
TBON
R
0
0
0
= Unimplemented
0
R = Reserved
0
0
U = Unaffected
0
Figure 2-2. Control, Status, and Data Registers (Sheet 2 of 6)
MC68HC908GP32 Data Sheet, Rev. 10
32
Freescale Semiconductor
Input/Output (I/O) Section
Addr.
Register Name
Bit 7
0
6
0
5
0
4
0
3
IRQF
2
0
ACK
0
0
IRQ Status and Control Read:
Register Write:
(INTSCR) Reset:
0
0
0
0
0
Read:
0
0
0
0
0
Configuration Register 2
$001E
(CONFIG2)† Write:
Reset:
0
0
0
0
0
0
Read:
COPRS
LVISTOP LVIRSTD LVIPWRD LVI5OR3†
SSREC
Configuration Register 1
$001F
† Write:
(CONFIG1)
Reset:
0
0
0
0
0
0
TOF
0
0
Timer 1 Status and Control Read:
TOIE
TSTOP
PS2
0
TRST
$0020
Register Write:
(T1SC) Reset:
0
0
1
0
0
0
Bit 15
14
13
12
11
10
Timer 1 Counter Read:
$0021
Register High Write:
(T1CNTH) Reset:
0
0
0
0
0
0
Read:
Bit
7
6
5
4
3
2
Timer 1 Counter
$0022
Register Low Write:
(T1CNTL) Reset:
0
0
0
0
0
0
Read:
Timer 1 Counter Modulo
Bit 15
14
13
12
11
10
$0023
Register High Write:
(T1MODH) Reset:
1
1
1
1
1
1
Timer 1 Counter Modulo Read:
Bit 7
6
5
4
3
2
$0024
Register Low Write:
(T1MODL) Reset:
1
1
1
1
1
1
Read:
CH0F
CH0IE
MS0B
MS0A
ELS0B
ELS0A
Timer 1 Channel 0 Status and
Write:
0
$0025
Control Register (T1SC0)
Reset:
0
0
0
0
0
0
Read:
Timer 1 Channel 0
Bit 15
14
13
12
11
10
$0026
Register High Write:
(T1CH0H) Reset:
Indeterminate after reset
Read:
Timer 1 Channel 0
Bit 7
6
5
4
3
2
$0027
Register Low Write:
(T1CH0L) Reset:
Indeterminate after reset
† One-time writable register after each reset, except LVI5OR3 bit. LVI5OR3 bit is only reset via POR (power-on reset).
$001D
Read:
Timer 1 Channel 1 Status and
Write:
Control Register (T1SC1)
Reset:
Timer 1 Channel 1 Read:
$0029
Register High Write:
(T1CH1H) Reset:
Timer 1 Channel 1 Read:
$002A
Register Low Write:
(T1CH1L) Reset:
$0028
CH1F
0
0
Bit 15
0
CH1IE
1
Bit 0
IMASK
MODE
0
0
OSCSCIBDSRC
STOPENB
0
0
STOP
COPD
0
0
PS1
PS0
0
9
0
Bit 8
0
1
0
Bit 0
0
0
9
Bit 8
1
1
1
Bit 0
1
1
TOV0
CH0MAX
0
0
9
Bit 8
1
Bit 0
MS1A
ELS1B
ELS1A
TOV1
CH1MAX
0
0
0
0
0
0
0
14
13
12
11
10
9
Bit 8
2
1
Bit 0
Indeterminate after reset
Bit 7
6
= Unimplemented
5
4
3
Indeterminate after reset
R = Reserved
U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 3 of 6)
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
33
Memory
Addr.
$002B
$002C
$002D
$002E
$002F
$0030
$0031
$0032
$0033
$0034
$0035
$0036
$0037
$0038
$0039
Register Name
Timer 2 Status and Control Read:
Register Write:
(T2SC) Reset:
Timer 2 Counter Read:
Register High Write:
(T2CNTH) Reset:
Timer 2 Counter Read:
Register Low Write:
(T2CNTL) Reset:
Timer 2 Counter Modulo Read:
Register High Write:
(T2MODH) Reset:
Timer 2 Counter Modulo Read:
Register Low Write:
(T2MODL) Reset:
Read:
Timer 2 Channel 0 Status and
Write:
Control Register (T2SC0)
Reset:
Timer 2 Channel 0 Read:
Register High Write:
(T2CH0H) Reset:
Timer 2 Channel 0 Read:
Register Low Write:
(T2CH0L) Reset:
Read:
Timer 2 Channel 1 Status and
Write:
Control Register (T2SC1)
Reset:
Timer 2 Channel 1 Read:
Register High Write:
(T2CH1H) Reset:
Timer 2 Channel 1 Read:
Register Low Write:
(T2CH1L) Reset:
Read:
PLL Control Register
Write:
(PCTL)
Reset:
PLL Bandwidth Control Read:
Register Write:
(PBWC) Reset:
PLL Multiplier Select High Read:
Register Write:
(PMSH) Reset:
PLL Multiplier Select Low Read:
Register Write:
(PMSL) Reset:
Bit 7
TOF
0
0
Bit 15
6
5
1
13
4
0
TRST
0
12
TOIE
TSTOP
0
14
0
Bit 7
0
6
0
5
0
0
Bit 15
3
0
2
1
Bit 0
PS2
PS1
PS0
0
11
0
10
0
9
0
Bit 8
0
4
0
3
0
2
0
1
0
Bit 0
0
0
0
0
0
0
14
13
12
11
10
9
Bit 8
1
1
1
1
1
1
1
1
Bit 7
6
5
4
3
2
1
Bit 0
1
CH0F
0
0
1
1
1
1
1
1
1
CH0IE
MS0B
MS0A
ELS0B
ELS0A
TOV0
CH0MAX
0
0
0
0
0
0
0
Bit 15
14
13
12
11
10
9
Bit 8
2
1
Bit 0
Indeterminate after reset
Bit 7
6
5
4
3
Indeterminate after reset
CH1F
0
0
Bit 15
CH1IE
0
MS1A
ELS1B
ELS1A
TOV1
CH1MAX
0
0
0
0
0
0
0
14
13
12
11
10
9
Bit 8
2
1
Bit 0
Indeterminate after reset
Bit 7
6
5
4
3
Indeterminate after reset
PLLIE
0
AUTO
PLLF
0
LOCK
PLLON
BCS
PRE1
PRE0
VPR1
VPR0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
MUL11
MUL10
MUL9
MUL8
ACQ
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
MUL7
MUL6
MUL5
MUL4
MUL3
MUL2
MUL1
MUL0
0
1
0
= Unimplemented
0
R = Reserved
0
0
0
U = Unaffected
0
Figure 2-2. Control, Status, and Data Registers (Sheet 4 of 6)
MC68HC908GP32 Data Sheet, Rev. 10
34
Freescale Semiconductor
Input/Output (I/O) Section
Addr.
$003A
$003B
$003C
$003D
$003E
$003F
$FE00
$FE01
$FE02
$FE03
$FE04
$FE05
$FE06
$FE07
Register Name
PLL VCO Range Select Read:
Register Write:
(PMRS) Reset:
PLL Reference Divider Read:
Select Register Write:
(PMDS) Reset:
Analog-to-Digital Status and Read:
Control Register Write:
(ADSCR) Reset:
Analog-to-Digital Data Read:
Register Write:
(ADR) Reset:
Analog-to-Digital Clock Read:
Register Write:
(ADCLK) Reset:
Read:
Unimplemented Write:
Reset:
Read:
SIM Break Status Register
Write:
(SBSR)
Reset:
Note: Writing a logic 0 clears SBSW.
Read:
SIM Reset Status Register
Write:
(SRSR)
POR:
SIM Upper Byte Address Read:
Register Write:
(SUBAR) Reset:
SIM Break Flag Control Read:
Register Write:
(SBFCR) Reset:
Read:
Interrupt Status Register 1
Write:
(INT1)
Reset:
Read:
Interrupt Status Register 2
Write:
(INT2)
Reset:
Read:
Interrupt Status Register 3
Write:
(INT3)
Reset:
Read:
Reserved Write:
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
VRS7
VRS6
VRS5
VRS4
VRS3
VRS2
VRS1
VRS0
0
0
1
0
0
0
0
0
0
0
0
0
RDS3
RDS2
RDS1
RDS0
0
COCO
R
0
AD7
0
0
0
0
0
0
1
AIEN
ADCO
ADCH4
ADCH3
ADCH2
ADCH1
ADCH0
0
AD6
0
AD5
1
AD4
1
AD3
1
AD2
1
AD1
1
AD0
0
0
0
0
ADIV2
ADIV1
ADIV0
ADICLK
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
R
R
R
R
R
POR
PIN
COP
ILOP
ILAD
MODRST
LVI
0
1
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
BCFE
R
R
R
R
R
R
R
0
IF6
R
0
IF14
R
0
0
R
0
IF5
R
0
IF13
R
0
0
R
0
IF4
R
0
IF12
R
0
0
R
0
IF3
R
0
IF11
R
0
0
R
0
IF2
R
0
IF10
R
0
0
R
0
IF1
R
0
IF9
R
0
0
R
0
0
R
0
IF8
R
0
IF16
R
0
0
R
0
IF7
R
0
IF15
R
0
R
R
R
R
R
R
R
R
0
0
0
U = Unaffected
0
0
0
0
= Unimplemented
0
R = Reserved
SBSW
Note
0
R
Figure 2-2. Control, Status, and Data Registers (Sheet 5 of 6)
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
35
Memory
Addr.
Register Name
Read:
FLASH Control Register
Write:
(FLCR)
Reset:
Break Address Read:
$FE09
Register High Write:
(BRKH) Reset:
Break Address Read:
$FE0A
Register Low Write:
(BRKL) Reset:
Break Status and Control Read:
$FE0B
Register Write:
(BRKSCR) Reset:
Read:
$FE0C LVI Status Register (LVISR) Write:
Reset:
FLASH Block Protect Read:
$FF7E
Register Write:
(FLBPR)† Reset:
Read:
COP Control Register
Write:
$FFFF
(COPCTL)
Reset:
† Non-volatile FLASH register
Bit 7
0
6
0
5
0
4
0
3
2
1
Bit 0
HVEN
MASS
ERASE
PGM
0
0
0
0
0
0
0
0
Bit 15
14
13
12
11
10
9
Bit 8
0
0
0
0
0
0
0
0
Bit 7
6
5
4
3
2
1
Bit 0
0
0
BRKE
BRKA
0
0
0
0
0
0
0
0
0
0
0
0
0
LVIOUT
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BPR7
BPR6
BPR5
BPR4
BPR3
BPR2
BPR1
BPR0
U
U
U
U
U
$FE08
= Unimplemented
U
U
U
Low byte of reset vector
Writing clears COP counter (any value)
Unaffected by reset
R = Reserved
U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 6 of 6)
MC68HC908GP32 Data Sheet, Rev. 10
36
Freescale Semiconductor
Input/Output (I/O) Section
.
Table 2-1. Vector Addresses
Vector Priority
Lowest
Vector
IF16
IF15
IF14
IF13
IF12
IF11
IF10
IF9
IF8
IF7
IF6
IF5
IF4
IF3
IF2
IF1
—
Highest
—
Address
Vector
$FFDC
Timebase Vector (High)
$FFDD
Timebase Vector (Low)
$FFDE
ADC Conversion Complete Vector (High)
$FFDF
ADC Conversion Complete Vector (Low)
$FFE0
Keyboard Vector (High)
$FFE1
Keyboard Vector (Low)
$FFE2
SCI Transmit Vector (High)
$FFE3
SCI Transmit Vector (Low)
$FFE4
SCI Receive Vector (High)
$FFE5
SCI Receive Vector (Low)
$FFE6
SCI Error Vector (High)
$FFE7
SCI Error Vector (Low)
$FFE8
SPI Transmit Vector (High)
$FFE9
SPI Transmit Vector (Low)
$FFEA
SPI Receive Vector (High)
$FFEB
SPI Receive Vector (Low)
$FFEC
TIM2 Overflow Vector (High)
$FFED
TIM2 Overflow Vector (Low)
$FFEE
TIM2 Channel 1 Vector (High)
$FFEF
TIM2 Channel 1 Vector (Low)
$FFF0
TIM2 Channel 0 Vector (High)
$FFF1
TIM2 Channel 0 Vector (Low)
$FFF2
TIM1 Overflow Vector (High)
$FFF3
TIM1 Overflow Vector (Low)
$FFF4
TIM1 Channel 1 Vector (High)
$FFF5
TIM1 Channel 1 Vector (Low)
$FFF6
TIM1 Channel 0 Vector (High)
$FFF7
TIM1 Channel 0 Vector (Low)
$FFF8
PLL Vector (High)
$FFF9
PLL Vector (Low)
$FFFA
IRQ Vector (High)
$FFFB
IRQ Vector (Low)
$FFFC
SWI Vector (High)
$FFFD
SWI Vector (Low)
$FFFE
Reset Vector (High)
$FFFF
Reset Vector (Low)
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
37
Memory
2.5 Random-Access Memory (RAM)
This section describes the 512 bytes of RAM (random-access memory).
Addresses $0040 through $023F are RAM locations. The location of the stack RAM is programmable.
The 16-bit stack pointer allows the stack to be anywhere in the 64-Kbyte memory space.
NOTE
For correct operation, the stack pointer must point only to RAM locations.
Within page zero are 192 bytes of RAM. Because the location of the stack RAM is programmable, all page
zero RAM locations can be used for I/O control and user data or code. When the stack pointer is moved
from its reset location at $00FF out of page zero, direct addressing mode instructions can efficiently
access all page zero RAM locations. Page zero RAM, therefore, provides ideal locations for frequently
accessed global variables.
Before processing an interrupt, the CPU uses five bytes of the stack to save the contents of the CPU
registers.
NOTE
For M6805 compatibility, the H register is not stacked.
During a subroutine call, the CPU uses two bytes of the stack to store the return address. The stack
pointer decrements during pushes and increments during pulls.
NOTE
Be careful when using nested subroutines. The CPU may overwrite data in
the RAM during a subroutine or during the interrupt stacking operation.
2.6 FLASH Memory
This subsection describes the operation of the embedded FLASH memory. This memory can be read,
programmed, and erased from a single external supply. The program, erase, and read operations are
enabled through the use of an internal charge pump.
2.6.1 Functional Description
The FLASH memory is an array of 32,256 bytes with an additional 36 bytes of user vectors and one byte
of block protection. An erased bit reads as 1 and a programmed bit reads as a 0. Memory in the FLASH
array is organized into two rows per page basis. The page size is 128 bytes per page. Hence the minimum
erase page size is 128 bytes and the minimum program row size is 64 bytes. Program and erase
operation operations are facilitated through control bits in FLASH Control Register (FLCR). Details for
these operations appear later in this section. The address ranges for the user memory, control registers,
and vectors are:
• $8000–$FDFF; user memory.
• $FF7E; FLASH block protect register.
• $FE08; FLASH control register.
• $FFDC–$FFFF; these locations are reserved for user-defined interrupt and reset vectors.
Programming tools are available from Freescale. Contact your local Freescale representative for more
information.
MC68HC908GP32 Data Sheet, Rev. 10
38
Freescale Semiconductor
FLASH Memory
NOTE
A security feature prevents viewing of the FLASH contents.(1)
2.6.2 FLASH Control Register
The FLASH control register (FLCR) controls FLASH program and erase operations.
Address:
Read:
$FE08
Bit 7
6
5
4
0
0
0
0
0
0
0
0
Write:
Reset:
3
2
1
Bit 0
HVEN
MASS
ERASE
PGM
0
0
0
0
= Unimplemented
Figure 2-3. FLASH Control Register (FLCR)
HVEN — High-Voltage Enable Bit
This read/write bit enables the charge pump to drive high voltages for program and erase operations
in the array. HVEN can only be set if either PGM = 1 or ERASE = 1 and the proper sequence for
program or erase is followed.
1 = High voltage enabled to array and charge pump on
0 = High voltage disabled to array and charge pump off
MASS — Mass Erase Control Bit
Setting this read/write bit configures the 32Kbyte FLASH array for mass erase operation.
1 = MASS erase operation selected
0 = PAGE erase operation selected
ERASE — Erase Control Bit
This read/write bit configures the memory for erase operation. ERASE is interlocked with the PGM bit
such that both bits cannot be equal to 1 or set to 1 at the same time.
1 = Erase operation selected
0 = Erase operation unselected
PGM — Program Control Bit
This read/write bit configures the memory for program operation. PGM is interlocked with the ERASE
bit such that both bits cannot be equal to 1 or set to 1 at the same time.
1 = Program operation selected
0 = Program operation unselected
2.6.3 FLASH Page Erase Operation
Use this step-by-step procedure to erase a page (128 bytes) of FLASH memory.
1. Set the ERASE bit, and clear the MASS bit in the FLASH control register.
2. Read the FLASH block protect register.
3. Write any data to any FLASH location within the page address range of the block to be erased.
4. Wait for a time, tnvs (min. 10 µs)
5. Set the HVEN bit.
1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for
unauthorized users.
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
39
Memory
6.
7.
8.
9.
10.
Wait for a time, tErase (min. 1 ms or 4 ms)
Clear the ERASE bit.
Wait for a time, tnvh (min. 5 µs)
Clear the HVEN bit.
After a time, trcv (typ. 1 µs), the memory can be accessed again in read mode.
NOTE
Programming and erasing of FLASH locations cannot be performed by
code being executed from FLASH memory. While these operations must
be performed in the order shown, other unrelated operations may occur
between the steps.
In applications that need more than 1000 program/erase cycles, use the 4-ms page erase specification
to get improved long-term reliability. Any application can use this 4-ms page erase specification.
However, in applications where a FLASH location will be erased and reprogrammed less than 1000 times,
and speed is important, use the 1-ms page erase specification to get a shorter cycle time.
2.6.4 FLASH Mass Erase Operation
Use this step-by-step procedure to erase entire FLASH memory.
1. Set both the ERASE bit, and the MASS bit in the FLASH control register.
2. Read the FLASH block protect register.
3. Write any data to any FLASH address(1) within the FLASH memory address range.
4. Wait for a time, tnvs (min. 10 µs)
5. Set the HVEN bit.
6. Wait for a time, tMErase (min. 4 ms)
7. Clear the ERASE and MASS bits.
NOTE
Mass erase is disabled whenever any block is protected (FLBPR does not
equal $FF).
8. Wait for a time, tnvhl (min. 100 µs)
9. Clear the HVEN bit.
10. After a time, trcv (min. 1 µs), the memory can be accessed again in read mode.
NOTE
Programming and erasing of FLASH locations cannot be performed by
code being executed from the FLASH memory. While these operations
must be performed in the order shown, other unrelated operations may
occur between the steps.
2.6.5 FLASH Program Operation
Programming of the FLASH memory is done on a row basis. A row consists of 64 consecutive bytes
starting from addresses $XX00, $XX40, $0080 and $XXC0.
1. When in Monitor mode, with security sequence failed (see 18.3.2 Security), write to the FLASH block protect register instead
of any FLASH address.
MC68HC908GP32 Data Sheet, Rev. 10
40
Freescale Semiconductor
FLASH Memory
During the programming cycle, make sure that all addresses being written to fit within one of the ranges
specified above. Attempts to program addresses in different row ranges in one programming cycle will
fail. Use this step-by-step procedure to program a row of FLASH memory (Figure 2-4 is a flowchart
representation).
NOTE
Only bytes which are currently $FF may be programmed.
1. Set the PGM bit. This configures the memory for program operation and enables the latching of
address and data for programming.
2. Read from the FLASH block protect register.
3. Write any data to any FLASH address within the row address range desired.
4. Wait for a time, tnvs (min. 10 µs).
5. Set the HVEN bit.
6. Wait for a time, tpgs (min. 5 µs).
7. Write data to the FLASH address to be programmed. (See note.)
8. Wait for a time, tPROG (min. 30 µs).
9. Repeat step 7 and 8 until all the bytes within the row are programmed.
10. Clear the PGM bit. (See note.)
11. Wait for a time, tnvh (min. 5 µs).
12. Clear the HVEN bit.
13. After time, tRCV (typical 1 µs), the memory can be accessed in read mode again.
This program sequence is repeated throughout the memory until all data is programmed.
NOTE
Programming and erasing of FLASH locations can not be performed by
code being executed from the same FLASH array.
NOTE
While these operations must be performed in the order shown, other
unrelated operations may occur between the steps. Care must be taken
within the FLASH array memory space such as the COP control register
(COPCTL) at $FFFF.
NOTE
It is highly recommended that interrupts be disabled during program/ erase
operations.
NOTE
Do not exceed tPROG maximum or tHV maximum. tHV is defined as the
cumulative high voltage programming time to the same row before next
erase. tHV must satisfy this condition:
tNVS + tNVH + tPGS + (tPROG x 64) ≤ tHV maximum
Refer to 19.17 Memory Characteristics.
NOTE
The time between programming the FLASH address change (step 7 to
step 7), or the time between the last FLASH programmed to clearing the
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
41
Memory
PGM bit (step 7 to step 10) must not exceed the maximum programming
time, tPROG maximum.
NOTE
Be cautious when programming the FLASH array to ensure that
non-FLASH locations are not used as the address that is written to when
selecting either the desired row address range in step 3 of the algorithm or
the byte to be programmed in step 7 of the algorithm. This applies
particularly to $FFD4–$FFDF.
2.6.6 FLASH Block Protection
Due to the ability of the on-board charge pump to erase and program the FLASH memory in the target
application, provision is made for protecting a block of memory from unintentional erase or program
operations due to system malfunction. This protection is done by using of a FLASH Block Protect Register
(FLBPR). The FLBPR determines the range of the FLASH memory which is to be protected. The range
of the protected area starts from a location defined by FLBPR and ends at the bottom of the FLASH
memory ($FFFF). When the memory is protected, the HVEN bit cannot be set in either ERASE or
PROGRAM operations.
NOTE
In performing a program or erase operation, the FLASH block protect
register must be read after setting the PGM or ERASE bit and before
asserting the HVEN bit
MC68HC908GP32 Data Sheet, Rev. 10
42
Freescale Semiconductor
FLASH Memory
1
Algorithm for programming
a row (64 bytes) of FLASH memory
2
3
4
5
6
7
8
Set PGM bit
Read the FLASH block protect register
Write any data to any FLASH address
within the row address range desired
Wait for a time, tnvs
Set HVEN bit
Wait for a time, tpgs
Write data to the FLASH address
to be programmed
Wait for a time, tPROG
Completed
programming
this row?
Y
N
NOTE:
The time between each FLASH address change (step 7 to step 7), or
the time between the last FLASH address programmed
to clearing PGM bit (step 7 to step 10)
must not exceed the maximum programming
time, tPROG max.
10
Clear PGM bit
11
Wait for a time, tnvh
12
Clear HVEN bit
13
Wait for a time, trcv
This row program algorithm assumes the row/s
to be programmed are initially erased.
End of programming
Figure 2-4. FLASH Programming Flowchart
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
43
Memory
When the FLBPR is programmed with all 0’s, the entire memory is protected from being programmed and
erased. When all the bits are erased (all 1’s), the entire memory is accessible for program and erase.
When bits within the FLBPR are programmed, they lock a block of memory, address ranges as shown in
2.6.6.1 FLASH Block Protect Register. Once the FLBPR is programmed with a value other than $FF, any
erase or program of the FLBPR or the protected block of FLASH memory is prohibited. Mass erase is
disabled whenever any block is protected (FLBPR does not equal $FF). The presence of a VTST on the
IRQ pin will bypass the block protection so that all of the memory included in the block protect register is
open for program and erase operations.
NOTE
The FLASH block protect register is not protected with special hardware or
software. Therefore, if this page is not protected by FLBPR the register is
erased by either a page or mass erase operation.
2.6.6.1 FLASH Block Protect Register
The FLASH block protect register (FLBPR) is implemented as a byte within the FLASH memory, and
therefore can only be written during a programming sequence of the FLASH memory. The value in this
register determines the starting location of the protected range within the FLASH memory.
Address:
Read:
Write:
Reset:
$FF7E
Bit 7
6
5
4
3
2
1
Bit 0
BPR7
BPR6
BPR5
BPR4
BPR3
BPR2
BPR1
BPR0
U
U
U
U
U
U
U
U
U = Unaffected by reset. Initial value from factory is 1.
Write to this register is by a programming sequence to the FLASH memory.
Figure 2-5. FLASH Block Protect Register (FLBPR)
BPR[7:0] — FLASH Block Protect Bits
These eight bits represent bits [14:7] of a 16-bit memory address.
Bit-15 is 1 and bits [6:0] are 0s.
The resultant 16-bit address is used for specifying the start address of the FLASH memory for block
protection. The FLASH is protected from this start address to the end of FLASH memory, at $FFFF.
With this mechanism, the protect start address can be XX00 and XX80 (128 bytes page boundaries)
within the FLASH memory.
16-bit memory address
Start address of FLASH block protect
1
FLBPR value
0
0
0
0
0
0
0
Figure 2-6. FLASH Block Protect Start Address
MC68HC908GP32 Data Sheet, Rev. 10
44
Freescale Semiconductor
FLASH Memory
Examples of protect start address:
BPR[7:0]
Start of Address of Protect Range
$00
The entire FLASH memory is protected.
$01 (0000 0001)
$8080 (1000 0000 1000 0000)
$02 (0000 0010)
$8100 (1000 0001 0000 0000)
and so on...
$FE (1111 1110)
$FF00 (1111 1111 0000 0000)
$FF
The entire FLASH memory is not protected.
Note: The end address of the protected range is always $FFFF.
2.6.7 Wait Mode
Putting the MCU into wait mode while the FLASH is in read mode does not affect the operation of the
FLASH memory directly, but there will not be any memory activity since the CPU is inactive.
The WAIT instruction should not be executed while performing a program or erase operation on the
FLASH, otherwise the operation will discontinue, and the FLASH will be on Standby Mode.
2.6.8 Stop Mode
Putting the MCU into stop mode while the FLASH is in read mode does not affect the operation of the
FLASH memory directly, but there will not be any memory activity since the CPU is inactive.
The STOP instruction should not be executed while performing a program or erase operation on the
FLASH, otherwise the operation will discontinue, and the FLASH will be on Standby Mode
NOTE
Standby Mode is the power saving mode of the FLASH module in which all
internal control signals to the FLASH are inactive and the current
consumption of the FLASH is at a minimum.
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
45
Memory
MC68HC908GP32 Data Sheet, Rev. 10
46
Freescale Semiconductor
Chapter 3
Low-Power Modes
3.1 Introduction
The MCU may enter two low-power modes: wait mode and stop mode. They are common to all HC08
MCUs and are entered through instruction execution. This section describes how each module acts in the
low-power modes.
3.1.1 Wait Mode
The WAIT instruction puts the MCU in a low-power standby mode in which the CPU clock is disabled but
the bus clock continues to run. Power consumption can be further reduced by disabling the LVI module
and/or the timebase module through bits in the CONFIG register. (See Chapter 6 Configuration Register
(CONFIG).)
3.1.2 Stop Mode
Stop mode is entered when a STOP instruction is executed. The CPU clock is disabled and the bus clock
is disabled if the OSCSTOPENB bit in the CONFIG register is at a logic 0. (See Chapter 6 Configuration
Register (CONFIG).)
3.2 Analog-to-Digital Converter (ADC)
3.2.1 Wait Mode
The ADC continues normal operation during wait mode. Any enabled CPU interrupt request from the ADC
can bring the MCU out of wait mode. If the ADC is not required to bring the MCU out of wait mode, power
down the ADC by setting ADCH4–ADCH0 bits in the ADC status and control register before executing
the WAIT instruction.
3.2.2 Stop Mode
The ADC module is inactive after the execution of a STOP instruction. Any pending conversion is aborted.
ADC conversions resume when the MCU exits stop mode after an external interrupt. Allow one
conversion cycle to stabilize the analog circuitry.
3.3 Break Module (BRK)
3.3.1 Wait Mode
If enabled, the break module is active in wait mode. In the break routine, the user can subtract one from
the return address on the stack if the SBSW bit in the break status register is set.
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
47
Low-Power Modes
3.3.2 Stop Mode
The break module is inactive in stop mode. The STOP instruction does not affect break module register
states.
3.4 Central Processor Unit (CPU)
3.4.1 Wait Mode
The WAIT instruction:
• Clears the interrupt mask (I bit) in the condition code register, enabling interrupts. After exit from
wait mode by interrupt, the I bit remains clear. After exit by reset, the I bit is set.
• Disables the CPU clock
3.4.2 Stop Mode
The STOP instruction:
• Clears the interrupt mask (I bit) in the condition code register, enabling external interrupts. After
exit from stop mode by external interrupt, the I bit remains clear. After exit by reset, the I bit is set.
• Disables the CPU clock
After exiting stop mode, the CPU clock begins running after the oscillator stabilization delay.
3.5 Clock Generator Module (CGM)
3.5.1 Wait Mode
The CGM remains active in wait mode. Before entering wait mode, software can disengage and turn off
the PLL by clearing the BCS and PLLON bits in the PLL control register (PCTL). Less power-sensitive
applications can disengage the PLL without turning it off. Applications that require the PLL to wake the
MCU from wait mode also can deselect the PLL output without turning off the PLL.
3.5.2 Stop Mode
If the OSCSTOPEN bit in the CONFIG register is cleared (default), then the STOP instruction disables
the CGM (oscillator and phase-locked loop) and holds low all CGM outputs (CGMXCLK, CGMOUT, and
CGMINT).
If the OSCSTOPEN bit in the CONFIG register is set, then the phase locked loop is shut off but the
oscillator will continue to operate in stop mode.
3.6 Computer Operating Properly Module (COP)
3.6.1 Wait Mode
The COP remains active in wait mode. To prevent a COP reset during wait mode, periodically clear the
COP counter in a CPU interrupt routine.
MC68HC908GP32 Data Sheet, Rev. 10
48
Freescale Semiconductor
External Interrupt Module (IRQ)
3.6.2 Stop Mode
Stop mode turns off the CGMXCLK input to the COP and clears the COP prescaler. Service the COP
immediately before entering or after exiting stop mode to ensure a full COP timeout period after entering
or exiting stop mode.
The STOP bit in the configuration register (CONFIG) enables the STOP instruction. To prevent
inadvertently turning off the COP with a STOP instruction, disable the STOP instruction by clearing the
STOP bit.
3.7 External Interrupt Module (IRQ)
3.7.1 Wait Mode
The IRQ module remains active in wait mode. Clearing the IMASK bit in the IRQ status and control
register enables IRQ CPU interrupt requests to bring the MCU out of wait mode.
3.7.2 Stop Mode
The IRQ module remains active in stop mode. Clearing the IMASK bit in the IRQ status and control
register enables IRQ CPU interrupt requests to bring the MCU out of stop mode.
3.8 Keyboard Interrupt Module (KBI)
3.8.1 Wait Mode
The keyboard module remains active in wait mode. Clearing the IMASKK bit in the keyboard status and
control register enables keyboard interrupt requests to bring the MCU out of wait mode.
3.8.2 Stop Mode
The keyboard module remains active in stop mode. Clearing the IMASKK bit in the keyboard status and
control register enables keyboard interrupt requests to bring the MCU out of stop mode.
3.9 Low-Voltage Inhibit Module (LVI)
3.9.1 Wait Mode
If enabled, the LVI module remains active in wait mode. If enabled to generate resets, the LVI module can
generate a reset and bring the MCU out of wait mode.
3.9.2 Stop Mode
If enabled, the LVI module remains active in stop mode. If enabled to generate resets, the LVI module
can generate a reset and bring the MCU out of stop mode.
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
49
Low-Power Modes
3.10 Serial Communications Interface Module (SCI)
3.10.1 Wait Mode
The SCI module remains active in wait mode. Any enabled CPU interrupt request from the SCI module
can bring the MCU out of wait mode.
If SCI module functions are not required during wait mode, reduce power consumption by disabling the
module before executing the WAIT instruction.
3.10.2 Stop Mode
The SCI module is inactive in stop mode. The STOP instruction does not affect SCI register states. SCI
module operation resumes after the MCU exits stop mode.
Because the internal clock is inactive during stop mode, entering stop mode during an SCI transmission
or reception results in invalid data.
3.11 Serial Peripheral Interface Module (SPI)
3.11.1 Wait Mode
The SPI module remains active in wait mode. Any enabled CPU interrupt request from the SPI module
can bring the MCU out of wait mode.
If SPI module functions are not required during wait mode, reduce power consumption by disabling the
SPI module before executing the WAIT instruction.
3.11.2 Stop Mode
The SPI module is inactive in stop mode. The STOP instruction does not affect SPI register states. SPI
operation resumes after an external interrupt. If stop mode is exited by reset, any transfer in progress is
aborted, and the SPI is reset.
3.12 Timer Interface Module (TIM1 and TIM2)
3.12.1 Wait Mode
The TIM remains active in wait mode. Any enabled CPU interrupt request from the TIM can bring the MCU
out of wait mode.
If TIM functions are not required during wait mode, reduce power consumption by stopping the TIM before
executing the WAIT instruction.
3.12.2 Stop Mode
The TIM is inactive in stop mode. The STOP instruction does not affect register states or the state of the
TIM counter. TIM operation resumes when the MCU exits stop mode after an external interrupt.
MC68HC908GP32 Data Sheet, Rev. 10
50
Freescale Semiconductor
Timebase Module (TBM)
3.13 Timebase Module (TBM)
3.13.1 Wait Mode
The timebase module remains active after execution of the WAIT instruction. In wait mode, the timebase
register is not accessible by the CPU.
If the timebase functions are not required during wait mode, reduce the power consumption by stopping
the timebase before enabling the WAIT instruction.
3.13.2 Stop Mode
The timebase module may remain active after execution of the STOP instruction if the oscillator has been
enabled to operate during stop mode through the OSCSTOPEN bit in the CONFIG register. The timebase
module can be used in this mode to generate a periodic wakeup from stop mode.
If the oscillator has not been enabled to operate in stop mode, the timebase module will not be active
during stop mode. In stop mode, the timebase register is not accessible by the CPU.
If the timebase functions are not required during stop mode, reduce the power consumption by stopping
the timebase before enabling the STOP instruction.
3.14 Exiting Wait Mode
These events restart the CPU clock and load the program counter with the reset vector or with an interrupt
vector:
• External reset — A logic 0 on the RST pin resets the MCU and loads the program counter with the
contents of locations $FFFE and $FFFF.
• External interrupt — A high-to-low transition on an external interrupt pin (IRQ pin) loads the
program counter with the contents of locations: $FFFA and $FFFB; IRQ pin.
• Break interrupt — A break interrupt loads the program counter with the contents of $FFFC and
$FFFD.
• Computer operating properly module (COP) reset — A timeout of the COP counter resets the MCU
and loads the program counter with the contents of $FFFE and $FFFF.
• Low-voltage inhibit module (LVI) reset — A power supply voltage below the Vtripf voltage resets the
MCU and loads the program counter with the contents of locations $FFFE and $FFFF.
• Clock generator module (CGM) interrupt — A CPU interrupt request from the phase-locked loop
(PLL) loads the program counter with the contents of $FFF8 and $FFF9.
• Keyboard module (KBI) interrupt — A CPU interrupt request from the KBI module loads the
program counter with the contents of $FFE0 and $FFE1.
• Timer 1 interface module (TIM1) interrupt — A CPU interrupt request from the TIM1 loads the
program counter with the contents of:
– $FFF2 and $FFF3; TIM1 overflow
– $FFF4 and $FFF5; TIM1 channel 1
– $FFF6 and $FFF7; TIM1 channel 0
• Timer 2 interface module (TIM2) interrupt — A CPU interrupt request from the TIM2 loads the
program counter with the contents of:
– $FFEC and $FFED; TIM2 overflow
– $FFEE and $FFEF; TIM2 channel 1
– $FFF0 and $FFF1; TIM2 channel 0
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
51
Low-Power Modes
•
•
•
•
Serial peripheral interface module (SPI) interrupt — A CPU interrupt request from the SPI loads
the program counter with the contents of:
– $FFE8 and $FFE9; SPI transmitter
– $FFEA and $FFEB; SPI receiver
Serial communications interface module (SCI) interrupt — A CPU interrupt request from the SCI
loads the program counter with the contents of:
– $FFE2 and $FFE3; SCI transmitter
– $FFE4 and $FFE5; SCI receiver
– $FFE6 and $FFE7; SCI receiver error
Analog-to-digital converter module (ADC) interrupt — A CPU interrupt request from the ADC loads
the program counter with the contents of: $FFDE and $FFDF; ADC conversion complete.
Timebase module (TBM) interrupt — A CPU interrupt request from the TBM loads the program
counter with the contents of: $FFDC and $FFDD; TBM interrupt.
3.15 Exiting Stop Mode
These events restart the system clocks and load the program counter with the reset vector or with an
interrupt vector:
• External reset — A logic 0 on the RST pin resets the MCU and loads the program counter with the
contents of locations $FFFE and $FFFF.
• External interrupt — A high-to-low transition on an external interrupt pin loads the program counter
with the contents of locations:
– $FFFA and $FFFB; IRQ pin
– $FFE0 and $FFE1; keyboard interrupt pins
• Low-voltage inhibit (LVI) reset — A power supply voltage below the LVItripf voltage resets the MCU
and loads the program counter with the contents of locations $FFFE and $FFFF.
• Break interrupt — A break interrupt loads the program counter with the contents of locations
$FFFC and $FFFD.
• Timebase module (TBM) interrupt — A TBM interrupt loads the program counter with the contents
of locations $FFDC and $FFDD when the timebase counter has rolled over. This allows the TBM
to generate a periodic wakeup from stop mode.
Upon exit from stop mode, the system clocks begin running after an oscillator stabilization delay. A 12-bit
stop recovery counter inhibits the system clocks for 4096 CGMXCLK cycles after the reset or external
interrupt.
The short stop recovery bit, SSREC, in the configuration register controls the oscillator stabilization delay
during stop recovery. Setting SSREC reduces stop recovery time from 4096 CGMXCLK cycles to 32
CGMXCLK cycles.
NOTE
Use the full stop recovery time (SSREC = 0) in applications that use an
external crystal.
MC68HC908GP32 Data Sheet, Rev. 10
52
Freescale Semiconductor
Chapter 4
Analog-to-Digital Converter (ADC)
4.1 Introduction
This section describes the 8-bit analog-to-digital converter (ADC).
4.2 Features
Features of the ADC module include:
• Eight channels with multiplexed input
• Linear successive approximation with monotonicity
• 8-bit resolution
• Single or continuous conversion
• Conversion complete flag or conversion complete interrupt
• Selectable ADC clock
4.3 Functional Description
The ADC provides eight pins for sampling external sources at pins PTB7/AD7–PTB0/AD0. An analog
multiplexer allows the single ADC converter to select one of eight ADC channels as ADC voltage in
(VADIN). VADIN is converted by the successive approximation register-based analog-to-digital converter.
When the conversion is completed, ADC places the result in the ADC data register and sets a flag or
generates an interrupt. (See Figure 4-1.)
4.3.1 ADC Port I/O Pins
PTB7/AD7–PTB0/AD0 are general-purpose I/O (input/output) pins that share with the ADC channels. The
channel select bits define which ADC channel/port pin will be used as the input signal. The ADC overrides
the port I/O logic by forcing that pin as input to the ADC. The remaining ADC channels/port pins are
controlled by the port I/O logic and can be used as general-purpose I/O. Writes to the port register or DDR
will not have any affect on the port pin that is selected by the ADC. Read of a port pin in use by the ADC
will return a logic 0.
4.3.2 Voltage Conversion
When the input voltage to the ADC equals VREFH, the ADC converts the signal to $FF (full scale). If the
input voltage equals VREFL, the ADC converts it to $00. Input voltages between VREFH and VREFL are a
straight-line linear conversion.
NOTE
Inside the ADC module, the reference voltages VREFH is connected to the
ADC analog power, VDDAD; and VREFL is connected to the ADC analog
ground, VSSAD. Therefore, the ADC input voltage should not exceed these
analog supply voltages.
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
53
Analog-to-Digital Converter (ADC)
INTERNAL
DATA BUS
READ DDRBx
WRITE DDRBx
DISABLE
DDRBx
RESET
WRITE PTBx
PTBx
PTBx
ADC CHANNEL x
READ PTBx
DISABLE
ADC DATA REGISTER
CONVERSION
INTERRUPT COMPLETE
LOGIC
AIEN
ADC
ADC
VOLTAGE IN
(VADIN)
CHANNEL
SELECT
ADCH4–ADCH0
ADC CLOCK
COCO
CGMXCLK
BUS CLOCK
CLOCK
GENERATOR
ADIV2–ADIV0
ADICLK
Figure 4-1. ADC Block Diagram
NOTE
Connect the VDDAD pin to the same voltage potential as the VDD pin, and
connect the VSSAD pin to the same voltage potential as the VSS pin.
The VDDAD pin should be routed carefully for maximum noise immunity.
4.3.3 Conversion Time
Conversion starts after a write to the ADSCR. One conversion will take between 16 and 17 ADC clock
cycles. The ADIVx and ADICLK bits should be set to provide a 1-MHz ADC clock frequency.
Conversion time = 16 to 17 ADC cycles
ADC frequency
Number of bus cycles = conversion time × bus frequency
MC68HC908GP32 Data Sheet, Rev. 10
54
Freescale Semiconductor
Interrupts
4.3.4 Conversion
In continuous conversion mode, the ADC data register will be filled with new data after each conversion.
Data from the previous conversion will be overwritten whether that data has been read or not.
Conversions will continue until the ADCO bit is cleared. The COCO bit is set after the first conversion and
will stay set until the next read of the ADC data register.
In single conversion mode, conversion begins with a write to the ADSCR. Only one conversion occurs
between writes to the ADSCR.
When a conversion is in process and the ADSCR is written, the current conversion data should be
discarded to prevent an incorrect reading.
4.3.5 Accuracy and Precision
The conversion process is monotonic and has no missing codes.
4.4 Interrupts
When the AIEN bit is set, the ADC module is capable of generating CPU interrupts after each ADC
conversion. A CPU interrupt is generated if the COCO bit is at logic 0. The COCO bit is not used as a
conversion complete flag when interrupts are enabled.
4.5 Low-Power Modes
The WAIT and STOP instruction can put the MCU in low power- consumption standby modes.
4.5.1 Wait Mode
The ADC continues normal operation during wait mode. Any enabled CPU interrupt request from the ADC
can bring the MCU out of wait mode. If the ADC is not required to bring the MCU out of wait mode, power
down the ADC by setting ADCH4–ADCH0 bits in the ADC status and control register before executing
the WAIT instruction.
4.5.2 Stop Mode
The ADC module is inactive after the execution of a STOP instruction. Any pending conversion is aborted.
ADC conversions resume when the MCU exits stop mode after an external interrupt. Allow one
conversion cycle to stabilize the analog circuitry.
4.6 I/O Signals
The ADC module has eight pins shared with port B, PTB7/AD7–PTB0/AD0.
4.6.1 ADC Analog Power Pin (VDDAD)/ADC Voltage Reference High Pin (VREFH)
The ADC analog portion uses VDDAD as its power pin. Connect the VDDAD pin to the same voltage
potential as VDD. External filtering may be necessary to ensure clean VDDAD for good results.
NOTE
For maximum noise immunity, route VDDAD carefully and place bypass
capacitors as close as possible to the package.
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
55
Analog-to-Digital Converter (ADC)
4.6.2 ADC Analog Ground Pin (VSSAD)/ADC Voltage Reference Low Pin (VREFL)
The ADC analog portion uses VSSAD as its ground pin. Connect the VSSAD pin to the same voltage
potential as VSS.
NOTE
Route VSSAD cleanly to avoid any offset errors.
4.6.3 ADC Voltage In (VADIN)
VADIN is the input voltage signal from one of the eight ADC channels to the ADC module.
4.7 I/O Registers
These I/O registers control and monitor ADC operation:
• ADC status and control register (ADSCR)
• ADC data register (ADR)
• ADC clock register (ADCLK)
4.7.1 ADC Status and Control Register
Function of the ADC status and control register (ADSCR) is described here.
Address:
$003C
Bit 7
6
5
4
3
2
1
Bit 0
AIEN
ADCO
ADCH4
ADCH3
ADCH2
ADCH1
ADCH0
0
1
1
1
1
1
Read:
COCO
Write:
R
Reset:
0
0
R
= Reserved
Figure 4-2. ADC Status and Control Register (ADSCR)
COCO — Conversions Complete Bit
In non-interrupt mode (AIEN = 0), COCO is a read-only bit that is set at the end of each conversion.
COCO will stay set until cleared by a read of the ADC data register. Reset clears this bit.
In interrupt mode (AIEN = 1), COCO is a read-only bit that is not set at the end of a conversion. It
always reads as a 0.
1 = Conversion completed (AIEN = 0)
0 = Conversion not completed (AIEN = 0) or CPU interrupt enabled (AIEN = 1)
NOTE
The write function of the COCO bit is reserved. When writing to the ADSCR
register, always have a 0 in the COCO bit position.
AIEN — ADC Interrupt Enable Bit
When this bit is set, an interrupt is generated at the end of an ADC conversion. The interrupt signal is
cleared when the data register is read or the status/control register is written. Reset clears the AIEN bit.
1 = ADC interrupt enabled
0 = ADC interrupt disabled
MC68HC908GP32 Data Sheet, Rev. 10
56
Freescale Semiconductor
I/O Registers
ADCO — ADC Continuous Conversion Bit
When set, the ADC will convert samples continuously and update the ADR register at the end of each
conversion. Only one conversion is completed between writes to the ADSCR when this bit is cleared.
Reset clears the ADCO bit.
1 = Continuous ADC conversion
0 = One ADC conversion
ADCH4–ADCH0 — ADC Channel Select Bits
ADCH4–ADCH0 form a 5-bit field which is used to select one of 16 ADC channels. Only eight
channels, AD7–AD0, are available on this MCU. The channels are detailed in Table 4-1. Care should
be taken when using a port pin as both an analog and digital input simultaneously to prevent switching
noise from corrupting the analog signal. (See Table 4-1.)
The ADC subsystem is turned off when the channel select bits are all set to 1. This feature allows for
reduced power consumption for the MCU when the ADC is not being used.
NOTE
Recovery from the disabled state requires one conversion cycle to stabilize.
The voltage levels supplied from internal reference nodes, as specified in Table 4-1, are used to verify
the operation of the ADC converter both in production test and for user applications.
Table 4-1. Mux Channel Select
ADCH4
ADCH3
ADCH2
ADCH1
ADCH0
Input Select
0
0
0
0
0
PTB0/AD0
0
0
0
0
1
PTB1/AD1
0
0
0
1
0
PTB2/AD2
0
0
0
1
1
PTB3/AD3
0
0
1
0
0
PTB4/AD4
0
0
1
0
1
PTB5/AD5
0
0
1
1
0
PTB6/AD6
0
0
1
1
1
PTB7/AD7
0
1
0
0
0
↓
↓
↓
↓
↓
1
1
1
0
0
1
1
1
0
1
VREFH
1
1
1
1
0
VREFL
1
1
1
1
1
ADC power off
Reserved
NOTE: If any unused channels are selected, the resulting ADC conversion will be unknown
or reserved.
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
57
Analog-to-Digital Converter (ADC)
4.7.2 ADC Data Register
One 8-bit result register, ADC data register (ADR), is provided. This register is updated each time an ADC
conversion completes.
Address:
Read:
$003D
Bit 7
6
5
4
3
2
1
Bit 0
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
0
0
0
0
0
0
0
0
Write:
Reset:
= Unimplemented
Figure 4-3. ADC Data Register (ADR)
4.7.3 ADC Clock Register
The ADC clock register (ADCLK) selects the clock frequency for the ADC.
Address:
Read:
Write:
Reset:
$003E
Bit 7
6
5
4
ADIV2
ADIV1
ADIV0
ADICLK
0
0
0
0
3
2
1
Bit 0
0
0
0
0
0
0
0
0
= Unimplemented
Figure 4-4. ADC Clock Register (ADCLK)
ADIV2–ADIV0 — ADC Clock Prescaler Bits
ADIV2–ADIV0 form a 3-bit field which selects the divide ratio used by the ADC to generate the internal
ADC clock. Table 4-2 shows the available clock configurations. The ADC clock should be set to
approximately 1 MHz.
Table 4-2. ADC Clock Divide Ratio
ADIV2
ADIV1
ADIV0
0
0
0
ADC input clock ÷ 1
ADC Clock Rate
0
0
1
ADC input clock ÷ 2
0
1
0
ADC input clock ÷ 4
0
1
1
ADC input clock ÷ 8
1
X
X
ADC input clock ÷ 16
X = don’t care
MC68HC908GP32 Data Sheet, Rev. 10
58
Freescale Semiconductor
I/O Registers
ADICLK — ADC Input Clock Select Bit
ADICLK selects either the bus clock or CGMXCLK as the input clock source to generate the internal
ADC clock. Reset selects CGMXCLK as the ADC clock source.
If the external clock (CGMXCLK) is equal to or greater than 1 MHz, CGMXCLK can be used as the
clock source for the ADC. If CGMXCLK is less than 1 MHz, use the PLL-generated bus clock as the
clock source. As long as the internal ADC clock is at approximately 1 MHz, correct operation can be
guaranteed.
1 = Internal bus clock
0 = External clock (CGMXCLK)
ADC input clock frequency
------------------------------------------------------------------------ = 1MHz
ADIV 2 –ADIV 0
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
59
Analog-to-Digital Converter (ADC)
MC68HC908GP32 Data Sheet, Rev. 10
60
Freescale Semiconductor
Chapter 5
Clock Generator Module (CGM)
5.1 Introduction
This section describes the clock generator module. The CGM generates the crystal clock signal,
CGMXCLK, which operates at the frequency of the crystal. The CGM also generates the base clock
signal, CGMOUT, which is based on either the crystal clock divided by two or the phase-locked loop (PLL)
clock, CGMVCLK, divided by two. In user mode, CGMOUT is the clock from which the SIM derives the
system clocks, including the bus clock, which is at a frequency of CGMOUT/2. In monitor mode, PTC3
determines the bus clock. The PLL is a fully functional frequency generator designed for use with crystals
or ceramic resonators. The PLL can generate an 8-MHz bus frequency using a 32-kHz crystal.
5.2 Features
Features of the CGM include:
• Phase-locked loop with output frequency in integer multiples of an integer dividend of the crystal
reference
• Low-frequency crystal operation with low-power operation and high-output frequency resolution
• Programmable prescaler for power-of-two increases in frequency
• Programmable hardware voltage-controlled oscillator (VCO) for low-jitter operation
• Automatic bandwidth control mode for low-jitter operation
• Automatic frequency lock detector
• CPU interrupt on entry or exit from locked condition
• Configuration register bit to allow oscillator operation during stop mode
5.3 Functional Description
The CGM consists of three major submodules:
• Crystal oscillator circuit — The crystal oscillator circuit generates the constant crystal frequency
clock, CGMXCLK.
• Phase-locked loop (PLL) — The PLL generates the programmable VCO frequency clock,
CGMVCLK.
• Base clock selector circuit — This software-controlled circuit selects either CGMXCLK divided by
two or the VCO clock, CGMVCLK, divided by two as the base clock, CGMOUT. The SIM derives
the system clocks from either CGMOUT or CGMXCLK.
Figure 5-1 shows the structure of the CGM.
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
61
Clock Generator Module (CGM)
OSCILLATOR (OSC)
OSC2
CGMXCLK
(TO: SIM, TIMTB15A, ADC)
OSC1
SIMOSCEN (FROM SIM)
OSCSTOPENB
(FROM CONFIG)
PHASE-LOCKED LOOP (PLL)
CGMRDV
REFERENCE
DIVIDER
CGMRCLK
CLOCK
SELECT
CIRCUIT
BCS
R
RDS3–RDS0
VDDA
CGMXFC
÷2
A
CGMOUT
B S*
(TO SIM)
*WHEN S = 1,
CGMOUT = B
VSSA
SIMDIV2
(FROM SIM)
VPR1–VPR0
VRS7–VRS0
L
VOLTAGE
CONTROLLED
OSCILLATOR
LOOP
FILTER
PHASE
DETECTOR
2E
CGMVCLK
PLL ANALOG
AUTOMATIC
MODE
CONTROL
LOCK
DETECTOR
LOCK
AUTO
MUL11–MUL0
N
CGMVDV
FREQUENCY
DIVIDER
ACQ
INTERRUPT
CONTROL
PLLIE
PLLIREQ
(TO SIM)
PLLF
PRE1–PRE0
2P
FREQUENCY
DIVIDER
Figure 5-1. CGM Block Diagram
MC68HC908GP32 Data Sheet, Rev. 10
62
Freescale Semiconductor
Functional Description
5.3.1 Crystal Oscillator Circuit
The crystal oscillator circuit consists of an inverting amplifier and an external crystal. The OSC1 pin is the
input to the amplifier and the OSC2 pin is the output. The SIMOSCEN signal from the system integration
module (SIM) or the OSCSTOPENB bit in the CONFIG register enable the crystal oscillator circuit.
The CGMXCLK signal is the output of the crystal oscillator circuit and runs at a rate equal to the crystal
frequency. CGMXCLK is then buffered to produce CGMRCLK, the PLL reference clock.
CGMXCLK can be used by other modules which require precise timing for operation. The duty cycle of
CGMXCLK is not guaranteed to be 50% and depends on external factors, including the crystal and related
external components. An externally generated clock also can feed the OSC1 pin of the crystal oscillator
circuit. Connect the external clock to the OSC1 pin and let the OSC2 pin float.
5.3.2 Phase-Locked Loop Circuit (PLL)
The PLL is a frequency generator that can operate in either acquisition mode or tracking mode, depending
on the accuracy of the output frequency. The PLL can change between acquisition and tracking modes
either automatically or manually.
5.3.3 PLL Circuits
The PLL consists of these circuits:
• Voltage-controlled oscillator (VCO)
• Reference divider
• Frequency prescaler
• Modulo VCO frequency divider
• Phase detector
• Loop filter
• Lock detector
The operating range of the VCO is programmable for a wide range of frequencies and for maximum
immunity to external noise, including supply and CGMXFC noise. The VCO frequency is bound to a range
from roughly one-half to twice the center-of-range frequency, fVRS. Modulating the voltage on the
CGM/XFC pin changes the frequency within this range. By design, fVRS is equal to the nominal
center-of-range frequency, fNOM, (38.4 kHz) times a linear factor, L, and a power-of-two factor, E, or
(L × 2E)fNOM.
CGMRCLK is the PLL reference clock, a buffered version of CGMXCLK. CGMRCLK runs at a frequency,
fRCLK, and is fed to the PLL through a programmable modulo reference divider, which divides fRCLK by a
factor, R. The divider’s output is the final reference clock, CGMRDV, running at a frequency,
fRDV = fRCLK/R. With an external crystal (30 kHz–100 kHz), always set R = 1 for specified performance.
With an external high-frequency clock source, use R to divide the external frequency to between 30 kHz
and 100 kHz.
The VCO’s output clock, CGMVCLK, running at a frequency, fVCLK, is fed back through a programmable
prescale divider and a programmable modulo divider. The prescaler divides the VCO clock by a
power-of-two factor P and the modulo divider reduces the VCO clock by a factor, N. The dividers’ output
is the VCO feedback clock, CGMVDV, running at a frequency, fVDV = fVCLK/(N × 2P). (See 5.3.6
Programming the PLL for more information.)
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
63
Clock Generator Module (CGM)
The phase detector then compares the VCO feedback clock, CGMVDV, with the final reference clock,
CGMRDV. A correction pulse is generated based on the phase difference between the two signals. The
loop filter then slightly alters the DC voltage on the external capacitor connected to CGM/XFC based on
the width and direction of the correction pulse. The filter can make fast or slow corrections depending on
its mode, described in 5.3.4 Acquisition and Tracking Modes. The value of the external capacitor and the
reference frequency determines the speed of the corrections and the stability of the PLL.
The lock detector compares the frequencies of the VCO feedback clock, CGMVDV, and the final
reference clock, CGMRDV. Therefore, the speed of the lock detector is directly proportional to the final
reference frequency, fRDV. The circuit determines the mode of the PLL and the lock condition based on
this comparison.
5.3.4 Acquisition and Tracking Modes
The PLL filter is manually or automatically configurable into one of two operating modes:
• Acquisition mode — In acquisition mode, the filter can make large frequency corrections to the
VCO. This mode is used at PLL startup or when the PLL has suffered a severe noise hit and the
VCO frequency is far off the desired frequency. When in acquisition mode, the ACQ bit is clear in
the PLL bandwidth control register. (See 5.5.2 PLL Bandwidth Control Register.)
• Tracking mode — In tracking mode, the filter makes only small corrections to the frequency of the
VCO. PLL jitter is much lower in tracking mode, but the response to noise is also slower. The PLL
enters tracking mode when the VCO frequency is nearly correct, such as when the PLL is selected
as the base clock source. (See 5.3.8 Base Clock Selector Circuit.) The PLL is automatically in
tracking mode when not in acquisition mode or when the ACQ bit is set.
5.3.5 Manual and Automatic PLL Bandwidth Modes
The PLL can change the bandwidth or operational mode of the loop filter manually or automatically.
Automatic mode is recommended for most users.
In automatic bandwidth control mode (AUTO = 1), the lock detector automatically switches between
acquisition and tracking modes. Automatic bandwidth control mode also is used to determine when the
VCO clock, CGMVCLK, is safe to use as the source for the base clock, CGMOUT. (See 5.5.2 PLL
Bandwidth Control Register.) If PLL interrupts are enabled, the software can wait for a PLL interrupt
request and then check the LOCK bit. If interrupts are disabled, software can poll the LOCK bit
continuously (during PLL startup, usually) or at periodic intervals. In either case, when the LOCK bit is
set, the VCO clock is safe to use as the source for the base clock. (See 5.3.8 Base Clock Selector Circuit.)
If the VCO is selected as the source for the base clock and the LOCK bit is clear, the PLL has suffered a
severe noise hit and the software must take appropriate action, depending on the application. (See 5.6
Interrupts for information and precautions on using interrupts.)
The following conditions apply when the PLL is in automatic bandwidth control mode:
• The ACQ bit (See 5.5.2 PLL Bandwidth Control Register.) is a read-only indicator of the mode of
the filter. (See 5.3.4 Acquisition and Tracking Modes.)
• The ACQ bit is set when the VCO frequency is within a certain tolerance and is cleared when the
VCO frequency is out of a certain tolerance. (See 5.8 Acquisition/Lock Time Specifications for
more information.)
• The LOCK bit is a read-only indicator of the locked state of the PLL.
MC68HC908GP32 Data Sheet, Rev. 10
64
Freescale Semiconductor
Functional Description
•
•
The LOCK bit is set when the VCO frequency is within a certain tolerance and is cleared when the
VCO frequency is out of a certain tolerance. (See 5.8 Acquisition/Lock Time Specifications for
more information.)
CPU interrupts can occur if enabled (PLLIE = 1) when the PLL’s lock condition changes, toggling
the LOCK bit. (See 5.5.1 PLL Control Register.)
The PLL also may operate in manual mode (AUTO = 0). Manual mode is used by systems that do not
require an indicator of the lock condition for proper operation. Such systems typically operate well below
fBUSMAX.
The following conditions apply when in manual mode:
• ACQ is a writable control bit that controls the mode of the filter. Before turning on the PLL in manual
mode, the ACQ bit must be clear.
• Before entering tracking mode (ACQ = 1), software must wait a given time, tACQ (See 5.8
Acquisition/Lock Time Specifications.), after turning on the PLL by setting PLLON in the PLL
control register (PCTL).
• Software must wait a given time, tAL, after entering tracking mode before selecting the PLL as the
clock source to CGMOUT (BCS = 1).
• The LOCK bit is disabled.
• CPU interrupts from the CGM are disabled.
5.3.6 Programming the PLL
The following procedure shows how to program the PLL.
NOTE
The round function in the following equations means that the real number
should be rounded to the nearest integer number.
1. Choose the desired bus frequency, fBUSDES.
2. Calculate the desired VCO frequency (four times the desired bus frequency).
f VCLKDES = 4 × f BUSDES
3. Choose a practical PLL (crystal) reference frequency, fRCLK, and the reference clock divider, R.
Typically, the reference crystal is 32.768 kHz and R = 1.
Frequency errors to the PLL are corrected at a rate of fRCLK/R. For stability and lock time reduction,
this rate must be as fast as possible. The VCO frequency must be an integer multiple of this rate.
The relationship between the VCO frequency, fVCLK, and the reference frequency, fRCLK, is
P
2 N
f VCLK = ------------ ( f RCLK )
R
P, the power of two multiplier, and N, the range multiplier, are integers.
In cases where desired bus frequency has some tolerance, choose fRCLK to a value determined
either by other module requirements (such as modules which are clocked by CGMXCLK), cost
requirements, or ideally, as high as the specified range allows. See Chapter 19 Electrical
Specifications. Choose the reference divider, R = 1. After choosing N and P, the actual bus
frequency can be determined using equation in 2 above.
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
65
Clock Generator Module (CGM)
When the tolerance on the bus frequency is tight, choose fRCLK to an integer divisor of fBUSDES,
and R = 1. If fRCLK cannot meet this requirement, use the following equation to solve for R with
practical choices of fRCLK, and choose the fRCLK that gives the lowest R.
⎛ f VCLKDES⎞ ⎫
⎧ ⎛ f VCLKDES⎞
R = round R MAX × ⎨ ⎜ --------------------------⎟ – integer ⎜ --------------------------⎟ ⎬
⎝ f RCLK ⎠ ⎭
⎩ ⎝ f RCLK ⎠
4. Select a VCO frequency multiplier, N.
⎛ R × f VCLKDES⎞
N = round ⎜ -------------------------------------⎟
f RCLK
⎝
⎠
Reduce N/R to the lowest possible R.
5. If N is < Nmax, use P = 0. If N > Nmax, choose P using this table:
Current N Value
P
0 < N ≤ N max
0
N max < N ≤ N max × 2
1
N max × 2 < N ≤ N max × 4
2
N max × 4 < N ≤ N max × 8
3
Then recalculate N:
⎛ R × f VCLKDES⎞
N = round ⎜ ------------------------------------⎟
P
⎝ f
×2 ⎠
RCLK
6. Calculate and verify the adequacy of the VCO and bus frequencies fVCLK and fBUS.
P
f VCLK = ( 2 × N ⁄ R ) × f RCLK
f BUS = ( f VCLK ) ⁄ 4
7. Select the VCO’s power-of-two range multiplier E, according to this table:
Frequency Range
E
0 < fVCLK < 9,830,400
0
9,830,400 ≤ fVCLK < 19,660,800
1
19,660,800 ≤ fVCLK < 39,321,600
2
NOTE: Do not program E to a value of 3.
8. Select a VCO linear range multiplier, L, where fNOM = 38.4 kHz
⎛ f VCLK ⎞
L = round ⎜ -------------------------⎟
⎝ 2E × f
⎠
NOM
MC68HC908GP32 Data Sheet, Rev. 10
66
Freescale Semiconductor
Functional Description
9. Calculate and verify the adequacy of the VCO programmed center-of-range frequency, fVRS. The
center-of-range frequency is the midpoint between the minimum and maximum frequencies
attainable by the PLL.
E
f VRS = ( L × 2 )f NOM
For proper operation,
E
f NOM × 2
f VRS – f VCLK ≤ ---------------------------2
10. Verify the choice of P, R, N, E, and L by comparing fVCLK to fVRS and fVCLKDES. For proper
operation, fVCLK must be within the application’s tolerance of fVCLKDES, and fVRS must be as close
as possible to fVCLK.
NOTE
Exceeding the recommended maximum bus frequency or VCO frequency
can crash the MCU.
11. Program the PLL registers accordingly:
a. In the PRE bits of the PLL control register (PCTL), program the binary equivalent of P.
b.
c.
In the VPR bits of the PLL control register (PCTL), program the binary equivalent of E.
d.
e.
In the PLL VCO range select register (PMRS), program the binary coded equivalent of L.
In the PLL multiplier select register low (PMSL) and the PLL multiplier select register high
(PMSH), program the binary equivalent of N.
In the PLL reference divider select register (PMDS), program the binary coded equivalent of
R.
NOTE
The values for P, E, N, L, and R can only be programmed when the PLL is
off (PLLON = 0).
Table 5-1 provides numeric examples (numbers are in hexadecimal notation):
Table 5-1. Numeric Example
fBUS
fRCLK
R
N
P
E
L
2.0 MHz
32.768 kHz
1
F5
0
0
D1
2.4576 MHz
32.768 kHz
1
12C
0
1
80
2.5 MHz
32.768 kHz
1
132
0
1
83
4.0 MHz
32.768 kHz
1
1E9
0
1
D1
4.9152 MHz
32.768 kHz
1
258
0
2
80
5.0 MHz
32.768 kHz
1
263
0
2
82
7.3728 MHz
32.768 kHz
1
384
0
2
C0
8.0 MHz
32.768 kHz
1
3D1
0
2
D0
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
67
Clock Generator Module (CGM)
5.3.7 Special Programming Exceptions
The programming method described in 5.3.6 Programming the PLL does not account for three possible
exceptions. A value of 0 for R, N, or L is meaningless when used in the equations given. To account for
these exceptions:
• A 0 value for R or N is interpreted exactly the same as a value of 1.
• A 0 value for L disables the PLL and prevents its selection as the source for the base clock.
(See 5.3.8 Base Clock Selector Circuit.)
5.3.8 Base Clock Selector Circuit
This circuit is used to select either the crystal clock, CGMXCLK, or the VCO clock, CGMVCLK, as the
source of the base clock, CGMOUT. The two input clocks go through a transition control circuit that waits
up to three CGMXCLK cycles and three CGMVCLK cycles to change from one clock source to the other.
During this time, CGMOUT is held in stasis. The output of the transition control circuit is then divided by
two to correct the duty cycle. Therefore, the bus clock frequency, which is one-half of the base clock
frequency, is one-fourth the frequency of the selected clock (CGMXCLK or CGMVCLK).
The BCS bit in the PLL control register (PCTL) selects which clock drives CGMOUT. The VCO clock
cannot be selected as the base clock source if the PLL is not turned on. The PLL cannot be turned off if
the VCO clock is selected. The PLL cannot be turned on or off simultaneously with the selection or
deselection of the VCO clock. The VCO clock also cannot be selected as the base clock source if the
factor L is programmed to a 0. This value would set up a condition inconsistent with the operation of the
PLL, so that the PLL would be disabled and the crystal clock would be forced as the source of the base
clock.
5.3.9 CGM External Connections
In its typical configuration, the CGM requires up to nine external components. Five of these are for the
crystal oscillator and two or four are for the PLL.
The crystal oscillator is normally connected in a Pierce oscillator configuration, as shown in Figure 5-2.
Figure 5-2 shows only the logical representation of the internal components and may not represent actual
circuitry. The oscillator configuration uses five components:
• Crystal, X1
• Fixed capacitor, C1
• Tuning capacitor, C2 (can also be a fixed capacitor)
• Feedback resistor, RB
• Series resistor, RS
The series resistor (RS) is included in the diagram to follow strict Pierce oscillator guidelines. Refer to the
crystal manufacturer’s data for more information regarding values for C1 and C2.
Figure 5-2 also shows the external components for the PLL:
• Bypass capacitor, CBYP
• Filter network
Routing should be done with great care to minimize signal cross talk and noise.
See 19.16.1 CGM Component Specifications for capacitor and resistor values.
MC68HC908GP32 Data Sheet, Rev. 10
68
Freescale Semiconductor
I/O Signals
SIMOSCEN
OSCSTOPENB
(FROM CONFIG)
CGMXCLK
OSC1
OSC2
VSSA
CGMXFC
VDDA
VDD
RB
10 kΩ
RS
0.01 µF
CBYP
0.1 µF
0.033 µF
X1
C1
C2
Note: Filter network in box can be replaced with a 0.47µF capacitor, but will degrade stability.
Figure 5-2. CGM External Connections
5.4 I/O Signals
The following paragraphs describe the CGM I/O signals.
5.4.1 Crystal Amplifier Input Pin (OSC1)
The OSC1 pin is an input to the crystal oscillator amplifier.
5.4.2 Crystal Amplifier Output Pin (OSC2)
The OSC2 pin is the output of the crystal oscillator inverting amplifier.
5.4.3 External Filter Capacitor Pin (CGMXFC)
The CGMXFC pin is required by the loop filter to filter out phase corrections. An external filter network is
connected to this pin. (See Figure 5-2.)
NOTE
To prevent noise problems, the filter network should be placed as close to
the CGMXFC pin as possible, with minimum routing distances and no
routing of other signals across the network.
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
69
Clock Generator Module (CGM)
5.4.4 PLL Analog Power Pin (VDDA)
VDDA is a power pin used by the analog portions of the PLL. Connect the VDDA pin to the same voltage
potential as the VDD pin.
NOTE
Route VDDA carefully for maximum noise immunity and place bypass
capacitors as close as possible to the package.
5.4.5 PLL Analog Ground Pin (VSSA)
VSSA is a ground pin used by the analog portions of the PLL. Connect the VSSA pin to the same voltage
potential as the VSS pin.
NOTE
Route VSSA carefully for maximum noise immunity and place bypass
capacitors as close as possible to the package.
5.4.6 Oscillator Enable Signal (SIMOSCEN)
The SIMOSCEN signal comes from the system integration module (SIM) and enables the oscillator and
PLL.
5.4.7 Oscillator Stop Mode Enable Bit (OSCSTOPENB)
OSCSTOPENB is a bit in the CONFIG register that enables the oscillator to continue operating during
stop mode. If this bit is set, the Oscillator continues running during stop mode. If this bit is not set (default),
the oscillator is controlled by the SIMOSCEN signal which will disable the oscillator during stop mode.
5.4.8 Crystal Output Frequency Signal (CGMXCLK)
CGMXCLK is the crystal oscillator output signal. It runs at the full speed of the crystal (fXCLK) and comes
directly from the crystal oscillator circuit. Figure 5-2 shows only the logical relation of CGMXCLK to OSC1
and OSC2 and may not represent the actual circuitry. The duty cycle of CGMXCLK is unknown and may
depend on the crystal and other external factors. Also, the frequency and amplitude of CGMXCLK can be
unstable at startup.
5.4.9 CGM Base Clock Output (CGMOUT)
CGMOUT is the clock output of the CGM. This signal goes to the SIM, which generates the MCU clocks.
CGMOUT is a 50 percent duty cycle clock running at twice the bus frequency. CGMOUT is software
programmable to be either the oscillator output, CGMXCLK, divided by two or the VCO clock, CGMVCLK,
divided by two.
5.4.10 CGM CPU Interrupt (CGMINT)
CGMINT is the interrupt signal generated by the PLL lock detector.
MC68HC908GP32 Data Sheet, Rev. 10
70
Freescale Semiconductor
CGM Registers
5.5 CGM Registers
These registers control and monitor operation of the CGM:
• PLL control register (PCTL)
(See 5.5.1 PLL Control Register.)
• PLL bandwidth control register (PBWC)
(See 5.5.2 PLL Bandwidth Control Register.)
• PLL multiplier select register high (PMSH)
(See 5.5.3 PLL Multiplier Select Register High.)
• PLL multiplier select register low (PMSL)
(See 5.5.4 PLL Multiplier Select Register Low.)
• PLL VCO range select register (PMRS)
(See 5.5.5 PLL VCO Range Select Register.)
• PLL reference divider select register (PMDS)
(See 5.5.6 PLL Reference Divider Select Register.)
Figure 5-3 is a summary of the CGM registers.
Addr.
Register Name
$0036
PLL Control Register
(PCTL)
$0037
PLL Bandwidth Control
Register
(PBWC)
$0038
PLL Multiplier Select High
Register
(PMSH)
$0039
PLL Multiplier Select Low
Register
(PMSL)
$003A
PLL VCO Range Select
Register
(PMRS)
$003B
PLL Reference Divider
Select Register
(PMDS)
Bit 7
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
PLLIE
0
AUTO
6
PLLF
0
LOCK
5
4
3
2
1
Bit 0
PLLON
BCS
PRE1
PRE0
VPR1
VPR0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
MUL11
MUL10
MUL9
MUL8
ACQ
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
MUL7
MUL6
MUL5
MUL4
MUL3
MUL2
MUL1
MUL0
0
1
0
0
0
0
0
0
VRS7
VRS6
VRS5
VRS4
VRS3
VRS2
VRS1
VRS0
0
0
1
0
0
0
0
0
0
0
0
0
RDS3
RDS2
RDS1
RDS0
0
0
= Unimplemented
0
R
0
= Reserved
0
0
1
0
NOTES:
1. When AUTO = 0, PLLIE is forced clear and is read-only.
2. When AUTO = 0, PLLF and LOCK read as clear.
3. When AUTO = 1, ACQ is read-only.
4. When PLLON = 0 or VRS7:VRS0 = $0, BCS is forced clear and is read-only.
5. When PLLON = 1, the PLL programming register is read-only.
6. When BCS = 1, PLLON is forced set and is read-only.
Figure 5-3. CGM I/O Register Summary
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
71
Clock Generator Module (CGM)
5.5.1 PLL Control Register
The PLL control register (PCTL) contains the interrupt enable and flag bits, the on/off switch, the base
clock selector bit, the prescaler bits, and the VCO power-of-two range selector bits.
Address:
$0036
Bit 7
Read:
Write:
Reset:
PLLIE
0
6
PLLF
5
4
3
2
1
Bit 0
PLLON
BCS
PRE1
PRE0
VPR1
VPR0
1
0
0
0
0
0
0
= Unimplemented
Figure 5-4. PLL Control Register (PCTL)
PLLIE — PLL Interrupt Enable Bit
This read/write bit enables the PLL to generate an interrupt request when the LOCK bit toggles, setting
the PLL flag, PLLF. When the AUTO bit in the PLL bandwidth control register (PBWC) is clear, PLLIE
cannot be written and reads as logic 0. Reset clears the PLLIE bit.
1 = PLL interrupts enabled
0 = PLL interrupts disabled
PLLF — PLL Interrupt Flag Bit
This read-only bit is set whenever the LOCK bit toggles. PLLF generates an interrupt request if the
PLLIE bit also is set. PLLF always reads as logic 0 when the AUTO bit in the PLL bandwidth control
register (PBWC) is clear. Clear the PLLF bit by reading the PLL control register. Reset clears the PLLF
bit.
1 = Change in lock condition
0 = No change in lock condition
NOTE
Do not inadvertently clear the PLLF bit. Any read or read-modify-write
operation on the PLL control register clears the PLLF bit.
PLLON — PLL On Bit
This read/write bit activates the PLL and enables the VCO clock, CGMVCLK. PLLON cannot be
cleared if the VCO clock is driving the base clock, CGMOUT (BCS = 1). (See 5.3.8 Base Clock
Selector Circuit.) Reset sets this bit so that the loop can stabilize as the MCU is powering up.
1 = PLL on
0 = PLL off
BCS — Base Clock Select Bit
This read/write bit selects either the crystal oscillator output, CGMXCLK, or the VCO clock,
CGMVCLK, as the source of the CGM output, CGMOUT. CGMOUT frequency is one-half the
frequency of the selected clock. BCS cannot be set while the PLLON bit is clear. After toggling BCS,
it may take up to three CGMXCLK and three CGMVCLK cycles to complete the transition from one
source clock to the other. During the transition, CGMOUT is held in stasis. (See 5.3.8 Base Clock
Selector Circuit.) Reset clears the BCS bit.
1 = CGMVCLK divided by two drives CGMOUT
0 = CGMXCLK divided by two drives CGMOUT
NOTE
PLLON and BCS have built-in protection that prevents the base clock
selector circuit from selecting the VCO clock as the source of the base clock
MC68HC908GP32 Data Sheet, Rev. 10
72
Freescale Semiconductor
CGM Registers
if the PLL is off. Therefore, PLLON cannot be cleared when BCS is set, and
BCS cannot be set when PLLON is clear. If the PLL is off (PLLON = 0),
selecting CGMVCLK requires two writes to the PLL control register. (See
5.3.8 Base Clock Selector Circuit.)
PRE1 and PRE0 — Prescaler Program Bits
These read/write bits control a prescaler that selects the prescaler power-of-two multiplier, P. (See
5.3.3 PLL Circuits and 5.3.6 Programming the PLL.) PRE1 and PRE0 cannot be written when the
PLLON bit is set. Reset clears these bits.
NOTE
The value of P is normally 0 when using a 32.768-kHz crystal as the
reference.
Table 5-2. PRE1 and PRE0 Programming
PRE1 and PRE0
P
Prescaler Multiplier
00
0
1
01
1
2
10
2
4
11
3
8
VPR1 and VPR0 — VCO Power-of-Two Range Select Bits
These read/write bits control the VCO’s hardware power-of-two range multiplier E that, in conjunction
with L (See 5.3.3 PLL Circuits, 5.3.6 Programming the PLL, and 5.5.5 PLL VCO Range Select
Register.) controls the hardware center-of-range frequency, fVRS. VPR1:VPR0 cannot be written when
the PLLON bit is set. Reset clears these bits.
Table 5-3. VPR1 and VPR0 Programming
VPR1 and VPR0
E
VCO Power-of-Two
Range Multiplier
00
0
1
01
1
2
10
2
4
11
(1)
8
3
1. Do not program E to a value of 3.
5.5.2 PLL Bandwidth Control Register
The PLL bandwidth control register (PBWC):
• Selects automatic or manual (software-controlled) bandwidth control mode
• Indicates when the PLL is locked
• In automatic bandwidth control mode, indicates when the PLL is in acquisition or tracking mode
• In manual operation, forces the PLL into acquisition or tracking mode
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
73
Clock Generator Module (CGM)
Address:
$0037
Bit 7
Read:
Write:
Reset:
AUTO
0
6
5
LOCK
ACQ
0
0
= Unimplemented
4
3
2
1
0
0
0
0
0
0
0
0
R
Bit 0
R
0
= Reserved
Figure 5-5. PLL Bandwidth Control Register (PBWC)
AUTO — Automatic Bandwidth Control Bit
This read/write bit selects automatic or manual bandwidth control. When initializing the PLL for manual
operation (AUTO = 0), clear the ACQ bit before turning on the PLL. Reset clears the AUTO bit.
1 = Automatic bandwidth control
0 = Manual bandwidth control
LOCK — Lock Indicator Bit
When the AUTO bit is set, LOCK is a read-only bit that becomes set when the VCO clock, CGMVCLK,
is locked (running at the programmed frequency). When the AUTO bit is clear, LOCK reads as logic 0
and has no meaning. The write one function of this bit is reserved for test, so this bit must always be
written a 0. Reset clears the LOCK bit.
1 = VCO frequency correct or locked
0 = VCO frequency incorrect or unlocked
ACQ — Acquisition Mode Bit
When the AUTO bit is set, ACQ is a read-only bit that indicates whether the PLL is in acquisition mode
or tracking mode. When the AUTO bit is clear, ACQ is a read/write bit that controls whether the PLL is
in acquisition or tracking mode.
In automatic bandwidth control mode (AUTO = 1), the last-written value from manual operation is
stored in a temporary location and is recovered when manual operation resumes. Reset clears this bit,
enabling acquisition mode.
1 = Tracking mode
0 = Acquisition mode
5.5.3 PLL Multiplier Select Register High
The PLL multiplier select register high (PMSH) contains the programming information for the high byte of
the modulo feedback divider.
Address:
Read:
$0038
Bit 7
6
5
4
0
0
0
0
0
0
0
0
Write:
Reset:
3
2
1
Bit 0
MUL11
MUL10
MUL9
MUL8
0
0
0
0
= Unimplemented
Figure 5-6. PLL Multiplier Select Register High (PMSH)
MUL11–MUL8 — Multiplier Select Bits
These read/write bits control the high byte of the modulo feedback divider that selects the VCO
frequency multiplier N. (See 5.3.3 PLL Circuits and 5.3.6 Programming the PLL.) A value of $0000 in
MC68HC908GP32 Data Sheet, Rev. 10
74
Freescale Semiconductor
CGM Registers
the multiplier select registers configures the modulo feedback divider the same as a value of $0001.
Reset initializes the registers to $0040 for a default multiply value of 64.
NOTE
The multiplier select bits have built-in protection such that they cannot be
written when the PLL is on (PLLON = 1).
Bit7–Bit4 — Unimplemented Bits
These bits have no function and always read as logic 0s.
5.5.4 PLL Multiplier Select Register Low
The PLL multiplier select register low (PMSL) contains the programming information for the low byte of
the modulo feedback divider.
Address:
Read:
Write:
Reset:
$0038
Bit 7
6
5
4
3
2
1
Bit 0
MUL7
MUL6
MUL5
MUL4
MUL3
MUL2
MUL1
MUL0
0
1
0
0
0
0
0
0
Figure 5-7. PLL Multiplier Select Register Low (PMSL)
MUL7–MUL0 — Multiplier Select Bits
These read/write bits control the low byte of the modulo feedback divider that selects the VCO
frequency multiplier, N. (See 5.3.3 PLL Circuits and 5.3.6 Programming the PLL.) MUL7–MUL0 cannot
be written when the PLLON bit in the PCTL is set. A value of $0000 in the multiplier select registers
configures the modulo feedback divider the same as a value of $0001. Reset initializes the register to
$40 for a default multiply value of 64.
NOTE
The multiplier select bits have built-in protection such that they cannot be
written when the PLL is on (PLLON = 1).
5.5.5 PLL VCO Range Select Register
NOTE
PMRS may be called PVRS on other HC08 derivatives.
The PLL VCO range select register (PMRS) contains the programming information required for the
hardware configuration of the VCO.
Address:
Read:
Write:
Reset:
$003A
Bit 7
6
5
4
3
2
1
Bit 0
VRS7
VRS6
VRS5
VRS4
VRS3
VRS2
VRS1
VRS0
0
1
0
0
0
0
0
0
Figure 5-8. PLL VCO Range Select Register (PMRS)
VRS7–VRS0 — VCO Range Select Bits
These read/write bits control the hardware center-of-range linear multiplier L which, in conjunction with
E (See 5.3.3 PLL Circuits, 5.3.6 Programming the PLL, and 5.5.1 PLL Control Register.), controls the
hardware center-of-range frequency, fVRS. VRS7–VRS0 cannot be written when the PLLON bit in the
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
75
Clock Generator Module (CGM)
PCTL is set. (See 5.3.7 Special Programming Exceptions.) A value of $00 in the VCO range select
register disables the PLL and clears the BCS bit in the PLL control register (PCTL). (See 5.3.8 Base
Clock Selector Circuit and 5.3.7 Special Programming Exceptions.). Reset initializes the register to
$40 for a default range multiply value of 64.
NOTE
The VCO range select bits have built-in protection such that they cannot be
written when the PLL is on (PLLON = 1) and such that the VCO clock
cannot be selected as the source of the base clock (BCS = 1) if the VCO
range select bits are all clear.
The PLL VCO range select register must be programmed correctly.
Incorrect programming can result in failure of the PLL to achieve lock.
5.5.6 PLL Reference Divider Select Register
NOTE
PMDS may be called PRDS on other HC08 derivatives.
The PLL reference divider select register (PMDS) contains the programming information for the modulo
reference divider.
Address:
Read:
$003B
Bit 7
6
5
4
0
0
0
0
0
0
0
0
Write:
Reset:
3
2
1
Bit 0
RDS3
RDS2
RDS1
RDS0
0
0
0
1
= Unimplemented
Figure 5-9. PLL Reference Divider Select Register (PMDS)
RDS3–RDS0 — Reference Divider Select Bits
These read/write bits control the modulo reference divider that selects the reference division factor, R.
(See 5.3.3 PLL Circuits and 5.3.6 Programming the PLL.) RDS7–RDS0 cannot be written when the
PLLON bit in the PCTL is set. A value of $00 in the reference divider select register configures the
reference divider the same as a value of $01. (See 5.3.7 Special Programming Exceptions.) Reset
initializes the register to $01 for a default divide value of 1.
NOTE
The reference divider select bits have built-in protection such that they
cannot be written when the PLL is on (PLLON = 1).
NOTE
The default divide value of 1 is recommended for all applications.
Bit7–Bit4 — Unimplemented Bits
These bits have no function and always read as 0s.
5.6 Interrupts
When the AUTO bit is set in the PLL bandwidth control register (PBWC), the PLL can generate a CPU
interrupt request every time the LOCK bit changes state. The PLLIE bit in the PLL control register (PCTL)
enables CPU interrupts from the PLL. PLLF, the interrupt flag in the PCTL, becomes set whether
MC68HC908GP32 Data Sheet, Rev. 10
76
Freescale Semiconductor
Special Modes
interrupts are enabled or not. When the AUTO bit is clear, CPU interrupts from the PLL are disabled and
PLLF reads as logic 0.
Software should read the LOCK bit after a PLL interrupt request to see if the request was due to an entry
into lock or an exit from lock. When the PLL enters lock, the VCO clock, CGMVCLK, divided by two can
be selected as the CGMOUT source by setting BCS in the PCTL. When the PLL exits lock, the VCO clock
frequency is corrupt, and appropriate precautions should be taken. If the application is not frequency
sensitive, interrupts should be disabled to prevent PLL interrupt service routines from impeding software
performance or from exceeding stack limitations.
NOTE
Software can select the CGMVCLK divided by two as the CGMOUT source
even if the PLL is not locked (LOCK = 0). Therefore, software should make
sure the PLL is locked before setting the BCS bit.
5.7 Special Modes
The WAIT instruction puts the MCU in low power-consumption standby modes.
5.7.1 Wait Mode
The WAIT instruction does not affect the CGM. Before entering wait mode, software can disengage and
turn off the PLL by clearing the BCS and PLLON bits in the PLL control register (PCTL) to save power.
Less power-sensitive applications can disengage the PLL without turning it off, so that the PLL clock is
immediately available at WAIT exit. This would be the case also when the PLL is to wake the MCU from
wait mode, such as when the PLL is first enabled and waiting for LOCK or LOCK is lost.
5.7.2 Stop Mode
If the OSCSTOPENB bit in the CONFIG register is cleared (default), then the STOP instruction disables
the CGM (oscillator and phase locked loop) and holds low all CGM outputs (CGMXCLK, CGMOUT, and
CGMINT).
If the STOP instruction is executed with the VCO clock, CGMVCLK, divided by two driving CGMOUT, the
PLL automatically clears the BCS bit in the PLL control register (PCTL), thereby selecting the crystal
clock, CGMXCLK, divided by two as the source of CGMOUT. When the MCU recovers from STOP, the
crystal clock divided by two drives CGMOUT and BCS remains clear.
If the OSCSTOPENB bit in the CONFIG register is set, then the phase locked loop is shut off but the
oscillator will continue to operate in stop mode.
5.7.3 CGM During Break Interrupts
The system integration module (SIM) controls whether status bits in other modules can be cleared during
the break state. The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear
status bits during the break state. (See 14.7.3 SIM Break Flag Control Register.)
To allow software to clear status bits during a break interrupt, write a logic 1 to the BCFE bit. If a status
bit is cleared during the break state, it remains cleared when the MCU exits the break state.
To protect the PLLF bit during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its
default state), software can read and write the PLL control register during the break state without affecting
the PLLF bit.
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
77
Clock Generator Module (CGM)
5.8 Acquisition/Lock Time Specifications
The acquisition and lock times of the PLL are, in many applications, the most critical PLL design
parameters. Proper design and use of the PLL ensures the highest stability and lowest acquisition/lock
times.
5.8.1 Acquisition/Lock Time Definitions
Typical control systems refer to the acquisition time or lock time as the reaction time, within specified
tolerances, of the system to a step input. In a PLL, the step input occurs when the PLL is turned on or
when it suffers a noise hit. The tolerance is usually specified as a percent of the step input or when the
output settles to the desired value plus or minus a percent of the frequency change. Therefore, the
reaction time is constant in this definition, regardless of the size of the step input. For example, consider
a system with a 5 percent acquisition time tolerance. If a command instructs the system to change from
0 Hz to 1 MHz, the acquisition time is the time taken for the frequency to reach 1 MHz ±50 kHz.
Fifty kHz = 5% of the 1-MHz step input. If the system is operating at 1 MHz and suffers a –100-kHz noise
hit, the acquisition time is the time taken to return from 900 kHz to 1 MHz ±5 kHz. Five kHz = 5% of the
100-kHz step input.
Other systems refer to acquisition and lock times as the time the system takes to reduce the error
between the actual output and the desired output to within specified tolerances. Therefore, the acquisition
or lock time varies according to the original error in the output. Minor errors may not even be registered.
Typical PLL applications prefer to use this definition because the system requires the output frequency to
be within a certain tolerance of the desired frequency regardless of the size of the initial error.
5.8.2 Parametric Influences on Reaction Time
Acquisition and lock times are designed to be as short as possible while still providing the highest possible
stability. These reaction times are not constant, however. Many factors directly and indirectly affect the
acquisition time.
The most critical parameter which affects the reaction times of the PLL is the reference frequency, fRDV.
This frequency is the input to the phase detector and controls how often the PLL makes corrections. For
stability, the corrections must be small compared to the desired frequency, so several corrections are
required to reduce the frequency error. Therefore, the slower the reference the longer it takes to make
these corrections. This parameter is under user control via the choice of crystal frequency fXCLK and the
R value programmed in the reference divider. (See 5.3.3 PLL Circuits, 5.3.6 Programming the PLL, and
5.5.6 PLL Reference Divider Select Register.)
Another critical parameter is the external filter network. The PLL modifies the voltage on the VCO by
adding or subtracting charge from capacitors in this network. Therefore, the rate at which the voltage
changes for a given frequency error (thus change in charge) is proportional to the capacitance. The size
of the capacitor also is related to the stability of the PLL. If the capacitor is too small, the PLL cannot make
small enough adjustments to the voltage and the system cannot lock. If the capacitor is too large, the PLL
may not be able to adjust the voltage in a reasonable time. (See 5.8.3 Choosing a Filter.)
Also important is the operating voltage potential applied to VDDA. The power supply potential alters the
characteristics of the PLL. A fixed value is best. Variable supplies, such as batteries, are acceptable if
they vary within a known range at very slow speeds. Noise on the power supply is not acceptable,
because it causes small frequency errors which continually change the acquisition time of the PLL.
MC68HC908GP32 Data Sheet, Rev. 10
78
Freescale Semiconductor
Acquisition/Lock Time Specifications
Temperature and processing also can affect acquisition time because the electrical characteristics of the
PLL change. The part operates as specified as long as these influences stay within the specified limits.
External factors, however, can cause drastic changes in the operation of the PLL. These factors include
noise injected into the PLL through the filter capacitor, filter capacitor leakage, stray impedances on the
circuit board, and even humidity or circuit board contamination.
5.8.3 Choosing a Filter
As described in 5.8.2 Parametric Influences on Reaction Time, the external filter network is critical to the
stability and reaction time of the PLL. The PLL is also dependent on reference frequency and supply
voltage.
Either of the filter networks in Figure 5-10 is recommended when using a 32.768kHz reference crystal.
Figure 5-10 (a) is used for applications requiring better stability. Figure 5-10 (b) is used in low-cost
applications where stability is not critical.
CGMXFC
CGMXFC
10 kΩ
0.01 µF
0.47 µF
0.033 µF
VSSA
(a)
VSSA
(b)
Figure 5-10. PLL Filter
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
79
Clock Generator Module (CGM)
MC68HC908GP32 Data Sheet, Rev. 10
80
Freescale Semiconductor
Chapter 6
Configuration Register (CONFIG)
6.1 Introduction
This section describes the configuration registers, CONFIG1 and CONFIG2. The configuration registers
enable or disable these options:
• Stop mode recovery time (32 CGMXCLK cycles or 4096 CGMXCLK cycles)
• COP timeout period (262,128 or 8176 CGMXCLK cycles)
• STOP instruction
• Computer operating properly module (COP)
• Low-voltage inhibit (LVI) module control and voltage trip point selection
• Enable/disable the oscillator (OSC) during stop mode
6.2 Functional Description
The configuration registers are used in the initialization of various options. The configuration registers can
be written once after each reset. All of the configuration register bits are cleared during reset. Since the
various options affect the operation of the MCU, it is recommended that these registers be written
immediately after reset. The configuration registers are located at $001E and $001F. The configuration
register may be read at anytime.
NOTE
On a FLASH device, the options except LVI5OR3 are one-time writeable
by the user after each reset. The LVI5OR3 bit is one-time writeable by the
user only after each POR (power-on reset). The CONFIG registers are not
in the FLASH memory but are special registers containing one-time
writeable latches after each reset. Upon a reset, the CONFIG registers
default to predetermined settings as shown in Figure 6-1 and Figure 6-2.
Address:
Read:
$001E
Bit 7
6
5
4
3
2
0
0
0
0
0
0
0
0
0
0
0
0
Write:
Reset:
1
Bit 0
OSCSTOPENB SCIBDSRC
0
0
= Unimplemented
Figure 6-1. Configuration Register 2 (CONFIG2)
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
81
Configuration Register (CONFIG)
Address:
Read:
Write:
Reset:
$001F
Bit 7
6
5
4
3
2
1
Bit 0
COPRS
LVISTOP
LVIRSTD
LVIPWRD
LVI5OR3
SSREC
STOP
COPD
0
0
0
0
See Note
0
0
0
Note: LVI5OR3 bit is only reset via POR (power-on reset)
Figure 6-2. Configuration Register 1 (CONFIG1)
OSCSTOPENB— Oscillator Stop Mode Enable Bar Bit
OSCSTOPENB enables the oscillator to continue operating during stop mode. Setting the
OSCSTOPENB bit allows the oscillator to operate continuously even during stop mode. This is useful
for driving the timebase module to allow it to generate periodic wakeup while in stop mode. (See 3.5
Clock Generator Module (CGM) subsection 3.5.2 Stop Mode.)
1 = Oscillator enabled to operate during stop mode
0 = Oscillator disabled during stop mode (default)
SCIBDSRC — SCI Baud Rate Clock Source Bit
SCIBDSRC controls the clock source used for the SCI. The setting of this bit affects the frequency at
which the SCI operates.
1 = Internal data bus clock used as clock source for SCI
0 = External oscillator used as clock source for SCI
COPRS — COP Rate Select Bit
COPRS selects the COP timeout period. Reset clears COPRS. (See Chapter 7 Computer Operating
Properly (COP).)
1 = COP timeout period = 8176 CGMXCLK cycles
0 = COP timeout period = 262,128 CGMXCLK cycles
LVISTOP — LVI Enable in Stop Mode Bit
When the LVIPWRD bit is clear, setting the LVISTOP bit enables the LVI to operate during stop mode.
Reset clears LVISTOP. (See
3.5.2 Stop Mode.)
1 = LVI enabled during stop mode
0 = LVI disabled during stop mode
LVIRSTD — LVI Reset Disable Bit
LVIRSTD disables the reset signal from the LVI module. (See Chapter 11 Low-Voltage Inhibit (LVI).)
1 = LVI module resets disabled
0 = LVI module resets enabled
LVIPWRD — LVI Power Disable Bit
LVIPWRD disables the LVI module. (See Chapter 11 Low-Voltage Inhibit (LVI).)
1 = LVI module power disabled
0 = LVI module power enabled
MC68HC908GP32 Data Sheet, Rev. 10
82
Freescale Semiconductor
Functional Description
LVI5OR3 — LVI 5-V or 3-V Operating Mode Bit
LVI5OR3 selects the voltage operating mode of the LVI module. (See Chapter 11 Low-Voltage Inhibit
(LVI).) The voltage mode selected for the LVI should match the operating VDD. See Chapter 19
Electrical Specifications for the LVI’s voltage trip points for each of the modes.
1 = LVI operates in 5-V mode.
0 = LVI operates in 3-V mode.
SSREC — Short Stop Recovery Bit
SSREC enables the CPU to exit stop mode with a delay of 32 CGMXCLK cycles instead of a
4096-CGMXCLK cycle delay.
1 = Stop mode recovery after 32 CGMXCLK cycles
0 = Stop mode recovery after 4096 CGMXCLKC cycles
NOTE
Exiting stop mode by pulling reset will result in the long stop recovery.
If using an external crystal oscillator, do not set the SSREC bit.
NOTE
When the LVISTOP is enabled, the system stabilization time for power on
reset and long stop recovery (both 4096 CGMXCLK cycles) gives a delay
longer than the enable time for the LVI. There is no period where the MCU
is not protected from a low power condition. However, when using the short
stop recovery configuration option, the 32-CGMXCLK delay is less than the
LVI’s turn-on time and there exists a period in startup where the LVI is not
protecting the MCU.
STOP — STOP Instruction Enable Bit
STOP enables the STOP instruction.
1 = STOP instruction enabled
0 = STOP instruction treated as illegal opcode
COPD — COP Disable Bit
COPD disables the COP module. (See Chapter 7 Computer Operating Properly (COP).)
1 = COP module disabled
0 = COP module enabled
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
83
Configuration Register (CONFIG)
MC68HC908GP32 Data Sheet, Rev. 10
84
Freescale Semiconductor
Chapter 7
Computer Operating Properly (COP)
7.1 Introduction
The computer operating properly (COP) module contains a free-running counter that generates a reset if
allowed to overflow. The COP module helps software recover from runaway code. Prevent a COP reset
by clearing the COP counter periodically. The COP module can be disabled through the COPD bit in the
CONFIG register.
7.2 Functional Description
Figure 7-1 shows the structure of the COP module.
RESET STATUS REGISTER
COP TIMEOUT
CLEAR STAGES 5–12
STOP INSTRUCTION
INTERNAL RESET SOURCES
RESET VECTOR FETCH
RESET CIRCUIT
12-BIT COP PRESCALER
CLEAR ALL STAGES
CGMXCLK
COPCTL WRITE
COP CLOCK
COP MODULE
6-BIT COP COUNTER
COPEN (FROM SIM)
COP DISABLE
(FROM CONFIG)
RESET
COPCTL WRITE
CLEAR
COP COUNTER
COP RATE SEL
(FROM CONFIG)
Figure 7-1. COP Block Diagram
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
85
Computer Operating Properly (COP)
The COP counter is a free-running 6-bit counter preceded by a 12-bit prescaler counter. If not cleared by
software, the COP counter overflows and generates an asynchronous reset after 262,128 or 8176
CGMXCLK cycles, depending on the state of the COP rate select bit, COPRS, in the configuration
register. With a 8176 CGMXCLK cycle overflow option, a 32.768-kHz crystal gives a COP timeout period
of 250 ms. Writing any value to location $FFFF before an overflow occurs prevents a COP reset by
clearing the COP counter and stages 12 through 5 of the prescaler.
NOTE
Service the COP immediately after reset and before entering or after exiting
stop mode to guarantee the maximum time before the first COP counter
overflow.
A COP reset pulls the RST pin low for 32 CGMXCLK cycles and sets the COP bit in the reset status
register (RSR).
In monitor mode, the COP is disabled if the RST pin or the IRQ is held at VTST. During the break state,
VTST on the RST pin disables the COP.
NOTE
Place COP clearing instructions in the main program and not in an interrupt
subroutine. Such an interrupt subroutine could keep the COP from
generating a reset even while the main program is not working properly.
7.3 I/O Signals
The following paragraphs describe the signals shown in Figure 7-1.
7.3.1 CGMXCLK
CGMXCLK is the crystal oscillator output signal. CGMXCLK frequency is equal to the crystal frequency.
7.3.2 STOP Instruction
The STOP instruction clears the COP prescaler.
7.3.3 COPCTL Write
Writing any value to the COP control register (COPCTL) (see 7.4 COP Control Register) clears the COP
counter and clears bits 12 through 5 of the prescaler. Reading the COP control register returns the low
byte of the reset vector.
7.3.4 Power-On Reset
The power-on reset (POR) circuit clears the COP prescaler 4096 CGMXCLK cycles after power-up.
7.3.5 Internal Reset
An internal reset clears the COP prescaler and the COP counter.
7.3.6 Reset Vector Fetch
A reset vector fetch occurs when the vector address appears on the data bus. A reset vector fetch clears
the COP prescaler.
MC68HC908GP32 Data Sheet, Rev. 10
86
Freescale Semiconductor
COP Control Register
7.3.7 COPD (COP Disable)
The COPD signal reflects the state of the COP disable bit (COPD) in the configuration register. (See
Chapter 6 Configuration Register (CONFIG).)
7.3.8 COPRS (COP Rate Select)
The COPRS signal reflects the state of the COP rate select bit (COPRS) in the configuration register.
(See Chapter 6 Configuration Register (CONFIG).)
7.4 COP Control Register
The COP control register is located at address $FFFF and overlaps the reset vector. Writing any value to
$FFFF clears the COP counter and starts a new timeout period. Reading location $FFFF returns the low
byte of the reset vector.
Address: $FFFF
Bit 7
6
5
4
3
Read:
Low byte of reset vector
Write:
Clear COP counter
Reset:
Unaffected by reset
2
1
Bit 0
Figure 7-2. COP Control Register (COPCTL)
7.5 Interrupts
The COP does not generate CPU interrupt requests.
7.6 Monitor Mode
When monitor mode is entered with VTST on the IRQ pin, the COP is disabled as long as VTST remains
on the IRQ pin or the RST pin. When monitor mode is entered by having blank reset vectors and not
having VTST on the IRQ pin, the COP is automatically disabled until a POR occurs.
7.7 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption standby modes.
7.7.1 Wait Mode
The COP remains active during wait mode. To prevent a COP reset during wait mode, periodically clear
the COP counter in a CPU interrupt routine.
7.7.2 Stop Mode
Stop mode turns off the CGMXCLK input to the COP and clears the COP prescaler. Service the COP
immediately before entering or after exiting stop mode to ensure a full COP timeout period after entering
or exiting stop mode.
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
87
Computer Operating Properly (COP)
To prevent inadvertently turning off the COP with a STOP instruction, a configuration option is available
that disables the STOP instruction. When the STOP bit in the configuration register has the STOP
instruction is disabled, execution of a STOP instruction results in an illegal opcode reset.
7.8 COP Module During Break Mode
The COP is disabled during a break interrupt when VTST is present on the RST pin.
MC68HC908GP32 Data Sheet, Rev. 10
88
Freescale Semiconductor
Chapter 8
Central Processor Unit (CPU)
8.1 Introduction
The M68HC08 CPU (central processor unit) is an enhanced and fully object-code-compatible version of
the M68HC05 CPU. The CPU08 Reference Manual (document order number CPU08RM/AD) contains a
description of the CPU instruction set, addressing modes, and architecture.
8.2 Features
Features of the CPU include:
• Object code fully upward-compatible with M68HC05 Family
• 16-bit stack pointer with stack manipulation instructions
• 16-bit index register with x-register manipulation instructions
• 8-MHz CPU internal bus frequency
• 64-Kbyte program/data memory space
• 16 addressing modes
• Memory-to-memory data moves without using accumulator
• Fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions
• Enhanced binary-coded decimal (BCD) data handling
• Modular architecture with expandable internal bus definition for extension of addressing range
beyond 64 Kbytes
• Low-power stop and wait modes
8.3 CPU Registers
Figure 8-1 shows the five CPU registers. CPU registers are not part of the memory map.
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
89
Central Processor Unit (CPU)
7
0
ACCUMULATOR (A)
15
0
H
X
INDEX REGISTER (H:X)
0
15
STACK POINTER (SP)
0
15
PROGRAM COUNTER (PC)
7
0
V 1 1 H I N Z C
CONDITION CODE REGISTER (CCR)
CARRY/BORROW FLAG
ZERO FLAG
NEGATIVE FLAG
INTERRUPT MASK
HALF-CARRY FLAG
TWO’S COMPLEMENT OVERFLOW FLAG
Figure 8-1. CPU Registers
8.3.1 Accumulator
The accumulator is a general-purpose 8-bit register. The CPU uses the accumulator to hold operands
and the results of arithmetic/logic operations.
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
Unaffected by reset
Figure 8-2. Accumulator (A)
8.3.2 Index Register
The 16-bit index register allows indexed addressing of a 64-Kbyte memory space. H is the upper byte of
the index register, and X is the lower byte. H:X is the concatenated 16-bit index register.
In the indexed addressing modes, the CPU uses the contents of the index register to determine the
conditional address of the operand.
The index register can serve also as a temporary data storage location.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Bit
0
0
0
0
0
0
0
0
0
X
X
X
X
X
X
X
X
Read:
Write:
Reset:
X = Indeterminate
Figure 8-3. Index Register (H:X)
MC68HC908GP32 Data Sheet, Rev. 10
90
Freescale Semiconductor
CPU Registers
8.3.3 Stack Pointer
The stack pointer is a 16-bit register that contains the address of the next location on the stack. During a
reset, the stack pointer is preset to $00FF. The reset stack pointer (RSP) instruction sets the least
significant byte to $FF and does not affect the most significant byte. The stack pointer decrements as data
is pushed onto the stack and increments as data is pulled from the stack.
In the stack pointer 8-bit offset and 16-bit offset addressing modes, the stack pointer can function as an
index register to access data on the stack. The CPU uses the contents of the stack pointer to determine
the conditional address of the operand.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Bit
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Read:
Write:
Reset:
Figure 8-4. Stack Pointer (SP)
NOTE
The location of the stack is arbitrary and may be relocated anywhere in
random-access memory (RAM). Moving the SP out of page 0 ($0000 to
$00FF) frees direct address (page 0) space. For correct operation, the
stack pointer must point only to RAM locations.
8.3.4 Program Counter
The program counter is a 16-bit register that contains the address of the next instruction or operand to be
fetched.
Normally, the program counter automatically increments to the next sequential memory location every
time an instruction or operand is fetched. Jump, branch, and interrupt operations load the program
counter with an address other than that of the next sequential location.
During reset, the program counter is loaded with the reset vector address located at $FFFE and $FFFF.
The vector address is the address of the first instruction to be executed after exiting the reset state.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Bit
0
Read:
Write:
Reset:
Loaded with vector from $FFFE and $FFFF
Figure 8-5. Program Counter (PC)
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
91
Central Processor Unit (CPU)
8.3.5 Condition Code Register
The 8-bit condition code register contains the interrupt mask and five flags that indicate the results of the
instruction just executed. Bits 6 and 5 are set permanently to 1. The following paragraphs describe the
functions of the condition code register.
Read:
Write:
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
V
1
1
H
I
N
Z
C
X
1
1
X
1
X
X
X
X = Indeterminate
Figure 8-6. Condition Code Register (CCR)
V — Overflow Flag
The CPU sets the overflow flag when a two's complement overflow occurs. The signed branch
instructions BGT, BGE, BLE, and BLT use the overflow flag.
1 = Overflow
0 = No overflow
H — Half-Carry Flag
The CPU sets the half-carry flag when a carry occurs between accumulator bits 3 and 4 during an
add-without-carry (ADD) or add-with-carry (ADC) operation. The half-carry flag is required for
binary-coded decimal (BCD) arithmetic operations. The DAA instruction uses the states of the H and
C flags to determine the appropriate correction factor.
1 = Carry between bits 3 and 4
0 = No carry between bits 3 and 4
I — Interrupt Mask
When the interrupt mask is set, all maskable CPU interrupts are disabled. CPU interrupts are enabled
when the interrupt mask is cleared. When a CPU interrupt occurs, the interrupt mask is set
automatically after the CPU registers are saved on the stack, but before the interrupt vector is fetched.
1 = Interrupts disabled
0 = Interrupts enabled
NOTE
To maintain M6805 Family compatibility, the upper byte of the index
register (H) is not stacked automatically. If the interrupt service routine
modifies H, then the user must stack and unstack H using the PSHH and
PULH instructions.
After the I bit is cleared, the highest-priority interrupt request is serviced first.
A return-from-interrupt (RTI) instruction pulls the CPU registers from the stack and restores the
interrupt mask from the stack. After any reset, the interrupt mask is set and can be cleared only by the
clear interrupt mask software instruction (CLI).
N — Negative Flag
The CPU sets the negative flag when an arithmetic operation, logic operation, or data manipulation
produces a negative result, setting bit 7 of the result.
1 = Negative result
0 = Non-negative result
MC68HC908GP32 Data Sheet, Rev. 10
92
Freescale Semiconductor
Arithmetic/Logic Unit (ALU)
Z — Zero Flag
The CPU sets the zero flag when an arithmetic operation, logic operation, or data manipulation
produces a result of $00.
1 = Zero result
0 = Non-zero result
C — Carry/Borrow Flag
The CPU sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the
accumulator or when a subtraction operation requires a borrow. Some instructions — such as bit test
and branch, shift, and rotate — also clear or set the carry/borrow flag.
1 = Carry out of bit 7
0 = No carry out of bit 7
8.4 Arithmetic/Logic Unit (ALU)
The ALU performs the arithmetic and logic operations defined by the instruction set.
Refer to the CPU08 Reference Manual (document order number CPU08RM/AD) for a description of the
instructions and addressing modes and more detail about the architecture of the CPU.
8.5 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption standby modes.
8.5.1 Wait Mode
The WAIT instruction:
• Clears the interrupt mask (I bit) in the condition code register, enabling interrupts. After exit from
wait mode by interrupt, the I bit remains clear. After exit by reset, the I bit is set.
• Disables the CPU clock
8.5.2 Stop Mode
The STOP instruction:
• Clears the interrupt mask (I bit) in the condition code register, enabling external interrupts. After
exit from stop mode by external interrupt, the I bit remains clear. After exit by reset, the I bit is set.
• Disables the CPU clock
After exiting stop mode, the CPU clock begins running after the oscillator stabilization delay.
8.6 CPU During Break Interrupts
If a break module is present on the MCU, the CPU starts a break interrupt by:
• Loading the instruction register with the SWI instruction
• Loading the program counter with $FFFC:$FFFD or with $FEFC:$FEFD in monitor mode
The break interrupt begins after completion of the CPU instruction in progress. If the break address
register match occurs on the last cycle of a CPU instruction, the break interrupt begins immediately.
A return-from-interrupt instruction (RTI) in the break routine ends the break interrupt and returns the MCU
to normal operation if the break interrupt has been deasserted.
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
93
Central Processor Unit (CPU)
8.7 Instruction Set Summary
Table 8-1 provides a summary of the M68HC08 instruction set.
ADC #opr
ADC opr
ADC opr
ADC opr,X
ADC opr,X
ADC ,X
ADC opr,SP
ADC opr,SP
ADD #opr
ADD opr
ADD opr
ADD opr,X
ADD opr,X
ADD ,X
ADD opr,SP
ADD opr,SP
V H I N Z C
A ← (A) + (M) + (C)
Add with Carry
A ← (A) + (M)
Add without Carry
IMM
DIR
EXT
↕ ↕ – ↕ ↕ ↕ IX2
IX1
IX
SP1
SP2
IMM
DIR
EXT
↕ ↕ – ↕ ↕ ↕ IX2
IX1
IX
SP1
SP2
A9
B9
C9
D9
E9
F9
9EE9
9ED9
AB
BB
CB
DB
EB
FB
9EEB
9EDB
ii
dd
hh ll
ee ff
ff
Cycles
Effect
on CCR
Description
Operand
Operation
Opcode
Source
Form
Address
Mode
Table 8-1. Instruction Set Summary (Sheet 1 of 6)
ff
ee ff
2
3
4
4
3
2
4
5
2
3
4
4
3
2
4
5
ff
ee ff
ii
dd
hh ll
ee ff
ff
AIS #opr
Add Immediate Value (Signed) to SP
SP ← (SP) + (16 « M)
– – – – – – IMM
A7
ii
2
AIX #opr
Add Immediate Value (Signed) to H:X
H:X ← (H:X) + (16 « M)
– – – – – – IMM
AF
ii
2
ii
dd
hh ll
ee ff
ff
AND #opr
AND opr
AND opr
AND opr,X
AND opr,X
AND ,X
AND opr,SP
AND opr,SP
ASL opr
ASLA
ASLX
ASL opr,X
ASL ,X
ASL opr,SP
ASR opr
ASRA
ASRX
ASR opr,X
ASR opr,X
ASR opr,SP
BCC rel
A ← (A) & (M)
Logical AND
Arithmetic Shift Left
(Same as LSL)
C
0
b7
C
b7
rr
3
– – – – – – REL
92
rr
3
– – – – – – REL
– – – – – – REL
– – – – – – REL
28
29
22
rr
rr
rr
3
3
3
– – – – – –
Mn ← 0
– – – – – –
BCS rel
BEQ rel
Branch if Carry Bit Set (Same as BLO)
PC ← (PC) + 2 + rel ? (C) = 1
Branch if Equal
PC ← (PC) + 2 + rel ? (Z) = 1
Branch if Greater Than or Equal To
PC ← (PC) + 2 + rel ? (N ⊕ V) = 0
(Signed Operands)
Branch if Greater Than (Signed
PC ← (PC) + 2 + rel ? (Z) | (N ⊕ V) = 0
Operands)
Branch if Half Carry Bit Clear
PC ← (PC) + 2 + rel ? (H) = 0
Branch if Half Carry Bit Set
PC ← (PC) + 2 + rel ? (H) = 1
Branch if Higher
PC ← (PC) + 2 + rel ? (C) | (Z) = 0
BHCC rel
BHCS rel
BHI rel
90
↕ – – ↕ ↕ ↕
PC ← (PC) + 2 + rel ? (C) = 0
Clear Bit n in M
BGT opr
– – – – – – REL
↕ – – ↕ ↕ ↕
b0
BCLR n, opr
BGE opr
ff
rr
dd
dd
dd
dd
dd
dd
dd
dd
rr
rr
2
3
4
4
3
2
4
5
4
1
1
4
3
5
4
1
1
4
3
5
3
4
4
4
4
4
4
4
4
3
3
b0
Arithmetic Shift Right
Branch if Carry Bit Clear
A4
B4
C4
D4
E4
F4
9EE4
9ED4
38
48
58
68
78
9E68
37
47
57
67
77
9E67
24
11
13
15
17
19
1B
1D
1F
25
27
0 – – ↕ ↕ –
– – – – – –
– – – – – –
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
DIR
INH
INH
IX1
IX
SP1
DIR
INH
INH
IX1
IX
SP1
REL
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
REL
REL
ff
ee ff
dd
ff
ff
dd
ff
MC68HC908GP32 Data Sheet, Rev. 10
94
Freescale Semiconductor
Instruction Set Summary
BHS rel
BIH rel
BIL rel
BIT #opr
BIT opr
BIT opr
BIT opr,X
BIT opr,X
BIT ,X
BIT opr,SP
BIT opr,SP
Branch if Higher or Same
(Same as BCC)
Branch if IRQ Pin High
Branch if IRQ Pin Low
Bit Test
PC ← (PC) + 2 + rel ? (C) = 0
– – – – – – REL
24
PC ← (PC) + 2 + rel ? IRQ = 1
PC ← (PC) + 2 + rel ? IRQ = 0
– – – – – – REL
– – – – – – REL
IMM
DIR
EXT
0 – – ↕ ↕ – IX2
IX1
IX
SP1
SP2
2F
2E
A5
B5
C5
D5
E5
F5
9EE5
9ED5
(A) & (M)
Branch if Less Than or Equal To
(Signed Operands)
BLO rel
BLS rel
Branch if Lower (Same as BCS)
Branch if Lower or Same
PC ← (PC) + 2 + rel ? (C) = 1
PC ← (PC) + 2 + rel ? (C) | (Z) = 1
BLT opr
Branch if Less Than (Signed Operands)
PC ← (PC) + 2 + rel ? (N ⊕ V) =1
BMC rel
BMI rel
BMS rel
BNE rel
BPL rel
BRA rel
Branch if Interrupt Mask Clear
Branch if Minus
Branch if Interrupt Mask Set
Branch if Not Equal
Branch if Plus
Branch Always
BRCLR n,opr,rel Branch if Bit n in M Clear
Branch Never
BRSET n,opr,rel Branch if Bit n in M Set
BSET n,opr
Set Bit n in M
BSR rel
Branch to Subroutine
CBEQ opr,rel
CBEQA #opr,rel
CBEQX #opr,rel Compare and Branch if Equal
CBEQ opr,X+,rel
CBEQ X+,rel
CBEQ opr,SP,rel
CLC
Clear Carry Bit
CLI
Clear Interrupt Mask
PC ← (PC) + 2 + rel ? (Z) | (N ⊕ V) = 1 – – – – – – REL
PC ← (PC) + 2 + rel ? (I) = 0
PC ← (PC) + 2 + rel ? (N) = 1
PC ← (PC) + 2 + rel ? (I) = 1
PC ← (PC) + 2 + rel ? (Z) = 0
PC ← (PC) + 2 + rel ? (N) = 0
PC ← (PC) + 2 + rel
– – – – – – REL
– – – – – – REL
rr
3
rr
rr
ii
dd
hh ll
ee ff
ff
ff
ee ff
3
3
2
3
4
4
3
2
4
5
93
rr
3
25
23
rr
rr
3
3
– – – – – – REL
91
rr
3
–
–
–
–
–
–
2C
2B
2D
26
2A
20
01
03
05
07
09
0B
0D
0F
21
00
02
04
06
08
0A
0C
0E
10
12
14
16
18
1A
1C
1E
rr
rr
rr
rr
rr
rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd
dd
dd
dd
dd
dd
dd
dd
3
3
3
3
3
3
5
5
5
5
5
5
5
5
3
5
5
5
5
5
5
5
5
4
4
4
4
4
4
4
4
– – – – – – REL
AD
rr
4
DIR
IMM
– – – – – – IMM
IX1+
IX+
SP1
– – – – – 0 INH
– – 0 – – – INH
31
41
51
61
71
9E61
98
9A
dd rr
ii rr
ii rr
ff rr
rr
ff rr
5
4
4
5
4
6
1
2
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
PC ← (PC) + 3 + rel ? (Mn) = 0
– – – – – ↕
PC ← (PC) + 2
– – – – – –
PC ← (PC) + 3 + rel ? (Mn) = 1
– – – – – ↕
Mn ← 1
– – – – – –
PC ← (PC) + 2; push (PCL)
SP ← (SP) – 1; push (PCH)
SP ← (SP) – 1
PC ← (PC) + rel
PC ← (PC) + 3 + rel ? (A) – (M) = $00
PC ← (PC) + 3 + rel ? (A) – (M) = $00
PC ← (PC) + 3 + rel ? (X) – (M) = $00
PC ← (PC) + 3 + rel ? (A) – (M) = $00
PC ← (PC) + 2 + rel ? (A) – (M) = $00
PC ← (PC) + 4 + rel ? (A) – (M) = $00
C←0
I←0
Cycles
V H I N Z C
BLE opr
BRN rel
Effect
on CCR
Description
Operand
Operation
Opcode
Source
Form
Address
Mode
Table 8-1. Instruction Set Summary (Sheet 2 of 6)
REL
REL
REL
REL
REL
REL
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
REL
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
95
Central Processor Unit (CPU)
CLR opr
CLRA
CLRX
CLRH
CLR opr,X
CLR ,X
CLR opr,SP
CMP #opr
CMP opr
CMP opr
CMP opr,X
CMP opr,X
CMP ,X
CMP opr,SP
CMP opr,SP
COM opr
COMA
COMX
COM opr,X
COM ,X
COM opr,SP
V H I N Z C
M ← $00
A ← $00
X ← $00
H ← $00
M ← $00
M ← $00
M ← $00
Clear
Compare A with M
(A) – (M)
Complement (One’s Complement)
CPHX #opr
CPHX opr
CPX #opr
CPX opr
CPX opr
CPX ,X
CPX opr,X
CPX opr,X
CPX opr,SP
CPX opr,SP
Compare H:X with M
DAA
Decimal Adjust A
Compare X with M
EOR #opr
EOR opr
EOR opr
EOR opr,X
EOR opr,X
EOR ,X
EOR opr,SP
EOR opr,SP
INC opr
INCA
INCX
INC opr,X
INC ,X
INC opr,SP
Divide
Exclusive OR M with A
Increment
M ← (M) = $FF – (M)
A ← (A) = $FF – (M)
X ← (X) = $FF – (M)
M ← (M) = $FF – (M)
M ← (M) = $FF – (M)
M ← (M) = $FF – (M)
(H:X) – (M:M + 1)
(X) – (M)
(A)10
DBNZ opr,rel
DBNZA rel
DBNZX rel
Decrement and Branch if Not Zero
DBNZ opr,X,rel
DBNZ X,rel
DBNZ opr,SP,rel
DEC opr
DECA
DECX
Decrement
DEC opr,X
DEC ,X
DEC opr,SP
DIV
Effect
on CCR
DIR
INH
INH
0 – – 0 1 – INH
IX1
IX
SP1
IMM
DIR
EXT
↕ – – ↕ ↕ ↕ IX2
IX1
IX
SP1
SP2
3F
4F
5F
8C
6F
7F
9E6F
A1
B1
C1
D1
E1
F1
9EE1
9ED1
DIR
INH
0 – – ↕ ↕ 1 INH
IX1
IX
SP1
↕ – – ↕ ↕ ↕ IMM
DIR
IMM
DIR
EXT
↕ – – ↕ ↕ ↕ IX2
IX1
IX
SP1
SP2
33
43
53
63
73
9E63
65
75
A3
B3
C3
D3
E3
F3
9EE3
9ED3
U – – ↕ ↕ ↕ INH
72
A ← (A) – 1 or M ← (M) – 1 or X ← (X) – 1
PC ← (PC) + 3 + rel ? (result) ≠ 0
PC ← (PC) + 2 + rel ? (result) ≠ 0
PC ← (PC) + 2 + rel ? (result) ≠ 0
– – – – – –
PC ← (PC) + 3 + rel ? (result) ≠ 0
PC ← (PC) + 2 + rel ? (result) ≠ 0
PC ← (PC) + 4 + rel ? (result) ≠ 0
M ← (M) – 1
A ← (A) – 1
X ← (X) – 1
↕ – – ↕ ↕ –
M ← (M) – 1
M ← (M) – 1
M ← (M) – 1
A ← (H:A)/(X)
– – – – ↕ ↕
H ← Remainder
A ← (A ⊕ M)
M ← (M) + 1
A ← (A) + 1
X ← (X) + 1
M ← (M) + 1
M ← (M) + 1
M ← (M) + 1
DIR
INH
INH
IX1
IX
SP1
DIR
INH
INH
IX1
IX
SP1
3B
4B
5B
6B
7B
9E6B
3A
4A
5A
6A
7A
9E6A
INH
52
IMM
DIR
EXT
0 – – ↕ ↕ – IX2
IX1
IX
SP1
SP2
DIR
INH
↕ – – ↕ ↕ – INH
IX1
IX
SP1
A8
B8
C8
D8
E8
F8
9EE8
9ED8
3C
4C
5C
6C
7C
9E6C
dd
ff
ff
ii
dd
hh ll
ee ff
ff
ff
ee ff
dd
ff
ff
ii ii+1
dd
ii
dd
hh ll
ee ff
ff
ff
ee ff
Cycles
Description
Operand
Operation
Opcode
Source
Form
Address
Mode
Table 8-1. Instruction Set Summary (Sheet 3 of 6)
3
1
1
1
3
2
4
2
3
4
4
3
2
4
5
4
1
1
4
3
5
3
4
2
3
4
4
3
2
4
5
2
dd rr
rr
rr
ff rr
rr
ff rr
dd
ff
ff
5
3
3
5
4
6
4
1
1
4
3
5
7
ii
dd
hh ll
ee ff
ff
ff
ee ff
dd
ff
ff
2
3
4
4
3
2
4
5
4
1
1
4
3
5
MC68HC908GP32 Data Sheet, Rev. 10
96
Freescale Semiconductor
Instruction Set Summary
JMP opr
JMP opr
JMP opr,X
JMP opr,X
JMP ,X
JSR opr
JSR opr
JSR opr,X
JSR opr,X
JSR ,X
LDA #opr
LDA opr
LDA opr
LDA opr,X
LDA opr,X
LDA ,X
LDA opr,SP
LDA opr,SP
LDHX #opr
LDHX opr
LDX #opr
LDX opr
LDX opr
LDX opr,X
LDX opr,X
LDX ,X
LDX opr,SP
LDX opr,SP
LSL opr
LSLA
LSLX
LSL opr,X
LSL ,X
LSL opr,SP
LSR opr
LSRA
LSRX
LSR opr,X
LSR ,X
LSR opr,SP
MOV opr,opr
MOV opr,X+
MOV #opr,opr
MOV X+,opr
MUL
NEG opr
NEGA
NEGX
NEG opr,X
NEG ,X
NEG opr,SP
NOP
NSA
ORA #opr
ORA opr
ORA opr
ORA opr,X
ORA opr,X
ORA ,X
ORA opr,SP
ORA opr,SP
PSHA
PSHH
PSHX
V H I N Z C
PC ← Jump Address
Jump
Jump to Subroutine
PC ← (PC) + n (n = 1, 2, or 3)
Push (PCL); SP ← (SP) – 1
Push (PCH); SP ← (SP) – 1
PC ← Unconditional Address
A ← (M)
Load A from M
Load H:X from M
Logical Shift Right
Unsigned multiply
Negate (Two’s Complement)
No Operation
Nibble Swap A
Inclusive OR A and M
Push A onto Stack
Push H onto Stack
Push X onto Stack
0 – – ↕ ↕ –
0 – – ↕ ↕ –
X ← (M)
0 – – ↕ ↕ –
C
0
b7
↕ – – ↕ ↕ ↕
b0
0
C
b7
Move
– – – – – –
H:X ← (M:M + 1)
Load X from M
Logical Shift Left
(Same as ASL)
– – – – – –
b0
(M)Destination ← (M)Source
H:X ← (H:X) + 1 (IX+D, DIX+)
X:A ← (X) × (A)
M ← –(M) = $00 – (M)
A ← –(A) = $00 – (A)
X ← –(X) = $00 – (X)
M ← –(M) = $00 – (M)
M ← –(M) = $00 – (M)
None
A ← (A[3:0]:A[7:4])
A ← (A) | (M)
Push (A); SP ← (SP) – 1
Push (H); SP ← (SP) – 1
Push (X); SP ← (SP) – 1
↕ – – 0 ↕ ↕
DIR
EXT
IX2
IX1
IX
DIR
EXT
IX2
IX1
IX
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
IMM
DIR
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
DIR
INH
INH
IX1
IX
SP1
DIR
INH
INH
IX1
IX
SP1
DD
0 – – ↕ ↕ – DIX+
IMD
IX+D
– 0 – – – 0 INH
DIR
INH
↕ – – ↕ ↕ ↕ INH
IX1
IX
SP1
– – – – – – INH
– – – – – – INH
IMM
DIR
EXT
0 – – ↕ ↕ – IX2
IX1
IX
SP1
SP2
– – – – – – INH
– – – – – – INH
– – – – – – INH
BC
CC
DC
EC
FC
BD
CD
DD
ED
FD
A6
B6
C6
D6
E6
F6
9EE6
9ED6
45
55
AE
BE
CE
DE
EE
FE
9EEE
9EDE
38
48
58
68
78
9E68
34
44
54
64
74
9E64
dd
hh ll
ee ff
ff
dd
hh ll
ee ff
ff
ii
dd
hh ll
ee ff
ff
ff
ee ff
ii jj
dd
ii
dd
hh ll
ee ff
ff
ff
ee ff
dd
ff
ff
dd
Cycles
Effect
on CCR
Description
Operand
Operation
Opcode
Source
Form
Address
Mode
Table 8-1. Instruction Set Summary (Sheet 4 of 6)
2
3
4
3
2
4
5
6
5
4
2
3
4
4
3
2
4
5
3
4
2
3
4
4
3
2
4
5
4
1
1
4
3
5
4
1
1
ff
4
3
ff
5
4E dd dd 5
5E dd
4
6E ii dd
4
7E dd
4
42
5
30 dd
4
40
1
50
1
60 ff
4
70
3
9E60 ff
5
9D
1
62
3
AA ii
2
BA dd
3
CA hh ll
4
DA ee ff
4
EA ff
3
FA
2
9EEA ff
4
9EDA ee ff
5
87
2
8B
2
89
2
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
97
Central Processor Unit (CPU)
Pull A from Stack
Pull H from Stack
Pull X from Stack
RTI
Return from Interrupt
RTS
Return from Subroutine
STOP
STX opr
STX opr
STX opr,X
STX opr,X
STX ,X
STX opr,SP
STX opr,SP
SUB #opr
SUB opr
SUB opr
SUB opr,X
SUB opr,X
SUB ,X
SUB opr,SP
SUB opr,SP
SP ← (SP + 1); Pull (A)
SP ← (SP + 1); Pull (H)
SP ← (SP + 1); Pull (X)
C
Rotate Left through Carry
b7
b0
C
Rotate Right through Carry
b7
SP ← $FF
SP ← (SP) + 1; Pull (CCR)
SP ← (SP) + 1; Pull (A)
SP ← (SP) + 1; Pull (X)
SP ← (SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCL)
SP ← SP + 1; Pull (PCH)
SP ← SP + 1; Pull (PCL)
Reset Stack Pointer
A ← (A) – (M) – (C)
Subtract with Carry
C←1
I←1
Set Carry Bit
Set Interrupt Mask
M ← (A)
Store A in M
Store H:X in M
Enable Interrupts, Stop Processing,
Refer to MCU Documentation
Store X in M
Subtract
b0
(M:M + 1) ← (H:X)
I ← 0; Stop Processing
M ← (X)
A ← (A) – (M)
Cycles
V H I N Z C
PULA
PULH
PULX
ROL opr
ROLA
ROLX
ROL opr,X
ROL ,X
ROL opr,SP
ROR opr
RORA
RORX
ROR opr,X
ROR ,X
ROR opr,SP
RSP
SBC #opr
SBC opr
SBC opr
SBC opr,X
SBC opr,X
SBC ,X
SBC opr,SP
SBC opr,SP
SEC
SEI
STA opr
STA opr
STA opr,X
STA opr,X
STA ,X
STA opr,SP
STA opr,SP
STHX opr
Effect
on CCR
Description
Operand
Operation
Opcode
Source
Form
Address
Mode
Table 8-1. Instruction Set Summary (Sheet 5 of 6)
– – – – – – INH
– – – – – – INH
– – – – – – INH
DIR
INH
↕ – – ↕ ↕ ↕ INH
IX1
IX
SP1
DIR
INH
↕ – – ↕ ↕ ↕ INH
IX1
IX
SP1
– – – – – – INH
86
8A
88
39
49
59
69
79
9E69
36
46
56
66
76
9E66
9C
↕ ↕ ↕ ↕ ↕ ↕ INH
80
7
– – – – – – INH
81
4
↕ – – ↕ ↕ ↕
– – – – – 1
– – 1 – – –
0 – – ↕ ↕ –
0 – – ↕ ↕ –
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
INH
INH
DIR
EXT
IX2
IX1
IX
SP1
SP2
DIR
A2
B2
C2
D2
E2
F2
9EE2
9ED2
99
9B
B7
C7
D7
E7
F7
9EE7
9ED7
35
– – 0 – – – INH
8E
DIR
EXT
IX2
0 – – ↕ ↕ – IX1
IX
SP1
SP2
IMM
DIR
EXT
↕ – – ↕ ↕ ↕ IX2
IX1
IX
SP1
SP2
BF
CF
DF
EF
FF
9EEF
9EDF
A0
B0
C0
D0
E0
F0
9EE0
9ED0
dd
ff
ff
dd
ff
ff
ii
dd
hh ll
ee ff
ff
ff
ee ff
dd
hh ll
ee ff
ff
ff
ee ff
dd
2
2
2
4
1
1
4
3
5
4
1
1
4
3
5
1
2
3
4
4
3
2
4
5
1
2
3
4
4
3
2
4
5
4
1
dd
hh ll
ee ff
ff
ff
ee ff
ii
dd
hh ll
ee ff
ff
ff
ee ff
3
4
4
3
2
4
5
2
3
4
4
3
2
4
5
MC68HC908GP32 Data Sheet, Rev. 10
98
Freescale Semiconductor
Opcode Map
V H I N Z C
SWI
Software Interrupt
TAP
TAX
TPA
TST opr
TSTA
TSTX
TST opr,X
TST ,X
TST opr,SP
TSX
TXA
TXS
Transfer A to CCR
Transfer A to X
Transfer CCR to A
PC ← (PC) + 1; Push (PCL)
SP ← (SP) – 1; Push (PCH)
SP ← (SP) – 1; Push (X)
SP ← (SP) – 1; Push (A)
SP ← (SP) – 1; Push (CCR)
SP ← (SP) – 1; I ← 1
PCH ← Interrupt Vector High Byte
PCL ← Interrupt Vector Low Byte
CCR ← (A)
X ← (A)
A ← (CCR)
Test for Negative or Zero
(A) – $00 or (X) – $00 or (M) – $00
WAIT
A
C
CCR
dd
dd rr
DD
DIR
DIX+
ee ff
EXT
ff
H
H
hh ll
I
ii
IMD
IMM
INH
IX
IX+
IX+D
IX1
IX1+
IX2
M
N
Effect
on CCR
– – 1 – – – INH
↕ ↕ ↕ ↕ ↕ ↕ INH
– – – – – – INH
– – – – – – INH
DIR
INH
0 – – ↕ ↕ – INH
IX1
IX
SP1
– – – – – – INH
– – – – – – INH
– – – – – – INH
83
84
97
85
3D dd
4D
5D
6D ff
7D
9E6D ff
95
9F
94
H:X ← (SP) + 1
A ← (X)
(SP) ← (H:X) – 1
I bit ← 0; Inhibit CPU clocking
Enable Interrupts; Wait for Interrupt
– – 0 – – – INH
8F
until interrupted
Accumulator
n
Any bit
Carry/borrow bit
opr Operand (one or two bytes)
Condition code register
PC Program counter
Direct address of operand
PCH Program counter high byte
Direct address of operand and relative offset of branch instruction
PCL Program counter low byte
Direct to direct addressing mode
REL Relative addressing mode
Direct addressing mode
rel
Relative program counter offset byte
Direct to indexed with post increment addressing mode
rr
Relative program counter offset byte
High and low bytes of offset in indexed, 16-bit offset addressing
SP1 Stack pointer, 8-bit offset addressing mode
Extended addressing mode
SP2 Stack pointer 16-bit offset addressing mode
Offset byte in indexed, 8-bit offset addressing
SP Stack pointer
Half-carry bit
U
Undefined
Index register high byte
V
Overflow bit
High and low bytes of operand address in extended addressing
X
Index register low byte
Interrupt mask
Z
Zero bit
Immediate operand byte
&
Logical AND
Immediate source to direct destination addressing mode
|
Logical OR
Immediate addressing mode
⊕ Logical EXCLUSIVE OR
Inherent addressing mode
()
Contents of
Indexed, no offset addressing mode
–( ) Negation (two’s complement)
Indexed, no offset, post increment addressing mode
#
Immediate value
Indexed with post increment to direct addressing mode
«
Sign extend
Indexed, 8-bit offset addressing mode
←
Loaded with
Indexed, 8-bit offset, post increment addressing mode
?
If
Indexed, 16-bit offset addressing mode
:
Concatenated with
Memory location
↕
Set or cleared
Negative bit
—
Not affected
Transfer SP to H:X
Transfer X to A
Transfer H:X to SP
Cycles
Description
Operand
Operation
Opcode
Source
Form
Address
Mode
Table 8-1. Instruction Set Summary (Sheet 6 of 6)
9
2
1
1
3
1
1
3
2
4
2
1
2
1
8.8 Opcode Map
See Table 8-2.
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
99
MSB
Branch
REL
DIR
INH
3
4
0
1
2
5
BRSET0
3 DIR
5
BRCLR0
3 DIR
5
BRSET1
3 DIR
5
BRCLR1
3 DIR
5
BRSET2
3 DIR
5
BRCLR2
3 DIR
5
BRSET3
3 DIR
5
BRCLR3
3 DIR
5
BRSET4
3 DIR
5
BRCLR4
3 DIR
5
BRSET5
3 DIR
5
BRCLR5
3 DIR
5
BRSET6
3 DIR
5
BRCLR6
3 DIR
5
BRSET7
3 DIR
5
BRCLR7
3 DIR
4
BSET0
2 DIR
4
BCLR0
2 DIR
4
BSET1
2 DIR
4
BCLR1
2 DIR
4
BSET2
2 DIR
4
BCLR2
2 DIR
4
BSET3
2 DIR
4
BCLR3
2 DIR
4
BSET4
2 DIR
4
BCLR4
2 DIR
4
BSET5
2 DIR
4
BCLR5
2 DIR
4
BSET6
2 DIR
4
BCLR6
2 DIR
4
BSET7
2 DIR
4
BCLR7
2 DIR
3
BRA
2 REL
3
BRN
2 REL
3
BHI
2 REL
3
BLS
2 REL
3
BCC
2 REL
3
BCS
2 REL
3
BNE
2 REL
3
BEQ
2 REL
3
BHCC
2 REL
3
BHCS
2 REL
3
BPL
2 REL
3
BMI
2 REL
3
BMC
2 REL
3
BMS
2 REL
3
BIL
2 REL
3
BIH
2 REL
Read-Modify-Write
INH
IX1
5
6
1
NEGX
1 INH
4
CBEQX
3 IMM
7
DIV
1 INH
1
COMX
1 INH
1
LSRX
1 INH
4
LDHX
2 DIR
1
RORX
1 INH
1
ASRX
1 INH
1
LSLX
1 INH
1
ROLX
1 INH
1
DECX
1 INH
3
DBNZX
2 INH
1
INCX
1 INH
1
TSTX
1 INH
4
MOV
2 DIX+
1
CLRX
1 INH
4
NEG
2
IX1
5
CBEQ
3 IX1+
3
NSA
1 INH
4
COM
2 IX1
4
LSR
2 IX1
3
CPHX
3 IMM
4
ROR
2 IX1
4
ASR
2 IX1
4
LSL
2 IX1
4
ROL
2 IX1
4
DEC
2 IX1
5
DBNZ
3 IX1
4
INC
2 IX1
3
TST
2 IX1
4
MOV
3 IMD
3
CLR
2 IX1
SP1
IX
9E6
7
Control
INH
INH
8
9
Register/Memory
IX2
SP2
IMM
DIR
EXT
A
B
C
D
9ED
4
SUB
3 EXT
4
CMP
3 EXT
4
SBC
3 EXT
4
CPX
3 EXT
4
AND
3 EXT
4
BIT
3 EXT
4
LDA
3 EXT
4
STA
3 EXT
4
EOR
3 EXT
4
ADC
3 EXT
4
ORA
3 EXT
4
ADD
3 EXT
3
JMP
3 EXT
5
JSR
3 EXT
4
LDX
3 EXT
4
STX
3 EXT
4
SUB
3 IX2
4
CMP
3 IX2
4
SBC
3 IX2
4
CPX
3 IX2
4
AND
3 IX2
4
BIT
3 IX2
4
LDA
3 IX2
4
STA
3 IX2
4
EOR
3 IX2
4
ADC
3 IX2
4
ORA
3 IX2
4
ADD
3 IX2
4
JMP
3 IX2
6
JSR
3 IX2
4
LDX
3 IX2
4
STX
3 IX2
5
SUB
4 SP2
5
CMP
4 SP2
5
SBC
4 SP2
5
CPX
4 SP2
5
AND
4 SP2
5
BIT
4 SP2
5
LDA
4 SP2
5
STA
4 SP2
5
EOR
4 SP2
5
ADC
4 SP2
5
ORA
4 SP2
5
ADD
4 SP2
IX1
SP1
IX
E
9EE
F
LSB
0
1
2
3
4
MC68HC908GP32 Data Sheet, Rev. 10
5
6
7
8
9
A
B
C
D
E
Freescale Semiconductor
F
4
1
NEG
NEGA
2 DIR 1 INH
5
4
CBEQ CBEQA
3 DIR 3 IMM
5
MUL
1 INH
4
1
COM
COMA
2 DIR 1 INH
4
1
LSR
LSRA
2 DIR 1 INH
4
3
STHX
LDHX
2 DIR 3 IMM
4
1
ROR
RORA
2 DIR 1 INH
4
1
ASR
ASRA
2 DIR 1 INH
4
1
LSL
LSLA
2 DIR 1 INH
4
1
ROL
ROLA
2 DIR 1 INH
4
1
DEC
DECA
2 DIR 1 INH
5
3
DBNZ DBNZA
3 DIR 2 INH
4
1
INC
INCA
2 DIR 1 INH
3
1
TST
TSTA
2 DIR 1 INH
5
MOV
3 DD
3
1
CLR
CLRA
2 DIR 1 INH
INH Inherent
REL Relative
IMM Immediate
IX
Indexed, No Offset
DIR Direct
IX1 Indexed, 8-Bit Offset
EXT Extended
IX2 Indexed, 16-Bit Offset
DD Direct-Direct
IMD Immediate-Direct
IX+D Indexed-Direct DIX+ Direct-Indexed
*Pre-byte for stack pointer indexed instructions
5
3
NEG
NEG
3 SP1 1 IX
6
4
CBEQ
CBEQ
4 SP1 2 IX+
2
DAA
1 INH
5
3
COM
COM
3 SP1 1 IX
5
3
LSR
LSR
3 SP1 1 IX
4
CPHX
2 DIR
5
3
ROR
ROR
3 SP1 1 IX
5
3
ASR
ASR
3 SP1 1 IX
5
3
LSL
LSL
3 SP1 1 IX
5
3
ROL
ROL
3 SP1 1 IX
5
3
DEC
DEC
3 SP1 1 IX
6
4
DBNZ
DBNZ
4 SP1 2 IX
5
3
INC
INC
3 SP1 1 IX
4
2
TST
TST
3 SP1 1 IX
4
MOV
2 IX+D
4
2
CLR
CLR
3 SP1 1 IX
SP1 Stack Pointer, 8-Bit Offset
SP2 Stack Pointer, 16-Bit Offset
IX+ Indexed, No Offset with
Post Increment
IX1+ Indexed, 1-Byte Offset with
Post Increment
7
3
RTI
BGE
1 INH 2 REL
4
3
RTS
BLT
1 INH 2 REL
3
BGT
2 REL
9
3
SWI
BLE
1 INH 2 REL
2
2
TAP
TXS
1 INH 1 INH
1
2
TPA
TSX
1 INH 1 INH
2
PULA
1 INH
2
1
PSHA
TAX
1 INH 1 INH
2
1
PULX
CLC
1 INH 1 INH
2
1
PSHX
SEC
1 INH 1 INH
2
2
PULH
CLI
1 INH 1 INH
2
2
PSHH
SEI
1 INH 1 INH
1
1
CLRH
RSP
1 INH 1 INH
1
NOP
1 INH
1
STOP
*
1 INH
1
1
WAIT
TXA
1 INH 1 INH
2
SUB
2 IMM
2
CMP
2 IMM
2
SBC
2 IMM
2
CPX
2 IMM
2
AND
2 IMM
2
BIT
2 IMM
2
LDA
2 IMM
2
AIS
2 IMM
2
EOR
2 IMM
2
ADC
2 IMM
2
ORA
2 IMM
2
ADD
2 IMM
3
SUB
2 DIR
3
CMP
2 DIR
3
SBC
2 DIR
3
CPX
2 DIR
3
AND
2 DIR
3
BIT
2 DIR
3
LDA
2 DIR
3
STA
2 DIR
3
EOR
2 DIR
3
ADC
2 DIR
3
ORA
2 DIR
3
ADD
2 DIR
2
JMP
2 DIR
4
4
BSR
JSR
2 REL 2 DIR
2
3
LDX
LDX
2 IMM 2 DIR
2
3
AIX
STX
2 IMM 2 DIR
MSB
0
3
SUB
2 IX1
3
CMP
2 IX1
3
SBC
2 IX1
3
CPX
2 IX1
3
AND
2 IX1
3
BIT
2 IX1
3
LDA
2 IX1
3
STA
2 IX1
3
EOR
2 IX1
3
ADC
2 IX1
3
ORA
2 IX1
3
ADD
2 IX1
3
JMP
2 IX1
5
JSR
2 IX1
5
3
LDX
LDX
4 SP2 2 IX1
5
3
STX
STX
4 SP2 2 IX1
4
SUB
3 SP1
4
CMP
3 SP1
4
SBC
3 SP1
4
CPX
3 SP1
4
AND
3 SP1
4
BIT
3 SP1
4
LDA
3 SP1
4
STA
3 SP1
4
EOR
3 SP1
4
ADC
3 SP1
4
ORA
3 SP1
4
ADD
3 SP1
2
SUB
1 IX
2
CMP
1 IX
2
SBC
1 IX
2
CPX
1 IX
2
AND
1 IX
2
BIT
1 IX
2
LDA
1 IX
2
STA
1 IX
2
EOR
1 IX
2
ADC
1 IX
2
ORA
1 IX
2
ADD
1 IX
2
JMP
1 IX
4
JSR
1 IX
4
2
LDX
LDX
3 SP1 1 IX
4
2
STX
STX
3 SP1 1 IX
High Byte of Opcode in Hexadecimal
LSB
Low Byte of Opcode in Hexadecimal
0
5
Cycles
BRSET0 Opcode Mnemonic
3 DIR Number of Bytes / Addressing Mode
Central Processor Unit (CPU)
100
Table 8-2. Opcode Map
Bit Manipulation
DIR
DIR
Chapter 9
External Interrupt (IRQ)
9.1 Introduction
The IRQ (external interrupt) module provides a maskable interrupt input.
9.2 Features
Features of the IRQ module include:
• A dedicated external interrupt pin IRQ
• IRQ interrupt control bits
• Programmable edge-only or edge and level interrupt sensitivity
• Automatic interrupt acknowledge
• Internal pullup device
9.3 Functional Description
A low level applied to the external interrupt request (IRQ) pin can latch a CPU interrupt request. Figure 9-1
shows the structure of the IRQ module.
RESET
INTERNAL ADDRESS BUS
ACK
TO CPU FOR
BIL/BIH
INSTRUCTIONS
IRQ VECTOR
FETCH
DECODER
VDD
INTERNAL
PULLUP
DEVICE
VDD
IRQF
D
CLR
Q
SYNCHRONIZER
CK
IRQ
IRQ LATCH
IRQ
INTERRUPT
REQUEST
IMASK
MODE
HIGH
VOLTAGE
DETECT
TO MONITOR
MODE SELECT
(NOTE)
NOTE: On FLASH devices, high-voltage disables FLASH block protection.
Figure 9-1. IRQ Module Block Diagram
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
101
External Interrupt (IRQ)
Interrupt signals on the IRQ pin are latched into the IRQ latch. The IRQ latch remains set until one of the
following actions occurs:
• IRQ vector fetch. An IRQ vector fetch automatically generates an interrupt acknowledge signal that
clears the latch that caused the vector fetch.
• Software clear. Software can clear the IRQ latch by writing a 1 to ACK in the interrupt status and
control register (INTSCR).
• Reset. A reset automatically clears the IRQ latch.
The external IRQ pin is falling edge sensitive out of reset and is software-configurable to be either falling
edge or falling edge and low level sensitive. MODE in INTSCR controls the triggering sensitivity of the
IRQ pin.
ACK is useful in applications that poll the IRQ pin and require software to clear the IRQ latch. A trigger
event (falling edge or low level) that occurs after writing to ACK latches another interrupt request.
IRQF in INTSCR can be read to check for pending interrupts. IRQF is not affected by IMASK, which
makes it useful in applications where polling is preferred.
When set, IMASK in INTSCR masks the IRQ interrupt request.
NOTE
The interrupt mask (I) in the condition code register (CCR) masks all
interrupt requests, including the IRQ interrupt request.
A falling edge on the IRQ pin can latch an interrupt request into the IRQ latch. An IRQ vector fetch,
software clear, or reset clears the IRQ latch.
9.3.1 MODE = 1
If MODE is set, the IRQ pin is both falling edge sensitive and low level sensitive. With MODE set, both of
the following actions must occur to clear the IRQ interrupt request:
• Return of the IRQ pin to a high level. As long as the IRQ pin is low, the IRQ request remains active.
• IRQ vector fetch or software clear. An IRQ vector fetch generates an interrupt acknowledge signal
to clear the IRQ latch. Software generates the interrupt acknowledge signal by writing a 1 to ACK
in INTSCR.
The IRQ vector fetch or software clear and the return of the IRQ pin to a high level may occur in any order.
The interrupt request remains pending as long as the IRQ pin is low. A reset will clear the IRQ latch and
the MODE control bit, thereby clearing the interrupt even if the pin stays low.
Use the BIH or BIL instruction to read the logic level on the IRQ pin.
NOTE
When using the level-sensitive interrupt trigger, avoid false IRQ interrupts
by masking interrupt requests in the interrupt routine.
9.3.2 MODE = 0
If MODE is clear, the IRQ pin is falling edge sensitive only. With MODE clear, an IRQ vector fetch or
software clear immediately clears the IRQ latch.
MC68HC908GP32 Data Sheet, Rev. 10
102
Freescale Semiconductor
Interrupts
9.4 Interrupts
The interrupt flag (IRQF) is set when the IRQ pin is asserted based on the IRQ mode. The IRQ interrupt
mask bit, IMASK, is used to enable or disable IRQ interrupt requests.
9.5 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption standby modes.
9.5.1 Wait Mode
The IRQ module remains active in wait mode. Clearing IMASK in INTSCR enables IRQ interrupt requests
to bring the MCU out of wait mode.
9.5.2 Stop Mode
The IRQ module remains active in stop mode and provides an asynchronous wakeup. Clearing IMASK
in INTSCR enables IRQ interrupt requests to bring the MCU out of stop mode.
9.6 IRQ Module During Break Interrupts
The system integration module (SIM) controls whether status bits in other modules can be cleared during
the break state. BCFE in the break flag control register (BFCR) enables software to clear status bits
during the break state. See BFCR in the SIM section of this data sheet.
To allow software to clear status bits during a break interrupt, write a 1 to BCFE. If a status bit is cleared
during the break state, it remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a 0 to BCFE. With BCFE cleared (its default state),
software can read and write registers during the break state without affecting status bits. Some status bits
have a two-step read/write clearing procedure. If software does the first step on such a bit before the
break, the bit cannot change during the break state as long as BCFE is cleared. After the break, doing
the second step clears the status bit.
9.7 I/O Signals
The IRQ module does not share its pin with any module on this MCU.
9.7.1 IRQ Input Pins (IRQ)
The IRQ pin provides a maskable external interrupt source. The IRQ pin contains an internal pullup
device.
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
103
External Interrupt (IRQ)
9.8 Registers
The IRQ status and control register (INTSCR) controls and monitors operation of the IRQ module. The
INTSCR:
• Shows the state of the IRQ flag
• Clears the IRQ latch
• Masks the IRQ interrupt request
• Controls triggering sensitivity of the IRQ interrupt pin
Read:
Bit 7
6
5
4
3
2
0
0
0
0
IRQF
0
Write:
Reset:
ACK
0
0
0
0
0
1
Bit 0
IMASK
MODE
0
0
0
= Unimplemented
Figure 9-2. IRQ Status and Control Register (INTSCR)
IRQF — IRQ Flag Bit
This read-only status bit is set when the IRQ interrupt is pending.
1 = IRQ interrupt pending
0 = IRQ interrupt not pending
ACK — IRQ Interrupt Request Acknowledge Bit
Writing a 1 to this write-only bit clears the IRQ latch. ACK always reads 0.
IMASK — IRQ Interrupt Mask Bit
Writing a 1 to this read/write bit disables the IRQ interrupt request.
1 = IRQ interrupt request disabled
0 = IRQ interrupt request enabled
MODE — IRQ Edge/Level Select Bit
This read/write bit controls the triggering sensitivity of the IRQ pin.
1 = IRQ interrupt request on falling edges and low levels
0 = IRQ interrupt request on falling edges only
MC68HC908GP32 Data Sheet, Rev. 10
104
Freescale Semiconductor
Chapter 10
Keyboard Interrupt (KBI) Module
10.1 Introduction
The keyboard interrupt module (KBI) provides independently maskable external interrupts.
The KBI shares its pins with general-purpose input/output (I/O) port pins.
10.2 Features
Features of the keyboard interrupt module include:
• Keyboard interrupt pins with separate keyboard interrupt enable bits and one keyboard interrupt
mask
• Pullup device automatically enabled when pin is used for KBI input
• Programmable edge-only or edge and level interrupt sensitivity
• Exit from low-power modes
10.3 Functional Description
The keyboard interrupt module controls the enabling/disabling of interrupt functions on the KBI pins.
These pins can be enabled/disabled independently of each other.
INTERNAL BUS
VECTOR FETCH
DECODER
ACKK
RESET
KBI0
KBIE0
VDD
KEYF
D
CLR
Q
SYNCHRONIZER
CK
KBIx
KBI LATCH
IMASKK
KBIEx
KEYBOARD
INTERRUPT
REQUEST
MODEK
Figure 10-1. Keyboard Interrupt Block Diagram
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
105
Keyboard Interrupt (KBI) Module
10.4 Keyboard Operation
Writing to the KBIEx bits in the keyboard interrupt enable register (INTKBIER) independently enables or
disables each KBI pin. Enabling a keyboard interrupt pin also enables its internal pullup device
irrespective of PUEx bits in the input pullup enable register. A low applied to an enabled keyboard
interrupt pin latches a keyboard interrupt request.
The keyboard interrupt latch is set when one or more keyboard interrupt input goes low after all were high.
MODEK in the keyboard status and control register (INTKBSCR) controls the triggering mode of the
keyboard interrupt.
• If the keyboard interrupt is edge-sensitive only, a falling edge on a keyboard interrupt input does
not latch an interrupt request if another keyboard pin is already low. To prevent losing an interrupt
request on one input because another input remains low, software can disable the latter input while
it is low.
• If the keyboard interrupt is falling edge and low-level sensitive, an interrupt request is present as
long as any keyboard interrupt input is low.
10.4.1 MODEK = 1
If MODEK is set, the keyboard interrupt inputs are both falling edge and low-level sensitive. With MODEK
set, both of the following actions must occur to clear a keyboard interrupt request:
• Return of all enabled keyboard interrupt inputs to a high level. As long as any enabled keyboard
interrupt pin is low, the keyboard interrupt remains active.
• Vector fetch or software clear. A KBI vector fetch generates an interrupt acknowledge signal to
clear the KBI latch. Software generates the interrupt acknowledge signal by writing a 1 to ACKK in
INTKBSCR. ACKK is useful in applications that poll the keyboard interrupt inputs and require
software to clear the KBI latch. Writing to ACKK prior to leaving an interrupt service routine can
also prevent spurious interrupts due to noise. Setting ACKK does not affect subsequent transitions
on the keyboard interrupt inputs. A falling edge that occurs after writing to ACKK latches another
interrupt request. If the keyboard interrupt mask bit, IMASKK, is clear, the CPU loads the program
counter with the KBI vector address.
The KBI vector fetch or software clear and the return of all enabled keyboard interrupt pins to a high level
may occur in any order.
Reset clears the keyboard interrupt request and MODEK, clearing the interrupt request even if a keyboard
interrupt input stays low.
10.4.2 MODEK = 0
If MODEK is clear, the keyboard interrupt pin is falling-edge sensitive only. A KBI vector fetch or software
clear immediately clears the KBI latch.
The keyboard flag bit (KEYF) in INTKBSCR can be read to check for pending interrupts. KEYF is not
affected by IMASKK, which makes it useful in applications where polling is preferred.
NOTE
Setting a keyboard interrupt enable bit (KBIEx) forces the corresponding
keyboard interrupt pin to be an input, overriding the data direction register.
However, the data direction register bit must be a 0 for software to read the
pin.
MC68HC908GP32 Data Sheet, Rev. 10
106
Freescale Semiconductor
Interrupts
10.4.3 Keyboard Initialization
When a keyboard interrupt pin is enabled, it takes time for the internal pullup to pull the pin to a high level.
Therefore a false interrupt can occur as soon as the pin is enabled.
To prevent a false interrupt on keyboard initialization:
1. Mask keyboard interrupts by setting IMASKK in INTKBSCR.
2. Enable the KBI pins by setting the appropriate KBIEx bits in INTKBIER.
3. Write to ACKK in INTKBSCR to clear any false interrupts.
4. Clear IMASKK.
An interrupt signal on an edge sensitive pin can be acknowledged immediately after enabling the pin. An
interrupt signal on an edge and level sensitive pin must be acknowledged after a delay that depends on
the external load.
10.5 Interrupts
The following KBI source can generate interrupt requests:
• Keyboard flag (KEYF) — KEYF is set when any enabled KBI pin is asserted based on the KBI
mode. The keyboard interrupt mask bit, IMASKK, is used to enable or disable KBI interrupt
requests.
10.6 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption standby modes.
10.6.1 Wait Mode
The KBI module remains active in wait mode. Clearing IMASKK in INTKBSCR enables keyboard interrupt
requests to bring the MCU out of wait mode.
10.6.2 Stop Mode
The KBI module remains active in stop mode. Clearing IMASKK in INTKBSCR enables keyboard interrupt
requests to bring the MCU out of stop mode.
10.7 KBI During Break Interrupts
The system integration module (SIM) controls whether status bits in other modules can be cleared during
the break state. BCFE in the break flag control register (BFCR) enables software to clear status bits
during the break state. See BFCR in the SIM section of this data sheet.
To allow software to clear status bits during a break interrupt, write a 1 to BCFE. If a status bit is cleared
during the break state, it remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a 0 to BCFE. With BCFE cleared (its default state),
software can read and write registers during the break state without affecting status bits. Some status bits
have a two-step read/write clearing procedure. If software does the first step on such a bit before the
break, the bit cannot change during the break state as long as BCFE is cleared. After the break, doing
the second step clears the status bit.
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
107
Keyboard Interrupt (KBI) Module
10.8 I/O Signals
The KBI module can share its pins with the general-purpose I/O pins.
10.8.1 KBI Input Pins (KBI7:KBI0)
Each KBI pin is independently programmable as an external interrupt source. Each KBI pin when enabled
will automatically configure a pullup device.
10.9 Registers
The following registers control and monitor operation of the KBI module:
• INTKBSCR (keyboard interrupt status and control register)
• INTKBIER (keyboard interrupt enable register)
10.9.1 Keyboard Status and Control Register (INTKBSCR)
Features of the INTKBSCR:
• Flags keyboard interrupt requests
• Acknowledges keyboard interrupt requests
• Masks keyboard interrupt requests
• Controls keyboard interrupt triggering sensitivity
Read:
Bit 7
6
5
4
3
0
0
0
0
KEYF
Write:
Reset:
2
0
ACKK
0
0
0
0
0
0
1
Bit 0
IMASKK
MODEK
0
0
= Unimplemented
Figure 10-2. Keyboard Status and Control Register (INTKBSCR)
Bits 7–4 — Not used
KEYF — Keyboard Flag Bit
This read-only bit is set when a keyboard interrupt is pending.
1 = Keyboard interrupt pending
0 = No keyboard interrupt pending
ACKK — Keyboard Acknowledge Bit
Writing a 1 to this write-only bit clears the KBI request. ACKK always reads 0.
IMASKK— Keyboard Interrupt Mask Bit
Writing a 1 to this read/write bit prevents the output of the KBI latch from generating interrupt requests.
1 = Keyboard interrupt requests disabled
0 = Keyboard interrupt requests enabled
MODEK — Keyboard Triggering Sensitivity Bit
This read/write bit controls the triggering sensitivity of the keyboard interrupt pins.
1 = Keyboard interrupt requests on falling edges and low levels
0 = Keyboard interrupt requests on falling edges only
MC68HC908GP32 Data Sheet, Rev. 10
108
Freescale Semiconductor
Registers
10.9.2 Keyboard Interrupt Enable Register (INTKBIER)
INTKBIER enables or disables each keyboard interrupt pin.
Read:
Write:
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
KBIE7
KBIE6
KBIE5
KBIE4
KBIE3
KBIE2
KBIE1
KBIE0
0
0
0
0
0
0
0
0
Figure 10-3. Keyboard Interrupt Enable Register (INTKBIER)
KBIE7–KBIE0 — Keyboard Interrupt Enable Bits
Each of these read/write bits enables the corresponding keyboard interrupt pin to latch KBI interrupt
requests.
1 = KBIx pin enabled as keyboard interrupt pin
0 = KBIx pin not enabled as keyboard interrupt pin
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
109
Keyboard Interrupt (KBI) Module
MC68HC908GP32 Data Sheet, Rev. 10
110
Freescale Semiconductor
Chapter 11
Low-Voltage Inhibit (LVI)
11.1 Introduction
This section describes the low-voltage inhibit (LVI) module, which monitors the voltage on the VDD pin
and can force a reset when the VDD voltage falls below the LVI trip falling voltage, VTRIPF.
11.2 Features
Features of the LVI module include:
• Programmable LVI reset
• Selectable LVI trip voltage
• Programmable stop mode operation
11.3 Functional Description
Figure 11-1 shows the structure of the LVI module. The LVI is enabled out of reset. The LVI module
contains a bandgap reference circuit and comparator. Clearing the LVI power disable bit, LVIPWRD,
enables the LVI to monitor VDD voltage. Clearing the LVI reset disable bit, LVIRSTD, enables the LVI
module to generate a reset when VDD falls below a voltage, VTRIPF. Setting the LVI enable in stop mode
bit, LVISTOP, enables the LVI to operate in stop mode. Setting the LVI 5-V or 3-V trip point bit, LVI5OR3,
enables the trip point voltage, VTRIPF, to be configured for 5-V operation. Clearing the LVI5OR3 bit
enables the trip point voltage, VTRIPF, to be configured for 3-V operation. The actual trip points are shown
in Chapter 19 Electrical Specifications.
NOTE
After a power-on reset (POR) the LVI’s default mode of operation is 3 V. If
a 5-V system is used, the user must set the LVI5OR3 bit to raise the trip
point to 5-V operation. Note that this must be done after every power-on
reset since the default will revert back to 3-V mode after each power-on
reset. If the VDD supply is below the 5-V mode trip voltage but above the
3-V mode trip voltage when POR is released, the part will operate because
VTRIPF defaults to 3-V mode after a POR. So, in a 5-V system care must be
taken to ensure that VDD is above the 5-V mode trip voltage after POR is
released.
NOTE
If the user requires 5-V mode and sets the LVI5OR3 bit after a power-on
reset while the VDD supply is not above the VTRIPR for 5-V mode, the MCU
will immediately go into reset. The LVI in this case will hold the part in reset
until either VDD goes above the rising 5-V trip point, VTRIPR, which will
release reset or VDD decreases to approximately 0 V which will re-trigger
the power-on reset and reset the trip point to 3-V operation.
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
111
Low-Voltage Inhibit (LVI)
LVISTOP, LVIPWRD, LVI5OR3, and LVIRSTD are in the configuration register (CONFIG1). See 6.2
Functional Description for details of the LVI’s configuration bits. Once an LVI reset occurs, the MCU
remains in reset until VDD rises above a voltage, VTRIPR, which causes the MCU to exit reset. See
14.3.2.5 Low-Voltage Inhibit (LVI) Reset for details of the interaction between the SIM and the LVI. The
output of the comparator controls the state of the LVIOUT flag in the LVI status register (LVISR).
An LVI reset also drives the RST pin low to provide low-voltage protection to external peripheral devices.
VDD
STOP INSTRUCTION
LVISTOP
FROM CONFIG1
FROM CONFIG1
LVIRSTD
LVIPWRD
FROM CONFIG
LOW VDD
DETECTOR
VDD > LVITrip = 0
LVI RESET
VDD ≤ LVITrip = 1
LVIOUT
LVI5OR3
FROM CONFIG1
Figure 11-1. LVI Module Block Diagram
Addr.
Register Name
Read:
Bit 7
6
5
4
3
2
1
Bit 0
LVIOUT
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
$FE0C LVI Status Register (LVISR) Write:
Reset:
= Unimplemented
Figure 11-2. LVI I/O Register Summary
11.3.1 Polled LVI Operation
In applications that can operate at VDD levels below the VTRIPF level, software can monitor VDD by polling
the LVIOUT bit. In the configuration register, the LVIPWRD bit must be at logic 0 to enable the LVI
module, and the LVIRSTD bit must be at logic 1 to disable LVI resets.
11.3.2 Forced Reset Operation
In applications that require VDD to remain above the VTRIPF level, enabling LVI resets allows the LVI
module to reset the MCU when VDD falls below the VTRIPF level. In the configuration register, the
LVIPWRD and LVIRSTD bits must be at logic 0 to enable the LVI module and to enable LVI resets.
MC68HC908GP32 Data Sheet, Rev. 10
112
Freescale Semiconductor
LVI Status Register
11.3.3 Voltage Hysteresis Protection
Once the LVI has triggered (by having VDD fall below VTRIPF), the LVI will maintain a reset condition until
VDD rises above the rising trip point voltage, VTRIPR. This prevents a condition in which the MCU is
continually entering and exiting reset if VDD is approximately equal to VTRIPF. VTRIPR is greater than
VTRIPF by the hysteresis voltage, VHYS.
11.3.4 LVI Trip Selection
The LVI5OR3 bit in the configuration register selects whether the LVI is configured for 5-V or 3-V
protection.
NOTE
The microcontroller is guaranteed to operate at a minimum supply voltage.
The trip point (VTRIPF [5 V] or VTRIPF [3 V]) may be lower than this. (See
Chapter 19 Electrical Specifications for the actual trip point voltages.)
11.4 LVI Status Register
The LVI status register (LVISR) indicates if the VDD voltage was detected below the VTRIPF level.
Address:
Read:
$FE0C
Bit 7
6
5
4
3
2
1
Bit 0
LVIOUT
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Write:
Reset:
= Unimplemented
Figure 11-3. LVI Status Register (LVISR)
LVIOUT — LVI Output Bit
This read-only flag becomes set when the VDD voltage falls below the VTRIPF trip voltage.
(See Table 11-1.) Reset clears the LVIOUT bit.
Table 11-1. LVIOUT Bit Indication
VDD
LVIOUT
VDD > VTRIPR
0
VDD < VTRIPF
1
VTRIPF < VDD < VTRIPR
Previous value
11.5 LVI Interrupts
The LVI module does not generate interrupt requests.
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
113
Low-Voltage Inhibit (LVI)
11.6 Low-Power Modes
The STOP and WAIT instructions put the MCU in low power-consumption standby modes.
11.6.1 Wait Mode
If enabled, the LVI module remains active in wait mode. If enabled to generate resets, the LVI module can
generate a reset and bring the MCU out of wait mode.
11.6.2 Stop Mode
If enabled in stop mode (LVISTOP set), the LVI module remains active in stop mode. If enabled to
generate resets, the LVI module can generate a reset and bring the MCU out of stop mode.
MC68HC908GP32 Data Sheet, Rev. 10
114
Freescale Semiconductor
Chapter 12
Input/Output (I/O) Ports
12.1 Introduction
Thirty-three (33) bidirectional input-output (I/O) pins form five parallel ports. All I/O pins are programmable
as inputs or outputs. All individual bits within port A, port C, and port D are software configurable with
pullup devices if configured as input port bits. The pullup devices are automatically and dynamically
disabled when a port bit is switched to output mode.
Input pins and I/O port pins that are not used in the application must be terminated. This prevents excess
current caused by floating inputs, and enhances immunity during noise or transient events. Termination
methods include:
1. Configuring unused pins as outputs and driving high or low;
2. Configuring unused pins as inputs and enabling internal pull-ups;
3. Configuring unused pins as inputs and using external pull-up or pull-down resistors.
Never connect unused pins directly to VDD or VSS.
Since some general-purpose I/O pins are not available on all packages, these pins must be terminated
as well. Either method 1 or 2 above are appropriate.
Addr.
$0000
$0001
$0002
$0003
Register Name
Read:
Port A Data Register
Write:
(PTA)
Reset:
Read:
Port B Data Register
Write:
(PTB)
Reset:
Read:
Port C Data Register
Write:
(PTC)
Reset:
Read:
Port D Data Register
Write:
(PTD)
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
PTA7
PTA6
PTA5
PTA4
PTA3
PTA2
PTA1
PTA0
PTB2
PTB1
PTB0
PTC2
PTC1
PTC0
PTD2
PTD1
PTD0
Unaffected by reset
PTB7
PTB6
PTB5
PTB4
PTB3
Unaffected by reset
0
PTC6
PTC5
PTC4
PTC3
Unaffected by reset
PTD7
PTD6
PTD5
PTD4
PTD3
Unaffected by reset
= Unimplemented
Figure 12-1. I/O Port Register Summary
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
115
Input/Output (I/O) Ports
Addr.
$0004
$0005
$0006
$0007
$0008
$000C
$000D
$000E
$000F
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
DDRA7
DDRA6
DDRA5
DDRA4
DDRA3
DDRA2
DDRA1
DDRA0
0
0
0
0
0
0
0
0
DDRB7
DDRB6
DDRB5
DDRB4
DDRB3
DDRB2
DDRB1
DDRB0
0
0
0
0
0
0
0
0
DDRC6
DDRC5
DDRC4
DDRC3
DDRC2
DDRC1
DDRC0
0
0
0
0
0
0
0
0
DDRD7
DDRD6
DDRD5
DDRD4
DDRD3
DDRD2
DDRD1
DDRD0
0
0
0
0
0
0
0
0
Read:
Port E Data Register
Write:
(PTE)
Reset:
0
0
0
0
0
0
PTE1
PTE0
Read:
Data Direction Register E
Write:
(DDRE)
Reset:
0
DDRE1
DDRE0
Read:
Data Direction Register A
Write:
(DDRA)
Reset:
Read:
Data Direction Register B
Write:
(DDRB)
Reset:
Read:
Data Direction Register C
Write:
(DDRC)
Reset:
Read:
Data Direction Register D
Write:
(DDRD)
Reset:
0
Unaffected by reset
0
Read:
Port A Input Pullup Enable
PTAPUE7
Register Write:
(PTAPUE)
Reset:
0
Read:
Port C Input Pullup Enable
Register Write:
(PTCPUE)
Reset:
0
0
0
0
0
0
0
0
0
0
0
0
PTAPUE6
PTAPUE5
PTAPUE4
PTAPUE3
PTAPUE2
PTAPUE1
PTAPUE0
0
0
0
0
0
0
0
PTCPUE6
PTCPUE5
PTCPUE4
PTCPUE3
PTCPUE2
PTCPUE1
PTCPUE0
0
0
0
0
0
0
0
PTDPUE6
PTDPUE5
PTDPUE4
PTDPUE3
PTDPUE2
PTDPUE1
PTDPUE0
0
0
0
0
0
0
0
0
0
Read:
Port D Input Pullup Enable
PTDPUE7
Register Write:
(PTDPUE)
Reset:
0
= Unimplemented
Figure 12-1. I/O Port Register Summary (Continued)
MC68HC908GP32 Data Sheet, Rev. 10
116
Freescale Semiconductor
Introduction
Table 12-1. Port Control Register Bits Summary
Port
A
B
C
D
E
Bit
DDR
Module Control
0
DDRA0
KBIE0
PTA0/KBD0
1
DDRA1
KBIE1
PTA1/KBD1
2
DDRA2
KBIE2
PTA2/KBD2
3
DDRA3
KBIE3
PTA3/KBD3
4
DDRA4
KBIE4
PTA4/KBD4
5
DDRA5
KBIE5
PTA5/KBD5
6
DDRA6
KBIE6
PTA6/KBD6
7
DDRA7
KBIE7
PTA7/KBD7
0
DDRB0
PTB0/AD0
1
DDRB1
PTB1/AD1
2
DDRB2
PTB2/AD2
3
DDRB3
4
DDRB4
5
DDRB5
PTB5/AD5
6
DDRB6
PTB6/AD6
7
DDRB7
PTB7/AD7
0
DDRC0
PTC0
1
DDRC1
PTC1
2
DDRC2
PTC2
3
DDRC3
PTC3
4
DDRC4
PTC4
5
DDRC5
PTC5
6
DDRC6
PTC6
0
DDRD0
PTD0/SS
1
DDRD1
2
DDRD2
3
DDRD3
4
DDRD4
5
DDRD5
6
DDRD6
7
DDRD7
0
DDRE0
1
DDRE1
KBD
ADC
SPI
ADCH4–ADCH0
SPE
Pin
PTB3/AD3
PTB4/AD4
PTD1/MISO
PTD2/MOSI
PTD3/SPSCK
TIM1
TIM2
SCI
ELS0B:ELS0A
PTD4/T1CH0
ELS1B:ELS1A
PTD5/T1CH1
ELS0B:ELS0A
PTD6/T2CH0
ELS1B:ELS1A
PTD7/T2CH1
ENSCI
PTE0/TxD
PTE1/RxD
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
117
Input/Output (I/O) Ports
12.2 Port A
Port A is an 8-bit special-function port that shares all eight of its pins with the keyboard interrupt (KBI)
module. Port A also has software configurable pullup devices if configured as an input port.
12.2.1 Port A Data Register
The port A data register (PTA) contains a data latch for each of the eight port A pins.
Address:
$0000
Read:
Write:
Bit 7
6
5
4
3
2
1
Bit 0
PTA7
PTA6
PTA5
PTA4
PTA3
PTA2
PTA1
PTA0
KBD7
KBD6
KBD5
KBD2
KBD1
KBD0
Reset:
Unaffected by reset
Alternate Function:
KBD4
KBD3
Figure 12-2. Port A Data Register (PTA)
PTA7–PTA0 — Port A Data Bits
These read/write bits are software programmable. Data direction of each port A pin is under the control
of the corresponding bit in data direction register A. Reset has no effect on port A data.
KBD7–KBD0 — Keyboard Inputs
The keyboard interrupt enable bits, KBIE7–KBIE0, in the keyboard interrupt control register (KBICR)
enable the port A pins as external interrupt pins. (see Chapter 10 Keyboard Interrupt (KBI) Module)
12.2.2 Data Direction Register A
Data direction register A (DDRA) determines whether each port A pin is an input or an output. Writing a
logic 1 to a DDRA bit enables the output buffer for the corresponding port A pin; a logic 0 disables the
output buffer.
Address:
Read:
Write:
Reset:
$0004
Bit 7
6
5
4
3
2
1
Bit 0
DDRA7
DDRA6
DDRA5
DDRA4
DDRA3
DDRA2
DDRA1
DDRA0
0
0
0
0
0
0
0
0
Figure 12-3. Data Direction Register A (DDRA)
DDRA7–DDRA0 — Data Direction Register A Bits
These read/write bits control port A data direction. Reset clears DDRA7–DDRA0, configuring all port
A pins as inputs.
1 = Corresponding port A pin configured as output
0 = Corresponding port A pin configured as input
NOTE
Avoid glitches on port A pins by writing to the port A data register before
changing data direction register A bits from 0 to 1.
MC68HC908GP32 Data Sheet, Rev. 10
118
Freescale Semiconductor
Port A
Figure 12-4 shows the port A I/O logic.
READ DDRA ($0004)
INTERNAL DATA BUS
WRITE DDRA ($0004)
DDRAx
RESET
WRITE PTA ($0000)
PTAx
PTAx
VDD
PTAPUEx
INTERNAL
PULLUP
DEVICE
READ PTA ($0000)
Figure 12-4. Port A I/O Circuit
When bit DDRAx is a logic 1, reading address $0000 reads the PTAx data latch. When bit DDRAx is a
logic 0, reading address $0000 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 12-2 summarizes the operation of the port A pins.
Table 12-2. Port A Pin Functions
PTAPUE Bit
DDRA Bit
PTA Bit
Accesses to DDRA
I/O Pin Mode
Accesses to PTA
Read/Write
Read
Write
(4)
DDRA7–DDRA0
Pin
PTA7–PTA0(3)
1
0
X(1)
0
0
X
Input, Hi-Z(2)
DDRA7–DDRA0
Pin
PTA7–PTA0(3)
X
1
X
Output
DDRA7–DDRA0
PTA7–PTA0
PTA7–PTA0
Input, VDD
NOTES:
1. X = Don’t care
2. Hi-Z = High impedance
3. Writing affects data register, but does not affect input.
4. I/O pin pulled up to VDD by internal pullup device
12.2.3 Port A Input Pullup Enable Register
The port A input pullup enable register (PTAPUE) contains a software configurable pullup device for each
of the eight port A pins. Each bit is individually configurable and requires that the data direction register,
DDRA, bit be configured as an input. Each pullup is automatically and dynamically disabled when a port
bit’s DDRA is configured for output mode.
Address:
$000D
Read:
Write:
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
PTAPUE7
PTAPUE6
PTAPUE5
PTAPUE4
PTAPUE3
PTAPUE2
PTAPUE1
PTAPUE0
0
0
0
0
0
0
0
0
Figure 12-5. Port A Input Pullup Enable Register (PTAPUE)
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
119
Input/Output (I/O) Ports
PTAPUE7–PTAPUE0 — Port A Input Pullup Enable Bits
These writable bits are software programmable to enable pullup devices on an input port bit.
1 = Corresponding port A pin configured to have internal pullup
0 = Corresponding port A pin has internal pullup disconnected
12.3 Port B
Port B is an 8-bit special-function port that shares all eight of its pins with the analog-to-digital converter
(ADC) module.
12.3.1 Port B Data Register
The port B data register (PTB) contains a data latch for each of the eight port pins.
Address:
$0001
Read:
Write:
Bit 7
6
5
4
3
2
1
Bit 0
PTB7
PTB6
PTB5
PTB4
PTB3
PTB2
PTB1
PTB0
AD2
AD1
AD0
Reset:
Unaffected by reset
Alternate Function:
AD7
AD6
AD5
AD4
AD3
Figure 12-6. Port B Data Register (PTB)
PTB7–PTB0 — Port B Data Bits
These read/write bits are software-programmable. Data direction of each port B pin is under the control
of the corresponding bit in data direction register B. Reset has no effect on port B data.
AD7–AD0 — Analog-to-Digital Input Bits
AD7–AD0 are pins used for the input channels to the analog-to-digital converter module. The channel
select bits in the ADC status and control register define which port B pin will be used as an ADC input
and overrides any control from the port I/O logic by forcing that pin as the input to the analog circuitry.
NOTE
Care must be taken when reading port B while applying analog voltages to
AD7–AD0 pins. If the appropriate ADC channel is not enabled, excessive
current drain may occur if analog voltages are applied to the PTBx/ADx pin,
while PTB is read as a digital input. Those ports not selected as analog
input channels are considered digital I/O ports.
12.3.2 Data Direction Register B
Data direction register B (DDRB) determines whether each port B pin is an input or an output. Writing a
logic 1 to a DDRB bit enables the output buffer for the corresponding port B pin; a logic 0 disables the
output buffer.
Address:
Read:
Write:
Reset:
$0005
Bit 7
6
5
4
3
2
1
Bit 0
DDRB7
DDRB6
DDRB5
DDRB4
DDRB3
DDRB2
DDRB1
DDRB0
0
0
0
0
0
0
0
0
Figure 12-7. Data Direction Register B (DDRB)
MC68HC908GP32 Data Sheet, Rev. 10
120
Freescale Semiconductor
Port B
DDRB7–DDRB0 — Data Direction Register B Bits
These read/write bits control port B data direction. Reset clears DDRB7–DDRB0], configuring all port
B pins as inputs.
1 = Corresponding port B pin configured as output
0 = Corresponding port B pin configured as input
NOTE
Avoid glitches on port B pins by writing to the port B data register before
changing data direction register B bits from 0 to 1.
Figure 12-8 shows the port B I/O logic.
READ DDRB ($0005)
INTERNAL DATA BUS
WRITE DDRB ($0005)
RESET
DDRBx
WRITE PTB ($0001)
PTBx
PTBx
READ PTB ($0001)
Figure 12-8. Port B I/O Circuit
When bit DDRBx is a logic 1, reading address $0001 reads the PTBx data latch. When bit DDRBx is a
logic 0, reading address $0001 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 12-3 summarizes the operation of the port B pins.
Table 12-3. Port B Pin Functions
DDRB Bit
0
1
PTB Bit
(1)
X
X
I/O Pin Mode
Input,
Hi-Z(2)
Output
Accesses to DDRB
Accesses to PTB
Read/Write
Read
Write
DDRB7–DDRB0
Pin
PTB7–PTB0(3)
DDRB7–DDRB0
PTB7–PTB0
PTB7–PTB0
Notes:
1. X = Don’t care
2. Hi-Z = High impedance
3. Writing affects data register, but does not affect input.
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
121
Input/Output (I/O) Ports
12.4 Port C
Port C is a 7-bit, general-purpose bidirectional I/O port. Port C also has software configurable pullup
devices if configured as an input port.
12.4.1 Port C Data Register
The port C data register (PTC) contains a data latch for each of the seven port C pins.
NOTE
Bit 6 and bit 5 of PTC are not available in a 40-pin dual in-line package and
42-pin shrink dual in-line package.
Address:
$0002
Bit 7
Read:
0
Write:
6
5
4
3
2
1
Bit 0
PTC6
PTC5
PTC4
PTC3
PTC2
PTC1
PTC0
Reset:
Unaffected by reset
= Unimplemented
Figure 12-9. Port C Data Register (PTC)
PTC6–PTC0 — Port C Data Bits
These read/write bits are software-programmable. Data direction of each port C pin is under the control
of the corresponding bit in data direction register C. Reset has no effect on port C data.
12.4.2 Data Direction Register C
Data direction register C (DDRC) determines whether each port C pin is an input or an output. Writing a
logic 1 to a DDRC bit enables the output buffer for the corresponding port C pin; a logic 0 disables the
output buffer.
Address:
$0006
Bit 7
Read:
0
Write:
Reset:
0
6
5
4
3
2
1
Bit 0
DDRC6
DDRC5
DDRC4
DDRC3
DDRC2
DDRC1
DDRC0
0
0
0
0
0
0
0
= Unimplemented
Figure 12-10. Data Direction Register C (DDRC)
DDRC6–DDRC0 — Data Direction Register C Bits
These read/write bits control port C data direction. Reset clears DDRC6–DDRC0, configuring all port
C pins as inputs.
1 = Corresponding port C pin configured as output
0 = Corresponding port C pin configured as input
NOTE
Avoid glitches on port C pins by writing to the port C data register before
changing data direction register C bits from 0 to 1.
MC68HC908GP32 Data Sheet, Rev. 10
122
Freescale Semiconductor
Port C
Figure 12-11 shows the port C I/O logic.
NOTE
For those devices packaged in a 40-pin dual in-line package and 42-pin
shrink dual in-line package, PTC5 and PTC6 are connected to ground
internally. DDRC5 and DDRC6 should be set to a 0 to configure PTC5 and
PTC6 as inputs.
READ DDRC ($0006)
INTERNAL DATA BUS
WRITE DDRC ($0006)
DDRCx
RESET
WRITE PTC ($0002)
PTCx
PTCx
VDD
PTCPUEx
READ PTC ($0002)
INTERNAL
PULLUP
DEVICE
Figure 12-11. Port C I/O Circuit
When bit DDRCx is a logic 1, reading address $0002 reads the PTCx data latch. When bit DDRCx is a
logic 0, reading address $0002 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 12-4 summarizes the operation of the port C pins.
Table 12-4. Port C Pin Functions
PTCPUE Bit
DDRC Bit
PTC Bit
I/O Pin Mode
1
0
X(1)
0
0
X
1
Accesses to DDRC
Accesses to PTC
Read/Write
Read
Write
Input, VDD(4)
DDRC6–DDRC0
Pin
PTC6–PTC0(3)
X
Input, Hi-Z(2)
DDRC6–DDRC0
Pin
PTC6–PTC0(3)
X
Output
DDRC6–DDRC0
PTC6–PTC0
PTC6–PTC0
Notes:
1. X = Don’t care
2. Hi-Z = High impedance
3. Writing affects data register, but does not affect input.
4. I/O pin pulled up to VDD by internal pullup device.
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
123
Input/Output (I/O) Ports
12.4.3 Port C Input Pullup Enable Register
The port C input pullup enable register (PTCPUE) contains a software configurable pullup device for each
of the seven port C pins. Each bit is individually configurable and requires that the data direction register,
DDRC, bit be configured as an input. Each pullup is automatically and dynamically disabled when a port
bit’s DDRC is configured for output mode.
Address:
$000E
Bit 7
Read:
0
Write:
Reset:
6
5
4
3
2
1
Bit 0
PTCPUE6
PTCPUE5
PTCPUE4
PTCPUE3
PTCPUE2
PTCPUE1
PTCPUE0
0
0
0
0
0
0
0
0
= Unimplemented
Figure 12-12. Port C Input Pullup Enable Register (PTCPUE)
PTCPUE6–PTCPUE0 — Port C Input Pullup Enable Bits
These writable bits are software programmable to enable pullup devices on an input port bit.
1 = Corresponding port C pin configured to have internal pullup
0 = Corresponding port C pin internal pullup disconnected
12.5 Port D
Port D is an 8-bit special-function port that shares four of its pins with the serial peripheral interface (SPI)
module and four of its pins with two timer interface (TIM1 and TIM2) modules. Port D also has software
configurable pullup devices if configured as an input port.
12.5.1 Port D Data Register
The port D data register (PTD) contains a data latch for each of the eight port D pins.
NOTE
Bit 7 and bit 6 of PTD are not available in a 40-pin dual in-line package.
Address:
Read:
Write:
$0003
Bit 7
6
5
4
3
2
1
Bit 0
PTD7
PTD6
PTD5
PTD4
PTD3
PTD2
PTD1
PTD0
T2CH1
T2CH0
T1CH1
T1CH0
MOSI
MISO
SS
Reset:
Alternate Function:
Unaffected by reset
SPSCK
Figure 12-13. Port D Data Register (PTD)
PTD7–PTD0 — Port D Data Bits
These read/write bits are software-programmable. Data direction of each port D pin is under the control
of the corresponding bit in data direction register D. Reset has no effect on port D data.
T2CH1 and T2CH0 — Timer 2 Channel I/O Bits
The PTD7/T2CH1–PTD6/T2CH0 pins are the TIM2 input capture/output compare pins. The edge/level
select bits, ELSxB:ELSxA, determine whether the PTD7/T2CH1–PTD6/T2CH0 pins are timer channel
I/O pins or general-purpose I/O pins. See Chapter 17 Timer Interface Module (TIM).
MC68HC908GP32 Data Sheet, Rev. 10
124
Freescale Semiconductor
Port D
T1CH1 and T1CH0 — Timer 1 Channel I/O Bits
The PTD7/T1CH1–PTD6/T1CH0 pins are the TIM1 input capture/output compare pins. The edge/level
select bits, ELSxB and ELSxA, determine whether the PTD7/T1CH1–PTD6/T1CH0 pins are timer
channel I/O pins or general-purpose I/O pins. See Chapter 17 Timer Interface Module (TIM).
SPSCK — SPI Serial Clock
The PTD3/SPSCK pin is the serial clock input of the SPI module. When the SPE bit is clear, the
PTD3/SPSCK pin is available for general-purpose I/O.
MOSI — Master Out/Slave In
The PTD2/MOSI pin is the master out/slave in terminal of the SPI module. When the SPE bit is clear,
the PTD2/MOSI pin is available for general-purpose I/O.
MISO — Master In/Slave Out
The PTD1/MISO pin is the master in/slave out terminal of the SPI module. When the SPI enable bit,
SPE, is clear, the SPI module is disabled, and the PTD1/MISO pin is available for general-purpose I/O.
Data direction register D (DDRD) does not affect the data direction of port D pins that are being used
by the SPI module. However, the DDRD bits always determine whether reading port D returns the
states of the latches or the states of the pins. See Table 12-5.
SS — Slave Select
The PTD0/SS pin is the slave select input of the SPI module. When the SPE bit is clear, or when the
SPI master bit, SPMSTR, is set, the PTD0/SS pin is available for general-purpose I/O. When the SPI
is enabled, the DDRD0 bit in data direction register D (DDRD) has no effect on the PTD0/SS pin.
12.5.2 Data Direction Register D
Data direction register D (DDRD) determines whether each port D pin is an input or an output. Writing a
logic 1 to a DDRD bit enables the output buffer for the corresponding port D pin; a logic 0 disables the
output buffer.
Address:
Read:
Write:
Reset:
$0007
Bit 7
6
5
4
3
2
1
Bit 0
DDRD7
DDRD6
DDRD5
DDRD4
DDRD3
DDRD2
DDRD1
DDRD0
0
0
0
0
0
0
0
0
Figure 12-14. Data Direction Register D (DDRD)
DDRD7–DDRD0 — Data Direction Register D Bits
These read/write bits control port D data direction. Reset clears DDRD7–DDRD0, configuring all port
D pins as inputs.
1 = Corresponding port D pin configured as output
0 = Corresponding port D pin configured as input
NOTE
Avoid glitches on port D pins by writing to the port D data register before
changing data direction register D bits from 0 to 1.
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
125
Input/Output (I/O) Ports
Figure 12-15 shows the port D I/O logic.
NOTE
For those devices packaged in a 40-pin dual in-line package, PTD6 and
PTD7 are not connected. DDRD6 and DDRD7 should be set to a 1 to
configure PTD6 and PTD7 as outputs.
READ DDRD ($0007)
INTERNAL DATA BUS
WRITE DDRD ($0007)
DDRDx
RESET
WRITE PTD ($0003)
PTDx
PTDx
VDD
PTDPUEx
READ PTD ($0003)
INTERNAL
PULLUP
DEVICE
Figure 12-15. Port D I/O Circuit
When bit DDRDx is a logic 1, reading address $0003 reads the PTDx data latch. When bit DDRDx is a
logic 0, reading address $0003 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 12-5 summarizes the operation of the port D pins.
Table 12-5. Port D Pin Functions
PTDPUE Bit
DDRD Bit
PTD Bit
I/O Pin Mode
1
0
X(1)
0
0
X
1
Accesses to DDRD
Accesses to PTD
Read/Write
Read
Write
Input, VDD(4)
DDRD7–DDRD0
Pin
PTD7–PTD0(3)
X
Input, Hi-Z(2)
DDRD7–DDRD0
Pin
PTD7–PTD0(3)
X
Output
DDRD7–DDRD0
PTD7–PTD0
PTD7–PTD0
Notes:
1. X = Don’t care
2. Hi-Z = High impedance
3. Writing affects data register, but does not affect input.
4. I/O pin pulled up to VDD by internal pullup device.
MC68HC908GP32 Data Sheet, Rev. 10
126
Freescale Semiconductor
Port E
12.5.3 Port D Input Pullup Enable Register
The port D input pullup enable register (PTDPUE) contains a software configurable pullup device for each
of the eight port D pins. Each bit is individually configurable and requires that the data direction register,
DDRD, bit be configured as an input. Each pullup is automatically and dynamically disabled when a port
bit’s DDRD is configured for output mode.
Address:
$000F
Read:
Write:
Bit 7
6
5
4
3
2
1
Bit 0
PTDPUE7
PTDPUE6
PTDPUE5
PTDPUE4
PTDPUE3
PTDPUE2
PTDPUE1
PTDPUE0
0
0
0
0
0
0
0
0
Reset:
Figure 12-16. Port D Input Pullup Enable Register (PTDPUE)
PTDPUE7–PTDPUE0 — Port D Input Pullup Enable Bits
These writable bits are software programmable to enable pullup devices on an input port bit.
1 = Corresponding port D pin configured to have internal pullup
0 = Corresponding port D pin has internal pullup disconnected
12.6 Port E
Port E is a 2-bit special-function port that shares two of its pins with the serial communications interface
(SCI) module.
12.6.1 Port E Data Register
The port E data register contains a data latch for each of the two port E pins.
Address:
Read:
$0008
Bit 7
6
5
4
3
2
0
0
0
0
0
0
Write:
Reset:
1
Bit 0
PTE1
PTE0
RxD
TxD
Unaffected by reset
Alternate Function:
= Unimplemented
Figure 12-17. Port E Data Register (PTE)
PTE1 and PTE0 — Port E Data Bits
PTE1 and PTE0 are read/write, software programmable bits. Data direction of each port E pin is under
the control of the corresponding bit in data direction register E.
NOTE
Data direction register E (DDRE) does not affect the data direction of port
E pins that are being used by the SCI module. However, the DDRE bits
always determine whether reading port E returns the states of the latches
or the states of the pins. See Table 12-6.
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
127
Input/Output (I/O) Ports
RxD — SCI Receive Data Input
The PTE1/RxD pin is the receive data input for the SCI module. When the enable SCI bit, ENSCI, is
clear, the SCI module is disabled, and the PTE1/RxD pin is available for general-purpose I/O. See
Chapter 13 Serial Communications Interface Module (SCI).
TxD — SCI Transmit Data Output
The PTE0/TxD pin is the transmit data output for the SCI module. When the enable SCI bit, ENSCI, is
clear, the SCI module is disabled, and the PTE0/TxD pin is available for general-purpose I/O. See
Chapter 13 Serial Communications Interface Module (SCI).
12.6.2 Data Direction Register E
Data direction register E (DDRE) determines whether each port E pin is an input or an output. Writing a
logic 1 to a DDRE bit enables the output buffer for the corresponding port E pin; a logic 0 disables the
output buffer.
Address:
Read:
$000C
Bit 7
6
5
4
3
2
0
0
0
0
0
0
0
0
0
0
0
Write:
Reset:
0
1
Bit 0
DDRE1
DDRE0
0
0
= Unimplemented
Figure 12-18. Data Direction Register E (DDRE)
DDRE1 and DDRE0 — Data Direction Register E Bits
These read/write bits control port E data direction. Reset clears DDRE1 and DDRE0, configuring all
port E pins as inputs.
1 = Corresponding port E pin configured as output
0 = Corresponding port E pin configured as input
NOTE
Avoid glitches on port E pins by writing to the port E data register before
changing data direction register E bits from 0 to 1.
Figure 12-19 shows the port E I/O logic.
INTERNAL DATA BUS
READ DDRE ($000C)
WRITE DDRE ($000C)
RESET
DDREx
WRITE PTE ($0008)
PTEx
PTEx
READ PTE ($0008)
Figure 12-19. Port E I/O Circuit
MC68HC908GP32 Data Sheet, Rev. 10
128
Freescale Semiconductor
Port E
When bit DDREx is a logic 1, reading address $0008 reads the PTEx data latch. When bit DDREx is a
logic 0, reading address $0008 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 12-6 summarizes the operation of the port E pins.
Table 12-6. Port E Pin Functions
DDRE Bit
0
1
PTE Bit
(1)
X
X
I/O Pin Mode
Input, Hi-Z
Output
(2)
Accesses to DDRE
Accesses to PTE
Read/Write
Read
Write
DDRE1–DDRE0
Pin
PTE1–PTE0(3)
DDRE1–DDRE0
PTE1–PTE0
PTE1–PTE0
Notes:
1. X = Don’t care
2. Hi-Z = High impedance
3. Writing affects data register, but does not affect input.
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
129
Input/Output (I/O) Ports
MC68HC908GP32 Data Sheet, Rev. 10
130
Freescale Semiconductor
Chapter 13
Serial Communications Interface Module (SCI)
13.1 Introduction
This section describes the serial communications interface (SCI) module, which allows high-speed
asynchronous communications with peripheral devices and other MCUs.
13.2 Features
Features of the SCI module include:
• Full-duplex operation
• Standard mark/space non-return-to-zero (NRZ) format
• 32 programmable baud rates
• Programmable 8-bit or 9-bit character length
• Separately enabled transmitter and receiver
• Separate receiver and transmitter CPU interrupt requests
• Programmable transmitter output polarity
• Two receiver wakeup methods:
– Idle line wakeup
– Address mark wakeup
• Interrupt-driven operation with eight interrupt flags:
– Transmitter empty
– Transmission complete
– Receiver full
– Idle receiver input
– Receiver overrun
– Noise error
– Framing error
– Parity error
• Receiver framing error detection
• Hardware parity checking
• 1/16 bit-time noise detection
• Configuration register bit, SCIBDSRC, to allow selection of baud rate clock source
13.3 Pin Name Conventions
The generic names of the SCI I/O pins are:
• RxD (receive data)
• TxD (transmit data)
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
131
Serial Communications Interface Module (SCI)
SCI I/O (input/output) lines are implemented by sharing parallel I/O port pins. The full name of an SCI
input or output reflects the name of the shared port pin. Table 13-1 shows the full names and the generic
names of the SCI I/O pins.
The generic pin names appear in the text of this section.
Table 13-1. Pin Name Conventions
Generic Pin Names:
RxD
TxD
Full Pin Names:
PTE1/RxD
PTE0/TxD
13.4 Functional Description
Figure 13-1 shows the structure of the SCI module. The SCI allows full-duplex, asynchronous, NRZ serial
communication among the MCU and remote devices, including other MCUs. The transmitter and receiver
of the SCI operate independently, although they use the same baud rate generator. During normal
operation, the CPU monitors the status of the SCI, writes the data to be transmitted, and processes
received data.
The baud rate clock source for the SCI can be selected via the configuration bit, SCIBDSRC, of the
CONFIG2 register ($001E). Source selection values are shown in Figure 13-1.
MC68HC908GP32 Data Sheet, Rev. 10
132
Freescale Semiconductor
Functional Description
INTERNAL BUS
SCI DATA
REGISTER
ERROR
INTERRUPT
CONTROL
RECEIVE
SHIFT REGISTER
PTE1/RxD
RECEIVER
INTERRUPT
CONTROL
TRANSMITTER
INTERRUPT
CONTROL
SCI DATA
REGISTER
TRANSMIT
SHIFT REGISTER
PTE0/TxD
TXINV
SCTIE
R8
TCIE
T8
SCRIE
ILIE
TE
SCTE
RE
TC
RWU
SCRF
SBK
IDLE
OR
ORIE
NF
NEIE
FE
FEIE
PE
PEIE
LOOPS
LOOPS
SCIBDSRC
FROM
CONFIG2
FLAG
CONTROL
RECEIVE
CONTROL
WAKEUP
CONTROL
ENSCI
ENSCI
TRANSMIT
CONTROL
BKF
M
RPF
WAKE
ILTY
CGMXCLK
BUS CLOCK
A SL
X
B
÷4
PRESCALER
PEN
BAUD
DIVIDER
SL = 0 => SCICLK = CGMXCLK
SL = 1 => SCICLK = BUS CLOCK
÷16
PTY
DATA SELECTION
CONTROL
Figure 13-1. SCI Module Block Diagram
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
133
Serial Communications Interface Module (SCI)
Addr.
$0013
$0014
$0015
$0016
$0017
$0018
Register Name
Read:
SCI Control Register 1
Write:
(SCC1)
Reset:
Read:
SCI Control Register 2
Write:
(SCC2)
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
LOOPS
ENSCI
TXINV
M
WAKE
ILTY
PEN
PTY
0
0
0
0
0
0
0
0
SCTIE
TCIE
SCRIE
ILIE
TE
RE
RWU
SBK
0
0
0
0
0
0
0
0
T8
R
R
ORIE
NEIE
FEIE
PEIE
Read:
R8
SCI Control Register 3
Write:
(SCC3)
Reset:
U
U
0
0
0
0
0
0
SCTE
TC
SCRF
IDLE
OR
NF
FE
PE
1
1
0
0
0
0
0
0
BKF
RPF
Read:
SCI Status Register 1
Write:
(SCS1)
Reset:
Read:
SCI Status Register 2
Write:
(SCS2)
Reset:
Read:
SCI Data Register
Write:
(SCDR)
Reset:
0
0
0
0
0
0
0
0
R7
R6
R5
R4
R3
R2
R1
R0
T7
T6
T5
T4
T3
T2
T1
T0
Unaffected by reset
Read:
$0019
SCI Baud Rate Register
Write:
(SCBR)
Reset:
0
SCP1
SCP0
R
SCR2
SCR1
SCR0
0
0
0
0
0
0
0
= Unimplemented
R
= Reserved U = Unaffected
Figure 13-2. SCI I/O Register Summary
13.4.1 Data Format
The SCI uses the standard non-return-to-zero mark/space data format illustrated in Figure 13-3.
8-BIT DATA FORMAT
BIT M IN SCC1 CLEAR
START
BIT
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
PARITY
BIT
BIT 6
BIT 7
9-BIT DATA FORMAT
BIT M IN SCC1 SET
START
BIT
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
STOP
BIT
NEXT
START
BIT
PARITY
BIT
BIT 6
BIT 7
BIT 8
STOP
BIT
NEXT
START
BIT
Figure 13-3. SCI Data Formats
MC68HC908GP32 Data Sheet, Rev. 10
134
Freescale Semiconductor
Functional Description
13.4.2 Transmitter
Figure 13-4 shows the structure of the SCI transmitter.
The baud rate clock source for the SCI can be selected via the configuration bit, SCIBDSRC. Source
selection values are shown in Figure 13-4.
SCIBDSRC
FROM
CONFIG2
SL
X
SL = 0 => SCICLK = CGMXCLK
SL = 1 => SCICLK = BUS CLOCK
÷4
INTERNAL BUS
PRESCALER
BAUD
DIVIDER
÷ 16
SCI DATA REGISTER
SCP1
11-BIT
TRANSMIT
SHIFT REGISTER
STOP
SCP0
SCR2
H
SCR1
8
7
6
5
4
3
2
START
CGMXCLK
BUS CLOCK
1
0
L
PTE0/TxD
MSB
SCR0
TXINV
T8
BREAK
ALL 0s
TRANSMITTER CPU
INTERRUPT REQUEST
PARITY
GENERATION
PREAMBLE
ALL 1s
PTY
SHIFT ENABLE
PEN
LOAD FROM SCDR
M
TRANSMITTER
CONTROL LOGIC
SCTE
SCTIE
TC
TCIE
SCTE
SCTIE
SBK
LOOPS
TC
ENSCI
TCIE
TE
Figure 13-4. SCI Transmitter Block Diagram
13.4.2.1 Character Length
The transmitter can accommodate either 8-bit or 9-bit data. The state of the M bit in SCI control register 1
(SCC1) determines character length. When transmitting 9-bit data, bit T8 in SCI control register 3 (SCC3)
is the ninth bit (bit 8).
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
135
Serial Communications Interface Module (SCI)
13.4.2.2 Character Transmission
During an SCI transmission, the transmit shift register shifts a character out to the PTE0/TxD pin. The SCI
data register (SCDR) is the write-only buffer between the internal data bus and the transmit shift register.
To initiate an SCI transmission:
1. Enable the SCI by writing a logic 1 to the enable SCI bit (ENSCI) in SCI control register 1 (SCC1).
2. Enable the transmitter by writing a logic 1 to the transmitter enable bit (TE) in SCI control register
2 (SCC2).
3. Clear the SCI transmitter empty bit by first reading SCI status register 1 (SCS1) and then writing
to the SCDR.
4. Repeat step 3 for each subsequent transmission.
At the start of a transmission, transmitter control logic automatically loads the transmit shift register with
a preamble of logic 1s. After the preamble shifts out, control logic transfers the SCDR data into the
transmit shift register. A logic 0 start bit automatically goes into the least significant bit position of the
transmit shift register. A logic 1 stop bit goes into the most significant bit position.
The SCI transmitter empty bit, SCTE, in SCS1 becomes set when the SCDR transfers a byte to the
transmit shift register. The SCTE bit indicates that the SCDR can accept new data from the internal data
bus. If the SCI transmit interrupt enable bit, SCTIE, in SCC2 is also set, the SCTE bit generates a
transmitter CPU interrupt request.
When the transmit shift register is not transmitting a character, the PTE0/TxD pin goes to the idle
condition, logic 1. If at any time software clears the ENSCI bit in SCI control register 1 (SCC1), the
transmitter and receiver relinquish control of the port E pins.
13.4.2.3 Break Characters
Writing a logic 1 to the send break bit, SBK, in SCC2 loads the transmit shift register with a break
character. A break character contains all logic 0s and has no start, stop, or parity bit. Break character
length depends on the M bit in SCC1. As long as SBK is at logic 1, transmitter logic continuously loads
break characters into the transmit shift register. After software clears the SBK bit, the shift register finishes
transmitting the last break character and then transmits at least one logic 1. The automatic logic 1 at the
end of a break character guarantees the recognition of the start bit of the next character.
The SCI recognizes a break character when a start bit is followed by eight or nine logic 0 data bits and a
logic 0 where the stop bit should be.
Receiving a break character has these effects on SCI registers:
• Sets the framing error bit (FE) in SCS1
• Sets the SCI receiver full bit (SCRF) in SCS1
• Clears the SCI data register (SCDR)
• Clears the R8 bit in SCC3
• Sets the break flag bit (BKF) in SCS2
• May set the overrun (OR), noise flag (NF), parity error (PE), or reception in progress flag (RPF) bits
13.4.2.4 Idle Characters
An idle character contains all logic 1s and has no start, stop, or parity bit. Idle character length depends
on the M bit in SCC1. The preamble is a synchronizing idle character that begins every transmission.
MC68HC908GP32 Data Sheet, Rev. 10
136
Freescale Semiconductor
Functional Description
If the TE bit is cleared during a transmission, the PTE0/TxD pin becomes idle after completion of the
transmission in progress. Clearing and then setting the TE bit during a transmission queues an idle
character to be sent after the character currently being transmitted.
NOTE
When queueing an idle character, return the TE bit to logic 1 before the stop
bit of the current character shifts out to the TxD pin. Setting TE after the
stop bit appears on TxD causes data previously written to the SCDR to be
lost.
Toggle the TE bit for a queued idle character when the SCTE bit becomes
set and just before writing the next byte to the SCDR.
13.4.2.5 Inversion of Transmitted Output
The transmit inversion bit (TXINV) in SCI control register 1 (SCC1) reverses the polarity of transmitted
data. All transmitted values, including idle, break, start, and stop bits, are inverted when TXINV is at
logic 1. (See 13.8.1 SCI Control Register 1.)
13.4.2.6 Transmitter Interrupts
These conditions can generate CPU interrupt requests from the SCI transmitter:
• SCI transmitter empty (SCTE) — The SCTE bit in SCS1 indicates that the SCDR has transferred
a character to the transmit shift register. SCTE can generate a transmitter CPU interrupt request.
Setting the SCI transmit interrupt enable bit, SCTIE, in SCC2 enables the SCTE bit to generate
transmitter CPU interrupt requests.
• Transmission complete (TC) — The TC bit in SCS1 indicates that the transmit shift register and
the SCDR are empty and that no break or idle character has been generated. The transmission
complete interrupt enable bit, TCIE, in SCC2 enables the TC bit to generate transmitter CPU
interrupt requests.
13.4.3 Receiver
Figure 13-5 shows the structure of the SCI receiver.
13.4.3.1 Character Length
The receiver can accommodate either 8-bit or 9-bit data. The state of the M bit in SCI control register 1
(SCC1) determines character length. When receiving 9-bit data, bit R8 in SCI control register 2 (SCC2)
is the ninth bit (bit 8). When receiving 8-bit data, bit R8 is a copy of the eighth bit (bit 7).
13.4.3.2 Character Reception
During an SCI reception, the receive shift register shifts characters in from the PTE1/RxD pin. The SCI
data register (SCDR) is the read-only buffer between the internal data bus and the receive shift register.
After a complete character shifts into the receive shift register, the data portion of the character transfers
to the SCDR. The SCI receiver full bit, SCRF, in SCI status register 1 (SCS1) becomes set, indicating that
the received byte can be read. If the SCI receive interrupt enable bit, SCRIE, in SCC2 is also set, the
SCRF bit generates a receiver CPU interrupt request.
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
137
Serial Communications Interface Module (SCI)
INTERNAL BUS
SCP0
SCR0
÷4
SL = 0 => SCICLK = CGMXCLK
SL = 1 => SCICLK = BUS CLOCK
PRESCALER
BAUD
DIVIDER
÷ 16
DATA
RECOVERY
PTE1/RxD
BKF
SCI DATA REGISTER
H
11-BIT
RECEIVE SHIFT REGISTER
8
7
M
ILTY
PEN
ERROR CPU
INTERRUPT REQUEST
PTY
6
5
4
3
2
1
0
L
ALL 0s
RPF
WAKE
START
SL
X
SCR1
STOP
CGMXCLK
BUS CLOCK
SCR2
SCP1
MSB
SCIBDSRC
FROM
CONFIG2
SCRF
WAKEUP
LOGIC
PARITY
CHECKING
OR
ORIE
NF
NEIE
FE
FEIE
PE
PEIE
RWU
IDLE
R8
OR
ORIE
NF
NEIE
FE
FEIE
PE
PEIE
Figure 13-5. SCI Receiver Block Diagram
MC68HC908GP32 Data Sheet, Rev. 10
138
Freescale Semiconductor
Functional Description
13.4.3.3 Data Sampling
The receiver samples the PTE1/RxD pin at the RT clock rate. The RT clock is an internal signal with a
frequency 16 times the baud rate. To adjust for baud rate mismatch, the RT clock is resynchronized at
the following times (see Figure 13-6):
• After every start bit
• After the receiver detects a data bit change from logic 1 to logic 0 (after the majority of data bit
samples at RT8, RT9, and RT10 returns a valid logic 1 and the majority of the next RT8, RT9, and
RT10 samples returns a valid logic 0)
To locate the start bit, data recovery logic does an asynchronous search for a logic 0 preceded by three
logic 1s. When the falling edge of a possible start bit occurs, the RT clock begins to count to 16.
START BIT
LSB
START BIT
VERIFICATION
DATA
SAMPLING
RT8
START BIT
QUALIFICATION
SAMPLES
RT3
PTE1/RxD
RT4
RT3
RT2
RT1
RT16
RT15
RT14
RT13
RT12
RT11
RT10
RT9
RT7
RT6
RT5
RT4
RT2
RT1
RT1
RT1
RT1
RT1
RT1
RT1
RT1
RT CLOCK
STATE
RT1
RT
CLOCK
RT CLOCK
RESET
Figure 13-6. Receiver Data Sampling
To verify the start bit and to detect noise, data recovery logic takes samples at RT3, RT5, and RT7.
Table 13-2 summarizes the results of the start bit verification samples.
Table 13-2. Start Bit Verification
RT3, RT5, and RT7
Samples
Start Bit
Verification
Noise Flag
000
Yes
0
001
Yes
1
010
Yes
1
011
No
0
100
Yes
1
101
No
0
110
No
0
111
No
0
Start bit verification is not successful if any two of the three verification samples are logic 1s. If start bit
verification is not successful, the RT clock is reset and a new search for a start bit begins.
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
139
Serial Communications Interface Module (SCI)
To determine the value of a data bit and to detect noise, recovery logic takes samples at RT8, RT9, and
RT10. Table 13-3 summarizes the results of the data bit samples.
Table 13-3. Data Bit Recovery
RT8, RT9, and RT10
Samples
Data Bit
Determination
Noise Flag
000
0
0
001
0
1
010
0
1
011
1
1
100
0
1
101
1
1
110
1
1
111
1
0
NOTE
The RT8, RT9, and RT10 samples do not affect start bit verification. If any
or all of the RT8, RT9, and RT10 start bit samples are logic 1s following a
successful start bit verification, the noise flag (NF) is set and the receiver
assumes that the bit is a start bit.
To verify a stop bit and to detect noise, recovery logic takes samples at RT8, RT9, and RT10. Table 13-4
summarizes the results of the stop bit samples.
Table 13-4. Stop Bit Recovery
RT8, RT9, and RT10
Samples
Framing
Error Flag
Noise Flag
000
1
0
001
1
1
010
1
1
011
0
1
100
1
1
101
0
1
110
0
1
111
0
0
13.4.3.4 Framing Errors
If the data recovery logic does not detect a logic 1 where the stop bit should be in an incoming character,
it sets the framing error bit, FE, in SCS1. A break character also sets the FE bit because a break character
has no stop bit. The FE bit is set at the same time that the SCRF bit is set.
13.4.3.5 Baud Rate Tolerance
A transmitting device may be operating at a baud rate below or above the receiver baud rate.
Accumulated bit time misalignment can cause one of the three stop bit data samples to fall outside the
actual stop bit. Then a noise error occurs. If more than one of the samples is outside the stop bit, a framing
MC68HC908GP32 Data Sheet, Rev. 10
140
Freescale Semiconductor
Functional Description
error occurs. In most applications, the baud rate tolerance is much more than the degree of misalignment
that is likely to occur.
As the receiver samples an incoming character, it resynchronizes the RT clock on any valid falling edge
within the character. Resynchronization within characters corrects misalignments between transmitter bit
times and receiver bit times.
Slow Data Tolerance
Figure 13-7 shows how much a slow received character can be misaligned without causing a noise error
or a framing error. The slow stop bit begins at RT8 instead of RT1 but arrives in time for the stop bit data
samples at RT8, RT9, and RT10.
RT16
RT15
RT14
RT13
RT12
RT11
RT10
RT9
RT8
RT7
RT6
STOP
RT5
RT4
RT3
RT2
RECEIVER
RT CLOCK
RT1
MSB
DATA
SAMPLES
Figure 13-7. Slow Data
For an 8-bit character, data sampling of the stop bit takes the receiver
9 bit times × 16 RT cycles + 10 RT cycles = 154 RT cycles.
With the misaligned character shown in Figure 13-7, the receiver counts 154 RT cycles at the point when
the count of the transmitting device is
9 bit times × 16 RT cycles + 3 RT cycles = 147 RT cycles.
The maximum percent difference between the receiver count and the transmitter count of a slow 8-bit
character with no errors is
154 – 147 × 100 = 4.54%
-------------------------154
For a 9-bit character, data sampling of the stop bit takes the receiver
10 bit times × 16 RT cycles + 10 RT cycles = 170 RT cycles.
With the misaligned character shown in Figure 13-7, the receiver counts 170 RT cycles at the point when
the count of the transmitting device is
10 bit times × 16 RT cycles + 3 RT cycles = 163 RT cycles.
The maximum percent difference between the receiver count and the transmitter count of a slow 9-bit
character with no errors is
170 – 163 × 100 = 4.12%
-------------------------170
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
141
Serial Communications Interface Module (SCI)
Fast Data Tolerance
Figure 13-8 shows how much a fast received character can be misaligned without causing a noise error
or a framing error. The fast stop bit ends at RT10 instead of RT16 but is still there for the stop bit data
samples at RT8, RT9, and RT10.
RT16
RT15
RT14
RT13
RT12
RT11
RT10
RT9
RT8
RT7
IDLE OR NEXT CHARACTER
RT6
RT5
RT4
RT3
RT2
RECEIVER
RT CLOCK
RT1
STOP
DATA
SAMPLES
Figure 13-8. Fast Data
For an 8-bit character, data sampling of the stop bit takes the receiver
9 bit times × 16 RT cycles + 10 RT cycles = 154 RT cycles.
With the misaligned character shown in Figure 13-8, the receiver counts 154 RT cycles at the point when
the count of the transmitting device is
10 bit times × 16 RT cycles = 160 RT cycles.
The maximum percent difference between the receiver count and the transmitter count of a fast 8-bit
character with no errors is
154 – 160 × 100 = 3.90%
˙
-------------------------154
For a 9-bit character, data sampling of the stop bit takes the receiver
10 bit times × 16 RT cycles + 10 RT cycles = 170 RT cycles.
With the misaligned character shown in Figure 13-8, the receiver counts 170 RT cycles at the point when
the count of the transmitting device is
11 bit times × 16 RT cycles = 176 RT cycles.
The maximum percent difference between the receiver count and the transmitter count of a fast 9-bit
character with no errors is
170 – 176 × 100 = 3.53%
-------------------------170
13.4.3.6 Receiver Wakeup
So that the MCU can ignore transmissions intended only for other receivers in multiple-receiver systems,
the receiver can be put into a standby state. Setting the receiver wakeup bit, RWU, in SCC2 puts the
receiver into a standby state during which receiver interrupts are disabled.
MC68HC908GP32 Data Sheet, Rev. 10
142
Freescale Semiconductor
Functional Description
Depending on the state of the WAKE bit in SCC1, either of two conditions on the PTE1/RxD pin can bring
the receiver out of the standby state:
• Address mark — An address mark is a logic 1 in the most significant bit position of a received
character. When the WAKE bit is set, an address mark wakes the receiver from the standby state
by clearing the RWU bit. The address mark also sets the SCI receiver full bit, SCRF. Software can
then compare the character containing the address mark to the user-defined address of the
receiver. If they are the same, the receiver remains awake and processes the characters that
follow. If they are not the same, software can set the RWU bit and put the receiver back into the
standby state.
• Idle input line condition — When the WAKE bit is clear, an idle character on the PTE1/RxD pin
wakes the receiver from the standby state by clearing the RWU bit. The idle character that wakes
the receiver does not set the receiver idle bit, IDLE, or the SCI receiver full bit, SCRF. The idle line
type bit, ILTY, determines whether the receiver begins counting logic 1s as idle character bits after
the start bit or after the stop bit.
NOTE
With the WAKE bit clear, setting the RWU bit after the RxD pin has been
idle may cause the receiver to wake up immediately.
13.4.3.7 Receiver Interrupts
The following sources can generate CPU interrupt requests from the SCI receiver:
• SCI receiver full (SCRF) — The SCRF bit in SCS1 indicates that the receive shift register has
transferred a character to the SCDR. SCRF can generate a receiver CPU interrupt request. Setting
the SCI receive interrupt enable bit, SCRIE, in SCC2 enables the SCRF bit to generate receiver
CPU interrupts.
• Idle input (IDLE) — The IDLE bit in SCS1 indicates that 10 or 11 consecutive logic 1s shifted in
from the PTE1/RxD pin. The idle line interrupt enable bit, ILIE, in SCC2 enables the IDLE bit to
generate CPU interrupt requests.
13.4.3.8 Error Interrupts
The following receiver error flags in SCS1 can generate CPU interrupt requests:
• Receiver overrun (OR) — The OR bit indicates that the receive shift register shifted in a new
character before the previous character was read from the SCDR. The previous character remains
in the SCDR, and the new character is lost. The overrun interrupt enable bit, ORIE, in SCC3
enables OR to generate SCI error CPU interrupt requests.
• Noise flag (NF) — The NF bit is set when the SCI detects noise on incoming data or break
characters, including start, data, and stop bits. The noise error interrupt enable bit, NEIE, in SCC3
enables NF to generate SCI error CPU interrupt requests.
• Framing error (FE) — The FE bit in SCS1 is set when a logic 0 occurs where the receiver expects
a stop bit. The framing error interrupt enable bit, FEIE, in SCC3 enables FE to generate SCI error
CPU interrupt requests.
• Parity error (PE) — The PE bit in SCS1 is set when the SCI detects a parity error in incoming data.
The parity error interrupt enable bit, PEIE, in SCC3 enables PE to generate SCI error CPU interrupt
requests.
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
143
Serial Communications Interface Module (SCI)
13.5 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power- consumption standby modes.
13.5.1 Wait Mode
The SCI module remains active after the execution of a WAIT instruction. In wait mode, the SCI module
registers are not accessible by the CPU. Any enabled CPU interrupt request from the SCI module can
bring the MCU out of wait mode.
If SCI module functions are not required during wait mode, reduce power consumption by disabling the
module before executing the WAIT instruction.
Refer to Chapter 3 Low-Power Modes for information on exiting wait mode.
13.5.2 Stop Mode
The SCI module is inactive after the execution of a STOP instruction. The STOP instruction does not
affect SCI register states. SCI module operation resumes after an external interrupt.
Because the internal clock is inactive during stop mode, entering stop mode during an SCI transmission
or reception results in invalid data.
Refer to Chapter 3 Low-Power Modes for information on exiting stop mode.
13.6 SCI During Break Module Interrupts
The system integration module (SIM) controls whether status bits in other modules can be cleared during
the break state. The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear
status bits during the break state.
To allow software to clear status bits during a break interrupt, write a logic 1 to the BCFE bit. If a status
bit is cleared during the break state, it remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its
default state), software can read and write I/O registers during the break state without affecting status bits.
Some status bits have a 2-step read/write clearing procedure. If software does the first step on such a bit
before the break, the bit cannot change during the break state as long as BCFE is at logic 0. After the
break, doing the second step clears the status bit.
13.7 I/O Signals
Port E shares two of its pins with the SCI module. The two SCI I/O pins are:
• PTE0/TxD — Transmit data
• PTE1/RxD — Receive data
13.7.1 PTE0/TxD (Transmit Data)
The PTE0/TxD pin is the serial data output from the SCI transmitter. The SCI shares the PTE0/TxD pin
with port E. When the SCI is enabled, the PTE0/TxD pin is an output regardless of the state of the DDRE2
bit in data direction register E (DDRE).
MC68HC908GP32 Data Sheet, Rev. 10
144
Freescale Semiconductor
I/O Registers
13.7.2 PTE1/RxD (Receive Data)
The PTE1/RxD pin is the serial data input to the SCI receiver. The SCI shares the PTE1/RxD pin with
port E. When the SCI is enabled, the PTE1/RxD pin is an input regardless of the state of the DDRE1 bit
in data direction register E (DDRE).
13.8 I/O Registers
These I/O registers control and monitor SCI operation:
• SCI control register 1 (SCC1)
• SCI control register 2 (SCC2)
• SCI control register 3 (SCC3)
• SCI status register 1 (SCS1)
• SCI status register 2 (SCS2)
• SCI data register (SCDR)
• SCI baud rate register (SCBR)
13.8.1 SCI Control Register 1
SCI control register 1:
• Enables loop mode operation
• Enables the SCI
• Controls output polarity
• Controls character length
• Controls SCI wakeup method
• Controls idle character detection
• Enables parity function
• Controls parity type
Address:
Read:
Write:
Reset:
$0013
Bit 7
6
5
4
3
2
1
Bit 0
LOOPS
ENSCI
TXINV
M
WAKE
ILTY
PEN
PTY
0
0
0
0
0
0
0
0
Figure 13-9. SCI Control Register 1 (SCC1)
LOOPS — Loop Mode Select Bit
This read/write bit enables loop mode operation. In loop mode the PTE1/RxD pin is disconnected from
the SCI, and the transmitter output goes into the receiver input. Both the transmitter and the receiver
must be enabled to use loop mode. Reset clears the LOOPS bit.
1 = Loop mode enabled
0 = Normal operation enabled
ENSCI — Enable SCI Bit
This read/write bit enables the SCI and the SCI baud rate generator. Clearing ENSCI sets the SCTE
and TC bits in SCI status register 1 and disables transmitter interrupts. Reset clears the ENSCI bit.
1 = SCI enabled
0 = SCI disabled
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
145
Serial Communications Interface Module (SCI)
TXINV — Transmit Inversion Bit
This read/write bit reverses the polarity of transmitted data. Reset clears the TXINV bit.
1 = Transmitter output inverted
0 = Transmitter output not inverted
NOTE
Setting the TXINV bit inverts all transmitted values, including idle, break,
start, and stop bits.
M — Mode (Character Length) Bit
This read/write bit determines whether SCI characters are eight or nine bits long. (See Table 13-5.)
The ninth bit can serve as an extra stop bit, as a receiver wakeup signal, or as a parity bit. Reset clears
the M bit.
1 = 9-bit SCI characters
0 = 8-bit SCI characters
WAKE — Wakeup Condition Bit
This read/write bit determines which condition wakes up the SCI: a logic 1 (address mark) in the most
significant bit position of a received character or an idle condition on the PTE1/RxD pin. Reset clears
the WAKE bit.
1 = Address mark wakeup
0 = Idle line wakeup
ILTY — Idle Line Type Bit
This read/write bit determines when the SCI starts counting logic 1s as idle character bits. The
counting begins either after the start bit or after the stop bit. If the count begins after the start bit, then
a string of logic 1s preceding the stop bit may cause false recognition of an idle character. Beginning
the count after the stop bit avoids false idle character recognition, but requires properly synchronized
transmissions. Reset clears the ILTY bit.
1 = Idle character bit count begins after stop bit
0 = Idle character bit count begins after start bit
PEN — Parity Enable Bit
This read/write bit enables the SCI parity function. (See Table 13-5.) When enabled, the parity function
inserts a parity bit in the most significant bit position. (See Figure 13-3.) Reset clears the PEN bit.
1 = Parity function enabled
0 = Parity function disabled
PTY — Parity Bit
This read/write bit determines whether the SCI generates and checks for odd parity or even parity.
(See Table 13-5.) Reset clears the PTY bit.
1 = Odd parity
0 = Even parity
NOTE
Changing the PTY bit in the middle of a transmission or reception can
generate a parity error.
MC68HC908GP32 Data Sheet, Rev. 10
146
Freescale Semiconductor
I/O Registers
Table 13-5. Character Format Selection
Control Bits
Character Format
M
PEN and PTY
Start Bits
Data Bits
Parity
Stop Bits
Character Length
0
0X
1
8
None
1
10 bits
1
0X
1
9
None
1
11 bits
0
10
1
7
Even
1
10 bits
0
11
1
7
Odd
1
10 bits
1
10
1
8
Even
1
11 bits
1
11
1
8
Odd
1
11 bits
13.8.2 SCI Control Register 2
SCI control register 2:
• Enables the following CPU interrupt requests:
– Enables the SCTE bit to generate transmitter CPU interrupt requests
– Enables the TC bit to generate transmitter CPU interrupt requests
– Enables the SCRF bit to generate receiver CPU interrupt requests
– Enables the IDLE bit to generate receiver CPU interrupt requests
• Enables the transmitter
• Enables the receiver
• Enables SCI wakeup
• Transmits SCI break characters
Address:
Read:
Write:
Reset:
$0014
Bit 7
6
5
4
3
2
1
Bit 0
SCTIE
TCIE
SCRIE
ILIE
TE
RE
RWU
SBK
0
0
0
0
0
0
0
0
Figure 13-10. SCI Control Register 2 (SCC2)
SCTIE — SCI Transmit Interrupt Enable Bit
This read/write bit enables the SCTE bit to generate SCI transmitter CPU interrupt requests. Reset
clears the SCTIE bit.
1 = SCTE enabled to generate CPU interrupt
0 = SCTE not enabled to generate CPU interrupt
TCIE — Transmission Complete Interrupt Enable Bit
This read/write bit enables the TC bit to generate SCI transmitter CPU interrupt requests. Reset clears
the TCIE bit.
1 = TC enabled to generate CPU interrupt requests
0 = TC not enabled to generate CPU interrupt requests
SCRIE — SCI Receive Interrupt Enable Bit
This read/write bit enables the SCRF bit to generate SCI receiver CPU interrupt requests. Reset clears
the SCRIE bit.
1 = SCRF enabled to generate CPU interrupt
0 = SCRF not enabled to generate CPU interrupt
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
147
Serial Communications Interface Module (SCI)
ILIE — Idle Line Interrupt Enable Bit
This read/write bit enables the IDLE bit to generate SCI receiver CPU interrupt requests. Reset clears
the ILIE bit.
1 = IDLE enabled to generate CPU interrupt requests
0 = IDLE not enabled to generate CPU interrupt requests
TE — Transmitter Enable Bit
Setting this read/write bit begins the transmission by sending a preamble of 10 or 11 logic 1s from the
transmit shift register to the PTE0/TxD pin. If software clears the TE bit, the transmitter completes any
transmission in progress before the PTE0/TxD returns to the idle condition (logic 1). Clearing and then
setting TE during a transmission queues an idle character to be sent after the character currently being
transmitted. Reset clears the TE bit.
1 = Transmitter enabled
0 = Transmitter disabled
NOTE
Writing to the TE bit is not allowed when the enable SCI bit (ENSCI) is clear.
ENSCI is in SCI control register 1.
RE — Receiver Enable Bit
Setting this read/write bit enables the receiver. Clearing the RE bit disables the receiver but does not
affect receiver interrupt flag bits. Reset clears the RE bit.
1 = Receiver enabled
0 = Receiver disabled
NOTE
Writing to the RE bit is not allowed when the enable SCI bit (ENSCI) is
clear. ENSCI is in SCI control register 1.
RWU — Receiver Wakeup Bit
This read/write bit puts the receiver in a standby state during which receiver interrupts are disabled.
The WAKE bit in SCC1 determines whether an idle input or an address mark brings the receiver out
of the standby state and clears the RWU bit. Reset clears the RWU bit.
1 = Standby state
0 = Normal operation
SBK — Send Break Bit
Setting and then clearing this read/write bit transmits a break character followed by a logic 1. The logic
1 after the break character guarantees recognition of a valid start bit. If SBK remains set, the
transmitter continuously transmits break characters with no logic 1s between them. Reset clears the
SBK bit.
1 = Transmit break characters
0 = No break characters being transmitted
NOTE
Do not toggle the SBK bit immediately after setting the SCTE bit. Toggling
SBK before the preamble begins causes the SCI to send a break character
instead of a preamble.
MC68HC908GP32 Data Sheet, Rev. 10
148
Freescale Semiconductor
I/O Registers
13.8.3 SCI Control Register 3
SCI control register 3:
• Stores the ninth SCI data bit received and the ninth SCI data bit to be transmitted
• Enables these interrupts:
– Receiver overrun interrupts
– Noise error interrupts
– Framing error interrupts
• Parity error interrupts
Address:
$0015
Bit 7
Read:
R8
Write:
Reset:
U
6
5
4
3
2
1
Bit 0
T8
R
R
ORIE
NEIE
FEIE
PEIE
U
0
0
0
0
0
0
= Unimplemented
R = Reserved
U = Unaffected
Figure 13-11. SCI Control Register 3 (SCC3)
R8 — Received Bit 8
When the SCI is receiving 9-bit characters, R8 is the read-only ninth bit (bit 8) of the received
character. R8 is received at the same time that the SCDR receives the other 8 bits.
When the SCI is receiving 8-bit characters, R8 is a copy of the eighth bit (bit 7). Reset has no effect
on the R8 bit.
T8 — Transmitted Bit 8
When the SCI is transmitting 9-bit characters, T8 is the read/write ninth bit (bit 8) of the transmitted
character. T8 is loaded into the transmit shift register at the same time that the SCDR is loaded into
the transmit shift register. Reset has no effect on the T8 bit.
ORIE — Receiver Overrun Interrupt Enable Bit
This read/write bit enables SCI error CPU interrupt requests generated by the receiver overrun bit, OR.
1 = SCI error CPU interrupt requests from OR bit enabled
0 = SCI error CPU interrupt requests from OR bit disabled
NEIE — Receiver Noise Error Interrupt Enable Bit
This read/write bit enables SCI error CPU interrupt requests generated by the noise error bit, NE.
Reset clears NEIE.
1 = SCI error CPU interrupt requests from NE bit enabled
0 = SCI error CPU interrupt requests from NE bit disabled
FEIE — Receiver Framing Error Interrupt Enable Bit
This read/write bit enables SCI error CPU interrupt requests generated by the framing error bit, FE.
Reset clears FEIE.
1 = SCI error CPU interrupt requests from FE bit enabled
0 = SCI error CPU interrupt requests from FE bit disabled
PEIE — Receiver Parity Error Interrupt Enable Bit
This read/write bit enables SCI error CPU interrupt requests generated by the parity error bit, PE.
(See 13.8.4 SCI Status Register 1.) Reset clears PEIE.
1 = SCI error CPU interrupt requests from PE bit enabled
0 = SCI error CPU interrupt requests from PE bit disabled
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
149
Serial Communications Interface Module (SCI)
13.8.4 SCI Status Register 1
SCI status register 1 (SCS1) contains flags to signal these conditions:
• Transfer of SCDR data to transmit shift register complete
• Transmission complete
• Transfer of receive shift register data to SCDR complete
• Receiver input idle
• Receiver overrun
• Noisy data
• Framing error
• Parity error
Address:
$0016
Bit 7
6
5
4
3
2
1
Bit 0
Read:
SCTE
TC
SCRF
IDLE
OR
NF
FE
PE
1
1
0
0
0
0
0
0
Write:
Reset:
= Unimplemented
Figure 13-12. SCI Status Register 1 (SCS1)
SCTE — SCI Transmitter Empty Bit
This clearable, read-only bit is set when the SCDR transfers a character to the transmit shift register.
SCTE can generate an SCI transmitter CPU interrupt request. When the SCTIE bit in SCC2 is set,
SCTE generates an SCI transmitter CPU interrupt request. In normal operation, clear the SCTE bit by
reading SCS1 with SCTE set and then writing to SCDR. Reset sets the SCTE bit.
1 = SCDR data transferred to transmit shift register
0 = SCDR data not transferred to transmit shift register
TC — Transmission Complete Bit
This read-only bit is set when the SCTE bit is set, and no data, preamble, or break character is being
transmitted. TC generates an SCI transmitter CPU interrupt request if the TCIE bit in SCC2 is also set.
TC is automatically cleared when data, preamble or break is queued and ready to be sent. There may
be up to 1.5 transmitter clocks of latency between queueing data, preamble, and break and the
transmission actually starting. Reset sets the TC bit.
1 = No transmission in progress
0 = Transmission in progress
SCRF — SCI Receiver Full Bit
This clearable, read-only bit is set when the data in the receive shift register transfers to the SCI data
register. SCRF can generate an SCI receiver CPU interrupt request. When the SCRIE bit in SCC2 is
set, SCRF generates a CPU interrupt request. In normal operation, clear the SCRF bit by reading
SCS1 with SCRF set and then reading the SCDR. Reset clears SCRF.
1 = Received data available in SCDR
0 = Data not available in SCDR
IDLE — Receiver Idle Bit
This clearable, read-only bit is set when 10 or 11 consecutive logic 1s appear on the receiver input.
IDLE generates an SCI receiver CPU interrupt request if the ILIE bit in SCC2 is also set. Clear the IDLE
bit by reading SCS1 with IDLE set and then reading the SCDR. After the receiver is enabled, it must
MC68HC908GP32 Data Sheet, Rev. 10
150
Freescale Semiconductor
I/O Registers
receive a valid character that sets the SCRF bit before an idle condition can set the IDLE bit. Also, after
the IDLE bit has been cleared, a valid character must again set the SCRF bit before an idle condition
can set the IDLE bit. Reset clears the IDLE bit.
1 = Receiver input idle
0 = Receiver input active (or idle since the IDLE bit was cleared)
OR — Receiver Overrun Bit
This clearable, read-only bit is set when software fails to read the SCDR before the receive shift
register receives the next character. The OR bit generates an SCI error CPU interrupt request if the
ORIE bit in SCC3 is also set. The data in the shift register is lost, but the data already in the SCDR is
not affected. Clear the OR bit by reading SCS1 with OR set and then reading the SCDR. Reset clears
the OR bit.
1 = Receive shift register full and SCRF = 1
0 = No receiver overrun
Software latency may allow an overrun to occur between reads of SCS1 and SCDR in the flag-clearing
sequence. Figure 13-13 shows the normal flag-clearing sequence and an example of an overrun
caused by a delayed flag-clearing sequence. The delayed read of SCDR does not clear the OR bit
because OR was not set when SCS1 was read. Byte 2 caused the overrun and is lost. The next
flag-clearing sequence reads byte 3 in the SCDR instead of byte 2.
In applications that are subject to software latency or in which it is important to know which byte is lost
due to an overrun, the flag-clearing routine can check the OR bit in a second read of SCS1 after
reading the data register.
NF — Receiver Noise Flag Bit
This clearable, read-only bit is set when the SCI detects noise on the PTE1/RxD pin. NF generates an
SCI error CPU interrupt request if the NEIE bit in SCC3 is also set. Clear the NF bit by reading SCS1
and then reading the SCDR. Reset clears the NF bit.
1 = Noise detected
0 = No noise detected
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
151
Serial Communications Interface Module (SCI)
FE — Receiver Framing Error Bit
This clearable, read-only bit is set when a logic 0 is accepted as the stop bit. FE generates an SCI error
CPU interrupt request if the FEIE bit in SCC3 also is set. Clear the FE bit by reading SCS1 with FE set
and then reading the SCDR. Reset clears the FE bit.
1 = Framing error detected
0 = No framing error detected
BYTE 1
BYTE 2
BYTE 3
SCRF = 0
SCRF = 1
SCRF = 0
SCRF = 1
SCRF = 0
SCRF = 1
NORMAL FLAG CLEARING SEQUENCE
BYTE 4
READ SCS1
SCRF = 1
OR = 0
READ SCS1
SCRF = 1
OR = 0
READ SCS1
SCRF = 1
OR = 0
READ SCDR
BYTE 1
READ SCDR
BYTE 2
READ SCDR
BYTE 3
BYTE 1
BYTE 2
BYTE 3
SCRF = 0
OR = 0
SCRF = 1
OR = 1
SCRF = 0
OR = 1
SCRF = 1
SCRF = 1
OR = 1
DELAYED FLAG CLEARING SEQUENCE
BYTE 4
READ SCS1
SCRF = 1
OR = 0
READ SCS1
SCRF = 1
OR = 1
READ SCDR
BYTE 1
READ SCDR
BYTE 3
Figure 13-13. Flag Clearing Sequence
PE — Receiver Parity Error Bit
This clearable, read-only bit is set when the SCI detects a parity error in incoming data. PE generates
an SCI error CPU interrupt request if the PEIE bit in SCC3 is also set. Clear the PE bit by reading SCS1
with PE set and then reading the SCDR. Reset clears the PE bit.
1 = Parity error detected
0 = No parity error detected
13.8.5 SCI Status Register 2
SCI status register 2 contains flags to signal the following conditions:
• Break character detected
• Incoming data
MC68HC908GP32 Data Sheet, Rev. 10
152
Freescale Semiconductor
I/O Registers
Address:
$0017
Bit 7
6
5
4
3
2
Read:
1
Bit 0
BKF
RPF
0
0
Write:
Reset:
0
0
0
0
0
0
= Unimplemented
Figure 13-14. SCI Status Register 2 (SCS2)
BKF — Break Flag Bit
This clearable, read-only bit is set when the SCI detects a break character on the PTE1/RxD pin. In
SCS1, the FE and SCRF bits are also set. In 9-bit character transmissions, the R8 bit in SCC3 is
cleared. BKF does not generate a CPU interrupt request. Clear BKF by reading SCS2 with BKF set
and then reading the SCDR. Once cleared, BKF can become set again only after logic 1s again appear
on the PTE1/RxD pin followed by another break character. Reset clears the BKF bit.
1 = Break character detected
0 = No break character detected
RPF — Reception in Progress Flag Bit
This read-only bit is set when the receiver detects a logic 0 during the RT1 time period of the start bit
search. RPF does not generate an interrupt request. RPF is reset after the receiver detects false start
bits (usually from noise or a baud rate mismatch) or when the receiver detects an idle character. Polling
RPF before disabling the SCI module or entering stop mode can show whether a reception is in
progress.
1 = Reception in progress
0 = No reception in progress
13.8.6 SCI Data Register
The SCI data register (SCDR) is the buffer between the internal data bus and the receive and transmit
shift registers. Reset has no effect on data in the SCI data register.
Address:
$0018
Bit 7
6
5
4
3
2
1
Bit 0
Read:
R7
R6
R5
R4
R3
R2
R1
R0
Write:
T7
T6
T5
T4
T3
T2
T1
T0
Reset:
Unaffected by reset
Figure 13-15. SCI Data Register (SCDR)
R7/T7–R0/T0 — Receive/Transmit Data Bits
Reading the SCDR accesses the read-only received data bits, R7:R0. Writing to the SCDR writes the
data to be transmitted, T7:T0. Reset has no effect on the SCDR.
NOTE
Do not use read/modify/write instructions on the SCI data register.
13.8.7 SCI Baud Rate Register
The baud rate register (SCBR) selects the baud rate for both the receiver and the transmitter.
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
153
Serial Communications Interface Module (SCI)
Address:
$0019
Bit 7
6
Read:
Write:
Reset:
0
5
4
3
2
1
Bit 0
SCP1
SCP0
R
SCR2
SCR1
SCR0
0
0
0
0
0
0
R
= Reserved
0
= Unimplemented
Figure 13-16. SCI Baud Rate Register (SCBR)
SCP1 and SCP0 — SCI Baud Rate Prescaler Bits
These read/write bits select the baud rate prescaler divisor as shown in Table 13-6. Reset clears SCP1
and SCP0.
Table 13-6. SCI Baud Rate Prescaling
SCP1 and SCP0
Prescaler Divisor (PD)
00
1
01
3
10
4
11
13
SCR2–SCR0 — SCI Baud Rate Select Bits
These read/write bits select the SCI baud rate divisor as shown in Table 13-7. Reset clears
SCR2–SCR0.
Table 13-7. SCI Baud Rate Selection
SCR2, SCR1, and SCR0
Baud Rate Divisor (BD)
000
1
001
2
010
4
011
8
100
16
101
32
110
64
111
128
Use this formula to calculate the SCI baud rate:
SCI clock source
baud rate = --------------------------------------------64 × PD × BD
where:
SCI clock source = fBUS or CGMXCLK (selected by SCIBDSRC bit in CONFIG2 register)
PD = prescaler divisor
BD = baud rate divisor
Table 13-8 shows the SCI baud rates that can be generated with a 4.9152-MHz bus clock when fBUS is
selected as SCI clock source.
MC68HC908GP32 Data Sheet, Rev. 10
154
Freescale Semiconductor
I/O Registers
Table 13-8. SCI Baud Rate Selection Examples
SCP1 and SCP0
Prescaler
Divisor (PD)
SCR2, SCR1,
and SCR0
Baud Rate
Divisor (BD)
Baud Rate
(fBUS = 4.9152 MHz)
00
1
000
1
76,800
00
1
001
2
38,400
00
1
010
4
19,200
00
1
011
8
9600
00
1
100
16
4800
00
1
101
32
2400
00
1
110
64
1200
00
1
111
128
600
01
3
000
1
25,600
01
3
001
2
12,800
01
3
010
4
6400
01
3
011
8
3200
01
3
100
16
1600
01
3
101
32
800
01
3
110
64
400
01
3
111
128
200
10
4
000
1
19,200
10
4
001
2
9600
10
4
010
4
4800
10
4
011
8
2400
10
4
100
16
1200
10
4
101
32
600
10
4
110
64
300
10
4
111
128
150
11
13
000
1
5908
11
13
001
2
2954
11
13
010
4
1477
11
13
011
8
739
11
13
100
16
369
11
13
101
32
185
11
13
110
64
92
11
13
111
128
46
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
155
Serial Communications Interface Module (SCI)
MC68HC908GP32 Data Sheet, Rev. 10
156
Freescale Semiconductor
Chapter 14
System Integration Module (SIM)
14.1 Introduction
This section describes the system integration module (SIM). Together with the CPU, the SIM controls all
MCU activities. A block diagram of the SIM is shown in Figure 14-1. Table 14-1 is a summary of the SIM
input/output (I/O) registers. The SIM is a system state controller that coordinates CPU and exception
timing. The SIM is responsible for:
• Bus clock generation and control for CPU and peripherals:
– Stop/wait/reset/break entry and recovery
– Internal clock control
• Master reset control, including power-on reset (POR) and COP timeout
• Interrupt arbitration
Table 14-1 shows the internal signal names used in this section.
Table 14-1. Signal Name Conventions
Signal Name
CGMXCLK
Description
Buffered version of OSC1 from clock generator module (CGM)
CGMVCLK
PLL output
CGMOUT
PLL-based or OSC1-based clock output from CGM module
(Bus clock = CGMOUT divided by two)
IAB
Internal address bus
IDB
Internal data bus
PORRST
Signal from the power-on reset module to the SIM
IRST
Internal reset signal
R/W
Read/write signal
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
157
System Integration Module (SIM)
MODULE STOP
MODULE WAIT
CPU STOP (FROM CPU)
CPU WAIT (FROM CPU)
STOP/WAIT
CONTROL
SIMOSCEN (TO CGM)
SIM
COUNTER
COP CLOCK
CGMXCLK (FROM CGM)
CGMOUT (FROM CGM)
÷2
CLOCK
CONTROL
VDD
CLOCK GENERATORS
INTERNAL CLOCKS
INTERNAL
PULLUP
DEVICE
RESET
PIN LOGIC
LVI (FROM LVI MODULE)
POR CONTROL
MASTER
RESET
CONTROL
RESET PIN CONTROL
ILLEGAL OPCODE (FROM CPU)
ILLEGAL ADDRESS (FROM ADDRESS
MAP DECODERS)
COP (FROM COP MODULE)
SIM RESET STATUS REGISTER
RESET
INTERRUPT SOURCES
INTERRUPT CONTROL
AND PRIORITY DECODE
CPU INTERFACE
Figure 14-1. SIM Block Diagram
Addr.
$FE00
Register Name
Read:
SIM Break Status Register
Write:
(SBSR)
Reset:
Bit 7
6
5
4
3
2
R
R
R
R
R
R
1
SBSW
Note
Bit 0
R
0
Note: Writing a logic 0 clears SBSW.
$FE01
$FE02
Read:
SIM Reset Status Register
Write:
(SRSR)
POR:
Read:
SIM Upper Byte Address
Write:
Register (SUBAR)
Reset:
POR
PIN
COP
ILOP
ILAD
MODRST
LVI
0
1
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
R
= Reserved
= Unimplemented
Figure 14-2. SIM I/O Register Summary
MC68HC908GP32 Data Sheet, Rev. 10
158
Freescale Semiconductor
SIM Bus Clock Control and Generation
Addr.
Register Name
Read:
$FE03
$FE04
$FE05
$FE06
SIM Break Flag Control
Write:
Register (SBFCR)
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
BCFE
R
R
R
R
R
R
R
0
Read:
Interrupt Status Register 1
Write:
(INT1)
Reset:
IF6
IF5
IF4
IF3
IF2
IF1
0
0
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
Read:
Interrupt Status Register 2
Write:
(INT2)
Reset:
IF14
IF13
IF12
IF11
IF10
IF9
IF8
IF7
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
Read:
Interrupt Status Register 3
Write:
(INT3)
Reset:
0
0
0
0
0
0
IF16
IF15
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
R
= Reserved
0
= Unimplemented
Figure 14-2. SIM I/O Register Summary (Continued)
14.2 SIM Bus Clock Control and Generation
The bus clock generator provides system clock signals for the CPU and peripherals on the MCU. The
system clocks are generated from an incoming clock, CGMOUT, as shown in Figure 14-3. This clock can
come from either an external oscillator or from the on-chip PLL. (See Chapter 5 Clock Generator Module
(CGM).)
OSC2
OSCILLATOR (OSC)
CGMXCLK
OSC1
TO TIMTB15A, ADC
SIM
OSCSTOPENB
FROM
CONFIG
SIMOSCEN
SIM COUNTER
CGMRCLK
CGMOUT
÷2
PHASE-LOCKED LOOP (PLL)
IT12
TO REST
OF CHIP
BUS CLOCK
GENERATORS
IT23
TO REST
OF CHIP
PTC3
SIMDIV2
MONITOR MODE
USER MODE
Figure 14-3. CGM Clock Signals
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
159
System Integration Module (SIM)
14.2.1 Bus Timing
In user mode, the internal bus frequency is either the crystal oscillator output (CGMXCLK) divided by four
or the PLL output (CGMVCLK) divided by four.
14.2.2 Clock Startup from POR or LVI Reset
When the power-on reset module or the low-voltage inhibit module generates a reset, the clocks to the
CPU and peripherals are inactive and held in an inactive phase until after the 4096 CGMXCLK cycle POR
timeout has completed. The RST pin is driven low by the SIM during this entire period. The IBUS clocks
start upon completion of the timeout.
14.2.3 Clocks in Stop Mode and Wait Mode
Upon exit from stop mode by an interrupt, break, or reset, the SIM allows CGMXCLK to clock the SIM
counter. The CPU and peripheral clocks do not become active until after the stop delay timeout. This
timeout is selectable as 4096 or 32 CGMXCLK cycles. (See 14.6.2 Stop Mode.)
In wait mode, the CPU clocks are inactive. The SIM also produces two sets of clocks for other modules.
Refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode.
Some modules can be programmed to be active in wait mode.
14.3 Reset and System Initialization
The MCU has these reset sources:
• Power-on reset module (POR)
• External reset pin (RST)
• Computer operating properly module (COP)
• Low-voltage inhibit module (LVI)
• Illegal opcode
• Illegal address
All of these resets produce the vector $FFFE:$FFFF ($FEFE:$FEFF in monitor mode) and assert the
internal reset signal (IRST). IRST causes all registers to be returned to their default values and all
modules to be returned to their reset states.
An internal reset clears the SIM counter (see 14.4 SIM Counter), but an external reset does not. Each of
the resets sets a corresponding bit in the SIM reset status register (SRSR). (See 14.7 SIM Registers.)
14.3.1 External Pin Reset
The RST pin circuit includes an internal pullup device. Pulling the asynchronous RST pin low halts all
processing. The PIN bit of the SIM reset status register (SRSR) is set as long as RST is held low for a
minimum of 67 CGMXCLK cycles, assuming that neither the POR nor the LVI was the source of the reset.
See Table 14-2 for details. Figure 14-4 shows the relative timing.
Table 14-2. Reset Recovery Type
Reset Recovery Type
Actual Number of Cycles
POR/LVI
4163 (4096 + 64 + 3)
All others
67 (64 + 3)
MC68HC908GP32 Data Sheet, Rev. 10
160
Freescale Semiconductor
Reset and System Initialization
CGMOUT
RST
IAB
VECT H VECT L
PC
Figure 14-4. External Reset Timing
14.3.2 Active Resets from Internal Sources
All internal reset sources actively pull the RST pin low for 32 CGMXCLK cycles to allow resetting of
external peripherals. The internal reset signal IRST continues to be asserted for an additional 32 cycles.
See Figure 14-5. An internal reset can be caused by an illegal address, illegal opcode, COP timeout, LVI,
or POR. (See Figure 14-6.)
NOTE
For LVI or POR resets, the SIM cycles through 4096 + 32 CGMXCLK
cycles during which the SIM forces the RST pin low. The internal reset
signal then follows the sequence from the falling edge of RST shown in
Figure 14-5.
IRST
RST
RST PULLED LOW BY MCU
32 CYCLES
32 CYCLES
CGMXCLK
IAB
VECTOR HIGH
Figure 14-5. Internal Reset Timing
The COP reset is asynchronous to the bus clock.
ILLEGAL ADDRESS RST
ILLEGAL OPCODE RST
COPRST
LVI
POR
INTERNAL RESET
Figure 14-6. Sources of Internal Reset
The active reset feature allows the part to issue a reset to peripherals and other chips within a system
built around the MCU.
14.3.2.1 Power-On Reset
When power is first applied to the MCU, the power-on reset module (POR) generates a pulse to indicate
that power-on has occurred. The external reset pin (RST) is held low while the SIM counter counts out
4096 + 32 CGMXCLK cycles. Thirty-two CGMXCLK cycles later, the CPU and memories are released
from reset to allow the reset vector sequence to occur.
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
161
System Integration Module (SIM)
At power-on, these events occur:
• A POR pulse is generated.
• The internal reset signal is asserted.
• The SIM enables CGMOUT.
• Internal clocks to the CPU and modules are held inactive for 4096 CGMXCLK cycles to allow
stabilization of the oscillator.
• The RST pin is driven low during the oscillator stabilization time.
• The POR bit of the SIM reset status register (SRSR) is set and all other bits in the register are
cleared.
OSC1
PORRST
4096
CYCLES
32
CYCLES
32
CYCLES
CGMXCLK
CGMOUT
RST
IRST
IAB
$FFFE
$FFFF
Figure 14-7. POR Recovery
14.3.2.2 Computer Operating Properly (COP) Reset
An input to the SIM is reserved for the COP reset signal. The overflow of the COP counter causes an
internal reset and sets the COP bit in the SIM reset status register (SRSR). The SIM actively pulls down
the RST pin for all internal reset sources.
To prevent a COP module timeout, write any value to location $FFFF. Writing to location $FFFF clears
the COP counter and bits 12 through 5 of the SIM counter. The SIM counter output, which occurs at least
every 8176 CGMXCLK cycles, drives the COP counter. The COP should be serviced as soon as possible
out of reset to guarantee the maximum amount of time before the first timeout.
The COP module is disabled if the RST pin or the IRQ pin is held at VTST while the MCU is in monitor
mode. The COP module can be disabled only through combinational logic conditioned with the high
voltage signal on the RST or the IRQ pin. This prevents the COP from becoming disabled as a result of
external noise. During a break state, VTST on the RST pin disables the COP module.
14.3.2.3 Illegal Opcode Reset
The SIM decodes signals from the CPU to detect illegal instructions. An illegal instruction sets the ILOP
bit in the SIM reset status register (SRSR) and causes a reset.
MC68HC908GP32 Data Sheet, Rev. 10
162
Freescale Semiconductor
SIM Counter
If the stop enable bit, STOP, in the mask option register is logic 0, the SIM treats the STOP instruction as
an illegal opcode and causes an illegal opcode reset. The SIM actively pulls down the RST pin for all
internal reset sources.
14.3.2.4 Illegal Address Reset
An opcode fetch from an unmapped address generates an illegal address reset. The SIM verifies that the
CPU is fetching an opcode prior to asserting the ILAD bit in the SIM reset status register (SRSR) and
resetting the MCU. A data fetch from an unmapped address does not generate a reset. The SIM actively
pulls down the RST pin for all internal reset sources.
14.3.2.5 Low-Voltage Inhibit (LVI) Reset
The low-voltage inhibit module (LVI) asserts its output to the SIM when the VDD voltage falls to the
LVITRIPF voltage. The LVI bit in the SIM reset status register (SRSR) is set, and the external reset pin
(RST) is held low while the SIM counter counts out 4096 + 32 CGMXCLK cycles. Thirty-two CGMXCLK
cycles later, the CPU is released from reset to allow the reset vector sequence to occur. The SIM actively
pulls down the RST pin for all internal reset sources.
14.3.2.6 Monitor Mode Entry Module Reset (MODRST)
The monitor mode entry module reset (MODRST) asserts its output to the SIM when monitor mode is
entered in the condition where the reset vectors are blank ($FF). (see 18.3 Monitor Module (MON)) When
MODRST gets asserted, an internal reset occurs. The SIM actively pulls down the RST pin for all internal
reset sources.
14.4 SIM Counter
The SIM counter is used by the power-on reset module (POR) and in stop mode recovery to allow the
oscillator time to stabilize before enabling the internal bus (IBUS) clocks. The SIM counter also serves as
a prescaler for the computer operating properly module (COP). The SIM counter overflow supplies the
clock for the COP module. The SIM counter is 13 bits long and is clocked by the falling edge of
CGMXCLK.
14.4.1 SIM Counter During Power-On Reset
The power-on reset module (POR) detects power applied to the MCU. At power-on, the POR circuit
asserts the signal PORRST. Once the SIM is initialized, it enables the clock generation module (CGM) to
drive the bus clock state machine.
14.4.2 SIM Counter During Stop Mode Recovery
The SIM counter also is used for stop mode recovery. The STOP instruction clears the SIM counter. After
an interrupt, break, or reset, the SIM senses the state of the short stop recovery bit, SSREC, in the mask
option register. If the SSREC bit is a logic 1, then the stop recovery is reduced from the normal delay of
4096 CGMXCLK cycles down to 32 CGMXCLK cycles. This is ideal for applications using canned
oscillators that do not require long startup times from stop mode. External crystal applications should use
the full stop recovery time, that is, with SSREC cleared.
14.4.3 SIM Counter and Reset States
External reset has no effect on the SIM counter. (See 14.6.2 Stop Mode for details.) The SIM counter is
free-running after all reset states. (See 14.3.2 Active Resets from Internal Sources for counter control and
internal reset recovery sequences.)
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
163
System Integration Module (SIM)
14.5 Exception Control
Normal, sequential program execution can be changed in three different ways:
• Interrupts:
– Maskable hardware CPU interrupts
– Non-maskable software interrupt instruction (SWI)
• Reset
• Break interrupts
14.5.1 Interrupts
At the beginning of an interrupt, the CPU saves the CPU register contents on the stack and sets the
interrupt mask (I bit) to prevent additional interrupts. At the end of an interrupt, the RTI instruction recovers
the CPU register contents from the stack so that normal processing can resume. Figure 14-8 shows
interrupt entry timing. Figure 14-9 shows interrupt recovery timing.
Interrupts are latched, and arbitration is performed in the SIM at the start of interrupt processing. The
arbitration result is a constant that the CPU uses to determine which vector to fetch. Once an interrupt is
latched by the SIM, no other interrupt can take precedence, regardless of priority, until the latched
interrupt is serviced (or the I bit is cleared). (See Figure 14-10.)
MODULE
INTERRUPT
I BIT
IAB
IDB
DUMMY
SP
DUMMY
SP – 1
SP – 2
PC – 1[7:0] PC – 1[15:8]
SP – 3
X
SP – 4
A
VECT H
CCR
VECT L
V DATA H
START ADDR
V DATA L
OPCODE
R/W
Figure 14-8. Interrupt Entry Timing
MODULE
INTERRUPT
I BIT
IAB
IDB
SP – 4
SP – 3
CCR
SP – 2
A
SP – 1
X
SP
PC
PC – 1 [15:8] PC – 1 [7:0]
PC + 1
OPCODE
OPERAND
R/W
Figure 14-9. Interrupt Recovery Timing
MC68HC908GP32 Data Sheet, Rev. 10
164
Freescale Semiconductor
Exception Control
FROM RESET
BREAK
I BIT
SET?
INTERRUPT?
YES
NO
YES
I BIT SET?
NO
IRQ
INTERRUPT?
YES
NO
AS MANY INTERRUPTS
AS EXIST ON CHIP
STACK CPU REGISTERS
SET I BIT
LOAD PC WITH INTERRUPT VECTOR
FETCH NEXT
INSTRUCTION
SWI
INSTRUCTION?
YES
NO
RTI
INSTRUCTION?
YES
UNSTACK CPU REGISTERS
NO
EXECUTE INSTRUCTION
Figure 14-10. Interrupt Processing
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
165
System Integration Module (SIM)
14.5.1.1 Hardware Interrupts
A hardware interrupt does not stop the current instruction. Processing of a hardware interrupt begins after
completion of the current instruction. When the current instruction is complete, the SIM checks all pending
hardware interrupts. If interrupts are not masked (I bit clear in the condition code register) and if the
corresponding interrupt enable bit is set, the SIM proceeds with interrupt processing; otherwise, the next
instruction is fetched and executed.
If more than one interrupt is pending at the end of an instruction execution, the highest priority interrupt
is serviced first. Figure 14-11 demonstrates what happens when two interrupts are pending. If an interrupt
is pending upon exit from the original interrupt service routine, the pending interrupt is serviced before the
LDA instruction is executed.
CLI
BACKGROUND
ROUTINE
LDA #$FF
INT1
PSHH
INT1 INTERRUPT SERVICE ROUTINE
PULH
RTI
INT2
PSHH
INT2 INTERRUPT SERVICE ROUTINE
PULH
RTI
Figure 14-11. Interrupt Recognition Example
The LDA opcode is prefetched by both the INT1 and INT2 RTI instructions. However, in the case of the
INT1 RTI prefetch, this is a redundant operation.
NOTE
To maintain compatibility with the M6805 Family, the H register is not
pushed on the stack during interrupt entry. If the interrupt service routine
modifies the H register or uses the indexed addressing mode, software
should save the H register and then restore it prior to exiting the routine.
14.5.1.2 SWI Instruction
The SWI instruction is a non-maskable instruction that causes an interrupt regardless of the state of the
interrupt mask (I bit) in the condition code register.
NOTE
A software interrupt pushes PC onto the stack. A software interrupt does
not push PC – 1, as a hardware interrupt does.
MC68HC908GP32 Data Sheet, Rev. 10
166
Freescale Semiconductor
Exception Control
14.5.1.3 Interrupt Status Registers
The flags in the interrupt status registers identify maskable interrupt sources. Table 14-3 summarizes the
interrupt sources and the interrupt status register flags that they set. The interrupt status registers can be
useful for debugging.
Table 14-3. Interrupt Sources
Priority
Interrupt Source
Interrupt Status
Register Flag
Highest
Reset
—
SWI instruction
—
IRQ pin
IF1
PLL
IF2
TIM1 channel 0
IF3
TIM1 channel 1
IF4
TIM1 overflow
IF5
TIM2 channel 0
IF6
TIM2 channel 1
IF7
TIM2 overflow
IF8
SPI receiver full
IF9
SPI transmitter empty
IF10
SCI receive error
IF11
SCI receive
IF12
SCI transmit
IF13
Keyboard
IF14
ADC conversion complete
IF15
Timebase module
IF16
Lowest
Interrupt Status Register 1
Address:
$FE04
Bit 7
6
5
4
3
2
1
Bit 0
Read:
IF6
IF5
IF4
IF3
IF2
IF1
0
0
Write:
R
R
R
R
R
R
R
R
Reset:
0
0
0
0
0
0
0
0
R
= Reserved
Figure 14-12. Interrupt Status Register 1 (INT1)
IF6–IF1 — Interrupt Flags 1–6
These flags indicate the presence of interrupt requests from the sources shown in Table 14-3.
1 = Interrupt request present
0 = No interrupt request present
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
167
System Integration Module (SIM)
Bit 0 and Bit 1 — Always read 0
Interrupt Status Register 2
Address:
$FE05
Bit 7
6
5
4
3
2
1
Bit 0
Read:
IF14
IF13
IF12
IF11
IF10
IF9
IF8
IF7
Write:
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
R
= Reserved
Reset:
Figure 14-13. Interrupt Status Register 2 (INT2)
IF14–IF7 — Interrupt Flags 14–7
These flags indicate the presence of interrupt requests from the sources shown in Table 14-3.
1 = Interrupt request present
0 = No interrupt request present
Interrupt Status Register 3
Address:
$FE06
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
0
0
0
0
0
IF16
IF15
Write:
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
R
= Reserved
Reset:
Figure 14-14. Interrupt Status Register 3 (INT3)
Bits 7–2 — Always read 0
IF16–IF15 — Interrupt Flags 16–15
These flags indicate the presence of an interrupt request from the source shown in Table 14-3.
1 = Interrupt request present
0 = No interrupt request present
14.5.2 Reset
All reset sources always have equal and highest priority and cannot be arbitrated.
14.5.3 Break Interrupts
The break module can stop normal program flow at a software-programmable break point by asserting
its break interrupt output. (See Chapter 17 Timer Interface Module (TIM).) The SIM puts the CPU into the
break state by forcing it to the SWI vector location. Refer to the break interrupt subsection of each module
to see how each module is affected by the break state.
MC68HC908GP32 Data Sheet, Rev. 10
168
Freescale Semiconductor
Low-Power Modes
14.5.4 Status Flag Protection in Break Mode
The SIM controls whether status flags contained in other modules can be cleared during break mode. The
user can select whether flags are protected from being cleared by properly initializing the break clear flag
enable bit (BCFE) in the SIM break flag control register (SBFCR).
Protecting flags in break mode ensures that set flags will not be cleared while in break mode. This
protection allows registers to be freely read and written during break mode without losing status flag
information.
Setting the BCFE bit enables the clearing mechanisms. Once cleared in break mode, a flag remains
cleared even when break mode is exited. Status flags with a 2-step clearing mechanism — for example,
a read of one register followed by the read or write of another — are protected, even when the first step
is accomplished prior to entering break mode. Upon leaving break mode, execution of the second step
will clear the flag as normal.
14.6 Low-Power Modes
Executing the WAIT or STOP instruction puts the MCU in a low power-consumption mode for standby
situations. The SIM holds the CPU in a non-clocked state. The operation of each of these modes is
described in the following subsections. Both STOP and WAIT clear the interrupt mask (I) in the condition
code register, allowing interrupts to occur.
14.6.1 Wait Mode
In wait mode, the CPU clocks are inactive while the peripheral clocks continue to run. Figure 14-15 shows
the timing for wait mode entry.
A module that is active during wait mode can wake up the CPU with an interrupt if the interrupt is enabled.
Stacking for the interrupt begins one cycle after the WAIT instruction during which the interrupt occurred.
In wait mode, the CPU clocks are inactive. Refer to the wait mode subsection of each module to see if
the module is active or inactive in wait mode. Some modules can be programmed to be active in wait
mode.
Wait mode also can be exited by a reset (or break in emulation mode). A break interrupt during wait mode
sets the SIM break stop/wait bit, SBSW, in the SIM break status register (SBSR). If the COP disable bit,
COPD, in the mask option register is logic 0, then the computer operating properly module (COP) is
enabled and remains active in wait mode.
IAB
IDB
WAIT ADDR
WAIT ADDR + 1
PREVIOUS DATA
SAME
NEXT OPCODE
SAME
SAME
SAME
R/W
Note:
Previous data can be operand data or the WAIT opcode, depending on the
last instruction.
Figure 14-15. Wait Mode Entry Timing
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
169
System Integration Module (SIM)
Figure 14-16 and Figure 14-17 show the timing for WAIT recovery.
IAB
$6E0B
IDB
$A6
$A6
$6E0C
$A6
$01
$00FF
$0B
$00FE
$00FD
$00FC
$6E
EXITSTOPWAIT
Note: EXITSTOPWAIT = RST pin, CPU interrupt, or break interrupt
Figure 14-16. Wait Recovery from Interrupt or Break
32
CYCLES
IAB
IDB
$6E0B
$A6
$A6
32
CYCLES
RST VCT H RST VCT L
$A6
RST
CGMXCLK
Figure 14-17. Wait Recovery from Internal Reset
14.6.2 Stop Mode
In stop mode, the SIM counter is reset and the system clocks are disabled. An interrupt request from a
module can cause an exit from stop mode. Stacking for interrupts begins after the selected stop recovery
time has elapsed. Reset or break also causes an exit from stop mode.
The SIM disables the clock generator module outputs (CGMOUT and CGMXCLK) in stop mode, stopping
the CPU and peripherals. Stop recovery time is selectable using the SSREC bit in the mask option
register (MOR). If SSREC is set, stop recovery is reduced from the normal delay of 4096 CGMXCLK
cycles down to 32. This is ideal for applications using canned oscillators that do not require long startup
times from stop mode.
NOTE
External crystal applications should use the full stop recovery time by
clearing the SSREC bit unless the OSCSTOPEN bit is set in CONFIG2.
MC68HC908GP32 Data Sheet, Rev. 10
170
Freescale Semiconductor
SIM Registers
The SIM counter is held in reset from the execution of the STOP instruction until the beginning of stop
recovery. It is then used to time the recovery period. Figure 14-18 shows stop mode entry timing.
NOTE
To minimize stop current, all pins configured as inputs should be driven to
a logic 1 or logic 0.
CPUSTOP
IAB
IDB
STOP ADDR
STOP ADDR + 1
PREVIOUS DATA
SAME
SAME
NEXT OPCODE
SAME
SAME
R/W
Note : Previous data can be operand data or the STOP opcode, depending
on the last instruction.
Figure 14-18. Stop Mode Entry Timing
STOP RECOVERY PERIOD
CGMXCLK
INT/BREAK
IAB
STOP +1
STOP + 2
STOP + 2
SP
SP – 1
SP – 2
SP – 3
Figure 14-19. Stop Mode Recovery from Interrupt or Break
14.7 SIM Registers
The SIM has three memory-mapped registers. Table 14-4 shows the mapping of these registers.
Table 14-4. SIM Registers
Address
Register
Access Mode
$FE00
SBSR
User
$FE01
SRSR
User
$FE03
SBFCR
User
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
171
System Integration Module (SIM)
14.7.1 SIM Break Status Register
The SIM break status register (SBSR) contains a flag to indicate that a break caused an exit from wait
mode.
Address:
Read:
Write:
$FE00
Bit 7
6
5
4
3
2
R
R
R
R
R
R
R
= Reserved
1
SBSW
Note
Reset:
Bit 0
R
0
Note: Writing a logic 0 clears SBSW.
Figure 14-20. SIM Break Status Register (SBSR)
SBSW — SIM Break Stop/Wait
SBSW can be read within the break state SWI routine. The user can modify the return address on the
stack by subtracting one from it.
1 = Wait mode was exited by break interrupt.
0 = Wait mode was not exited by break interrupt.
14.7.2 SIM Reset Status Register
The SRSR register contains flags that show the source of the last reset. The status register will
automatically clear after reading SRSR. A power-on reset sets the POR bit and clears all other bits in the
register. All other reset sources set the individual flag bits but do not clear the register. More than one
reset source can be flagged at any time depending on the conditions at the time of the internal or external
reset. For example, the POR and LVI bit can both be set if the power supply has a slow rise time.
Address:
Read:
$FE01
Bit 7
6
5
4
3
2
1
Bit 0
POR
PIN
COP
ILOP
ILAD
MODRST
LVI
0
1
0
0
0
0
0
0
0
Write:
Reset:
= Unimplemented
Figure 14-21. SIM Reset Status Register (SRSR)
POR — Power-On Reset Bit
1 = Last reset caused by POR circuit
0 = Read of SRSR
PIN — External Reset Bit
1 = Last reset caused by external reset pin (RST)
0 = POR or read of SRSR
COP — Computer Operating Properly Reset Bit
1 = Last reset caused by COP counter
0 = POR or read of SRSR
MC68HC908GP32 Data Sheet, Rev. 10
172
Freescale Semiconductor
SIM Registers
ILOP — Illegal Opcode Reset Bit
1 = Last reset caused by an illegal opcode
0 = POR or read of SRSR
ILAD — Illegal Address Reset Bit (opcode fetches only)
1 = Last reset caused by an opcode fetch from an illegal address
0 = POR or read of SRSR
MODRST — Monitor Mode Entry Module Reset Bit
1 = Last reset caused by monitor mode entry when vector locations $FFFE and $FFFF are $FF after
POR while IRQ ≠ VTST
0 = POR or read of SRSR
LVI — Low-Voltage Inhibit Reset Bit
1 = Last reset caused by the LVI circuit
0 = POR or read of SRSR
14.7.3 SIM Break Flag Control Register
The SIM break control register contains a bit that enables software to clear status bits while the MCU is
in a break state.
Address:
Read:
Write:
Reset:
$FE03
Bit 7
6
5
4
3
2
1
Bit 0
BCFE
R
R
R
R
R
R
R
0
R
= Reserved
Figure 14-22. SIM Break Flag Control Register (SBFCR)
BCFE — Break Clear Flag Enable Bit
This read/write bit enables software to clear status bits by accessing status registers while the MCU is
in a break state. To clear status bits during the break state, the BCFE bit must be set.
1 = Status bits clearable during break
0 = Status bits not clearable during break
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
173
System Integration Module (SIM)
MC68HC908GP32 Data Sheet, Rev. 10
174
Freescale Semiconductor
Chapter 15
Serial Peripheral Interface Module (SPI)
15.1 Introduction
This section describes the serial peripheral interface (SPI) module, which allows full-duplex,
synchronous, serial communications with peripheral devices.
15.2 Features
Features of the SPI module include:
• Full-duplex operation
• Master and slave modes
• Double-buffered operation with separate transmit and receive registers
• Four master mode frequencies (maximum = bus frequency ÷ 2)
• Maximum slave mode frequency = bus frequency
• Serial clock with programmable polarity and phase
• Two separately enabled interrupts:
– SPRF (SPI receiver full)
– SPTE (SPI transmitter empty)
• Mode fault error flag with CPU interrupt capability
• Overflow error flag with CPU interrupt capability
• Programmable wired-OR mode
• I/O (input/output) port bit(s) software configurable with pullup device(s) if configured as input port
bit(s)
15.3 Pin Name Conventions
The text that follows describes the SPI. The SPI I/O pin names are SS (slave select), SPSCK (SPI serial
clock), CGND (clock ground), MOSI (master out slave in), and MISO (master in/slave out). The SPI
shares four I/O pins with four parallel I/O ports.
The full names of the SPI I/O pins are shown in Table 15-1. The generic pin names appear in the text that
follows.
Table 15-1. Pin Name Conventions
SPI Generic
Pin Names:
Full SPI
Pin Names:
SPI
MISO
MOSI
SS
SPSCK
CGND
PTD1/MISO
PTD2/MOSI
PTD0/SS
PTD3/SPSCK
VSS
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
175
Serial Peripheral Interface Module (SPI)
15.4 Functional Description
Figure 15-1 summarizes the SPI I/O registers and Figure 15-2 shows the structure of the SPI module.
Addr.
Register Name
Read:
$0010 SPI Control Register (SPCR) Write:
Reset:
$0011
Read:
SPI Status and Control
Write:
Register (SPSCR)
Reset:
Read:
$0012
SPI Data Register
Write:
(SPDR)
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
SPRIE
R
SPMSTR
CPOL
CPHA
SPWOM
SPE
SPTIE
0
0
1
0
1
0
0
0
OVRF
MODF
SPTE
MODFEN
SPR1
SPR0
SPRF
ERRIE
0
0
0
0
1
0
0
0
R7
R6
R5
R4
R3
R2
R1
R0
T7
T6
T5
T4
T3
T2
T1
T0
Unaffected by reset
= Unimplemented
R
= Reserved
Figure 15-1. SPI I/O Register Summary
The SPI module allows full-duplex, synchronous, serial communication between the MCU and peripheral
devices, including other MCUs. Software can poll the SPI status flags or SPI operation can be
interrupt-driven.
If a port bit is configured for input, then an internal pullup device may be enabled for that port bit. (See
12.4.3 Port C Input Pullup Enable Register.)
The following paragraphs describe the operation of the SPI module.
15.4.1 Master Mode
The SPI operates in master mode when the SPI master bit, SPMSTR, is set.
NOTE
Configure the SPI modules as master or slave before enabling them.
Enable the master SPI before enabling the slave SPI. Disable the slave SPI
before disabling the master SPI. (See 15.13.1 SPI Control Register.)
Only a master SPI module can initiate transmissions. Software begins the transmission from a master SPI
module by writing to the transmit data register. If the shift register is empty, the byte immediately transfers
to the shift register, setting the SPI transmitter empty bit, SPTE. The byte begins shifting out on the MOSI
pin under the control of the serial clock. (See Figure 15-3.)
The SPR1 and SPR0 bits control the baud rate generator and determine the speed of the shift register.
(See 15.13.2 SPI Status and Control Register.) Through the SPSCK pin, the baud rate generator of the
master also controls the shift register of the slave peripheral.
As the byte shifts out on the MOSI pin of the master, another byte shifts in from the slave on the master’s
MISO pin. The transmission ends when the receiver full bit, SPRF, becomes set. At the same time that
SPRF becomes set, the byte from the slave transfers to the receive data register. In normal operation,
SPRF signals the end of a transmission. Software clears SPRF by reading the SPI status and control
register with SPRF set and then reading the SPI data register. Writing to the SPI data register clears the
SPTE bit.
MC68HC908GP32 Data Sheet, Rev. 10
176
Freescale Semiconductor
Functional Description
INTERNAL BUS
TRANSMIT DATA REGISTER
SHIFT REGISTER
BUSCLK
7
6
5
4
3
2
1
MISO
0
÷2
MOSI
÷8
CLOCK
DIVIDER
RECEIVE DATA REGISTER
÷ 32
PIN
CONTROL
LOGIC
÷ 128
SPMSTR
SPE
CLOCK
SELECT
SPR1
SPSCK
M
CLOCK
LOGIC
S
SS
SPR0
SPMSTR
TRANSMITTER CPU INTERRUPT REQUEST
CPHA
MODFEN
CPOL
SPWOM
ERRIE
SPI
CONTROL
SPTIE
RECEIVER/ERROR CPU INTERRUPT REQUEST
SPRIE
SPE
SPRF
SPTE
OVRF
MODF
Figure 15-2. SPI Module Block Diagram
MASTER MCU
SHIFT REGISTER
SLAVE MCU
MISO
MISO
MOSI
MOSI
SPSCK
BAUD RATE
GENERATOR
SS
SHIFT REGISTER
SPSCK
VDD
SS
Figure 15-3. Full-Duplex Master-Slave Connections
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
177
Serial Peripheral Interface Module (SPI)
15.4.2 Slave Mode
The SPI operates in slave mode when the SPMSTR bit is clear. In slave mode, the SPSCK pin is the input
for the serial clock from the master MCU. Before a data transmission occurs, the SS pin of the slave SPI
must be at logic 0. SS must remain low until the transmission is complete. (See 15.7.2 Mode Fault Error.)
In a slave SPI module, data enters the shift register under the control of the serial clock from the master
SPI module. After a byte enters the shift register of a slave SPI, it transfers to the receive data register,
and the SPRF bit is set. To prevent an overflow condition, slave software then must read the receive data
register before another full byte enters the shift register.
The maximum frequency of the SPSCK for an SPI configured as a slave is the bus clock speed (which is
twice as fast as the fastest master SPSCK clock that can be generated). The frequency of the SPSCK for
an SPI configured as a slave does not have to correspond to any SPI baud rate. The baud rate only
controls the speed of the SPSCK generated by an SPI configured as a master. Therefore, the frequency
of the SPSCK for an SPI configured as a slave can be any frequency less than or equal to the bus speed.
When the master SPI starts a transmission, the data in the slave shift register begins shifting out on the
MISO pin. The slave can load its shift register with a new byte for the next transmission by writing to its
transmit data register. The slave must write to its transmit data register at least one bus cycle before the
master starts the next transmission. Otherwise, the byte already in the slave shift register shifts out on the
MISO pin. Data written to the slave shift register during a transmission remains in a buffer until the end of
the transmission.
When the clock phase bit (CPHA) is set, the first edge of SPSCK starts a transmission. When CPHA is
clear, the falling edge of SS starts a transmission. (See 15.5 Transmission Formats.)
NOTE
SPSCK must be in the proper idle state before the slave is enabled to
prevent SPSCK from appearing as a clock edge.
15.5 Transmission Formats
During an SPI transmission, data is simultaneously transmitted (shifted out serially) and received (shifted
in serially). A serial clock synchronizes shifting and sampling on the two serial data lines. A slave select
line allows selection of an individual slave SPI device; slave devices that are not selected do not interfere
with SPI bus activities. On a master SPI device, the slave select line can optionally be used to indicate
multiple-master bus contention.
15.5.1 Clock Phase and Polarity Controls
Software can select any of four combinations of serial clock (SPSCK) phase and polarity using two bits
in the SPI control register (SPCR). The clock polarity is specified by the CPOL control bit, which selects
an active high or low clock and has no significant effect on the transmission format.
The clock phase (CPHA) control bit selects one of two fundamentally different transmission formats. The
clock phase and polarity should be identical for the master SPI device and the communicating slave
device. In some cases, the phase and polarity are changed between transmissions to allow a master
device to communicate with peripheral slaves having different requirements.
NOTE
Before writing to the CPOL bit or the CPHA bit, disable the SPI by clearing
the SPI enable bit (SPE).
MC68HC908GP32 Data Sheet, Rev. 10
178
Freescale Semiconductor
Transmission Formats
15.5.2 Transmission Format When CPHA = 0
Figure 15-4 shows an SPI transmission in which CPHA is logic 0. The figure should not be used as a
replacement for data sheet parametric information.
Two waveforms are shown for SPSCK: one for CPOL = 0 and another for CPOL = 1. The diagram may
be interpreted as a master or slave timing diagram since the serial clock (SPSCK), master in/slave out
(MISO), and master out/slave in (MOSI) pins are directly connected between the master and the slave.
The MISO signal is the output from the slave, and the MOSI signal is the output from the master. The SS
line is the slave select input to the slave. The slave SPI drives its MISO output only when its slave select
input (SS) is at logic 0, so that only the selected slave drives to the master. The SS pin of the master is
not shown but is assumed to be inactive. The SS pin of the master must be high or must be reconfigured
as general-purpose I/O not affecting the SPI. (See 15.7.2 Mode Fault Error.) When CPHA = 0, the first
SPSCK edge is the MSB capture strobe. Therefore, the slave must begin driving its data before the first
SPSCK edge, and a falling edge on the SS pin is used to start the slave data transmission. The slave’s
SS pin must be toggled back to high and then low again between each byte transmitted as shown in
Figure 15-5.
SPSCK CYCLE #
FOR REFERENCE
1
2
3
4
5
6
7
8
MSB
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
LSB
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
LSB
SPSCK; CPOL = 0
SPSCK; CPOL =1
MOSI
FROM MASTER
MISO
FROM SLAVE
MSB
SS; TO SLAVE
CAPTURE STROBE
Figure 15-4. Transmission Format (CPHA = 0)
MISO/MOSI
BYTE 1
BYTE 2
BYTE 3
MASTER SS
SLAVE SS
CPHA = 0
SLAVE SS
CPHA = 1
Figure 15-5. CPHA/SS Timing
When CPHA = 0 for a slave, the falling edge of SS indicates the beginning of the transmission. This
causes the SPI to leave its idle state and begin driving the MISO pin with the MSB of its data. Once the
transmission begins, no new data is allowed into the shift register from the transmit data register.
Therefore, the SPI data register of the slave must be loaded with transmit data before the falling edge of
SS. Any data written after the falling edge is stored in the transmit data register and transferred to the shift
register after the current transmission.
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
179
Serial Peripheral Interface Module (SPI)
15.5.3 Transmission Format When CPHA = 1
Figure 15-6 shows an SPI transmission in which CPHA is logic 1. The figure should not be used as a
replacement for data sheet parametric information. Two waveforms are shown for SPSCK: one for
CPOL = 0 and another for CPOL = 1. The diagram may be interpreted as a master or slave timing
diagram since the serial clock (SPSCK), master in/slave out (MISO), and master out/slave in (MOSI) pins
are directly connected between the master and the slave. The MISO signal is the output from the slave,
and the MOSI signal is the output from the master. The SS line is the slave select input to the slave. The
slave SPI drives its MISO output only when its slave select input (SS) is at logic 0, so that only the selected
slave drives to the master. The SS pin of the master is not shown but is assumed to be inactive. The SS
pin of the master must be high or must be reconfigured as general-purpose I/O not affecting the SPI. (See
15.7.2 Mode Fault Error.) When CPHA = 1, the master begins driving its MOSI pin on the first SPSCK
edge. Therefore, the slave uses the first SPSCK edge as a start transmission signal. The SS pin can
remain low between transmissions. This format may be preferable in systems having only one master and
only one slave driving the MISO data line.
SPSCK CYCLE #
FOR REFERENCE
1
2
3
4
5
6
7
8
MOSI
FROM MASTER
MSB
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
LSB
MISO
FROM SLAVE
MSB
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
SPSCK; CPOL = 0
SPSCK; CPOL =1
LSB
SS; TO SLAVE
CAPTURE STROBE
Figure 15-6. Transmission Format (CPHA = 1)
When CPHA = 1 for a slave, the first edge of the SPSCK indicates the beginning of the transmission. This
causes the SPI to leave its idle state and begin driving the MISO pin with the MSB of its data. Once the
transmission begins, no new data is allowed into the shift register from the transmit data register.
Therefore, the SPI data register of the slave must be loaded with transmit data before the first edge of
SPSCK. Any data written after the first edge is stored in the transmit data register and transferred to the
shift register after the current transmission.
15.5.4 Transmission Initiation Latency
When the SPI is configured as a master (SPMSTR = 1), writing to the SPDR starts a transmission. CPHA
has no effect on the delay to the start of the transmission, but it does affect the initial state of the SPSCK
signal. When CPHA = 0, the SPSCK signal remains inactive for the first half of the first SPSCK cycle.
When CPHA = 1, the first SPSCK cycle begins with an edge on the SPSCK line from its inactive to its
active level. The SPI clock rate (selected by SPR1:SPR0) affects the delay from the write to SPDR and
the start of the SPI transmission. (See Figure 15-7.) The internal SPI clock in the master is a free-running
derivative of the internal MCU clock. To conserve power, it is enabled only when both the SPE and
SPMSTR bits are set. SPSCK edges occur halfway through the low time of the internal MCU clock. Since
the SPI clock is free-running, it is uncertain where the write to the SPDR occurs relative to the slower
MC68HC908GP32 Data Sheet, Rev. 10
180
Freescale Semiconductor
Queuing Transmission Data
SPSCK. This uncertainty causes the variation in the initiation delay shown in Figure 15-7. This delay is
no longer than a single SPI bit time. That is, the maximum delay is two MCU bus cycles for DIV2, eight
MCU bus cycles for DIV8, 32 MCU bus cycles for DIV32, and 128 MCU bus cycles for DIV128.
WRITE
TO SPDR
INITIATION DELAY
BUS
CLOCK
MOSI
MSB
BIT 6
1
2
BIT 5
SPSCK
CPHA = 1
SPSCK
CPHA = 0
SPSCK CYCLE
NUMBER
3
INITIATION DELAY FROM WRITE SPDR TO TRANSFER BEGIN
WRITE
TO SPDR
BUS
CLOCK
EARLIEST
LATEST
WRITE
TO SPDR
SPSCK = INTERNAL CLOCK ÷ 2;
2 POSSIBLE START POINTS
BUS
CLOCK
EARLIEST
WRITE
TO SPDR
SPSCK = INTERNAL CLOCK ÷ 8;
8 POSSIBLE START POINTS
LATEST
SPSCK = INTERNAL CLOCK ÷ 32;
32 POSSIBLE START POINTS
LATEST
SPSCK = INTERNAL CLOCK ÷ 128;
128 POSSIBLE START POINTS
LATEST
BUS
CLOCK
EARLIEST
WRITE
TO SPDR
BUS
CLOCK
EARLIEST
Figure 15-7. Transmission Start Delay (Master)
15.6 Queuing Transmission Data
The double-buffered transmit data register allows a data byte to be queued and transmitted. For an SPI
configured as a master, a queued data byte is transmitted immediately after the previous transmission
has completed. The SPI transmitter empty flag (SPTE) indicates when the transmit data buffer is ready
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
181
Serial Peripheral Interface Module (SPI)
to accept new data. Write to the transmit data register only when the SPTE bit is high. Figure 15-8 shows
the timing associated with doing back-to-back transmissions with the SPI (SPSCK has CPHA: CPOL =
1:0).
WRITE TO SPDR
1
SPTE
3
2
8
5
10
SPSCK
CPHA:CPOL = 1:0
MSB BIT BIT BIT BIT BIT BIT LSB MSB BIT BIT BIT BIT BIT BIT LSB MSB BIT BIT BIT
6 5 4 3 2 1
6 5 4 3 2 1
6 5 4
BYTE 1
BYTE 2
BYTE 3
MOSI
4
SPRF
9
6
READ SPSCR
11
7
READ SPDR
12
1 CPU WRITES BYTE 1 TO SPDR, CLEARING SPTE BIT.
7 CPU READS SPDR, CLEARING SPRF BIT.
2 BYTE 1 TRANSFERS FROM TRANSMIT DATA
REGISTER TO SHIFT REGISTER, SETTING SPTE BIT.
8 CPU WRITES BYTE 3 TO SPDR, QUEUEING BYTE
3 AND CLEARING SPTE BIT.
9 SECOND INCOMING BYTE TRANSFERS FROM SHIFT
REGISTER TO RECEIVE DATA REGISTER, SETTING
SPRF BIT.
10 BYTE 3 TRANSFERS FROM TRANSMIT DATA
REGISTER TO SHIFT REGISTER, SETTING SPTE BIT.
11 CPU READS SPSCR WITH SPRF BIT SET.
3 CPU WRITES BYTE 2 TO SPDR, QUEUEING BYTE 2
AND CLEARING SPTE BIT.
4 FIRST INCOMING BYTE TRANSFERS FROM SHIFT
REGISTER TO RECEIVE DATA REGISTER, SETTING
SPRF BIT.
5 BYTE 2 TRANSFERS FROM TRANSMIT DATA
REGISTER TO SHIFT REGISTER, SETTING SPTE BIT.
6 CPU READS SPSCR WITH SPRF BIT SET.
12 CPU READS SPDR, CLEARING SPRF BIT.
Figure 15-8. SPRF/SPTE CPU Interrupt Timing
The transmit data buffer allows back-to-back transmissions without the slave precisely timing its writes
between transmissions as in a system with a single data buffer. Also, if no new data is written to the data
buffer, the last value contained in the shift register is the next data word to be transmitted.
For an idle master or idle slave that has no data loaded into its transmit buffer, the SPTE is set again no
more than two bus cycles after the transmit buffer empties into the shift register. This allows the user to
queue up a 16-bit value to send. For an already active slave, the load of the shift register cannot occur
until the transmission is completed. This implies that a back-to-back write to the transmit data register is
not possible. The SPTE indicates when the next write can occur.
15.7 Error Conditions
The following flags signal SPI error conditions:
• Overflow (OVRF) — Failing to read the SPI data register before the next full byte enters the shift
register sets the OVRF bit. The new byte does not transfer to the receive data register, and the
unread byte still can be read. OVRF is in the SPI status and control register.
• Mode fault error (MODF) — The MODF bit indicates that the voltage on the slave select pin (SS)
is inconsistent with the mode of the SPI. MODF is in the SPI status and control register.
MC68HC908GP32 Data Sheet, Rev. 10
182
Freescale Semiconductor
Error Conditions
15.7.1 Overflow Error
The overflow flag (OVRF) becomes set if the receive data register still has unread data from a previous
transmission when the capture strobe of bit 1 of the next transmission occurs. The bit 1 capture strobe
occurs in the middle of SPSCK cycle 7. (See Figure 15-4 and Figure 15-6.) If an overflow occurs, all data
received after the overflow and before the OVRF bit is cleared does not transfer to the receive data
register and does not set the SPI receiver full bit (SPRF). The unread data that transferred to the receive
data register before the overflow occurred can still be read. Therefore, an overflow error always indicates
the loss of data. Clear the overflow flag by reading the SPI status and control register and then reading
the SPI data register.
OVRF generates a receiver/error CPU interrupt request if the error interrupt enable bit (ERRIE) is also
set. The SPRF, MODF, and OVRF interrupts share the same CPU interrupt vector. (See Figure 15-11.)
It is not possible to enable MODF or OVRF individually to generate a receiver/error CPU interrupt request.
However, leaving MODFEN low prevents MODF from being set.
If the CPU SPRF interrupt is enabled and the OVRF interrupt is not, watch for an overflow condition.
Figure 15-9 shows how it is possible to miss an overflow. The first part of Figure 15-9 shows how it is
possible to read the SPSCR and SPDR to clear the SPRF without problems. However, as illustrated by
the second transmission example, the OVRF bit can be set in between the time that SPSCR and SPDR
are read.
BYTE 1
BYTE 2
BYTE 3
BYTE 4
1
4
6
8
SPRF
OVRF
READ
SPSCR
2
READ
SPDR
5
3
7
1
BYTE 1 SETS SPRF BIT.
2
CPU READS SPSCR WITH SPRF BIT SET
AND OVRF BIT CLEAR.
CPU READS BYTE 1 IN SPDR,
CLEARING SPRF BIT.
BYTE 2 SETS SPRF BIT.
3
4
5
CPU READS SPSCR WITH SPRF BIT SET
AND OVRF BIT CLEAR.
6
BYTE 3 SETS OVRF BIT. BYTE 3 IS LOST.
7
CPU READS BYTE 2 IN SPDR, CLEARING SPRF BIT,
BUT NOT OVRF BIT.
8
BYTE 4 FAILS TO SET SPRF BIT BECAUSE
OVRF BIT IS NOT CLEARED. BYTE 4 IS LOST.
Figure 15-9. Missed Read of Overflow Condition
In this case, an overflow can be missed easily. Since no more SPRF interrupts can be generated until this
OVRF is serviced, it is not obvious that bytes are being lost as more transmissions are completed. To
prevent this, either enable the OVRF interrupt or do another read of the SPSCR following the read of the
SPDR. This ensures that the OVRF was not set before the SPRF was cleared and that future
transmissions can set the SPRF bit. Figure 15-10 illustrates this process. Generally, to avoid this second
SPSCR read, enable the OVRF to the CPU by setting the ERRIE bit.
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
183
Serial Peripheral Interface Module (SPI)
BYTE 1
SPI RECEIVE
COMPLETE
BYTE 2
5
1
BYTE 3
7
BYTE 4
11
SPRF
OVRF
READ
SPSCR
2
READ
SPDR
4
3
1
BYTE 1 SETS SPRF BIT.
2
CPU READS SPSCR WITH SPRF BIT SET
AND OVRF BIT CLEAR.
CPU READS BYTE 1 IN SPDR,
CLEARING SPRF BIT.
3
6
9
8
12
10
14
13
8
CPU READS BYTE 2 IN SPDR,
CLEARING SPRF BIT.
9
CPU READS SPSCR AGAIN
TO CHECK OVRF BIT.
10 CPU READS BYTE 2 SPDR,
CLEARING OVRF BIT.
4
CPU READS SPSCR AGAIN
TO CHECK OVRF BIT.
5
BYTE 2 SETS SPRF BIT.
12 CPU READS SPSCR.
6
CPU READS SPSCR WITH SPRF BIT SET
AND OVRF BIT CLEAR.
13 CPU READS BYTE 4 IN SPDR,
CLEARING SPRF BIT.
7
BYTE 3 SETS OVRF BIT. BYTE 3 IS LOST.
14 CPU READS SPSCR AGAIN
TO CHECK OVRF BIT.
11 BYTE 4 SETS SPRF BIT.
Figure 15-10. Clearing SPRF When OVRF Interrupt Is Not Enabled
15.7.2 Mode Fault Error
Setting the SPMSTR bit selects master mode and configures the SPSCK and MOSI pins as outputs and
the MISO pin as an input. Clearing SPMSTR selects slave mode and configures the SPSCK and MOSI
pins as inputs and the MISO pin as an output. The mode fault bit, MODF, becomes set any time the state
of the slave select pin, SS, is inconsistent with the mode selected by SPMSTR.
To prevent SPI pin contention and damage to the MCU, a mode fault error occurs if:
• The SS pin of a slave SPI goes high during a transmission
• The SS pin of a master SPI goes low at any time
For the MODF flag to be set, the mode fault error enable bit (MODFEN) must be set. Clearing the
MODFEN bit does not clear the MODF flag but does prevent MODF from being set again after MODF is
cleared.
MODF generates a receiver/error CPU interrupt request if the error interrupt enable bit (ERRIE) is also
set. The SPRF, MODF, and OVRF interrupts share the same CPU interrupt vector. (See Figure 15-11.)
It is not possible to enable MODF or OVRF individually to generate a receiver/error CPU interrupt request.
However, leaving MODFEN low prevents MODF from being set.
In a master SPI with the mode fault enable bit (MODFEN) set, the mode fault flag (MODF) is set if SS
goes to logic 0. A mode fault in a master SPI causes the following events to occur:
• If ERRIE = 1, the SPI generates an SPI receiver/error CPU interrupt request.
• The SPE bit is cleared.
• The SPTE bit is set.
• The SPI state counter is cleared.
• The data direction register of the shared I/O port regains control of port drivers.
MC68HC908GP32 Data Sheet, Rev. 10
184
Freescale Semiconductor
Interrupts
NOTE
To prevent bus contention with another master SPI after a mode fault error,
clear all SPI bits of the data direction register of the shared I/O port before
enabling the SPI.
When configured as a slave (SPMSTR = 0), the MODF flag is set if SS goes high during a transmission.
When CPHA = 0, a transmission begins when SS goes low and ends once the incoming SPSCK goes
back to its idle level following the shift of the eighth data bit. When CPHA = 1, the transmission begins
when the SPSCK leaves its idle level and SS is already low. The transmission continues until the SPSCK
returns to its idle level following the shift of the last data bit. (See 15.5 Transmission Formats.)
NOTE
Setting the MODF flag does not clear the SPMSTR bit. The SPMSTR bit
has no function when SPE = 0. Reading SPMSTR when MODF = 1 shows
the difference between a MODF occurring when the SPI is a master and
when it is a slave.
When CPHA = 0, a MODF occurs if a slave is selected (SS is at logic 0) and
later unselected (SS is at logic 1) even if no SPSCK is sent to that slave.
This happens because SS at logic 0 indicates the start of the transmission
(MISO driven out with the value of MSB) for CPHA = 0. When CPHA = 1, a
slave can be selected and then later unselected with no transmission
occurring. Therefore, MODF does not occur since a transmission was
never begun.
In a slave SPI (MSTR = 0), the MODF bit generates an SPI receiver/error CPU interrupt request if the
ERRIE bit is set. The MODF bit does not clear the SPE bit or reset the SPI in any way. Software can abort
the SPI transmission by clearing the SPE bit of the slave.
NOTE
A logic 1 voltage on the SS pin of a slave SPI puts the MISO pin in a high
impedance state. Also, the slave SPI ignores all incoming SPSCK clocks,
even if it was already in the middle of a transmission.
To clear the MODF flag, read the SPSCR with the MODF bit set and then write to the SPCR register. This
entire clearing mechanism must occur with no MODF condition existing or else the flag is not cleared.
15.8 Interrupts
Four SPI status flags can be enabled to generate CPU interrupt requests.
Table 15-2. SPI Interrupts
Flag
Request
SPTE
Transmitter empty
SPI transmitter CPU interrupt request
(SPTIE = 1, SPE = 1)
SPRF
Receiver full
SPI receiver CPU interrupt request
(SPRIE = 1)
OVRF
Overflow
SPI receiver/error interrupt request
(ERRIE = 1)
MODF
Mode fault
SPI receiver/error interrupt request
(ERRIE = 1)
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
185
Serial Peripheral Interface Module (SPI)
Reading the SPI status and control register with SPRF set and then reading the receive data register
clears SPRF. The clearing mechanism for the SPTE flag is always just a write to the transmit data
register.
The SPI transmitter interrupt enable bit (SPTIE) enables the SPTE flag to generate transmitter CPU
interrupt requests, provided that the SPI is enabled (SPE = 1).
The SPI receiver interrupt enable bit (SPRIE) enables the SPRF bit to generate receiver CPU interrupt
requests, regardless of the state of the SPE bit. (See Figure 15-11.)
The error interrupt enable bit (ERRIE) enables both the MODF and OVRF bits to generate a receiver/error
CPU interrupt request.
The mode fault enable bit (MODFEN) can prevent the MODF flag from being set so that only the OVRF
bit is enabled by the ERRIE bit to generate receiver/error CPU interrupt requests.
SPTE
SPTIE
SPE
SPI TRANSMITTER
CPU INTERRUPT REQUEST
SPRIE
SPRF
SPI RECEIVER/ERROR
ERRIE
CPU INTERRUPT REQUEST
MODF
OVRF
Figure 15-11. SPI Interrupt Request Generation
The following sources in the SPI status and control register can generate CPU interrupt requests:
• SPI receiver full bit (SPRF) — The SPRF bit becomes set every time a byte transfers from the shift
register to the receive data register. If the SPI receiver interrupt enable bit, SPRIE, is also set,
SPRF generates an SPI receiver/error CPU interrupt request.
• SPI transmitter empty (SPTE) — The SPTE bit becomes set every time a byte transfers from the
transmit data register to the shift register. If the SPI transmit interrupt enable bit, SPTIE, is also set,
SPTE generates an SPTE CPU interrupt request.
MC68HC908GP32 Data Sheet, Rev. 10
186
Freescale Semiconductor
Resetting the SPI
15.9 Resetting the SPI
Any system reset completely resets the SPI. Partial resets occur whenever the SPI enable bit (SPE) is
low. Whenever SPE is low, the following occurs:
• The SPTE flag is set.
• Any transmission currently in progress is aborted.
• The shift register is cleared.
• The SPI state counter is cleared, making it ready for a new complete transmission.
• All the SPI port logic is defaulted back to being general-purpose I/O.
These items are reset only by a system reset:
• All control bits in the SPCR register
• All control bits in the SPSCR register (MODFEN, ERRIE, SPR1, and SPR0)
• The status flags SPRF, OVRF, and MODF
By not resetting the control bits when SPE is low, the user can clear SPE between transmissions without
having to set all control bits again when SPE is set back high for the next transmission.
By not resetting the SPRF, OVRF, and MODF flags, the user can still service these interrupts after the
SPI has been disabled. The user can disable the SPI by writing 0 to the SPE bit. The SPI can also be
disabled by a mode fault occurring in an SPI that was configured as a master with the MODFEN bit set.
15.10 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption standby modes.
15.10.1 Wait Mode
The SPI module remains active after the execution of a WAIT instruction. In wait mode the SPI module
registers are not accessible by the CPU. Any enabled CPU interrupt request from the SPI module can
bring the MCU out of wait mode.
If SPI module functions are not required during wait mode, reduce power consumption by disabling the
SPI module before executing the WAIT instruction.
To exit wait mode when an overflow condition occurs, enable the OVRF bit to generate CPU interrupt
requests by setting the error interrupt enable bit (ERRIE). (See 15.8 Interrupts.)
15.10.2 Stop Mode
The SPI module is inactive after the execution of a STOP instruction. The STOP instruction does not
affect register conditions. SPI operation resumes after an external interrupt. If stop mode is exited by
reset, any transfer in progress is aborted, and the SPI is reset.
15.11 SPI During Break Interrupts
The system integration module (SIM) controls whether status bits in other modules can be cleared during
the break state. The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear
status bits during the break state. (See Chapter 14 System Integration Module (SIM).)
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
187
Serial Peripheral Interface Module (SPI)
To allow software to clear status bits during a break interrupt, write a logic 1 to the BCFE bit. If a status
bit is cleared during the break state, it remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its
default state), software can read and write I/O registers during the break state without affecting status bits.
Some status bits have a 2-step read/write clearing procedure. If software does the first step on such a bit
before the break, the bit cannot change during the break state as long as BCFE is at logic 0. After the
break, doing the second step clears the status bit.
Since the SPTE bit cannot be cleared during a break with the BCFE bit cleared, a write to the transmit
data register in break mode does not initiate a transmission nor is this data transferred into the shift
register. Therefore, a write to the SPDR in break mode with the BCFE bit cleared has no effect.
15.12 I/O Signals
The SPI module has five I/O pins and shares four of them with a parallel I/O port. They are:
• MISO — Data received
• MOSI — Data transmitted
• SPSCK — Serial clock
• SS — Slave select
• CGND — Clock ground (internally connected to VSS)
15.12.1 MISO (Master In/Slave Out)
MISO is one of the two SPI module pins that transmits serial data. In full duplex operation, the MISO pin
of the master SPI module is connected to the MISO pin of the slave SPI module. The master SPI
simultaneously receives data on its MISO pin and transmits data from its MOSI pin.
Slave output data on the MISO pin is enabled only when the SPI is configured as a slave. The SPI is
configured as a slave when its SPMSTR bit is logic 0 and its SS pin is at logic 0. To support a
multiple-slave system, a logic 1 on the SS pin puts the MISO pin in a high-impedance state.
When enabled, the SPI controls data direction of the MISO pin regardless of the state of the data direction
register of the shared I/O port.
15.12.2 MOSI (Master Out/Slave In)
MOSI is one of the two SPI module pins that transmits serial data. In full-duplex operation, the MOSI pin
of the master SPI module is connected to the MOSI pin of the slave SPI module. The master SPI
simultaneously transmits data from its MOSI pin and receives data on its MISO pin.
When enabled, the SPI controls data direction of the MOSI pin regardless of the state of the data direction
register of the shared I/O port.
15.12.3 SPSCK (Serial Clock)
The serial clock synchronizes data transmission between master and slave devices. In a master MCU,
the SPSCK pin is the clock output. In a slave MCU, the SPSCK pin is the clock input. In full-duplex
operation, the master and slave MCUs exchange a byte of data in eight serial clock cycles.
When enabled, the SPI controls data direction of the SPSCK pin regardless of the state of the data
direction register of the shared I/O port.
MC68HC908GP32 Data Sheet, Rev. 10
188
Freescale Semiconductor
I/O Signals
15.12.4 SS (Slave Select)
The SS pin has various functions depending on the current state of the SPI. For an SPI configured as a
slave, the SS is used to select a slave. For CPHA = 0, the SS is used to define the start of a transmission.
(See 15.5 Transmission Formats.) Since it is used to indicate the start of a transmission, the SS must be
toggled high and low between each byte transmitted for the CPHA = 0 format. However, it can remain low
between transmissions for the CPHA = 1 format. See Figure 15-12.
MISO/MOSI
BYTE 1
BYTE 2
BYTE 3
MASTER SS
SLAVE SS
CPHA = 0
SLAVE SS
CPHA = 1
Figure 15-12. CPHA/SS Timing
When an SPI is configured as a slave, the SS pin is always configured as an input. It cannot be used as
a general-purpose I/O regardless of the state of the MODFEN control bit. However, the MODFEN bit can
still prevent the state of the SS from creating a MODF error. (See 15.13.2 SPI Status and Control
Register.)
NOTE
A logic 1 voltage on the SS pin of a slave SPI puts the MISO pin in a
high-impedance state. The slave SPI ignores all incoming SPSCK clocks,
even if it was already in the middle of a transmission.
When an SPI is configured as a master, the SS input can be used in conjunction with the MODF flag to
prevent multiple masters from driving MOSI and SPSCK. (See 15.7.2 Mode Fault Error.) For the state of
the SS pin to set the MODF flag, the MODFEN bit in the SPSCK register must be set. If the MODFEN bit
is low for an SPI master, the SS pin can be used as a general-purpose I/O under the control of the data
direction register of the shared I/O port. With MODFEN high, it is an input-only pin to the SPI regardless
of the state of the data direction register of the shared I/O port.
The CPU can always read the state of the SS pin by configuring the appropriate pin as an input and
reading the port data register. (See Table 15-3.)
Table 15-3. SPI Configuration
SPE
SPMSTR
MODFEN
SPI Configuration
Function of SS Pin
0
X(1)
X
Not enabled
General-purpose I/O; SS ignored by SPI
1
1
1
0
1
1
X
0
1
Slave
Master without MODF
Master with MODF
Input-only to SPI
General-purpose I/O; SS ignored by SPI
Input-only to SPI
Note 1. X = Don’t care
15.12.5 CGND (Clock Ground)
CGND is the ground return for the serial clock pin, SPSCK, and the ground for the port output buffers. It
is internally connected to VSS as shown in Table 15-1.
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
189
Serial Peripheral Interface Module (SPI)
15.13 I/O Registers
Three registers control and monitor SPI operation:
• SPI control register (SPCR)
• SPI status and control register (SPSCR)
• SPI data register (SPDR)
15.13.1 SPI Control Register
The SPI control register:
• Enables SPI module interrupt requests
• Configures the SPI module as master or slave
• Selects serial clock polarity and phase
• Configures the SPSCK, MOSI, and MISO pins as open-drain outputs
• Enables the SPI module
Address: $0010
Read:
Write:
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
SPRIE
R
SPMSTR
CPOL
CPHA
SPWOM
SPE
SPTIE
0
0
1
0
1
0
0
0
R
= Reserved
Figure 15-13. SPI Control Register (SPCR)
SPRIE — SPI Receiver Interrupt Enable Bit
This read/write bit enables CPU interrupt requests generated by the SPRF bit. The SPRF bit is set
when a byte transfers from the shift register to the receive data register. Reset clears the SPRIE bit.
1 = SPRF CPU interrupt requests enabled
0 = SPRF CPU interrupt requests disabled
SPMSTR — SPI Master Bit
This read/write bit selects master mode operation or slave mode operation. Reset sets the SPMSTR
bit.
1 = Master mode
0 = Slave mode
CPOL — Clock Polarity Bit
This read/write bit determines the logic state of the SPSCK pin between transmissions. (See Figure
15-4 and Figure 15-6.) To transmit data between SPI modules, the SPI modules must have identical
CPOL values. Reset clears the CPOL bit.
CPHA — Clock Phase Bit
This read/write bit controls the timing relationship between the serial clock and SPI data. (See Figure
15-4 and Figure 15-6.) To transmit data between SPI modules, the SPI modules must have identical
CPHA values. When CPHA = 0, the SS pin of the slave SPI module must be set to logic 1 between
bytes. (See Figure 15-12.) Reset sets the CPHA bit.
SPWOM — SPI Wired-OR Mode Bit
This read/write bit disables the pullup devices on pins SPSCK, MOSI, and MISO so that those pins
become open-drain outputs.
MC68HC908GP32 Data Sheet, Rev. 10
190
Freescale Semiconductor
I/O Registers
1 = Wired-OR SPSCK, MOSI, and MISO pins
0 = Normal push-pull SPSCK, MOSI, and MISO pins
SPE — SPI Enable
This read/write bit enables the SPI module. Clearing SPE causes a partial reset of the SPI. (See 15.9
Resetting the SPI.) Reset clears the SPE bit.
1 = SPI module enabled
0 = SPI module disabled
SPTIE— SPI Transmit Interrupt Enable
This read/write bit enables CPU interrupt requests generated by the SPTE bit. SPTE is set when a byte
transfers from the transmit data register to the shift register. Reset clears the SPTIE bit.
1 = SPTE CPU interrupt requests enabled
0 = SPTE CPU interrupt requests disabled
15.13.2 SPI Status and Control Register
The SPI status and control register contains flags to signal these conditions:
• Receive data register full
• Failure to clear SPRF bit before next byte is received (overflow error)
• Inconsistent logic level on SS pin (mode fault error)
• Transmit data register empty
The SPI status and control register also contains bits that perform these functions:
• Enable error interrupts
• Enable mode fault error detection
• Select master SPI baud rate
Address: $0011
Bit 7
Read:
SPRF
Write:
Reset:
0
6
ERRIE
0
5
4
3
OVRF
MODF
SPTE
0
0
1
2
1
Bit 0
MODFEN
SPR1
SPR0
0
0
0
= Unimplemented
Figure 15-14. SPI Status and Control Register (SPSCR)
SPRF — SPI Receiver Full Bit
This clearable, read-only flag is set each time a byte transfers from the shift register to the receive data
register. SPRF generates a CPU interrupt request if the SPRIE bit in the SPI control register is set also.
During an SPRF CPU interrupt, the CPU clears SPRF by reading the SPI status and control register
with SPRF set and then reading the SPI data register.
Reset clears the SPRF bit.
1 = Receive data register full
0 = Receive data register not full
ERRIE — Error Interrupt Enable Bit
This read/write bit enables the MODF and OVRF bits to generate CPU interrupt requests. Reset clears
the ERRIE bit.
1 = MODF and OVRF can generate CPU interrupt requests
0 = MODF and OVRF cannot generate CPU interrupt requests
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
191
Serial Peripheral Interface Module (SPI)
OVRF — Overflow Bit
This clearable, read-only flag is set if software does not read the byte in the receive data register before
the next full byte enters the shift register. In an overflow condition, the byte already in the receive data
register is unaffected, and the byte that shifted in last is lost. Clear the OVRF bit by reading the SPI
status and control register with OVRF set and then reading the receive data register. Reset clears the
OVRF bit.
1 = Overflow
0 = No overflow
MODF — Mode Fault Bit
This clearable, read-only flag is set in a slave SPI if the SS pin goes high during a transmission with
the MODFEN bit set. In a master SPI, the MODF flag is set if the SS pin goes low at any time with the
MODFEN bit set. Clear the MODF bit by reading the SPI status and control register (SPSCR) with
MODF set and then writing to the SPI control register (SPCR). Reset clears the MODF bit.
1 = SS pin at inappropriate logic level
0 = SS pin at appropriate logic level
SPTE — SPI Transmitter Empty Bit
This clearable, read-only flag is set each time the transmit data register transfers a byte into the shift
register. SPTE generates an SPTE CPU interrupt request or an SPTE DMA service request if the
SPTIE bit in the SPI control register is set also.
NOTE
Do not write to the SPI data register unless the SPTE bit is high.
During an SPTE CPU interrupt, the CPU clears the SPTE bit by writing to the transmit data register.
Reset sets the SPTE bit.
1 = Transmit data register empty
0 = Transmit data register not empty
MODFEN — Mode Fault Enable Bit
This read/write bit, when set to 1, allows the MODF flag to be set. If the MODF flag is set, clearing the
MODFEN does not clear the MODF flag. If the SPI is enabled as a master and the MODFEN bit is low,
then the SS pin is available as a general-purpose I/O.
If the MODFEN bit is set, then this pin is not available as a general-purpose I/O. When the SPI is
enabled as a slave, the SS pin is not available as a general-purpose I/O regardless of the value of
MODFEN. (See 15.12.4 SS (Slave Select).)
If the MODFEN bit is low, the level of the SS pin does not affect the operation of an enabled SPI
configured as a master. For an enabled SPI configured as a slave, having MODFEN low only prevents
the MODF flag from being set. It does not affect any other part of SPI operation. (See 15.7.2 Mode
Fault Error.)
MC68HC908GP32 Data Sheet, Rev. 10
192
Freescale Semiconductor
I/O Registers
SPR1 and SPR0 — SPI Baud Rate Select Bits
In master mode, these read/write bits select one of four baud rates as shown in Table 15-4. SPR1 and
SPR0 have no effect in slave mode. Reset clears SPR1 and SPR0.
Table 15-4. SPI Master Baud Rate Selection
SPR1 and SPR0
Baud Rate Divisor (BD)
00
2
01
8
10
32
11
128
Use this formula to calculate the SPI baud rate:
BUSCLK
Baud rate = -----------------------2 × BD
15.13.3 SPI Data Register
The SPI data register consists of the read-only receive data register and the write-only transmit data
register. Writing to the SPI data register writes data into the transmit data register. Reading the SPI data
register reads data from the receive data register. The transmit data and receive data registers are
separate registers that can contain different values. (See Figure 15-2.)
Address: $0012
Bit 7
6
5
4
3
2
1
Bit 0
Read:
R7
R6
R5
R4
R3
R2
R1
R0
Write:
T7
T6
T5
T4
T3
T2
T1
T0
Reset:
Unaffected by reset
Figure 15-15. SPI Data Register (SPDR)
R7–R0/T7–T0 — Receive/Transmit Data Bits
NOTE
Do not use read-modify-write instructions on the SPI data register since the
register read is not the same as the register written.
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
193
Serial Peripheral Interface Module (SPI)
MC68HC908GP32 Data Sheet, Rev. 10
194
Freescale Semiconductor
Chapter 16
Timebase Module (TBM)
16.1 Introduction
This section describes the timebase module (TBM). The TBM will generate periodic interrupts at user
selectable rates using a counter clocked by the external crystal clock. This TBM version uses 15 divider
stages, eight of which are user selectable.
16.2 Features
Features of the TBM module include:
• Software programmable 1-Hz, 4-Hz, 16-Hz, 256-Hz, 512-Hz, 1024-Hz, 2048-Hz, and 4096-Hz
periodic interrupt using external 32.768-kHz crystal
• Configurable for operation during stop mode to allow periodic wakeup from stop
16.3 Functional Description
NOTE
This module is designed for a 32.768-kHz oscillator.
This module can generate a periodic interrupt by dividing the crystal frequency, CGMXCLK. The counter
is initialized to all 0s when TBON bit is cleared. The counter, shown in Figure 16-1, starts counting when
the TBON bit is set. When the counter overflows at the tap selected by TBR2:TBR0, the TBIF bit gets set.
If the TBIE bit is set, an interrupt request is sent to the CPU. The TBIF flag is cleared by writing a 1 to the
TACK bit. The first time the TBIF flag is set after enabling the timebase module, the interrupt is generated
at approximately half of the overflow period. Subsequent events occur at the exact period.
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
195
Timebase Module (TBM)
TBON
÷2
CGMXCLK
÷2
÷2
÷2
÷2
÷8
÷2
÷ 16
÷2
÷ 32
÷ 64
÷ 128
÷2
÷2
÷2
÷2
÷ 2048
÷2
÷ 8192
TACK
÷2
TBR0
÷2
TBR1
÷2
TBR2
TBMINT
÷ 32768
TBIF
000
TBIE
R
001
010
011
SEL
100
101
110
111
Figure 16-1. Timebase Block Diagram
16.4 Timebase Register Description
The timebase has one register, the TBCR, which is used to enable the timebase interrupts and set the
rate.
Address:
$001C
Bit 7
Read:
TBIF
Write:
Reset:
0
6
5
4
TBR2
TBR1
TBR0
0
0
0
= Unimplemented
3
2
1
Bit 0
TBIE
TBON
R
0
0
0
0
R
= Reserved
0
TACK
Figure 16-2. Timebase Control Register (TBCR)
TBIF — Timebase Interrupt Flag
This read-only flag bit is set when the timebase counter has rolled over.
1 = Timebase interrupt pending
0 = Timebase interrupt not pending
MC68HC908GP32 Data Sheet, Rev. 10
196
Freescale Semiconductor
Interrupts
TBR2:TBR0 — Timebase Rate Selection
These read/write bits are used to select the rate of timebase interrupts as shown in Table 16-1.
Table 16-1. Timebase Rate Selection for OSC1 = 32.768-kHz
TBR2
TBR1
TBR0
Divider
0
0
0
0
0
0
0
Timebase Interrupt Rate
Hz
ms
32768
1
1000
1
8192
4
250
1
0
2048
16
62.5
1
1
128
256
~ 3.9
1
0
0
64
512
~2
1
0
1
32
1024
~1
1
1
0
16
2048
~0.5
1
1
1
8
4096
~0.24
NOTE
Do not change TBR2:TBR0 bits while the timebase is enabled
(TBON = 1).
TACK — Timebase ACKnowledge
The TACK bit is a write-only bit and always reads as 0. Writing a logic 1 to this bit clears TBIF, the
timebase interrupt flag bit. Writing a logic 0 to this bit has no effect.
1 = Clear timebase interrupt flag
0 = No effect
TBIE — Timebase Interrupt Enabled
This read/write bit enables the timebase interrupt when the TBIF bit becomes set. Reset clears the
TBIE bit.
1 = Timebase interrupt enabled
0 = Timebase interrupt disabled
TBON — Timebase Enabled
This read/write bit enables the timebase. Timebase may be turned off to reduce power consumption
when its function is not necessary. The counter can be initialized by clearing and then setting this bit.
Reset clears the TBON bit.
1 = Timebase enabled
0 = Timebase disabled and the counter initialized to 0s
16.5 Interrupts
The timebase module can interrupt the CPU on a regular basis with a rate defined by TBR2:TBR0. When
the timebase counter chain rolls over, the TBIF flag is set. If the TBIE bit is set, enabling the timebase
interrupt, the counter chain overflow will generate a CPU interrupt request.
Interrupts must be acknowledged by writing a logic 1 to the TACK bit.
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
197
Timebase Module (TBM)
16.6 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power- consumption standby modes.
16.6.1 Wait Mode
The timebase module remains active after execution of the WAIT instruction. In wait mode, the timebase
register is not accessible by the CPU.
If the timebase functions are not required during wait mode, reduce the power consumption by stopping
the timebase before enabling the WAIT instruction.
16.6.2 Stop Mode
The timebase module may remain active after execution of the STOP instruction if the oscillator has been
enabled to operate during stop mode through the OSCSTOPEN bit in the CONFIG register. The timebase
module can be used in this mode to generate a periodic wakeup from stop mode.
If the oscillator has not been enabled to operate in stop mode, the timebase module will not be active
during STOP mode. In stop mode the timebase register is not accessible by the CPU.
If the timebase functions are not required during stop mode, reduce the power consumption by stopping
the timebase before enabling the STOP instruction.
MC68HC908GP32 Data Sheet, Rev. 10
198
Freescale Semiconductor
Chapter 17
Timer Interface Module (TIM)
17.1 Introduction
This section describes the timer interface (TIM) module. The TIM is a two-channel timer that provides a
timing reference with input capture, output compare, and pulse-width-modulation functions. Figure 17-1
is a block diagram of the TIM.
This particular MCU has two timer interface modules which are denoted as TIM1 and TIM2.
17.2 Features
Features of the TIM include:
• Two input capture/output compare channels:
– Rising-edge, falling-edge, or any-edge input capture trigger
– Set, clear, or toggle output compare action
• Buffered and unbuffered pulse-width-modulation (PWM) signal generation
• Programmable TIM clock input with 7-frequency internal bus clock prescaler selection
• Free-running or modulo up-count operation
• Toggle any channel pin on overflow
• TIM counter stop and reset bits
17.3 Pin Name Conventions
The text that follows describes both timers, TIM1 and TIM2. The TIM input/output (I/O) pin names are
T[1,2]CH0 (timer channel 0) and T[1,2]CH1 (timer channel 1), where “1” is used to indicate TIM1 and “2”
is used to indicate TIM2. The two TIMs share four I/O pins with four port D I/O port pins. The full names
of the TIM I/O pins are listed in Table 17-1. The generic pin names appear in the text that follows.
Table 17-1. Pin Name Conventions
TIM Generic Pin Names:
Full TIM
Pin Names:
T[1,2]CH0
T[1,2]CH1
TIM1
PTD4/T1CH0
PTD5/T1CH1
TIM2
PTD6/T2CH0
PTD7/T2CH1
NOTE
References to either timer 1 or timer 2 may be made in the following text by
omitting the timer number. For example, TCH0 may refer generically to
T1CH0 and T2CH0, and TCH1 may refer to T1CH1 and T2CH1.
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
199
Timer Interface Module (TIM)
17.4 Functional Description
Figure 17-1 shows the structure of the TIM. The central component of the TIM is the 16-bit TIM counter
that can operate as a free-running counter or a modulo up-counter. The TIM counter provides the timing
reference for the input capture and output compare functions. The TIM counter modulo registers,
TMODH:TMODL, control the modulo value of the TIM counter. Software can read the TIM counter value
at any time without affecting the counting sequence.
The two TIM channels (per timer) are programmable independently as input capture or output compare
channels. If a channel is configured as input capture, then an internal pullup device may be enabled for
that channel. (See 12.5.3 Port D Input Pullup Enable Register.)
PRESCALER SELECT
INTERNAL
BUS CLOCK
PRESCALER
TSTOP
PS2
TRST
PS1
PS0
16-BIT COUNTER
TOF
TOIE
INTERRUPT
LOGIC
16-BIT COMPARATOR
TMODH:TMODL
TOV0
CHANNEL 0
ELS0B
ELS0A
CH0MAX
16-BIT COMPARATOR
PORT
LOGIC
T[1,2]CH0
CH0F
TCH0H:TCH0L
16-BIT LATCH
MS0A
CH0IE
INTERRUPT
LOGIC
MS0B
INTERNAL BUS
TOV1
CHANNEL 1
ELS1B
ELS1A
CH1MAX
PORT
LOGIC
T[1,2]CH1
16-BIT COMPARATOR
CH1F
TCH1H:TCH1L
16-BIT LATCH
MS1A
CH1IE
INTERRUPT
LOGIC
Figure 17-1. TIM Block Diagram
Figure 17-2 summarizes the timer registers.
NOTE
References to either timer 1 or timer 2 may be made in the following text by
omitting the timer number. For example, TSC may generically refer to both
T1SC and T2SC.
MC68HC908GP32 Data Sheet, Rev. 10
200
Freescale Semiconductor
Functional Description
Addr.
Register Name
Bit 7
6
5
TOIE
TSTOP
4
3
0
0
2
1
Bit 0
PS2
PS1
PS0
Timer 1 Status and Control Read:
Register Write:
(T1SC) Reset:
TOF
0
0
1
0
0
0
0
0
Bit 15
14
13
12
11
10
9
Bit 8
$0021
Timer 1 Counter Read:
Register High Write:
(T1CNTH) Reset:
0
0
0
0
0
0
0
0
Bit 7
6
5
4
3
2
1
Bit 0
$0022
Timer 1 Counter Read:
Register Low Write:
(T1CNTL) Reset:
0
0
0
0
0
0
0
0
Bit 15
14
13
12
11
10
9
Bit 8
1
1
1
1
1
1
1
1
Bit 7
6
5
4
3
2
1
Bit 0
1
1
1
1
1
1
1
1
CH0IE
MS0B
MS0A
ELS0B
ELS0A
TOV0
CH0MAX
0
0
0
0
0
0
0
0
Bit 15
14
13
12
11
10
9
Bit 8
2
1
Bit 0
$0020
$0023
$0024
Timer 1 Counter Modulo Read:
Register High Write:
(T1MODH) Reset:
Timer 1 Counter Modulo Read:
Register Low Write:
(T1MODL) Reset:
Read:
Timer 1 Channel 0 Status and
Write:
$0025
Control Register (T1SC0)
Reset:
$0026
$0027
Timer 1 Channel 0 Read:
Register High Write:
(T1CH0H) Reset:
Timer 1 Channel 0 Read:
Register Low Write:
(T1CH0L) Reset:
Read:
Timer 1 Channel 1 Status and
Write:
$0028
Control Register (T1SC1)
Reset:
$0029
Timer 1 Channel 1 Read:
Register High Write:
(T1CH1H) Reset:
$002A
Timer 1 Channel 1 Read:
Register Low Write:
(T1CH1L) Reset:
$002B
Timer 2 Status and Control Read:
Register Write:
(T2SC) Reset:
0
CH0F
0
TRST
Indeterminate after reset
Bit 7
6
5
4
3
Indeterminate after reset
CH1F
0
0
CH1IE
MS1A
ELS1B
ELS1A
TOV1
CH1MAX
0
0
0
0
0
0
0
0
Bit 15
14
13
12
11
10
9
Bit 8
2
1
Bit 0
PS2
PS1
PS0
0
0
0
Indeterminate after reset
Bit 7
6
5
4
3
Indeterminate after reset
TOF
0
0
TOIE
TSTOP
0
1
0
0
TRST
0
0
= Unimplemented
Figure 17-2. TIM I/O Register Summary (Sheet 1 of 2)
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
201
Timer Interface Module (TIM)
Addr.
$002C
$002D
$002E
$002F
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Timer 2 Counter Read:
Register High Write:
(T2CNTH) Reset:
Bit 15
14
13
12
11
10
9
Bit 8
0
0
0
0
0
0
0
0
Timer 2 Counter Read:
Register Low Write:
(T2CNTL) Reset:
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
0
0
Bit 15
14
13
12
11
10
9
Bit 8
1
1
1
1
1
1
1
1
Bit 7
6
5
4
3
2
1
Bit 0
1
1
1
1
1
1
1
1
CH0IE
MS0B
MS0A
ELS0B
ELS0A
TOV0
CH0MAX
0
0
0
0
0
0
0
0
Bit 15
14
13
12
11
10
9
Bit 8
2
1
Bit 0
Timer 2 Counter Modulo Read:
Register High Write:
(T2MODH) Reset:
Timer 2 Counter Modulo Read:
Register Low Write:
(T2MODL) Reset:
Read:
$0030
$0031
$0032
Timer 2 Channel 0 Status and
Write:
Control Register (T2SC0)
Reset:
Timer 2 Channel 0 Read:
Register High Write:
(T2CH0H) Reset:
Timer 2 Channel 0 Read:
Register Low Write:
(T2CH0L) Reset:
Read:
Timer 2 Channel 1 Status and
Write:
$0033
Control Register (T2SC1)
Reset:
$0034
$0035
Timer 2 Channel 1 Read:
Register High Write:
(T2CH1H) Reset:
Timer 2 Channel 1 Read:
Register Low Write:
(T2CH1L) Reset:
CH0F
0
Indeterminate after reset
Bit 7
6
5
4
3
Indeterminate after reset
CH1F
0
0
CH1IE
MS1A
ELS1B
ELS1A
TOV1
CH1MAX
0
0
0
0
0
0
0
0
Bit 15
14
13
12
11
10
9
Bit 8
2
1
Bit 0
Indeterminate after reset
Bit 7
6
5
4
3
Indeterminate after reset
= Unimplemented
Figure 17-2. TIM I/O Register Summary (Sheet 2 of 2)
MC68HC908GP32 Data Sheet, Rev. 10
202
Freescale Semiconductor
Functional Description
17.4.1 TIM Counter Prescaler
The TIM clock source can be one of the seven prescaler outputs. The prescaler generates seven clock
rates from the internal bus clock. The prescaler select bits, PS[2:0], in the TIM status and control register
select the TIM clock source.
17.4.2 Input Capture
With the input capture function, the TIM can capture the time at which an external event occurs. When an
active edge occurs on the pin of an input capture channel, the TIM latches the contents of the TIM counter
into the TIM channel registers, TCHxH:TCHxL. The polarity of the active edge is programmable. Input
captures can generate TIM CPU interrupt requests.
17.4.3 Output Compare
With the output compare function, the TIM can generate a periodic pulse with a programmable polarity,
duration, and frequency. When the counter reaches the value in the registers of an output compare
channel, the TIM can set, clear, or toggle the channel pin. Output compares can generate TIM CPU
interrupt requests.
17.4.3.1 Unbuffered Output Compare
Any output compare channel can generate unbuffered output compare pulses as described in 17.4.3
Output Compare. The pulses are unbuffered because changing the output compare value requires writing
the new value over the old value currently in the TIM channel registers.
An unsynchronized write to the TIM channel registers to change an output compare value could cause
incorrect operation for up to two counter overflow periods. For example, writing a new value before the
counter reaches the old value but after the counter reaches the new value prevents any compare during
that counter overflow period. Also, using a TIM overflow interrupt routine to write a new, smaller output
compare value may cause the compare to be missed. The TIM may pass the new value before it is written.
Use the following methods to synchronize unbuffered changes in the output compare value on channel x:
• When changing to a smaller value, enable channel x output compare interrupts and write the new
value in the output compare interrupt routine. The output compare interrupt occurs at the end of
the current output compare pulse. The interrupt routine has until the end of the counter overflow
period to write the new value.
• When changing to a larger output compare value, enable TIM overflow interrupts and write the new
value in the TIM overflow interrupt routine. The TIM overflow interrupt occurs at the end of the
current counter overflow period. Writing a larger value in an output compare interrupt routine (at
the end of the current pulse) could cause two output compares to occur in the same counter
overflow period.
17.4.3.2 Buffered Output Compare
Channels 0 and 1 can be linked to form a buffered output compare channel whose output appears on the
TCH0 pin. The TIM channel registers of the linked pair alternately control the output.
Setting the MS0B bit in TIM channel 0 status and control register (TSC0) links channel 0 and channel 1.
The output compare value in the TIM channel 0 registers initially controls the output on the TCH0 pin.
Writing to the TIM channel 1 registers enables the TIM channel 1 registers to synchronously control the
output after the TIM overflows. At each subsequent overflow, the TIM channel registers (0 or 1) that
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
203
Timer Interface Module (TIM)
control the output are the ones written to last. TSC0 controls and monitors the buffered output compare
function, and TIM channel 1 status and control register (TSC1) is unused. While the MS0B bit is set, the
channel 1 pin, TCH1, is available as a general-purpose I/O pin.
NOTE
In buffered output compare operation, do not write new output compare
values to the currently active channel registers. User software should track
the currently active channel to prevent writing a new value to the active
channel. Writing to the active channel registers is the same as generating
unbuffered output compares.
17.4.4 Pulse Width Modulation (PWM)
By using the toggle-on-overflow feature with an output compare channel, the TIM can generate a PWM
signal. The value in the TIM counter modulo registers determines the period of the PWM signal. The
channel pin toggles when the counter reaches the value in the TIM counter modulo registers. The time
between overflows is the period of the PWM signal.
As Figure 17-3 shows, the output compare value in the TIM channel registers determines the pulse width
of the PWM signal. The time between overflow and output compare is the pulse width. Program the TIM
to clear the channel pin on output compare if the polarity of the PWM pulse is 1. Program the TIM to set
the pin if the polarity of the PWM pulse is 0.
The value in the TIM counter modulo registers and the selected prescaler output determines the
frequency of the PWM output. The frequency of an 8-bit PWM signal is variable in 256 increments. Writing
$00FF (255) to the TIM counter modulo registers produces a PWM period of 256 times the internal bus
clock period if the prescaler select value is $000. See 17.9.1 TIM Status and Control Register.
OVERFLOW
OVERFLOW
OVERFLOW
PERIOD
PULSE
WIDTH
TCHx
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
Figure 17-3. PWM Period and Pulse Width
The value in the TIM channel registers determines the pulse width of the PWM output. The pulse width
of an 8-bit PWM signal is variable in 256 increments. Writing $0080 (128) to the TIM channel registers
produces a duty cycle of 128/256 or 50%.
MC68HC908GP32 Data Sheet, Rev. 10
204
Freescale Semiconductor
Functional Description
17.4.4.1 Unbuffered PWM Signal Generation
Any output compare channel can generate unbuffered PWM pulses as described in 17.4.4 Pulse Width
Modulation (PWM). The pulses are unbuffered because changing the pulse width requires writing the new
pulse width value over the old value currently in the TIM channel registers.
An unsynchronized write to the TIM channel registers to change a pulse width value could cause incorrect
operation for up to two PWM periods. For example, writing a new value before the counter reaches the
old value but after the counter reaches the new value prevents any compare during that PWM period.
Also, using a TIM overflow interrupt routine to write a new, smaller pulse width value may cause the
compare to be missed. The TIM may pass the new value before it is written.
Use the following methods to synchronize unbuffered changes in the PWM pulse width on channel x:
• When changing to a shorter pulse width, enable channel x output compare interrupts and write the
new value in the output compare interrupt routine. The output compare interrupt occurs at the end
of the current pulse. The interrupt routine has until the end of the PWM period to write the new
value.
• When changing to a longer pulse width, enable TIM overflow interrupts and write the new value in
the TIM overflow interrupt routine. The TIM overflow interrupt occurs at the end of the current PWM
period. Writing a larger value in an output compare interrupt routine (at the end of the current pulse)
could cause two output compares to occur in the same PWM period.
NOTE
In PWM signal generation, do not program the PWM channel to toggle on
output compare. Toggling on output compare prevents reliable 0% duty
cycle generation and removes the ability of the channel to self-correct in the
event of software error or noise. Toggling on output compare also can
cause incorrect PWM signal generation when changing the PWM pulse
width to a new, much larger value.
17.4.4.2 Buffered PWM Signal Generation
Channels 0 and 1 can be linked to form a buffered PWM channel whose output appears on the TCH0 pin.
The TIM channel registers of the linked pair alternately control the pulse width of the output.
Setting the MS0B bit in TIM channel 0 status and control register (TSC0) links channel 0 and channel 1.
The TIM channel 0 registers initially control the pulse width on the TCH0 pin. Writing to the TIM channel
1 registers enables the TIM channel 1 registers to synchronously control the pulse width at the beginning
of the next PWM period. At each subsequent overflow, the TIM channel registers (0 or 1) that control the
pulse width are the ones written to last. TSC0 controls and monitors the buffered PWM function, and TIM
channel 1 status and control register (TSC1) is unused. While the MS0B bit is set, the channel 1 pin,
TCH1, is available as a general-purpose I/O pin.
NOTE
In buffered PWM signal generation, do not write new pulse width values to
the currently active channel registers. User software should track the
currently active channel to prevent writing a new value to the active
channel. Writing to the active channel registers is the same as generating
unbuffered PWM signals.
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
205
Timer Interface Module (TIM)
17.4.4.3 PWM Initialization
To ensure correct operation when generating unbuffered or buffered PWM signals, use the following
initialization procedure:
1. In the TIM status and control register (TSC):
a. Stop the TIM counter by setting the TIM stop bit, TSTOP.
b.
Reset the TIM counter and prescaler by setting the TIM reset bit, TRST.
2. In the TIM counter modulo registers (TMODH:TMODL), write the value for the required PWM
period.
3. In the TIM channel x registers (TCHxH:TCHxL), write the value for the required pulse width.
4. In TIM channel x status and control register (TSCx):
a. Write 0:1 (for unbuffered output compare or PWM signals) or 1:0 (for buffered output compare
or PWM signals) to the mode select bits, MSxB:MSxA. (See Table 17-3.)
b.
c.
Write 1 to the toggle-on-overflow bit, TOVx.
Write 1:0 (to clear output on compare) or 1:1 (to set output on compare) to the edge/level
select bits, ELSxB:ELSxA. The output action on compare must force the output to the
complement of the pulse width level. (See Table 17-3.)
NOTE
In PWM signal generation, do not program the PWM channel to toggle on
output compare. Toggling on output compare prevents reliable 0% duty
cycle generation and removes the ability of the channel to self-correct in the
event of software error or noise. Toggling on output compare can also
cause incorrect PWM signal generation when changing the PWM pulse
width to a new, much larger value.
5. In the TIM status control register (TSC), clear the TIM stop bit, TSTOP.
Setting MS0B links channels 0 and 1 and configures them for buffered PWM operation. The TIM
channel 0 registers (TCH0H:TCH0L) initially control the buffered PWM output. TIM channel 0 status and
control register (TSC0) controls and monitors the PWM signal from the linked channels.
Clearing the toggle-on-overflow bit, TOVx, inhibits output toggles on TIM overflows. Subsequent output
compares try to force the output to a state it is already in and have no effect. The result is a 0% duty cycle
output.
Setting the channel x maximum duty cycle bit (CHxMAX) and setting the TOVx bit generates a 100% duty
cycle output. (See 17.9.4 TIM Channel Status and Control Registers.)
MC68HC908GP32 Data Sheet, Rev. 10
206
Freescale Semiconductor
Interrupts
17.5 Interrupts
The following TIM sources can generate interrupt requests:
• TIM overflow flag (TOF) — The TOF bit is set when the TIM counter reaches the modulo value
programmed in the TIM counter modulo registers. The TIM overflow interrupt enable bit, TOIE,
enables TIM overflow CPU interrupt requests. TOF and TOIE are in the TIM status and control
register.
• TIM channel flags (CH1F:CH0F) — The CHxF bit is set when an input capture or output compare
occurs on channel x. Channel x TIM CPU interrupt requests are controlled by the channel x
interrupt enable bit, CHxIE. Channel x TIM CPU interrupt requests are enabled when CHxIE = 1.
CHxF and CHxIE are in the TIM channel x status and control register.
17.6 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power- consumption standby modes.
17.6.1 Wait Mode
The TIM remains active after the execution of a WAIT instruction. In wait mode, the TIM registers are not
accessible by the CPU. Any enabled CPU interrupt request from the TIM can bring the MCU out of wait
mode.
If TIM functions are not required during wait mode, reduce power consumption by stopping the TIM before
executing the WAIT instruction.
17.6.2 Stop Mode
The TIM is inactive after the execution of a STOP instruction. The STOP instruction does not affect
register conditions or the state of the TIM counter. TIM operation resumes when the MCU exits stop mode
after an external interrupt.
17.7 TIM During Break Interrupts
A break interrupt stops the TIM counter.
The system integration module (SIM) controls whether status bits in other modules can be cleared during
the break state. The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear
status bits during the break state. See 14.7.3 SIM Break Flag Control Register.
To allow software to clear status bits during a break interrupt, write a logic 1 to the BCFE bit. If a status
bit is cleared during the break state, it remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its
default state), software can read and write I/O registers during the break state without affecting status bits.
Some status bits have a 2-step read/write clearing procedure. If software does the first step on such a bit
before the break, the bit cannot change during the break state as long as BCFE is at logic 0. After the
break, doing the second step clears the status bit.
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
207
Timer Interface Module (TIM)
17.8 I/O Signals
Port D shares four of its pins with the TIM. The four TIM channel I/O pins are T1CH0, T1CH1, T2CH0,
and T2CH1 as described in 17.3 Pin Name Conventions.
Each channel I/O pin is programmable independently as an input capture pin or an output compare pin.
T1CH0 and T2CH0 can be configured as buffered output compare or buffered PWM pins.
17.9 I/O Registers
NOTE
References to either timer 1 or timer 2 may be made in the following text by
omitting the timer number. For example, TSC may generically refer to both
T1SC AND T2SC.
These I/O registers control and monitor operation of the TIM:
• TIM status and control register (TSC)
• TIM counter registers (TCNTH:TCNTL)
• TIM counter modulo registers (TMODH:TMODL)
• TIM channel status and control registers (TSC0, TSC1)
• TIM channel registers (TCH0H:TCH0L, TCH1H:TCH1L)
17.9.1 TIM Status and Control Register
The TIM status and control register (TSC):
• Enables TIM overflow interrupts
• Flags TIM overflows
• Stops the TIM counter
• Resets the TIM counter
• Prescales the TIM counter clock
Address: T1SC, $0020 and T2SC, $002B
Bit 7
Read:
TOF
Write:
0
Reset:
0
6
5
TOIE
TSTOP
0
1
4
3
0
0
TRST
0
2
1
Bit 0
PS2
PS1
PS0
0
0
0
0
= Unimplemented
Figure 17-4. TIM Status and Control Register (TSC)
TOF — TIM Overflow Flag Bit
This read/write flag is set when the TIM counter reaches the modulo value programmed in the TIM
counter modulo registers. Clear TOF by reading the TIM status and control register when TOF is set
and then writing a logic 0 to TOF. If another TIM overflow occurs before the clearing sequence is
complete, then writing logic 0 to TOF has no effect. Therefore, a TOF interrupt request cannot be lost
due to inadvertent clearing of TOF. Reset clears the TOF bit. Writing a logic 1 to TOF has no effect.
1 = TIM counter has reached modulo value
0 = TIM counter has not reached modulo value
MC68HC908GP32 Data Sheet, Rev. 10
208
Freescale Semiconductor
I/O Registers
TOIE — TIM Overflow Interrupt Enable Bit
This read/write bit enables TIM overflow interrupts when the TOF bit becomes set. Reset clears the
TOIE bit.
1 = TIM overflow interrupts enabled
0 = TIM overflow interrupts disabled
TSTOP — TIM Stop Bit
This read/write bit stops the TIM counter. Counting resumes when TSTOP is cleared. Reset sets the
TSTOP bit, stopping the TIM counter until software clears the TSTOP bit.
1 = TIM counter stopped
0 = TIM counter active
NOTE
Do not set the TSTOP bit before entering wait mode if the TIM is required
to exit wait mode.
TRST — TIM Reset Bit
Setting this write-only bit resets the TIM counter and the TIM prescaler. Setting TRST has no effect on
any other registers. Counting resumes from $0000. TRST is cleared automatically after the TIM
counter is reset and always reads as logic 0. Reset clears the TRST bit.
1 = Prescaler and TIM counter cleared
0 = No effect
NOTE
Setting the TSTOP and TRST bits simultaneously stops the TIM counter at
a value of $0000.
PS[2:0] — Prescaler Select Bits
These read/write bits select one of the seven prescaler outputs as the input to the TIM counter as
Table 17-2 shows. Reset clears the PS[2:0] bits.
Table 17-2. Prescaler Selection
PS2
PS1
PS0
TIM Clock Source
0
0
0
Internal bus clock ÷ 1
0
0
1
Internal bus clock ÷ 2
0
1
0
Internal bus clock ÷ 4
0
1
1
Internal bus clock ÷ 8
1
0
0
Internal bus clock ÷ 16
1
0
1
Internal bus clock ÷ 32
1
1
0
Internal bus clock ÷ 64
1
1
1
Not available
17.9.2 TIM Counter Registers
The two read-only TIM counter registers contain the high and low bytes of the value in the TIM counter.
Reading the high byte (TCNTH) latches the contents of the low byte (TCNTL) into a buffer. Subsequent
reads of TCNTH do not affect the latched TCNTL value until TCNTL is read. Reset clears the TIM counter
registers. Setting the TIM reset bit (TRST) also clears the TIM counter registers.
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
209
Timer Interface Module (TIM)
NOTE
If you read TCNTH during a break interrupt, be sure to unlatch TCNTL by
reading TCNTL before exiting the break interrupt. Otherwise, TCNTL
retains the value latched during the break.
Address: T1CNTH, $0021 and T2CNTH, $002C
Read:
Bit 7
6
5
4
3
2
1
Bit 0
Bit 15
14
13
12
11
10
9
Bit 8
0
0
0
0
0
0
0
0
Write:
Reset:
= Unimplemented
Figure 17-5. TIM Counter Registers High (TCNTH)
Address: T1CNTL, $0022 and T2CNTL, $002D
Read:
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
0
Write:
Reset:
0
= Unimplemented
Figure 17-6. TIM Counter Registers Low (TCNTL)
17.9.3 TIM Counter Modulo Registers
The read/write TIM modulo registers contain the modulo value for the TIM counter. When the TIM counter
reaches the modulo value, the overflow flag (TOF) becomes set, and the TIM counter resumes counting
from $0000 at the next timer clock. Writing to the high byte (TMODH) inhibits the TOF bit and overflow
interrupts until the low byte (TMODL) is written. Reset sets the TIM counter modulo registers.
Address: T1MODH, $0023 and T2MODH, $002E
Read:
Write:
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
Bit 15
14
13
12
11
10
9
Bit 8
1
1
1
1
1
1
1
1
Figure 17-7. TIM Counter Modulo Register High (TMODH)
Address: T1MODL, $0024 and T2MODL, $002F
Read:
Write:
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
6
5
4
3
2
1
Bit 0
1
1
1
1
1
1
1
1
Figure 17-8. TIM Counter Modulo Register Low (TMODL)
NOTE
Reset the TIM counter before writing to the TIM counter modulo registers.
MC68HC908GP32 Data Sheet, Rev. 10
210
Freescale Semiconductor
I/O Registers
17.9.4 TIM Channel Status and Control Registers
Each of the TIM channel status and control registers:
• Flags input captures and output compares
• Enables input capture and output compare interrupts
• Selects input capture, output compare, or PWM operation
• Selects high, low, or toggling output on output compare
• Selects rising edge, falling edge, or any edge as the active input capture trigger
• Selects output toggling on TIM overflow
• Selects 0% and 100% PWM duty cycle
• Selects buffered or unbuffered output compare/PWM operation
Address: T1SC0, $0025 and T2SC0, $0030
Bit 7
Read:
CH0F
Write:
0
Reset:
0
6
5
4
3
2
1
Bit 0
CH0IE
MS0B
MS0A
ELS0B
ELS0A
TOV0
CH0MAX
0
0
0
0
0
0
0
Figure 17-9. TIM Channel 0 Status and Control Register (TSC0)
Address: T1SC1, $0028 and T2SC1, $0033
Bit 7
Read:
CH1F
Write:
0
Reset:
0
6
5
CH1IE
0
0
0
4
3
2
1
Bit 0
MS1A
ELS1B
ELS1A
TOV1
CH1MAX
0
0
0
0
0
= Unimplemented
Figure 17-10. TIM Channel 1 Status and Control Register (TSC1)
CHxF — Channel x Flag Bit
When channel x is an input capture channel, this read/write bit is set when an active edge occurs on
the channel x pin. When channel x is an output compare channel, CHxF is set when the value in the
TIM counter registers matches the value in the TIM channel x registers.
When TIM CPU interrupt requests are enabled (CHxIE = 1), clear CHxF by reading TIM channel x
status and control register with CHxF set and then writing a logic 0 to CHxF. If another interrupt request
occurs before the clearing sequence is complete, then writing logic 0 to CHxF has no effect. Therefore,
an interrupt request cannot be lost due to inadvertent clearing of CHxF.
Reset clears the CHxF bit. Writing a logic 1 to CHxF has no effect.
1 = Input capture or output compare on channel x
0 = No input capture or output compare on channel x
CHxIE — Channel x Interrupt Enable Bit
This read/write bit enables TIM CPU interrupt service requests on channel x.
Reset clears the CHxIE bit.
1 = Channel x CPU interrupt requests enabled
0 = Channel x CPU interrupt requests disabled
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
211
Timer Interface Module (TIM)
MSxB — Mode Select Bit B
This read/write bit selects buffered output compare/PWM operation. MSxB exists only in the TIM1
channel 0 and TIM2 channel 0 status and control registers.
Setting MS0B disables the channel 1 status and control register and reverts TCH1 to general-purpose
I/O.
Reset clears the MSxB bit.
1 = Buffered output compare/PWM operation enabled
0 = Buffered output compare/PWM operation disabled
MSxA — Mode Select Bit A
When ELSxB:ELSxA ≠ 0:0, this read/write bit selects either input capture operation or unbuffered
output compare/PWM operation.
See Table 17-3.
1 = Unbuffered output compare/PWM operation
0 = Input capture operation
When ELSxB:ELSxA = 0:0, this read/write bit selects the initial output level of the TCHx pin. See Table
17-3. Reset clears the MSxA bit.
1 = Initial output level low
0 = Initial output level high
NOTE
Before changing a channel function by writing to the MSxB or MSxA bit, set
the TSTOP and TRST bits in the TIM status and control register (TSC).
ELSxB and ELSxA — Edge/Level Select Bits
When channel x is an input capture channel, these read/write bits control the active edge-sensing logic
on channel x.
When channel x is an output compare channel, ELSxB and ELSxA control the channel x output
behavior when an output compare occurs.
When ELSxB and ELSxA are both clear, channel x is not connected to port D, and pin PTDx/TCHx is
available as a general-purpose I/O pin. Table 17-3 shows how ELSxB and ELSxA work. Reset clears the
ELSxB and ELSxA bits.
Table 17-3. Mode, Edge, and Level Selection
MSxB:MSx
A
ELSxB:ELSx
A
X0
00
X1
00
00
01
00
10
00
11
Mode
Output preset
Configuration
Pin under port control; initial output level high
Pin under port control; initial output level low
Capture on rising edge only
Input capture
Capture on falling edge only
Capture on rising or falling edge
01
00
Software compare only
01
01
Toggle output on compare
01
10
01
11
1X
01
1X
10
1X
11
Output compare or PWM
Clear output on compare
Set output on compare
Buffered output
compare or
buffered PWM
Toggle output on compare
Clear output on compare
Set output on compare
MC68HC908GP32 Data Sheet, Rev. 10
212
Freescale Semiconductor
I/O Registers
NOTE
Before enabling a TIM channel register for input capture operation, make
sure that the PTDx/TCHx pin is stable for at least two bus clocks.
TOVx — Toggle On Overflow Bit
When channel x is an output compare channel, this read/write bit controls the behavior of the channel
x output when the TIM counter overflows. When channel x is an input capture channel, TOVx has no
effect.
Reset clears the TOVx bit.
1 = Channel x pin toggles on TIM counter overflow
0 = Channel x pin does not toggle on TIM counter overflow
NOTE
When TOVx is set, a TIM counter overflow takes precedence over a
channel x output compare if both occur at the same time.
CHxMAX — Channel x Maximum Duty Cycle Bit
When the TOVx bit is at logic 1, setting the CHxMAX bit forces the duty cycle of buffered and
unbuffered PWM signals to 100%. As Figure 17-11 shows, the CHxMAX bit takes effect in the cycle
after it is set or cleared. The output stays at the 100% duty cycle level until the cycle after CHxMAX is
cleared.
OVERFLOW
OVERFLOW
OVERFLOW
OVERFLOW
OVERFLOW
PERIOD
TCHx
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
CHxMAX
Figure 17-11. CHxMAX Latency
17.9.5 TIM Channel Registers
These read/write registers contain the captured TIM counter value of the input capture function or the
output compare value of the output compare function. The state of the TIM channel registers after reset
is unknown.
In input capture mode (MSxB:MSxA = 0:0), reading the high byte of the TIM channel x registers (TCHxH)
inhibits input captures until the low byte (TCHxL) is read.
In output compare mode (MSxB:MSxA ≠ 0:0), writing to the high byte of the TIM channel x registers
(TCHxH) inhibits output compares until the low byte (TCHxL) is written.
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
213
Timer Interface Module (TIM)
Address: T1CH0H, $0026 and T2CH0H, $0031
Read:
Write:
Bit 7
6
5
4
3
2
1
Bit 0
Bit 15
14
13
12
11
10
9
Bit 8
Reset:
Indeterminate after reset
Figure 17-12. TIM Channel 0 Register High (TCH0H)
Address: T1CH0L, $0027 and T2CH0L $0032
Read:
Write:
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
6
5
4
3
2
1
Bit 0
Reset:
Indeterminate after reset
Figure 17-13. TIM Channel 0 Register Low (TCH0L)
Address: T1CH1H, $0029 and T2CH1H, $0034
Read:
Write:
Bit 7
6
5
4
3
2
1
Bit 0
Bit 15
14
13
12
11
10
9
Bit 8
Reset:
Indeterminate after reset
Figure 17-14. TIM Channel 1 Register High (TCH1H)
Address: T1CH1L, $002A and T2CH1L, $0035
Read:
Write:
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
6
5
4
3
2
1
Bit 0
Indeterminate after reset
Figure 17-15. TIM Channel 1 Register Low (TCH1L)
MC68HC908GP32 Data Sheet, Rev. 10
214
Freescale Semiconductor
Chapter 18
Development Support
18.1 Introduction
This section describes the break module, the monitor module (MON), and the monitor mode entry
methods.
18.2 Break Module (BRK)
The break module can generate a break interrupt that stops normal program flow at a defined address to
enter a background program.
Features of the break module include:
• Accessible input/output (I/O) registers during the break Interrupt
• Central processor unit (CPU) generated break interrupts
• Software-generated break interrupts
• Computer operating properly (COP) disabling during break interrupts
18.2.1 Functional Description
When the internal address bus matches the value written in the break address registers, the break module
issues a breakpoint signal (BKPT) to the system integration module (SIM). The SIM then causes the CPU
to load the instruction register with a software interrupt instruction (SWI). The program counter vectors to
$FFFC and $FFFD ($FEFC and $FEFD in monitor mode).
The following events can cause a break interrupt to occur:
• A CPU generated address (the address in the program counter) matches the contents of the break
address registers.
• Software writes a 1 to the BRKA bit in the break status and control register.
When a CPU generated address matches the contents of the break address registers, the break interrupt
is generated. A return-from-interrupt instruction (RTI) in the break routine ends the break interrupt and
returns the microcontroller unit (MCU) to normal operation.
Figure 18-1 shows the structure of the break module.
Figure 18-2 provides a summary of the I/O registers.
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
215
Development Support
ADDRESS BUS[15:8]
BREAK ADDRESS REGISTER HIGH
8-BIT COMPARATOR
ADDRESS BUS[15:0]
BKPT
(TO SIM)
CONTROL
8-BIT COMPARATOR
BREAK ADDRESS REGISTER LOW
ADDRESS BUS[7:0]
Figure 18-1. Break Module Block Diagram
Addr.
$FE00
Register Name
Bit 7
SIM Break Status Register Read:
(SBSR) Write:
See page 218. Reset:
Read:
Reserved Write:
$FE02
Reset:
$FE03
SIM Break Flag Control Read:
Register (SBFCR) Write:
See page 219. Reset:
$FE09
Break Address High Read:
Register (BRKH) Write:
See page 218. Reset:
$FE0A
Break Address Low Read:
Register (BRKL) Write:
See page 218. Reset:
$FE0B
Break Status and Control Read:
Register (BRKSCR) Write:
See page 218. Reset:
1. Writing a 0 clears SBSW.
R
6
5
R
R
4
R
3
R
2
1
SBSW
R
Note(1)
Bit 0
R
0
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
BCFE
R
R
R
R
R
R
R
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
0
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
BRKE
BRKA
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
= Reserved
0
= Unimplemented
Figure 18-2. Break I/O Register Summary
MC68HC908GP32 Data Sheet, Rev. 10
216
Freescale Semiconductor
Break Module (BRK)
When the internal address bus matches the value written in the break address registers or when software
writes a 1 to the BRKA bit in the break status and control register, the CPU starts a break interrupt by:
• Loading the instruction register with the SWI instruction
• Loading the program counter with $FFFC and $FFFD ($FEFC and $FEFD in monitor mode)
The break interrupt timing is:
• When a break address is placed at the address of the instruction opcode, the instruction is not
executed until after completion of the break interrupt routine.
• When a break address is placed at an address of an instruction operand, the instruction is
executed before the break interrupt.
• When software writes a 1 to the BRKA bit, the break interrupt occurs just before the next instruction
is executed.
By updating a break address and clearing the BRKA bit in a break interrupt routine, a break interrupt can
be generated continuously.
CAUTION
A break address should be placed at the address of the instruction opcode. When software does not
change the break address and clears the BRKA bit in the first break interrupt routine, the next break
interrupt will not be generated after exiting the interrupt routine even when the internal address bus
matches the value written in the break address registers.
18.2.1.1 Flag Protection During Break Interrupts
The system integration module (SIM) controls whether or not module status bits can be cleared during
the break state. The BCFE bit in the break flag control register (SBFCR) enables software to clear status
bits during the break state. See Figure 18-7. SIM Break Flag Control Register (SBFCR) and the Break
Interrupts subsection for each module.
18.2.1.2 TIM During Break Interrupts
A break interrupt stops the timer counter.
18.2.1.3 COP During Break Interrupts
The COP is disabled during a break interrupt when VTST is present on the RST pin.
18.2.2 Break Module Registers
These registers control and monitor operation of the break module:
• Break status and control register (BRKSCR)
• Break address register high (BRKH)
• Break address register low (BRKL)
• Break status register (SBSR)
• Break flag control register (SBFCR)
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
217
Development Support
18.2.2.1 Break Status and Control Register
The break status and control register (BRKSCR) contains break module enable and status bits.
Address: $FE0B
Read:
Write:
Reset:
Bit 7
6
BRKE
BRKA
0
0
5
4
3
2
1
Bit 0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented
Figure 18-3. Break Status and Control Register (BRKSCR)
BRKE — Break Enable Bit
This read/write bit enables breaks on break address register matches. Clear BRKE by writing a 0 to
bit 7. Reset clears the BRKE bit.
1 = Breaks enabled on 16-bit address match
0 = Breaks disabled
BRKA — Break Active Bit
This read/write status and control bit is set when a break address match occurs. Writing a 1 to BRKA
generates a break interrupt. Clear BRKA by writing a 0 to it before exiting the break routine. Reset
clears the BRKA bit.
1 = Break address match
0 = No break address match
18.2.2.2 Break Address Registers
The break address registers (BRKH and BRKL) contain the high and low bytes of the desired breakpoint
address. Reset clears the break address registers.
Address: $FE09
Read:
Write:
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
0
0
0
0
0
0
0
0
Figure 18-4. Break Address Register High (BRKH)
Address: $FE0A
Read:
Write:
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
Figure 18-5. Break Address Register Low (BRKL)
MC68HC908GP32 Data Sheet, Rev. 10
218
Freescale Semiconductor
Break Module (BRK)
18.2.2.3 SIM Break Status Register
The SIM break status register (SBSR) contains a flag to indicate that a break caused an exit from wait
mode. This register is only used in emulation mode.
Address: $FE00
Read:
Write:
Bit 7
6
5
4
3
2
R
R
R
R
R
R
1
SBSW
Note(1)
Reset:
Bit 0
R
0
R
= Reserved
1. Writing a 0 clears SBSW.
Figure 18-6. SIM Break Status Register (SBSR)
SBSW — SIM Break Stop/Wait
SBSW can be read within the break state SWI routine. The user can modify the return address on the
stack by subtracting one from it.
1 = Wait mode was exited by break interrupt
0 = Wait mode was not exited by break interrupt
18.2.2.4 SIM Break Flag Control Register
The SIM break control register (SBFCR) contains a bit that enables software to clear status bits while the
MCU is in a break state.
Address: $FE03
Read:
Write:
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
BCFE
R
R
R
R
R
R
R
0
R
= Reserved
Figure 18-7. SIM Break Flag Control Register (SBFCR)
BCFE — Break Clear Flag Enable Bit
This read/write bit enables software to clear status bits by accessing status registers while the MCU is
in a break state. To clear status bits during the break state, the BCFE bit must be set.
1 = Status bits clearable during break
0 = Status bits not clearable during break
18.2.3 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power- consumption standby modes. If enabled,
the break module will remain enabled in wait and stop modes. However, since the internal address bus
does not increment in these modes, a break interrupt will never be triggered.
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
219
Development Support
18.3 Monitor Module (MON)
The monitor module allows debugging and programming of the microcontroller unit (MCU) through a
single-wire interface with a host computer. Monitor mode entry can be achieved without use of the higher
test voltage, VTST, as long as vector addresses $FFFE and $FFFF are blank, thus reducing the hardware
requirements for in-circuit programming.
Features of the monitor module include:
•
Normal user-mode pin functionality
•
One pin dedicated to serial communication between MCU and host computer
•
Standard mark/space non-return-to-zero (NRZ) communication with host computer
•
Standard communication baud rate
•
Execution of code in random-access memory (RAM) or Flash
•
Flash memory security feature(1)
•
Flash memory programming interface
•
External 4.92 MHz or 9.83 MHz clock used to generate internal frequency of 2.4576 MHz
•
Enhanced PLL option to allow use of 32.768 kHz crystal to generate internal bus frequency of
2.4576 MHz
•
Monitor mode entry without high voltage, VTST, if reset vector is blank ($FFFE and $FFFF contain
$FF)
•
Normal monitor mode entry if high voltage, VTST, is applied to IRQ
18.3.1 Functional Description
Figure 18-8 shows a simplified monitor mode entry flowchart.
The monitor ROM receives and executes commands from a host computer. Figure 18-9, Figure 18-10,
and Figure 18-11 show example circuits used to enter monitor mode and communicate with a host
computer via a standard RS-232 interface.
Simple monitor commands can access any memory address. In monitor mode, the MCU can execute
code downloaded into RAM by a host computer while most MCU pins retain normal operating mode
functions. All communication between the host computer and the MCU is through the PTA0 pin. A
level-shifting and multiplexing interface is required between PTA0 and the host computer. PTA0 is used
in a wired-OR configuration and requires a pullup resistor.
1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the Flash difficult for
unauthorized users.
MC68HC908GP32 Data Sheet, Rev. 10
220
Freescale Semiconductor
Monitor Module (MON)
POR RESET
NO
CONDITIONS
FROM Table 18-1
PTA0 = 1, PTA7 = 0
RESET
BLANK?
IRQ = VTST?
YES
PTA0 = 1, PTA7 = 0, ,
PTC0 = 1, PTC1 = 0, AND
PTC3 = 1?
NO
NO
YES
YES
FORCED
MONITOR MODE
NORMAL
USER MODE
NORMAL
MONITOR MODE
FACTORY
USE ONLY
SEND 8 BYTES
SECURITY
IS RESET
POR?
YES
NO
YES
ARE ALL
SECURITY BYTES
CORRECT?
ENABLE FLASH
NO
DISABLE FLASH
MONITOR MODE ENTRY
DEBUGGING
AND FLASH
PROGRAMMING
(IF FLASH
IS ENABLED)
EXECUTE
MONITOR CODE
YES
DOES RESET
OCCUR?
NO
Figure 18-8. Simplified Monitor Mode Entry Flowchart
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
221
Development Support
VDD
RST
VDD
0.1 µF
0.1 µF
N.C.
9.8304 MHz CLOCK
MAX232
4
1 µF
+
16
C1–
15
4
C2+
+
5 C2–
10 kΩ
PTC3
5
7
10
8
9
IRQ
VDD
10 kΩ
PTA7
9.1 V
10 kΩ
+
74HC125
5
6
DB9
3
PTC1
+
V– 6
10 kΩ
1 kΩ
V+ 2
1 µF
10 kΩ
PTC0
VTST
2
VDD
OSC1
0.1 µF
5
1 µF
OSC2
VDD
C1+
VDDA
74HC125
3
2
VSS
PTA0
VSSA
4
1
Figure 18-9. Standard Monitor Mode
MC68HC908GP32 Data Sheet, Rev. 10
222
Freescale Semiconductor
Monitor Module (MON)
VDD
VDDA
RST
VDD
0.1 µF
MAX232
4
1 µF
+
N.C.
16
C1+
OSC2
9.8304 MHz CLOCK
0.1 µF
5
0.1 µF
VDD
15
C1–
OSC1
PTC0
N.C.
PTC3
N.C.
PTC1
N.C.
VTST
4
1 µF
V+ 2
C2+
+
V– 6
5 C2–
1 µF
7
10
3
8
9
IRQ
10 kΩ
+
74HC125
5
6
DB9
2
N.C.
VDD
+
2
74HC125
3
10 kΩ
PTA7
PTA0
4
VSS
VSSA
1
5
Figure 18-10. Forced Monitor Mode (High)
VDD
RST
VDD
0.1 µF
15 pF
MAX232
4
1 µF
+
C1+
C1–
0.1 µF
330 k
OSC2
VDD
16
10 MΩ
15 pF
0.1 µF
5
32.768 kHz
15
OSC1
IRQ
VTST
4
1 µF
C2+
+
5 C2–
V– 6
3
7
10
8
9
5
VDD
+
N.C.
PTC3
N.C.
PTC1
N.C.
10 kΩ
PTA7
10 kΩ
+
74HC125
5
6
DB9
2
PTC0
10 kΩ
V+ 2
1 µF
VDDA
74HC125
3
2
PTA0
4
VSS
VSSA
1
Figure 18-11. Forced Monitor Mode (Low)
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
223
Development Support
Table 18-1 shows the pin conditions for entering monitor mode. As specified in the table, monitor mode
must be entered after a power-on reset (POR) and will allow communication at 9600 baud provided one
of the following sets of conditions is met:
1. If $FFFE and $FFFF does not contain $FF (programmed state):
– The external clock is 4.9152 MHz with PTC3 low or 9.8304 MHz with PTC3 high
– IRQ = VTST
2. If $FFFE and $FFFF contain $FF (erased state):
– The external clock is 9.8304 MHz
– IRQ = VDD (this can be implemented through the internal IRQ pullup)
3. If $FFFE and $FFFF contain $FF (erased state):
– IRQ = VSS (PLL is selected using a 32.768 kHz crystal)
Enter monitor mode with the pin configurations shown in Table 18-1 with a power-on-reset. The rising
edge of reset latches monitor mode. Once monitor mode is latched, the levels on the port pins except
PTA0 can change.
Once out of reset, the MCU waits for the host to send eight security bytes (see 18.3.2 Security). After the
security bytes, the MCU sends a break signal (10 consecutive 0s) to the host, indicating that it is ready to
receive a command.
MC68HC908GP32 Data Sheet, Rev. 10
224
Freescale Semiconductor
Monitor Module (MON)
Table 18-1. Monitor Mode Signal Requirements and Options
Mode
IRQ
User
Reset
Vector
Mode
Selection
Communication
Speed
Divider
PLL
PTA0
PTA7
PTC0
PTC1
PTC3
COP
External
Bus
Clock Frequency
Baud
Rate
VTST
VDD
or
VTST
X
1
0
1
0
0
OFF Disabled
4.9152
MHz
2.457 MHz
9600
VTST
VDD
or
VTST
X
1
0
1
0
1
OFF Disabled
9.8304
MHz
2.457 MHz
9600
VDD
VDD
$FFFF
(blank)
1
0
X
X
X
OFF Disabled
9.8304
MHz
2.457 MHz
9600
VSS
VDD
$FFFF
(blank)
1
0
X
X
X
ON Disabled
32.768
kHz
2.457 MHz
9600
VDD
or
VSS
VDD
Not
or $FFFF
VTST
X
X
X
X
X
X
Enabled
X
X
X
COM
[8]
SSEL
[10]
DIV4
[16]
—
—
OSC1
[13]
—
—
Normal
Monitor
Forced
Monitor
RST
Serial
Communication
MON08
VTST RST
Function
[4]
[6]
[Pin No.]
—
MOD0 MOD1
[12]
[14]
1. PTA0 must have a pullup resistor to VDD in monitor mode.
2. Communication speed in the table is an example to obtain a baud rate of 9600. Baud rate using external oscillator is bus
frequency / 256.
3. External clock is a 4.9152 MHz or 9.8304 MHz canned oscillator on OSC1 or a 32.768 kHz crystal on OSC1 and OSC2.
4. X = don’t care
5. MON08 pin refers to P&E Microcomputer Systems’ MON08-Cyclone 2 by 8-pin connector.
NC
1
2
GND
NC
3
4
RST
NC
5
6
IRQ
NC
7
8
PTA0
NC
9
10
PTA7
NC
11
12
PTC0
OSC1
13
14
PTC1
VDD
15
16
PTC3
18.3.1.1 Normal Monitor Mode
When VTST is applied to IRQ and PTC3 is low upon monitor mode entry, the bus frequency is a
divide-by-two of the input clock. If PTC3 is high with VTST applied to IRQ upon monitor mode entry, the
bus frequency will be a divide-by-four of the input clock. Holding the PTC3 pin low when entering monitor
mode causes a bypass of a divide-by-two stage at the oscillator only if VTST is applied to IRQ. In this
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
225
Development Support
event, the CGMOUT frequency is equal to the CGMXCLK frequency, and the OSC1 input directly
generates internal bus clocks. In this case, the OSC1 signal must have a 50% duty cycle at maximum bus
frequency.
If monitor mode was entered with VTST on IRQ, then the COP is disabled as long as VTST is applied to
either IRQ or RST.
This condition states that as long as VTST is maintained on the IRQ pin after entering monitor mode, or if
VTST is applied to RST after the initial reset to get into monitor mode (when VTST was applied to IRQ),
then the COP will be disabled. In the latter situation, after VTST is applied to the RST pin, VTST can be
removed from the IRQ pin in the interest of freeing the IRQ for normal functionality in monitor mode.
18.3.1.2 Forced Monitor Mode
If entering monitor mode without high voltage on IRQ (where applied voltage is either VDD or VSS), then
all port C pin requirements and conditions, including the PTC3 frequency divisor selection, are not in
effect. This is to reduce circuit requirements when performing in-circuit programming.
If IRQ = VDD on monitor mode entry, an external oscillator of 9.8304 MHz is required for a 9600 baud rate.
If IRQ = VSS on monitor mode entry, the monitor firmware initializes a 9600 baud rate using a 32.768 kHz
crystal.
When forced monitor mode is entered, the COP is always disabled regardless of the state of IRQ or RST.
NOTE
If the reset vector is blank and monitor mode is entered, the chip will see an
additional reset cycle after the initial POR reset. Once the part has been
programmed, the traditional method of applying a voltage, VTST, to IRQ
must be used to enter monitor mode.
18.3.1.3 Monitor Vectors
In monitor mode, the MCU uses different vectors for reset, SWI (software interrupt), and break interrupt
than those for user mode. The alternate vectors are in the $FE page instead of the $FF page and allow
code execution from the internal monitor firmware instead of user code.
NOTE
Exiting monitor mode after it has been initiated by having a blank reset
vector requires a power-on reset (POR). Pulling RST low will not exit
monitor mode in this situation.
Table 18-2 summarizes the differences between user mode and monitor mode.
Table 18-2. Mode Differences
Functions
Modes
Reset
Vector High
Reset
Vector Low
Break
Vector High
Break
Vector Low
SWI
Vector High
SWI
Vector Low
User
$FFFE
$FFFF
$FFFC
$FFFD
$FFFC
$FFFD
Monitor
$FEFE
$FEFF
$FEFC
$FEFD
$FEFC
$FEFD
MC68HC908GP32 Data Sheet, Rev. 10
226
Freescale Semiconductor
Monitor Module (MON)
18.3.1.4 Data Format
Communication with the monitor ROM is in standard non-return-to-zero (NRZ) mark/space data format.
Transmit and receive baud rates must be identical.
START
BIT
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
STOP
BIT
NEXT
START
BIT
Figure 18-12. Monitor Data Format
18.3.1.5 Break Signal
A start bit (0) followed by nine 0 bits is a break signal. When the monitor receives a break signal, it drives
the PTA0 pin high for the duration of two bits and then echoes back the break signal.
MISSING STOP BIT
2-STOP BIT DELAY BEFORE ZERO ECHO
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
Figure 18-13. Break Transaction
18.3.1.6 Baud Rate
The communication baud rate is controlled by the external clock and the state of the PTC3 pin (when IRQ
is set to VTST) upon entry into monitor mode. If monitor mode was entered with a blank reset vector and
VDD or VSS on IRQ, then the baud rate is independent of PTC3.
Table 18-1 lists external frequencies required to achieve a standard baud rate of 9600 bps. The effective
baud rate is the bus frequency divided by 256.
18.3.1.7 Commands
The monitor ROM firmware uses these commands:
•
READ (read memory)
•
WRITE (write memory)
•
IREAD (indexed read)
•
IWRITE (indexed write)
•
READSP (read stack pointer)
•
RUN (run user program)
The monitor ROM firmware echoes each received byte back to the PTA0 pin for error checking. An 11-bit
delay at the end of each command allows the host to send a break character to cancel the command. A
delay of two bit times occurs before each echo and before READ, IREAD, or READSP data is returned.
The data returned by a read command appears after the echo of the last byte of the command.
NOTE
Wait one bit time after each echo before sending the next byte.
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
227
Development Support
FROM
HOST
4
ADDRESS
HIGH
READ
READ
ADDRESS
HIGH
4
1
ADDRESS
LOW
1
ADDRESS
LOW
4
DATA
1
3, 2
4
ECHO
RETURN
Notes:
1 = Echo delay, approximately 2 bit times
2 = Data return delay, approximately 2 bit times
3 = Cancel command delay, 11 bit times
4 = Wait 1 bit time before sending next byte.
Figure 18-14. Read Transaction
FROM
HOST
3
ADDRESS
HIGH
WRITE
WRITE
3
1
ADDRESS
HIGH
1
ADDRESS
LOW
3
ADDRESS
LOW
1
DATA
DATA
3
1
2, 3
ECHO
Notes:
1 = Echo delay, approximately 2 bit times
2 = Cancel command delay, 11 bit times
3 = Wait 1 bit time before sending next byte.
Figure 18-15. Write Transaction
A brief description of each monitor mode command is given in Table 18-3 through Table 18-8.
Table 18-3. READ (Read Memory) Command
Description
Read byte from memory
Operand
2-byte address in high-byte:low-byte order
Data Returned
Returns contents of specified address
Opcode
$4A
Command Sequence
SENT TO MONITOR
READ
READ
ADDRESS
HIGH
ADDRESS
HIGH
ADDRESS
LOW
ADDRESS
LOW
ECHO
DATA
RETURN
MC68HC908GP32 Data Sheet, Rev. 10
228
Freescale Semiconductor
Monitor Module (MON)
Table 18-4. WRITE (Write Memory) Command
Description
Operand
Data Returned
Opcode
Write byte to memory
2-byte address in high-byte:low-byte order; low byte followed by data byte
None
$49
Command Sequence
FROM HOST
WRITE
ADDRESS
HIGH
WRITE
ADDRESS
HIGH
ADDRESS
LOW
ADDRESS
LOW
DATA
DATA
ECHO
Table 18-5. IREAD (Indexed Read) Command
Description
Operand
Data Returned
Opcode
Read next 2 bytes in memory from last address accessed
None
Returns contents of next two addresses
$1A
Command Sequence
FROM HOST
IREAD
IREAD
DATA
DATA
ECHO
RETURN
Table 18-6. IWRITE (Indexed Write) Command
Description
Operand
Data Returned
Opcode
Write to last address accessed + 1
Single data byte
None
$19
Command Sequence
FROM HOST
IWRITE
IWRITE
DATA
DATA
ECHO
A sequence of IREAD or IWRITE commands can access a block of memory sequentially over the full
64-Kbyte memory map.
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
229
Development Support
Table 18-7. READSP (Read Stack Pointer) Command
Description
Operand
Data Returned
Opcode
Reads stack pointer
None
Returns incremented stack pointer value (SP + 1) in high-byte:low-byte order
$0C
Command Sequence
FROM HOST
READSP
SP
HIGH
READSP
SP
LOW
ECHO
RETURN
Table 18-8. RUN (Run User Program) Command
Description
Executes PULH and RTI instructions
Operand
None
Data Returned
None
Opcode
$28
Command Sequence
FROM HOST
RUN
RUN
ECHO
The MCU executes the SWI and PSHH instructions when it enters monitor mode. The RUN command
tells the MCU to execute the PULH and RTI instructions. Before sending the RUN command, the host can
modify the stacked CPU registers to prepare to run the host program. The READSP command returns
the incremented stack pointer value, SP + 1. The high and low bytes of the program counter are at
addresses SP + 5 and SP + 6.
SP
HIGH BYTE OF INDEX REGISTER
SP + 1
CONDITION CODE REGISTER
SP + 2
ACCUMULATOR
SP + 3
LOW BYTE OF INDEX REGISTER
SP + 4
HIGH BYTE OF PROGRAM COUNTER
SP + 5
LOW BYTE OF PROGRAM COUNTER
SP + 6
SP + 7
Figure 18-16. Stack Pointer at Monitor Mode Entry
MC68HC908GP32 Data Sheet, Rev. 10
230
Freescale Semiconductor
Monitor Module (MON)
18.3.2 Security
A security feature discourages unauthorized reading of Flash locations while in monitor mode. The host
can bypass the security feature at monitor mode entry by sending eight security bytes that match the
bytes at locations $FFF6–$FFFD. Locations $FFF6–$FFFD contain user-defined data.
NOTE
Do not leave locations $FFF6–$FFFD blank. For security reasons, program
locations $FFF6–$FFFD even if they are not used for vectors.
During monitor mode entry, the MCU waits after the power-on reset for the host to send the eight security
bytes on pin PTA0. If the received bytes match those at locations $FFF6–$FFFD, the host bypasses the
security feature and can read all Flash locations and execute code from Flash. Security remains
bypassed until a power-on reset occurs. If the reset was not a power-on reset, security remains bypassed
and security code entry is not required. See Figure 18-17.
Upon power-on reset, if the received bytes of the security code do not match the data at locations
$FFF6–$FFFD, the host fails to bypass the security feature. The MCU remains in monitor mode, but
reading a Flash location returns an invalid value and trying to execute code from Flash causes an illegal
address reset. After receiving the eight security bytes from the host, the MCU transmits a break character,
signifying that it is ready to receive a command.
NOTE
The MCU does not transmit a break character until after the host sends the
eight security bytes.
VDD
COMMAND
4096 + 32 CGMXCLK CYCLES
BYTE 8
BYTE 2
BYTE 1
RST
FROM HOST
PA0
1
4
BREAK
2
1
COMMAND ECHO
Notes:
1 = Echo delay, approximately 2 bit times
2 = Data return delay, approximately 2 bit times
4 = Wait 1 bit time before sending next byte
5 = Wait until the monitor ROM runs
BYTE 1 ECHO
FROM MCU
1
BYTE 8 ECHO
4
1
BYTE 2 ECHO
5
Figure 18-17. Monitor Mode Entry Timing
To determine whether the security code entered is correct, check to see if bit 6 of RAM address $40 is
set. If it is, then the correct security code has been entered and Flash can be accessed.
If the security sequence fails, the device should be reset by a power-on reset and brought up in monitor
mode to attempt another entry. After failing the security sequence, the Flash module can also be mass
erased by executing an erase routine that was downloaded into internal RAM. The mass erase operation
clears the security code locations so that all eight security bytes become $FF (blank).
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
231
Development Support
MC68HC908GP32 Data Sheet, Rev. 10
232
Freescale Semiconductor
Chapter 19
Electrical Specifications
19.1 Introduction
This section contains electrical and timing specifications.
19.2 Absolute Maximum Ratings
Maximum ratings are the extreme limits to which the microcontroller unit (MCU) can be exposed without
permanently damaging it.
NOTE
This device is not guaranteed to operate properly at the maximum ratings.
Refer to 19.5 5.0-V DC Electrical Characteristics for guaranteed operating
conditions.
Characteristic(1)
Symbol
Value
Unit
Supply voltage
VDD
–0.3 to + 6.0
V
Input voltage
VIn
VSS – 0.3 to VDD + 0.3
V
I
± 15
mA
IPTC0–PTC4
± 25
mA
Maximum current into VDD
Imvdd
150
mA
Maximum current out of VSS
Imvss
150
mA
Tstg
–55 to +150
°C
Maximum current per pin excluding VDD, VSS , and PTC0–PTC4
Maximum current for pins PTC0–PTC4
Storage temperature
Note:
1. Voltages referenced to VSS
NOTE
This device contains circuitry to protect the inputs against damage due to
high static voltages or electric fields; however, it is advised that normal
precautions be taken to avoid application of any voltage higher than
maximum-rated voltages to this high-impedance circuit. For proper
operation, it is recommended that VIn and VOut be constrained to the range
VSS ≤ (VIn or VOut) ≤ VDD. Reliability of operation is enhanced if unused
inputs are connected to an appropriate logic voltage level (for example,
either VSS or VDD).
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
233
Electrical Specifications
19.3 Functional Operating Range
Characteristic
Operating temperature range
Operating voltage range
Symbol
Value
Unit
TA
–40 to +85
°C
VDD
3.0 ±10%
5.0 ±10%
V
19.4 Thermal Characteristics
Characteristic
Symbol
Value
Unit
Thermal resistance
40-pin PDIP
42-pin SDIP
44-pin QFP
θJA
60
60
95
°C/W
I/O pin power dissipation
PI/O
User determined
W
Power dissipation(1)
PD
PD = (IDD × VDD) + PI/O =
K/(TJ + 273 °C)
W
Constant(2)
K
Average junction temperature
TJ
PD × (TA + 273 °C)
+ PD2 × θJA
W/°C
TA + (PD × θJA)
°C
Notes:
1. Power dissipation is a function of temperature.
2. K is a constant unique to the device. K can be determined for a known TA and measured PD. With this value of K, PD and
TJ can be determined for any value of TA.
MC68HC908GP32 Data Sheet, Rev. 10
234
Freescale Semiconductor
5.0-V DC Electrical Characteristics
19.5 5.0-V DC Electrical Characteristics
Symbol
Min
Typ(2)
Max
Unit
VOH
VOH
VOH
IOH1
VDD – 0.8
VDD – 1.5
VDD – 0.8
—
—
—
—
—
—
—
—
50
V
V
V
mA
IOH2
—
—
50
mA
IOHT
—
—
100
mA
VOL
VOL
VOL
IOL1
—
—
—
—
—
—
—
—
0.4
1.5
1.0
50
V
V
V
mA
IOL2
—
—
50
mA
IOLT
—
—
100
mA
Input high voltage
All ports, IRQ, RST, OSC1
VIH
0.7 × VDD
—
VDD
V
Input low voltage
All ports, IRQ, RST, OSC1
VIL
VSS
—
0.2 × VDD
V
—
—
15
4
20
8
mA
mA
—
—
—
—
—
3
20
300
50
500
—
—
—
—
—
µA
µA
µA
µA
µA
0
0
—
—
2
–0.2
mA
0
0
—
—
25
–5
Characteristic(1)
Output high voltage
(ILoad = –2.0 mA) all I/O pins
(ILoad = –10.0 mA) all I/O pins
(ILoad = –10.0 mA) pins PTC0–PTC4 only
Maximum combined IOH for port C, port E,
port PTD0–PTD3
Maximum combined IOH for port PTD4–PTD7,
port A, port B
Maximum total IOH for all port pins
Output low voltage
(ILoad = 1.6 mA) all I/O pins
(ILoad = 10 mA) all I/O pins
(ILoad = 15 mA) pins PTC0–PTC4 only
Maximum combined IOL for port C, port E,
port PTD0–PTD3
Maximum combined IOL for port PTD4–PTD7,
port A, port B
Maximum total IOL for all port pins
VDD supply current
Run(3)
Wait(4)
Stop(5)
25 °C
25 °C with TBM enabled(6)
25 °C with LVI and TBM enabled(6)
–40 °C to 85 °C with TBM enabled(6)
–40 °C to 85 °C with LVI and TBM enabled(6)
IDD
DC injection current(7) (8) (9) (10)
Single pin limit
Vin > VDD
Vin < VSS
Total MCU limit, includes sum of all stressed pins
Vin > VDD
Vin < VSS
IIC
I/O ports Hi-Z leakage current(11)
IIL
—
—
±10
µA
Input current
IIn
—
—
±1
µA
Contined on next page
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
235
Electrical Specifications
Symbol
Min
Typ(2)
Max
Unit
RPU
20
45
65
kΩ
Capacitance
Ports (as input or output)
COut
CIn
—
—
—
—
12
8
pF
Monitor mode entry voltage
VTST
VDD + 2.5
—
9
V
Low-voltage inhibit, trip falling voltage
VTRIPF
3.90
4.25
4.50
V
Low-voltage inhibit, trip rising voltage
VTRIPR
4.20
4.35
4.60
V
Low-voltage inhibit reset/recover hysteresis
(VTRIPF + VHYS = VTRIPR)
VHYS
—
100
—
mV
POR rearm voltage(12)
VPOR
0
—
100
mV
POR reset voltage(13)
VPORRST
0
700
800
mV
RPOR
0.035
—
—
V/ms
Characteristic(1)
Pullup resistors (as input only)
Ports PTA7/KBD7–PTA0/KBD0, PTC6–PTC0,
PTD7/T2CH1–PTD0/SS
POR rise time ramp rate(14)
Notes:
1. VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted
2. Typical values reflect average measurements at midpoint of voltage range, 25 °C only.
3. Run (operating) IDD measured using external square wave clock source (fOSC = 32.8 MHz). All inputs 0.2V from rail. No
dc loads. Less than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly
affects run IDD. Measured with all modules enabled.
4. Wait IDD measured using external square wave clock source (fOSC = 32.8 MHz). All inputs 0.2 V from rail. No dc loads.
Less than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects
wait IDD. Measured with PLL and LVI enabled.
5. Stop IDD is measured with OSC1 = VSS.
6. Stop IDD with TBM enabled is measured using an external square wave clock source (fOSC = 32.8 MHz). All inputs 0.2V
from rail. No dc loads. Less than 100 pF on all outputs. All inputs configured as inputs.
7. This parameter is characterized and not tested on each device.
8. All functional non-supply pins are internally clamped to VSS and VDD.
9. Input must be current limited to the value specified. To determine the value of the required current-limiting resistor,
calculate resistance values for positive and negative clamp voltages, then use the larger of the two values.
10. Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current
conditions. If positive injection current (Vin > VDD) is greater than IDD, the injection current may flow out of VDD and could
result in external power supply going out of regulation. Ensure external VDD load will shunt current greater than maximum
injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock
is present, or if clock rate is very low (which would reduce overall power consumption).
11. Pullups and pulldowns are disabled. Port B leakage is specified in 19.12 ADC Characteristics.
12. Maximum is highest voltage that POR is guaranteed.
13. Maximum is highest voltage that POR is possible.
14. If minimum VDD is not reached before the internal POR reset is released, RST must be driven low externally until minimum
VDD is reached.
MC68HC908GP32 Data Sheet, Rev. 10
236
Freescale Semiconductor
3.0-V DC Electrical Characteristics
19.6 3.0-V DC Electrical Characteristics
Symbol
Min
Typ(2)
Max
Unit
VOH
VOH
VOH
IOH1
VDD – 0.3
VDD – 1.0
VDD – 0.5
—
—
—
—
—
—
—
—
30
V
V
V
mA
IOH2
—
—
30
mA
IOHT
—
—
60
mA
VOL
VOL
VOL
IOL1
—
—
—
—
—
—
—
—
0.3
1.0
0.8
30
V
V
V
mA
IOL2
—
—
30
mA
IOLT
—
—
60
mA
Input high voltage
All ports, IRQ, RST, OSC1
VIH
0.7 × VDD
—
VDD
V
Input low voltage
All ports, IRQ, RST, OSC1
VIL
VSS
—
0.3 × VDD
V
—
—
4.5
1.65
8
4
mA
mA
—
—
—
—
—
2
12
200
30
300
—
—
—
—
—
µA
µA
µA
µA
µA
0
0
—
—
2
–0.2
mA
0
0
—
—
25
–5
Characteristic(1)
Output high voltage
(ILoad = –0.6 mA) all I/O pins
(ILoad = –4.0 mA) all I/O pins
(ILoad = –4.0 mA) pins PTC0–PTC4 only
Maximum combined IOH for port C, port E,
port PTD0–PTD3
Maximum combined IOH for port PTD4–PTD7,
port A, port B
Maximum total IOH for all port pins
Output low voltage
(ILoad = 0.5 mA) all I/O pins
(ILoad = 6.0 mA) all I/O pins
(ILoad = 10.0 mA) pins PTC0–PTC4 only
Maximum combined IOL for port C, port E,
port PTD0–PTD3
Maximum combined IOL for port PTD4–PTD7,
port A, port B
Maximum total IOL for all port pins
VDD supply current
Run(3)
Wait(4)
Stop(5)
25 °C
25 °C with TBM enabled(6)
25 °C with LVI and TBM enabled(6)
–40 °C to 85 °C with TBM enabled(6)
–40 °C to 85 °C with LVI and TBM enabled(6)
IDD
DC injection current(7) (8) (9) (10)
Single pin limit
Vin > VDD
Vin < VSS
Total MCU limit, includes sum of all stressed pins
Vin > VDD
Vin < VSS
IIC
I/O ports Hi-Z leakage current(11)
IIL
—
—
±10
µA
Input current
IIn
—
—
±1
µA
Contined on next page
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
237
Electrical Specifications
Symbol
Min
Typ(2)
Max
Unit
RPU
20
45
65
kΩ
Capacitance
Ports (as input or output)
COut
CIn
—
—
—
—
12
8
pF
Monitor mode entry voltage
VTST
VDD + 2.5
—
9
V
Low-voltage inhibit, trip falling voltage
VTRIPF
2.45
2.60
2.70
V
Low-voltage inhibit, trip rising voltage
VTRIPR
2.55
2.66
2.80
V
Low-voltage inhibit reset/recover hysteresis
(VTRIPF + VHYS = VTRIPR)
VHYS
—
60
—
mV
POR rearm voltage(12)
VPOR
0
—
100
mV
POR reset voltage(13)
VPORRST
0
700
800
mV
RPOR
0.02
—
—
V/ms
Characteristic(1)
Pullup resistors (as input only)
Ports PTA7/KBD7–PTA0/KBD0, PTC6–PTC0,
PTD7/T2CH1–PTD0/SS
POR rise time ramp rate(14)
Notes:
1. VDD = 3.0 Vdc ± 10%, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted
2. Typical values reflect average measurements at midpoint of voltage range, 25 °C only.
3. Run (operating) IDD measured using external square wave clock source (fOSC = 16.4 MHz). All inputs 0.2V from rail. No
dc loads. Less than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly
affects run IDD. Measured with all modules enabled.
4. Wait IDD measured using external square wave clock source (fOSC = 16.4 MHz). All inputs 0.2 V from rail. No dc loads.
Less than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects
wait IDD. Measured with PLL and LVI enabled.
5. Stop IDD is measured with OSC1 = VSS.
6. Stop IDD with TBM enabled is measured using an external square wave clock source (fOSC = 16.4 MHz). All inputs 0.2V
from rail. No dc loads. Less than 100 pF on all outputs. All inputs configured as inputs.
7. This parameter is characterized and not tested on each device.
8. All functional non-supply pins are internally clamped to VSS and VDD.
9. Input must be current limited to the value specified. To determine the value of the required current-limiting resistor,
calculate resistance values for positive and negative clamp voltages, then use the larger of the two values.
10. Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current
conditions. If positive injection current (Vin > VDD) is greater than IDD, the injection current may flow out of VDD and could
result in external power supply going out of regulation. Ensure external VDD load will shunt current greater than maximum
injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock
is present, or if clock rate is very low (which would reduce overall power consumption).
11. Pullups and pulldowns are disabled.
12. Maximum is highest voltage that POR is guaranteed.
13. Maximum is highest voltage that POR is possible.
14. If minimum VDD is not reached before the internal POR reset is released, RST must be driven low externally until minimum
VDD is reached.
MC68HC908GP32 Data Sheet, Rev. 10
238
Freescale Semiconductor
5.0-V Control Timing
19.7 5.0-V Control Timing
Symbol
Min
Max
Unit
fOSC
32
dc
100
32.8
kHz
MHz
Internal operating frequency
fOP (fBUS)
—
8.2
MHz
Internal clock period (1/fOP)
tCYC
122
—
ns
RST input pulse width low
tIRL
100
—
ns
IRQ interrupt pulse width low
(edge-triggered)
tILIH
100
—
ns
IRQ interrupt pulse period
tILIL
(3)
—
tCYC
Characteristic(1)
Frequency of operation
Crystal option
External clock option(2)
Notes:
1. VSS = 0 Vdc; timing shown with respect to 20% VDD and 70% VDD unless otherwise noted.
2. No more than 10% duty cycle deviation from 50%
3. The minimum period, tILIL or tTLTL, should not be less than the number of cycles it takes to execute the interrupt service
routine plus tCYC.
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
239
Electrical Specifications
19.8 3.0-V Control Timing
Symbol
Min
Max
Unit
fOSC
32
dc
100
16.4
kHz
MHz
Internal operating frequency
fOP (fBUS)
—
4.1
MHz
Internal clock period (1/fOP)
tCYC
244
—
ns
RST input pulse width low
tIRL
200
—
ns
IRQ interrupt pulse width low
(edge-triggered)
tILIH
200
—
ns
IRQ interrupt pulse period
tILIL
(3)
—
tCYC
Characteristic(1)
Frequency of operation
Crystal option
External clock option(2)
Notes:
1. VSS = 0 Vdc; timing shown with respect to 20% VDD and 70% VDD unless otherwise noted.
2. No more than 10% duty cycle deviation from 50%
3. The minimum period, tILIL or tTLTL, should not be less than the number of cycles it takes to execute the interrupt service
routine plus tCYC.
tRL
RST
tILIL
tILIH
IRQ
Figure 19-1. RST and IRQ Timing
MC68HC908GP32 Data Sheet, Rev. 10
240
Freescale Semiconductor
Output High-Voltage Characteristics
19.9 Output High-Voltage Characteristics
0
–5
IOH (mA)
–10
–40
0
25
85
–15
–20
–25
–30
–35
–40
3
3.2
3.4
3.6
VOH (V)
3.8
4.0
4.2
VOH > VDD –0.8 V @ IOH = –2.0 mA
VOH > VDD –1.5 V @ IOH = –10.0 mA
Figure 19-2. Typical High-Side Driver Characteristics – Port PTA7–PTA0 (VDD = 4.5 Vdc)
0
IOH (mA)
–5
–40
0
25
85
–10
–15
–20
–25
1.3
1.5
1.7
1.9
VOH (V)
2.1
2.3
2.5
VOH > VDD –0.3 V @ IOH = –0.6 mA
VOH > VDD –1.0 V @ IOH = –4.0 mA
Figure 19-3. Typical High-Side Driver Characteristics – Port PTA7–PTA0 (VDD = 2.7 Vdc)
0
–5
IOH (mA)
–10
–40
0
25
85
–15
–20
–25
–30
–35
–40
3
3.2
3.4
3.6
VOH (V)
3.8
4.0
4.2
VOH > VDD –0.8 V @ IOH = –10.0 mA
Figure 19-4. Typical High-Side Driver Characteristics – Port PTC4–PTC0 (VDD = 4.5 Vdc)
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
241
Electrical Specifications
0
IOH (mA)
–5
–40
0
25
85
–10
–15
–20
–25
1.3
1.5
1.7
1.9
VOH (V)
VOH > VDD –0.5 V @ IOH = –4.0 mA
2.1
2.3
2.5
Figure 19-5. Typical High-Side Driver Characteristics – Port PTC4–PTC0 (VDD = 2.7 Vdc)
0
–10
–20
–40
0
25
85
IOH (mA)
–30
–40
–50
–60
–70
–80
–90
3
3.2
3.4
3.6
3.8
VOH (V)
4.0
4.2
4.4
4.6
VOH > VDD –0.8 V @ IOH = –2.0 mA
VOH > VDD –1.5 V @ IOH = –10.0 mA
Figure 19-6. Typical High-Side Driver Characteristics – Ports PTB7–PTB0, PTC6–PTC5,
PTD7–PTD0, and PTE1–PTE0 (VDD = 5.5 Vdc)
0
IOH (mA)
–5
–40
0
25
85
–10
–15
–20
–25
1.3
1.5
1.7
1.9
VOH (V)
2.1
2.3
2.5
VOH > VDD –0.3 V @ IOH = –0.6 mA
VOH > VDD –1.0 V @ IOH = –4.0 mA
Figure 19-7. Typical High-Side Driver Characteristics – Ports PTB7–PTB0, PTC6–PTC5,
PTD7–PTD0, and PTE1–PTE0 (VDD = 2.7 Vdc)
MC68HC908GP32 Data Sheet, Rev. 10
242
Freescale Semiconductor
Output Low-Voltage Characteristics
19.10 Output Low-Voltage Characteristics
35
30
–40
0
25
85
IOL (mA)
25
20
15
10
5
0
0
0.2
0.4
0.6
0.8
1.0
VOL (V)
1.2
1.4
1.6
VOL < 0.4 V @ IOL = 1.6 mA
VOL < 1.5 V @ IOL = 10.0 mA
Figure 19-8. Typical Low-Side Driver Characteristics – Port PTA7–PTA0 (VDD = 5.5 Vdc)
14
12
–40
0
25
85
IOL (mA)
10
8
6
4
2
0
0.2
0.4
0.6
0.8
1.0
VOL (V)
1.2
1.4
1.6
VOL < 0.3 V @ IOL = 0.5 mA
VOL < 1.0 V @ IOL = 6.0 mA
Figure 19-9. Typical Low-Side Driver Characteristics – Port PTA7–PTA0 (VDD = 2.7 Vdc)
60
IOL (mA)
50
40
–40
0
25
85
30
20
10
0
0.4
0.6
0.8
1.0
1.2
1.4
1.6
VOL (V)
VOL < 1.0 V @ IOL = 15 mA
Figure 19-10. Typical Low-Side Driver Characteristics – Port PTC4–PTC0 (VDD = 4.5 Vdc)
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
243
Electrical Specifications
30
IOL (mA)
25
–40
0
25
85
20
15
10
5
0
0.2
0.4
0.6
0.8
1.0
VOL (V)
1.2
1.6
1.4
VOL < 0.8 V @ IOL = 10 mA
Figure 19-11. Typical Low-Side Driver Characteristics – Port PTC4–PTC0 (VDD = 2.7 Vdc)
35
30
–40
0
25
85
IOL (mA)
25
20
15
10
5
0
0
0.2
0.4
0.6
0.8
1.0
VOL (V)
1.2
1.6
1.4
VOL < 0.4 V @ IOL = 1.6 mA
VOL < 1.5 V @ IOL = 10.0 mA
Figure 19-12. Typical Low-Side Driver Characteristics – Ports PTB7–PTB0, PTC6–PTC5,
PTD7–PTD0, and PTE1–PTE0 (VDD = 5.5 Vdc)
14
12
–40
0
25
85
IOL (mA)
10
8
6
4
2
0
0
0.2
0.4
0.6
0.8
1.0
VOL (V)
1.2
1.4
1.6
VOL < 0.3 V @ IOL = 0.5 mA
VOL < 1.0 V @ IOL = 6.0 mA
Figure 19-13. Typical Low-Side Driver Characteristics – Ports PTB7–PTB0, PTC6–PTC5,
PTD7–PTD0, and PTE1–PTE0 (VDD = 2.7 Vdc)
MC68HC908GP32 Data Sheet, Rev. 10
244
Freescale Semiconductor
Typical Supply Currents
19.11 Typical Supply Currents
16
14
12
IDD (mA)
10
8
6
4
5.5 V
3.6 V
2
0
0
1
2
3
4
5
fBUS (MHz)
6
7
8
9
Figure 19-14. Typical Operating IDD, with All Modules Turned On (–40 °C to 85 °C)
5.0
4.5
4.0
IDD (mA)
3.5
3.0
2.5
2.0
1.5
1.0
5.5 V
3.6 V
0.5
0
0
1
2
3
4
fBUS (MHz)
5
6
7
8
Figure 19-15. Typical Wait Mode IDD, with all Modules Disabled (–40 °C to 85 °C)
1.35
1.30
IDD (mA)
1.25
1.20
1.15
1.10
5.5 V
3.6 V
1.05
1
0
1
2
3
4
5
fBUS (MHz)
6
7
8
9
Figure 19-16. Typical Stop Mode IDD, with all Modules Disabled (–40 °C to 85 °C)
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
245
Electrical Specifications
19.12 ADC Characteristics
Characteristic(1)
Symbol
Min
Max
Unit
Comments
Supply voltage
VDDAD
2.7
(VDD min)
5.5
(VDD max)
V
VDDAD should be tied to
the same potential as VDD
via separate traces.
Input voltages
VADIN
0
VDDAD
V
VADIN ≤ VREFH
Resolution
BAD
8
8
Bits
Absolute accuracy
(VREFL = 0 V,
VREFH = VDDAD = 5 V ± 10%)
AAD
—
±1
LSB
Includes quantization
ADC internal clock
fADIC
0.5
1.048
MHz
tAIC = 1/fADIC, tested only
at 1 MHz
Conversion range
RAD
VREFL
VREFH
V
VREFH = VDDAD
VREFL = VSSAD
Power-up time
tADPU
16
Conversion time
tADC
16
17
tAIC cycles
Sample time(2)
tADS
5
—
tAIC cycles
Zero input reading(3)
ZADI
00
01
Hex
VIN = VREFL
Full-scale reading(3)
FADI
FE
FF
Hex
VIN = VREFH
Input capacitance
CADI
—
(20) 8
pF
Not tested
—
—
±1
µA
Input leakage
Port B
(4)
tAIC cycles
Notes:
1. VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, VDDAD = 5.0 Vdc ± 10%, VSSAD = 0 Vdc, VREFH = 5.0 Vdc ± 10%, VREFL = 0
2. Source impedances greater than 10 kΩ adversely affect internal RC charging time during input sampling.
3. Zero-input/full-scale reading requires sufficient decoupling measures for accurate conversions.
4. The external system error caused by input leakage current is approximately equal to the product of R source and input
current.
MC68HC908GP32 Data Sheet, Rev. 10
246
Freescale Semiconductor
5.0-V SPI Characteristics
19.13 5.0-V SPI Characteristics
Diagram
Number(1)
Characteristic(2)
Symbol
Min
Max
Unit
Operating frequency
Master
Slave
fOP(M)
fOP(S)
fOP/128
dc
fOP/2
fOP
MHz
MHz
1
Cycle time
Master
Slave
tCYC(M)
tCYC(S)
2
1
128
—
tCYC
tCYC
2
Enable lead time
tLead(S)
1
—
tCYC
3
Enable lag time
tLag(S)
1
—
tCYC
4
Clock (SPSCK) high time
Master
Slave
tSCKH(M)
tSCKH(S)
tCYC –25
1/2 tCYC –25
64 tCYC
—
ns
ns
5
Clock (SPSCK) low time
Master
Slave
tSCKL(M)
tSCKL(S)
tCYC –25
1/2 tCYC –25
64 tCYC
—
ns
ns
6
Data setup time (inputs)
Master
Slave
tSU(M)
tSU(S)
30
30
—
—
ns
ns
7
Data hold time (inputs)
Master
Slave
tH(M)
tH(S)
30
30
—
—
ns
ns
8
Access time, slave(3)
CPHA = 0
CPHA = 1
tA(CP0)
tA(CP1)
0
0
40
40
ns
ns
9
Disable time, slave(4)
tDIS(S)
—
40
ns
10
Data valid time, after enable edge
Master
Slave(5)
tV(M)
tV(S)
—
—
50
50
ns
ns
11
Data hold time, outputs, after enable edge
Master
Slave
tHO(M)
tHO(S)
0
0
—
—
ns
ns
Notes:
1. Numbers refer to dimensions in Figure 19-17 and Figure 19-18.
2. All timing is shown with respect to 20% VDD and 70% VDD, unless noted; 100 pF load on all SPI pins.
3. Time to data active from high-impedance state
4. Hold time to high-impedance state
5. With 100 pF on all SPI pins
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
247
Electrical Specifications
19.14 3.0-V SPI Characteristics
Diagram
Number(1)
Characteristic(2)
Symbol
Min
Max
Operating frequency
Master
Slave
fOP(M)
fOP(S)
fOP/128
fOP/2
dc
fOP
MHz
MHz
1
Cycle time
Master
Slave
tCYC(M)
tCYC(S)
2
1
128
—
tCYC
tCYC
2
Enable lead time
tLead(s)
1
—
tCYC
3
Enable lag time
tLag(s)
1
—
tCYC
4
Clock (SPSCK) high time
Master
Slave
tSCKH(M)
tSCKH(S)
tCYC –35
1/2 tCYC –35
64 tCYC
—
ns
ns
Clock (SPSCK) low time
Master
Slave
tSCKL(M)
tSCKL(S)
1/2 tCYC –35
64 tCYC
—
ns
ns
Data setup time (inputs)
Master
Slave
tSU(M)
tSU(S)
40
—
—
ns
ns
Data hold time (inputs)
Master
Slave
tH(M)
tH(S)
40
—
—
ns
ns
Access time, slave(3)
CPHA = 0
CPHA = 1
tA(CP0)
tA(CP1)
0
0
50
50
ns
9
Disable time, slave(4)
tDIS(S)
—
50
ns
10
Data valid time, after enable edge
Master
Slave(5)
tV(M)
tV(S)
—
—
60
60
ns
ns
tHO(M)
tHO(S)
0
—
—
ns
ns
5
6
7
8
11
Data hold time, outputs, after enable edge
Master
Slave
tCYC –35
40
40
0
Unit
ns
Notes:
1. Numbers refer to dimensions in Figure 19-17 and Figure 19-18.
2. All timing is shown with respect to 20% VDD and 70% VDD, unless noted; 100 pF load on all SPI pins.
3. Time to data active from high-impedance state
4. Hold time to high-impedance state
5. With 100 pF on all SPI pins
MC68HC908GP32 Data Sheet, Rev. 10
248
Freescale Semiconductor
3.0-V SPI Characteristics
SS
INPUT
SS PIN OF MASTER HELD HIGH
1
SPSCK OUTPUT
CPOL = 0
NOTE
SPSCK OUTPUT
CPOL = 1
NOTE
5
4
5
4
6
MISO
INPUT
BITS 6–1
MSB IN
11
MOSI
OUTPUT
MASTER MSB OUT
7
LSB IN
10
11
BITS 6–1
MASTER LSB OUT
Note: This first clock edge is generated internally, but is not seen at the SPSCK pin.
a) SPI Master Timing (CPHA = 0)
SS
INPUT
SS PIN OF MASTER HELD HIGH
1
SPSCK OUTPUT
CPOL = 0
5
NOTE
4
SPSCK OUTPUT
CPOL = 1
5
NOTE
4
6
MISO
INPUT
MSB IN
10
MOSI
OUTPUT
BITS 6–1
11
MASTER MSB OUT
7
LSB IN
10
BITS 6–1
MASTER LSB OUT
Note: This last clock edge is generated internally, but is not seen at the SPSCK pin.
b) SPI Master Timing (CPHA = 1)
Figure 19-17. SPI Master Timing
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
249
Electrical Specifications
SS
INPUT
3
1
SPSCK INPUT
CPOL = 0
5
4
2
SPSCK INPUT
CPOL = 1
5
4
9
8
MISO
INPUT
SLAVE
MSB OUT
6
MOSI
OUTPUT
BITS 6–1
7
NOTE
11
11
10
MSB IN
SLAVE LSB OUT
BITS 6–1
LSB IN
Note: Not defined but normally MSB of character just received
a) SPI Slave Timing (CPHA = 0)
SS
INPUT
1
SPSCK INPUT
CPOL = 0
5
4
2
3
SPSCK INPUT
CPOL = 1
8
MISO
OUTPUT
MOSI
INPUT
5
4
10
NOTE
9
SLAVE
MSB OUT
6
7
BITS 6–1
11
10
MSB IN
SLAVE LSB OUT
BITS 6–1
LSB IN
Note: Not defined but normally LSB of character previously transmitted
b) SPI Slave Timing (CPHA = 1)
Figure 19-18. SPI Slave Timing
MC68HC908GP32 Data Sheet, Rev. 10
250
Freescale Semiconductor
Timer Interface Module Characteristics
19.15 Timer Interface Module Characteristics
Characteristic
Symbol
Min
Max
Unit
tTH, tTL
2
—
tcyc
tTLTL
Note(1)
—
tcyc
tTCL, tTCH
tcyc + 5
—
ns
Timer input capture pulse width
Timer input capture period
Timer input clock pulse width
1. The minimum period is the number of cycles it takes to execute the interrupt service routine plus 1 tcyc.
tTLTL
tTH
INPUT CAPTURE
RISING EDGE
tTLTL
tTL
INPUT CAPTURE
FALLING EDGE
tTLTL
tTH
tTL
INPUT CAPTURE
BOTH EDGES
tTCH
TCLK
tTCL
Figure 19-19. Timer Input Timing
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
251
Electrical Specifications
19.16 Clock Generation Module Characteristics
19.16.1 CGM Component Specifications
Characteristic
Symbol
Min
Typ
Max
Unit
Crystal reference frequency
fXCLK
30
32.768
100
kHz
Crystal load capacitance(1)
CL
—
12.5
—
pF
(2)
C1
—
15
—
pF
Crystal tuning capacitance(2)
C2
—
15
—
pF
Feedback bias resistor
RB
1
10
22
MΩ
resistor(3)
RS
100
330
470
kΩ
Crystal fixed capacitance
Series
Notes:
1. Crystal manufacturer value.
2. Capacitor on OSC1 pin. Does not include parasitic capacitance due to package, pin, and board.
3. Capacitor on OSC2 pin. Does not include parasitic capacitance due to package, pin, and board.
MC68HC908GP32 Data Sheet, Rev. 10
252
Freescale Semiconductor
Memory Characteristics
19.16.2 CGM Electrical Specifications
Description
Symbol
Min
Typ
Max
Unit
VDD
2.7
—
5.5
V
T
–40
25
85
°C
Reference frequency
fRDV
30
32.768
100
kHz
Range nominal multiplier
fNOM
—
38.4
—
kHz
VCO center-of-range frequency(1)
fVRS
38.4 k
—
40.0 M
Hz
Medium-voltage VCO center-of-range frequency(2)
fVRS
38.4 k
—
40.0 M
Hz
VCO range linear range multiplier
L
1
—
255
VCO power-of-two range multiplier
2E
1
—
4
VCO multiply factor
N
1
—
4095
VCO prescale multiplier
2P
1
1
8
Reference divider factor
R
1
1
15
VCO operating frequency
fVCLK
38.4 k
—
40.0 M
Hz
Bus operating frequency(1)
fBUS
—
—
8.2
MHz
Bus frequency @ medium voltage(2)
fBUS
—
—
4.1
MHz
Manual acquisition time
tLock
—
—
50
ms
Automatic lock time
tLock
—
—
50
ms
(3)
fJ
0
—
fRCLK ×
0.025%
× 2P N/4
Hz
External clock input frequency
PLL disabled
fOSC
dc
—
32.8 M
Hz
External clock input frequency
PLL enabled
fOSC
30 k
—
1.5 M
Hz
Operating voltage
Operating temperature
PLL jitter
Notes:
1. 5.0 V ± 10% VDD
2. 3.0 V ± 10% VDD
3. Deviation of average bus frequency over 2 ms. N = VCO multiplier.
19.17 Memory Characteristics
Characteristic
RAM data retention voltage
FLASH program bus clock frequency
FLASH read bus clock frequency
FLASH page erase time
Limited endurance (<1 K cycles)
Maximum endurance (>1 K cycles)
Symbol
Min
Typ
Max
Unit
VRDR
1.3
—
—
V
—
1
—
—
MHz
fRead(1)
8k
—
8.4 M
Hz
tErase
0.9
3.6
1
4
1.1
5.5
ms
Contined on next page
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
253
Electrical Specifications
Characteristic
Symbol
Min
Typ
Max
Unit
tMErase
4
—
—
ms
FLASH PGM/ERASE to HVEN setup time
tNVS
10
—
—
µs
FLASH high-voltage hold time
tNVH
5
—
—
µs
FLASH high-voltage hold time (mass erase)
tNVHL
100
—
—
µs
FLASH program hold time
tPGS
5
—
—
µs
FLASH program time
tPROG
30
—
40
µs
FLASH return to read time
tRCV(2)
1
—
—
µs
FLASH cumulative program hv period
tHV(3)
—
—
4
ms
FLASH endurance
—
10 k
100 k
—
Cycles
FLASH data retention time(5)
—
15
100
—
Years
FLASH mass erase time
(4)
1. fRead is defined as the frequency range for which the FLASH memory can be read.
2. tRCV is defined as the time it needs before the FLASH can be read after turning off the high voltage charge pump, by
clearing HVEN to 0.
3. tHV is defined as the cumulative high voltage programming time to the same row before next erase.
tHV must satisfy this condition: tNVS + tNVH + tPGS + (tPROG x 64) ≤ tHV maximum.
4. Typical endurance was evaluated for this product family. For additional information on how Freescale defines Typical
Endurance, please refer to Engineering Bulletin EB619.
5. Typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated
to 25 Cusing the Arrhenius equation. For additional information on how Freescale defines Typical Data Retention, please
refer to Engineering Bulletin EB618.
MC68HC908GP32 Data Sheet, Rev. 10
254
Freescale Semiconductor
Chapter 20
Mechanical Specifications
20.1 Introduction
This section gives the dimensions for:
• 40-pin plastic dual in-line package (case 711-03)
• 42-pin shrink dual in-line package (case 858-01)
• 44-pin plastic quad flat pack (case 824A-01)
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
255
Chapter 21
Ordering Information
21.1 Introduction
This section contains ordering numbers for the MC68HC908GP32.
21.2 MC Order Numbers
Table 21-1. MC Order Numbers
Operating
temperature range
Package
MC908GP32CPE
–40 °C to +85 °C
40-pin PDIP
MC908GP32CBE
–40 °C to +85 °C
42-pin SDIP
MC908GP32CFBE
–40 °C to +85 °C
44-pin QFP
MC order number
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
263
Ordering Information
MC68HC908GP32 Data Sheet, Rev. 10
264
Freescale Semiconductor
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MC68HC908GP32
Rev. 10, 1/2008
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