CC1050
CC1050
Single Chip Very Low Power RF Transmitter
Applications
• Very low power UHF wireless data
transmitters
• 315 / 433 / 868 and 915 MHz ISM/SRD
band systems
•
•
•
•
•
•
RKE – Remote Keyless Entry
Home automation
Wireless alarm and security systems
AMR – Automatic Meter Reading
Low power telemetry
Game Controllers and advanced toys
Product Description
CC1050 is a true single-chip UHF trans-
CC1050 is based on Chipcon’s SmartRF®
mitter designed for very low power and
very low voltage wireless applications. The
circuit is mainly intended for the ISM
(Industrial, Scientific and Medical) and
SRD (Short Range Device) frequency
bands at 315, 433, 868 and 915 MHz, but
can easily be programmed for operation at
other frequencies in the 300-1000 MHz
range.
technology in 0.35 µm CMOS.
The main operating parameters of CC1050
can be programmed via an easy-tointerface serial bus, thus making CC1050 a
very flexible and easy to use transmitter.
In a typical system CC1050 will be used
together with a microcontroller and a few
external passive components.
Features
•
•
•
•
•
•
•
•
•
True single chip UHF RF transmitter
Very low current consumption
Frequency range 300 – 1000 MHz
Programmable output power –20 to
12 dBm
Small size (TSSOP-24 package)
Low supply voltage (2.1 V to 3.6 V)
Very few external components required
Single-ended antenna connection
FSK data rate up to 76.8 kBaud
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• Complies with EN 300 220 and FCC
CFR47 part 15
• Programmable frequency in 250 Hz
steps makes crystal temperature drift
compensation possible without TCXO
• Suitable
for
frequency
hopping
protocols
• Development Kit available
• Easy-to-use software for generating the
CC1050 configuration data
Page 1 of 40
CC1050
Table of Contents
Absolute Maximum Ratings ....................................................................................................... 4
Operating Conditions ................................................................................................................. 4
Electrical Specifications ............................................................................................................. 4
Pin Assignment .......................................................................................................................... 7
Application Circuit ...................................................................................................................... 9
Configuration Overview............................................................................................................ 10
Configuration Software............................................................................................................. 11
3-wire Serial Configuration Interface........................................................................................ 12
Microcontroller Interface........................................................................................................... 14
Signal interface ........................................................................................................................ 15
Frequency programming .......................................................................................................... 17
VCO ......................................................................................................................................... 17
VCO and PLL self-calibration................................................................................................... 17
VCO current control ................................................................................................................. 21
Power management ................................................................................................................. 21
Output Matching....................................................................................................................... 24
Output power programming ..................................................................................................... 25
Crystal oscillator....................................................................................................................... 26
Optional LC Filter ..................................................................................................................... 27
System Considerations and Guidelines ................................................................................... 28
PCB Layout Recommendations ............................................................................................... 29
Antenna Considerations........................................................................................................... 29
Configuration registers ............................................................................................................. 30
Package Description (TSSOP-24) ........................................................................................... 38
Soldering Information ............................................................................................................... 38
Plastic Tube Specification ........................................................................................................ 38
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Page 2 of 40
CC1050
Carrier Tape and Reel Specification ........................................................................................ 38
Ordering Information ................................................................................................................ 39
General Information ................................................................................................................. 39
Address Information ................................................................................................................. 40
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Page 3 of 40
CC1050
Absolute Maximum Ratings
Min.
Max.
Units
Supply voltage, VDD
Voltage on any pin
Parameter
-0.3
-0.3
V
V
Input RF level
Storage temperature range
Reflow soldering temperature
-50
5.0
VDD+0.3,
max 5.0
10
150
260
Under no circumstances the absolute
maximum ratings given above should be
violated. Stress exceeding one or more of
dBm
°C
°C
Condition
T = 10 s
the limiting values may cause permanent
damage to the device.
Caution! ESD sensitive device.
Precaution should be used when handling
the device in order to prevent permanent
damage.
Operating Conditions
Parameter
Min.
Typ.
Max.
Unit
Condition / Note
Programmable in steps of 250 Hz
RF Frequency Range
300
1000
MHz
Operating ambient temperature range
-40
85
°C
Supply voltage
2.1
3.0
3.6
V
Typ.
Max.
Unit
Condition / Note
0.6
76.8
kBaud
NRZ or Manchester encoding.
76.8 kBaud equals 76.8 kbit/s
using NRZ coding. See page 15.
0
65
kHz
The frequency separation is
programmable in 250 Hz steps.
65 kHz is the maximum
guaranteed separation at 1 MHz
reference frequency. Larger
separations can be achieved at
higher reference frequencies.
-20
-20
12
8
dBm
dBm
Note: The same supply voltage
should be used for digital (DVDD)
and analogue (AVDD) power.
Electrical Specifications
Tc = 25°C, VDD = 3.0 V if nothing else stated
Parameter
Min.
Transmit Section
Transmit data rate
Binary FSK frequency separation
Output power
433 MHz
868 MHz
RF output impedance
433/868 MHz
110 / 70
SWRS044
Ω
Delivered to 50 Ω load.
The output power is
programmable.
Transmit mode. For matching
details see p.24.
Page 4 of 40
CC1050
Parameter
Min.
Typ.
Spurious emission
Harmonics
Max.
Unit
Condition / Note
-36
dBm
Complies with EN 300 220
dBc
An external LC should be used to
reduce harmonics emission to
comply with SRD requirements.
See p.27.
MHz
Crystal frequency can be 3-4, 6-8
or 9-16 MHz. Recommended
frequencies are 3.6864, 7.3728,
11.0592 and 14.7456. See page
26 for details.
ppm
433 MHz
868 MHz
The crystal frequency accuracy
and drift (ageing and
temperature dependency) will
determine the frequency accuracy
of the transmitted signal.
-20
Frequency Synthesiser
Section
Crystal Oscillator Frequency
3
± 50
± 25
Crystal frequency accuracy
requirement
Crystal operation
Crystal load capacitance
16
Parallel
12
12
12
22
16
16
C3 and C4 are loading
capacitors, see page 26
30
30
16
pF
pF
pF
3-8 MHz, 22 pF recommended
6-8 MHz, 16 pF recommended
9-16 MHz, 16 pF recommended
3.6864 MHz, 16 pF load
7.3728 MHz, 16 pF load
16 MHz, 16 pF load
Crystal oscillator start-up time
4
1.5
2
ms
ms
ms
Output signal phase noise
-80
dBc/Hz
PLL lock time
200
µs
Up to 1 MHz frequency step
PLL turn-on time, crystal oscillator
on in power down mode
250
µs
Crystal oscillator running
At 100 kHz offset from carrier
Digital Inputs/Outputs
Logic "0" input voltage
0
0.3*VDD
V
Logic "1" input voltage
0.7*VDD
VDD
V
Logic "0" output voltage
0
0.4
V
Output current -2.5 mA,
3.0 V supply voltage
Logic "1" output voltage
2.5
VDD
V
Output current 2.5 mA,
3.0 V supply voltage
Logic "0" input current
NA
-1
µA
Input signal equals GND
Logic "1" input current
NA
1
µA
Input signal equals VDD
DI setup time
20
ns
DI hold time
10
ns
TX mode, minimum time DI must
be ready before the positive edge
of DCLK
TX mode, minimum time DI must
be held after the positive edge of
DCLK
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Page 5 of 40
CC1050
Parameter
Min.
Typ.
Max.
Unit
Serial interface (PCLK, PDATA and
PALE) timing specification
Condition / Note
See Table 2 page 13
Current Consumption
Power Down mode
0.2
1
µA
Oscillator core off
The output power is delivered to a
50Ω load
Current Consumption,
transmit mode 433/868 MHz:
P=0.01mW (-20dBm)
5.5/8.0
mA
P=0.3mW (-5dBm)
7.3/10.0
mA
P=1mW (0dBm)
9.1/14.2
mA
P=3mW (5dBm)
13.3/17.7
mA
P=6mW (8dBm)
15.9/24.9
mA
P=16mW (12dBm)
23.3/NA
mA
Current Consumption, crystal osc.
30
80
105
µA
µA
µA
Current Consumption, crystal osc.
and bias
400
µA
Current Consumption, crystal osc.,
bias and synthesiser
4.0
5.5
mA
mA
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3-8 MHz, 16 pF load
9-14 MHz, 12 pF load
14-16 MHz, 16 pF load
< 500 MHz
> 500 MHz
Page 6 of 40
CC1050
Pin Assignment
Pin no.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
Pin name
AVDD
AGND
AGND
AGND
L1
L2
AVDD
CHP_OUT
Pin type
Power (A)
Ground (A)
Ground (A)
Ground (A)
Analog input
Analog input
Power (A)
Analog output
R_BIAS
AGND
AVDD
AGND
XOSC_Q2
XOSC_Q1
AGND
DGND
DVDD
DGND
DI
DCLK
PCLK
PDATA
Analog output
Ground (A)
Power (A)
Ground (A)
Analog output
Analog input
Ground (A)
Ground (D)
Power (D)
Ground (D)
Digital input
Digital output
Digital input
Digital
input/output
Digital input
RF output
23
PALE
24
RF_OUT
A=Analog, D=Digital
Description
Power supply (3 V) for analog modules (PA)
Ground connection (0 V) for analog modules (PA)
Ground connection (0 V) for analog modules (PA)
Ground connection (0 V) for analog modules (VCO and prescaler)
Connection no 1 for external VCO tank inductor
Connection no 2 for external VCO tank inductor
Power supply (3 V) for analog modules (VCO and prescaler)
Charge pump current output when external loop filter is used
The pin can also be used as PLL Lock indicator. Output is high
when PLL is in lock.
Connection for external precision bias resistor (82 kΩ, ± 1%)
Ground connection (0 V) for analog modules (backplane)
Power supply (3 V) for analog modules (general)
Ground connection (0 V) for analog modules (general)
Crystal, pin 2
Crystal, pin 1, or external clock input
Ground connection (0 V) for analog modules (guard)
Ground connection (0 V) for digital modules (substrate)
Power supply (3 V) for digital modules
Ground connection (0 V) for digital modules
Data input in transmit mode
Clock for data in transmit mode
Programming clock for 3-wire bus
Programming data for 3-wire bus. Programming data input for
write operation, programming data output for read operation
Programming address latch enable for 3-wire bus
RF signal output to antenna
(Top View)
1
24
2
23
3
22
4
21
5
20
AVDD
RF_OUT
AGND
PALE
AGND
PDATA
AGND
PCLK
6
L2
7
AVDD
8
CHP_OUT
9
R_BIAS
DCLK
CC1050
L1
19
DI
18
DGND
17
DVDD
16
DGND
10
15
11
14
12
13
AGND
AGND
AVDD
XOSC_Q1
AGND
XOSC_Q2
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Page 7 of 40
CC1050
Circuit Description
CONTROL
DI
3
RF_OUT
DCLK
PDATA, PCLK, PALE
/N
PA
BIAS
VCO
~
L1 L2
CHARGE
PUMP
LPF
PD
/R
OSC
R_BIAS
XOSC_Q2
XOSC_Q1
CHP_OUT
Figure 1. Simplified block diagram
A simplified block diagram of CC1050 is
shown in Figure 1. Only signal pins are
shown.
The voltage controlled oscillator (VCO)
output signal is fed directly to the power
amplifier (PA). The RF output is frequency
shift keyed (FSK) by the digital bit stream
fed to the pin DI. The single ended PA
makes the antenna interface and matching
very easy.
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The frequency synthesiser generates the
local oscillator signal which is fed to the
PA in transmit mode. The frequency
synthesiser consists of a crystal oscillator
(OSC), phase detector (PD), charge pump
(CHARGE PUMP), VCO, and frequency
dividers (/R and /N). An external crystal
must be connected to XOSC, and only an
external inductor is required for the VCO.
The 3-wire digital serial interface
(CONTROL) is used for configuration.
Page 8 of 40
CC1050
Application Circuit
Very few external components are
required for the operation of CC1050. A
typical application circuit is shown Figure
2. Component values are shown in Table
1.
Crystal oscillator
C3 and C4 are the loading capacitors for
the crystal. See page 26 for details.
Additional filtering
Additional filtering (e.g. a low pass LCfilter) may be used in order to reduce the
harmonic emission. See also Optional LC
Filter p.27 for further information.
Output matching
C1, C2 and L2 are used to match the
transmitter to 50 Ω. See Output Matching
p.24 for details.
Power supply decoupling and filtering
Power supply decoupling and filtering
must be used (not shown in the
application circuit). The placement and
size of the decoupling capacitors and the
power supply filtering are very important to
achieve the optimum performance.
Chipcon provides a reference design
(CC1050EB) that should be followed very
closely.
VCO inductor
The VCO is completely integrated except
for the inductor L1. For further details see
p. 17.
Component values for the matching
network and VCO inductor are easily
calculated using the SmartRF® Studio
software.
AVDD=3V
AVDD=3V
AGND
3
L1
6
L2
7
AVDD
8
CHP_OUT
9
10
11
12
PDATA
CC1050
AGND
5
R1
PALE
AGND
4
NC
RF_OUT
AVDD
2
L1
C1
PCLK
DCLK
DI
DGND
DVDD
R_BIAS
DGND
AGND
AGND
AVDD
AGND
XOSC_ Q1
XOSC_ Q2
24
23
22
21
20
19
Antenna
(50 Oh m)
LC filter
C2
TO/FROM
MICROCONTROLLER
1
L2
Optional
18
DVDD=3V
17
16
15
14
13
XTA L
C3
C4
Figure 2. Typical CC1050 application circuit
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Page 9 of 40
CC1050
Item
C1
C2
C3*
C4*
L1
L2
R1
XTAL
315 MHz
5.6 pF, 5%, C0G, 0603
8.2 pF, 5%, C0G, 0603
15 pF, 5%, C0G, 0603
15 pF, 5%, C0G, 0603
56 nH, 5%, 0603
20 nH, 10%, 0805
82 kΩ, 1%, 0603
14.7456 MHz crystal,
16 pF load
433 MHz
12 pF, 5%, C0G, 0603
6.8 pF, 5%, C0G, 0603
15 pF, 5%, C0G, 0603
15 pF, 5%, C0G, 0603
33 nH, 5%, 0603
6.2 nH, 10%, 0805
82 kΩ, 1%, 0603
14.7456 MHz crystal,
16 pF load
868 MHz
4.7 pF, 5%, C0G, 0603
5.6 pF, 5%, C0G, 0603
15 pF, 5%, C0G, 0603
15 pF, 5%, C0G, 0603
5.6 nH, 5%, 0603
2.5 nH, 10%, 0805
82 kΩ, 1%, 0603
14.7456 MHz crystal,
16 pF load
915 MHz
4.7 pF, 5%, C0G, 0603
5.6 pF, 5%, C0G, 0603
15 pF, 5%, C0G, 0603
15 pF, 5%, C0G, 0603
5.6 nH, 5%, 0603
2.5 nH, 10%, 0805
82 kΩ, 1%, 0603
14.7456 MHz crystal,
16 pF load
Notes:
Items shaded are different for different frequencies.
Component values for 868 and 915 MHz are equal.
*) C3 and C4 will depend on the crystal load capacitance, see page 26.
Table 1. Bill of materials for the application circuit
Configuration Overview
CC1050 can be configured to achieve the
best
performance
for
different
applications. Through the programmable
configuration registers the following key
parameters can be programmed:
• Transmit mode / power-down / powerup mode
• RF output power
• Frequency
synthesiser
key
parameters: RF output frequency, FSK
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•
•
•
•
frequency
separation
(deviation),
crystal oscillator reference frequency
Crystal oscillator power-up / power
down
Data rate and data format (NRZ,
Manchester coded or UART interface)
Synthesiser lock indicator mode
Modulation spectrum shaping
Page 10 of 40
CC1050
Configuration Software
Chipcon provides users of CC1050 with a
software program, SmartRF® Studio
(Windows interface) that generates all
necessary CC1050 configuration data
based on the user's selections of various
parameters. These hexadecimal numbers
will then be the necessary input to the
microcontroller for the configuration of
CC1050. In addition the program will
provide the user with the component
values needed for the output matching
circuit and the VCO inductor.
Figure 3 shows the user interface of the
CC1050 configuration software.
Figure 3. SmartRF® Studio user interface
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Page 11 of 40
CC1050
3-wire Serial Configuration Interface
CC1050 is configured via a simple 3-wire
interface (PDATA, PCLK and PALE).
There are 19 8-bit configuration registers,
each addressed by a 7-bit address. A
Read/Write bit initiates a read or write
operation. A full configuration of CC1050
requires sending 19 data frames of 16 bits
each (7 address bits, R/W bit and 8 data
bits). The time needed for a full
configuration depend on the PCLK
frequency. With a PCLK frequency of 10
MHz the full configuration is done in less
than 30 µs. Setting the device in power
down mode requires sending one frame
only and will in this case take less than 2
µs. All registers are also readable.
The timing for the programming is also
shown in Figure 4 with reference to Table
2. The clocking of the data on PDATA is
done on the negative edge of PCLK.
When the last bit, D0, of the 8 data-bits
has been loaded, the data word is loaded
in the internal configuration register.
The configuration data is stored in internal
RAM and is valid after power-down mode,
but not when the power-supply is turned
off. The registers can be programmed in
any order.
The configuration registers can also be
read by the microcontroller via the same
configuration interface. The seven address
bits are sent first, then the R/W bit set low
to initiate the data read-back. CC1050 then
returns the data from the addressed
register. PDATA is in this case used as an
output and must be tri-stated (or set high n
the case of an open collector pin) by the
microcontroller during the data read-back
(D7:0). The read operation is illustrated in
Figure 5.
In each write-cycle 16 bits are sent on the
PDATA-line. The seven most significant
bits of each data frame (A6:0) are the
address-bits. A6 is the MSB (Most
Significant Bit) of the address and is sent
as the first bit. The next bit is the R/W bit
(high for write, low for read). During
address and R/W bit transfer the PALE
(Program Address Latch Enable) must be
kept low. The 8 data-bits are then
transferred (D7:0). See Figure 4.
TSA
THA
TCH,min
TCL,min
TSA
THD
TSD
PCLK
Address
PDATA
6
5
4
Write mode
3
2
1
0
W
Data byte
7
6
5
4
3
2
1
0
PALE
Figure 4. Configuration registers write operation
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Page 12 of 40
CC1050
PCLK
Address
PDATA
6
5
4
3
Read mode
2
1
0
R
Data byte
7
6
5
4
3
2
1
0
PALE
Figure 5. Configuration registers read operation
Parameter
Symbol
Min
Max
Units
Conditions
PCLK, clock
frequency
FCLOCK
-
10
MHz
PCLK low
pulse
duration
TCL,min
50
ns
The minimum time PCLK must be low.
PCLK high
pulse
duration
TCH,min
50
ns
The minimum time PCLK must be high.
PALE setup
time
TSA
10
-
ns
The minimum time PALE must be low before
negative edge of PCLK.
PALE hold
time
THA
10
-
ns
The minimum time PALE must be held low after
the positive edge of PCLK.
PDATA setup
time
TSD
10
-
ns
The minimum time data on PDATA must be ready
before the negative edge of PCLK.
PDATA hold
time
THD
10
-
ns
The minimum time data must be held at PDATA,
after the negative edge of PCLK.
Rise time
Trise
100
ns
The maximum rise time for PCLK and PALE
Fall time
Tfall
100
ns
The maximum fall time for PCLK and PALE
Note: The set-up- and hold-times refer to 50% of VDD.
Table 2. Serial interface, timing specification
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Page 13 of 40
CC1050
Microcontroller Interface
Used in a typical system, CC1050 will
interface to a microcontroller. This
microcontroller must be able to:
•
•
•
•
Program CC1050 into different modes
via the 3-wire serial configuration
interface (PDATA, PCLK and PALE).
Interface to the synchronous data
signal interface (DI and DCLK).
Connecting the microcontroller
The microcontroller uses 3 output pins for
the configuration interface (PDATA, PCLK
and PALE). PDATA should be a bidirectional pin for data read-back. The DI
pin is used for data to be transmitted.
DCLK providing the data timing should be
connected to a microcontroller input.
Optionally another pin can be used to
monitor the LOCK signal (available at the
CHP_OUT pin). This signal is logic level
high when the PLL is in lock. See
Figure 6.
CC1050
Optionally the microcontroller can do
data encoding / decoding.
Optionally the microcontroller can
monitor the frequency lock status from
pin CHP_OUT (LOCK).
The microcontroller pins connected to
PDATA and PCLK can be used for other
purposes when the configuration interface
is not used. PDATA and PCLK are high
impedance inputs as long as PALE high.
PALE has an internal pull-up resistor and
should be left open (tri-stated by the
microcontroller) or set to a high level
during power down mode in order to
prevent a trickle current flowing in the pullup.
PDATA
PCLK
PALE
Microcontroller
DI
DCLK
CHP_OUT
(LOCK)
(Optional)
Figure 6. Microcontroller interface
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Page 14 of 40
CC1050
Signal interface
The signal interface consists of DI and
DCLK and is used for the data to be
transmitted. DI is the data input line and
DCLK provides a synchronous clock
during data transmission.
the data rates 0.3, 0.6, 1.2, 2.4, 4.8, 9.6,
19.2 or 38.4 kbit/s. The 38.4 kbit/s rate
corresponds to the maximum 76.8 kBaud
due to the Manchester encoding. See
Figure 8.
The CC1050 can be used with NRZ (NonReturn-to-Zero) data or Manchester (also
known as bi-phase-level) encoded data.
CC1050 can be configured for three
different data formats:
Transparent Asynchronous UART mode.
In transmit mode DI is used as data input.
The data is modulated at RF without
synchronisation or encoding. Data rates in
the range from 0.6 to 76.8 kBaud can be
used. See Figure 9.
Synchronous NRZ mode. CC1050 provides
the data clock at DCLK, and DI is used as
data input. Data is clocked into CC1050 at
the rising edge of DCLK. The data is
modulated at RF without encoding. CC1050
can be configured for the data rates 0.6,
1.2, 2.4, 4.8, 9.6, 19.2, 38.4 or 76.8 kbit/s.
See Figure 7.
Manchester encoding
In the Synchronous Manchester encoded
mode CC1050 uses Manchester coding
when
modulating
the
data.
The
Manchester code is based on transitions;
a “0” is encoded as a low-to-high
transition, a “1” is encoded as a high-tolow transition. See Figure 10.
Synchronous Manchester encoded mode.
CC1050 provides the data clock at DCLK,
and DI is used as data input. Data is
clocked into CC1050 at the rising edge of
DCLK and should be in NRZ format. The
data is modulated at RF with Manchester
code. The encoding is done by CC1050. In
this mode CC1050 can be configured for
The Manchester code ensures that the
signal has a constant DC component,
which is necessary in some FSK
demodulators. Using this mode also
ensures compatibility with CC400/CC900
designs.
DCLK
Clock provided by CC1050
DI
Data provided by microcontroller
“RF”
FSK modulating signal (NRZ),
internal in CC1050
Figure 7. Synchronous NRZ mode
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Page 15 of 40
CC1050
DCLK
Clock provided by CC1050
DI
Data provided by microcontroller (NRZ)
“RF”
FSK modulating signal (Manchester encoded),
internal in CC1050
Figure 8. Synchronous Manchester encoded mode
DCLK
DCLK is not used
DI
Data provided by UART (TXD)
“RF”
FSK modulating signal,
internal in CC1050
Figure 9. Transparent Asynchronous UART mode
10110001101
TX
data
Time
Figure 10. Manchester encoding
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Page 16 of 40
CC1050
Frequency programming
The operation frequency is set by
programming the frequency word in the
configuration registers. There are two
frequency words registers, termed A and
B, which can be programmed to two
different frequencies in order to switch fast
between
two
different
channels.
Frequency word A or B is selected by the
F_REG bit in the MAIN register.
The frequency word is 24 bits (3 bytes)
located in FREQ_2A:FREQ_1A:FREQ_0A
and FREQ_2B:FREQ_1B:FREQ_0B for
the A and B word respectively.
The FSK
frequency separation is
programmed in the FSEP1:FSEP0
registers (11 bits).
The frequency word FREQ is calculated
by:
FREQ + 8192
16384
fVCO = f ref ⋅
where the reference frequency is the
crystal oscillator clock divided by REFDIV
(4 bits in the PLL register), a number
between 2 and 15:
f ref =
f xosc
REFDIV
The equation above gives the VCO
frequency, that is, fVCO is the f0 frequency
for transmit mode (lower FSK frequency).
The upper FSK frequency is given by:
f1 = f0 + fsep
where fsep is set by the separation word:
f sep = f ref ⋅
FSEP
16384
VCO
Only one external inductor (L1) is required
for the VCO. The inductor will determine
the operating frequency range of the
circuit. It is important to place the inductor
as close to the pins as possible in order to
reduce
stray
inductance.
It
is
recommended to use a high Q, low
tolerance inductor for best performance.
Typical tuning range for the integrated
varactor is 20-25%.
Component values for various frequencies
are given in Table 1. Component values
for other frequencies can be found using
the SmartRF® Studio software.
VCO and PLL self-calibration
To compensate for supply voltage,
temperature and process variations the
VCO and PLL must be calibrated. The
calibration is done automatically and sets
maximum VCO tuning range and optimum
charge pump current for PLL stability.
After setting up the device at the operating
frequency, the self-calibration can be
initiated by setting the CAL_START bit.
The calibration result is stored internally in
the chip, and is valid as long as power is
not turned off. If large supply voltage
variations (more than 0.5 V) or
temperature variations (more than 40
degrees) occur after calibration, a new
calibration should be performed.
SWRS044
The self-calibration is controlled through
the CAL register (see configuration
registers description p. 30). The
CAL_COMPLETE bit indicates complete
calibration. The user can poll this bit, or
simply wait for 26 ms (calibration wait time
when CAL_WAIT = 1). The wait time is
proportional to the internal PLL reference
frequency. The lowest permitted reference
frequency (1 MHz) gives 26 ms wait time,
which is therefore the worst case.
Reference
frequency [MHz]
2.4
2.0
1.5
1.0
Calibration time
[ms]
11
13
18
26
Page 17 of 40
CC1050
The CAL_COMPLETE bit can also be
monitored at the CHP_OUT (LOCK) pin
(configured by LOCK_SELECT[3:0]) and
used as an interrupt input to the
microcontroller.
The CAL_START bit must be set to 0 by
the microcontroller after the calibration is
done.
There are separate calibration values for
the two frequency registers. If the two
frequencies, A and B, differ more than 1
SWRS044
MHz, or different VCO currents are used
(VCO_CURRENT[3:0] in the CURRENT
register) the calibration should be done
separately. The CAL_DUAL bit in the CAL
register controls dual or separate
calibration.
The single calibration algorithm using
separate calibration for two frequencies is
illustrated in Figure 11.
In Figure 12 the dual calibration algorithm
is shown.
Page 18 of 40
CC1050
Start single calibration
Write FREQ_A, FREQ_B
If DR>=38kBd then {write TEST4: L2KIO=3Fh,
PRESCALER = 04h}
Write CAL: CAL_DUAL = 0
Write MAIN:
F_REG = 0; TX_PD = 0; FS_PD = 0
CORE_PD = 0; BIAS_PD = 0; RESET_N=1
Frequency register A and B are used for
two different channels
Frequency register A is calibrated first
‘Current’ is the VCO current to be used
for both frequencies
PA is turned off to prevent spurious emission
Write CURRENT:
VCO_CURRENT = Current
Write PA_POW = 00h
The result of the calibration is stored for
frequency FREQ_A and can be read from
the status registers TEST0 and TEST2
when F_REG = 0
Write CAL:
CAL_START=1
Calibration time depend on the reference
frequency, see text.
Wait for maximum 26 ms, or
Read CAL and wait until
CAL_COMPLETE=1
Write CAL:
CAL_START=0
Frequency register B is calibrated second
Write MAIN: F_REG = 1
The result of the calibration is stored for
frequency FREQ_B and can be read from
the status registers TEST0 and TEST2
when F_REG = 1
Write CAL:
CAL_START=1
Wait for 26 ms, or
Read CAL and wait until
CAL_COMPLETE=1
Write CAL:
CAL_START=0
End of calibration
Figure 11. Single calibration algorithm for two different frequencies
SWRS044
Page 19 of 40
CC1050
Start dual calibration
Write FREQ_A, FREQ_B
If DR>=38kBd then {write TEST4: L2KIO=3Fh,
PRESCALER = 04h}
Write CAL: CAL_DUAL = 1
Write MAIN:
F_REG = 0
TX_PD = 0; FS_PD = 0
CORE_PD = 0; BIAS_PD = 0; RESET_N=1
Write CURRENT:
VCO_CURRENT = Current
Write PA_POW = 00h
Frequency registers A and B are both used
Either frequency register A or B is selected
‘Current’ is the VCO current to be
used for both frequencies
The result of the calibration is stored for
Both frequency FREQ_A and FREQ_B, and
can be read from the status registers TEST0
and TEST2
Write CAL:
CAL_START=1
Wait for maximum 26 ms, or
Read CAL and wait until
CAL_COMPLETE=1
Calibration time depend on the reference
frequency, see text.
Write CAL:
CAL_START=0
End of calibration
Figure 12. Dual calibration algorithm
SWRS044
Page 20 of 40
CC1050
VCO current control
The VCO current is programmable and
should be set according to operating
frequency
and
output
power.
Recommended
settings
for
the
VCO_CURRENT bits in the CURRENT
register are shown in the tables on page
32.
The bias current for the PA buffers are
also
programmable.
Recommended
settings for the PA_DRIVE bits in the
CURRENT register are shown in the
tables on page 32.
Power management
CC1050 offers great flexibility for power
management in order to meet strict power
consumption requirements in battery
operated applications. Power Down mode
is controlled through the MAIN register.
There are separate bits to control the TX
part, the frequency synthesiser and the
crystal oscillator. This individual control
can be used to optimise for lowest
possible current consumption in a certain
application.
SWRS044
A typical power-on and initialising
sequence
for
minimum
power
consumption is shown in Figure 13 and
Figure 14.
PALE should be tri-stated or set to a high
level during power down mode in order to
prevent a trickle current from flowing in the
internal pull-up resistor.
PA_POW should be set to 00h during
power down mode to ensure lowest
possible
leakage
current.
Page 21 of 40
CC1050
Power Off
Power turned on
Initialise and reset:
MAIN:
F_REG = 0
TX_PD = 1
FS_PD = 1
CORE_PD = 0
BIAS_PD = 1
RESET_N = 0
Reset and turn on the
crystal oscillator core
MAIN: RESET_N = 1
Wait 2 ms*
*Time to wait depends on the crystal frequency
and the load capacitance
Program all registers except MAIN
Calibrate VCO and PLL
Calibration is performed according
to calibration algorithm
PA_POW = 00h
MAIN: TX_PD = 1, FS_PD = 1,
CORE_PD = 1, BIAS_PD = 1
Power Down
Figure 13. Initializing sequence
SWRS044
Page 22 of 40
CC1050
Power Down
Turn on crystal oscillator core
MAIN: CORE_PD = 0
Wait 2 ms*
*Time to wait depends on the crystal frequency
and the load capacitance
Turn on bias generator
BIAS_PD = 0
Wait 200 µs
Turn on TX:
PA_POW = 00h
MAIN: F_REG = 1
FS_PD = 0
Wait 250 µs
TX_PD = 0
PA_POW = ‘Output power’
Wait 20 µs
Waiting for the PLL to lock
Waiting for the PA to ramp up
TX mode
Turn off TX:
PA_POW = 00h
MAIN: TX_PD = 1, FS_PD = 1,
CORE_PD=1, BIAS_PD=1
Power Down
Figure 14. Sequence for activating TX mode
SWRS044
Page 23 of 40
CC1050
Output Matching
A few passive external components
ensures match in TX mode. The matching
network is shown in Figure 15.
Component values for various frequencies
TO ANTENNA
are given in Table 1. Component values
for other frequencies can be found using
the configuration software.
RF_OUT
CC1050
C2
C1
L2
AVDD=3V
Figure 15. Output matching network
SWRS044
Page 24 of 40
CC1050
Output power programming
The RF output power is programmable
and controlled by the PA_POW register.
In power down mode the PA_POW should
be set to 00h for minimum leakage
current.
Table 3 shows the closest programmable
value for output powers in steps of 1 dB.
The typical current consumption is also
shown.
Output power
[dBm]
-20
-19
-18
-17
-16
-15
-14
-13
-12
-11
-10
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
1
2
3
4
5
6
7
8
9
10
11
12
RF frequency 433 MHz
PA_POW
Current consumption,
[hex]
typ. [mA]
01
5.5
01
5.5
01
5.5
02
5.7
02
5.7
02
5.7
02
5.7
03
6.0
03
6.0
04
6.2
04
6.2
05
6.5
05
6.5
06
6.8
07
7.0
08
7.3
09
7.5
0A
7.8
0C
8.3
0D
8.5
0F
9.1
40
10.5
50
11.5
50
11.5
60
12.4
70
13.3
80
14.7
90
15.1
A0
15.9
C0
17.6
E0
19.2
F0
20.0
FF
23.3
RF frequency 868 MHz
PA_POW
Current consumption,
[hex]
typ. [mA]
02
8.0
02
8.0
02
8.0
03
8.3
03
8.3
04
8.5
04
8.5
05
8.7
05
8.7
06
8.9
06
8.9
07
9.1
08
9.4
09
9.6
0A
9.8
0B
10.0
0D
10.4
0E
10.6
0F
10.9
40
13.4
50
14.2
60
15.0
70
15.7
80
16.3
90
17.0
A0
17.7
C0
19.1
E0
20.0
FF
24.9
Table 3. Output power settings and typical current consumption
SWRS044
Page 25 of 40
CC1050
Crystal oscillator
CC1050 has
an advanced amplitude
regulated crystal oscillator. A high current
is used to start up the oscillations. When
the amplitude builds up, the current is
reduced to what is necessary to maintain
a 600 mVpp amplitude. This ensures a
fast
start-up,
keeps
the
current
consumption as well as the drive level to a
minimum and makes the oscillator
insensitive to ESR variations.
f xtal _ new = f xtal
DRnew
DR
Using the internal crystal oscillator, the
crystal must be connected between
XOSC_Q1 and XOSC_Q2. The oscillator
is designed for parallel mode operation of
the crystal. In addition loading capacitors
(C3 and C4) for the crystal are required.
The loading capacitor values depend on
the total load capacitance, CL, specified for
the crystal. The total load capacitance
seen between the crystal terminals should
equal CL for the crystal to oscillate at the
specified frequency.
An external clock signal or the internal
crystal oscillator can be used as main
frequency reference. An external clock
signal should be connected to XOSC_Q1,
while XOSC_Q2 should be left open. The
XOSC_BYPASS bit in the XOSC register
should be set when an external clock
signal is used.
CL =
The crystal frequency should be in the
range 3-4, 6-8 or 9-16 MHz. Because the
crystal frequency is used as reference for
the data rate (as well as other internal
functions), the following frequencies are
recommended: 3.6864, 7.3728, 11.0592
or 14.7456 MHz. These frequencies will
give accurate data rates. The crystal
frequency
range
is
selected
by
XOSC_FREQ1:0 in the MODEM0 register.
1
1
1
+
C3 C 4
+ C parasitic
The parasitic capacitance is constituted by
pin input capacitance and PCB stray
capacitance. Typically the total parasitic
capacitance is 8 pF. A trimming capacitor
may be placed across C4 for initial tuning
if necessary.
The crystal oscillator circuit is shown in
Figure 16. Typical component values for
different values of CL are given in Table 4.
To operate in synchronous mode at data
rates different from the standards at 1.2,
2.4, 4.8 kBaud and so on, the crystal
frequency can be scaled. The data rate
(DR) will change proportionally to the new
crystal frequency (f). To calculate the new
crystal frequency:
The initial tolerance, temperature drift,
ageing and load pulling should be carefully
specified in order to meet the required
frequency
accuracy
in
a
certain
application.
XOSC_Q1
XOSC_Q2
XTAL
C3
C4
Figure 16. Crystal oscillator circuit
Item
C3
C4
CL= 12 pF
6.8 pF
6.8 pF
CL= 16 pF
15 pF
15 pF
CL= 22 pF
27 pF
27 pF
Table 4. Crystal oscillator component values
SWRS044
Page 26 of 40
CC1050
Optional LC Filter
An optional LC filter may be added
between the antenna and the matching
network in certain applications. The filter
will reduce the emission of harmonics.
A T-Type LC filter can be used to further
attenuate harmonics if the Pi-type filter is
not sufficient. A T-type filter provides much
better stop-band attenuation than a Pitype filter due to improved insulation
between input and output. For more
details refer to Application Note AN028 LC
Filter with Improved High-Frequency
Attenuation available from the Chipcon
web
site.
A Pi-type filter topology is shown in Figure
17. Component values are given in Table
5. The filter is designed for 50 Ω
terminations. The component values may
have to be tuned to compensate for layout
parasitics.
L71
C71
C72
Figure 17. LC filter
Item
C71
C72
L71
315 MHz
30 pF
30 pF
15 nH
433 MHz
20 pF
20 pF
12 nH
868 MHz
10 pF
10 pF
5.6 nH
915 MHz
10 pF
10 pF
4.7 nH
Table 5. LC filter component values
SWRS044
Page 27 of 40
CC1050
System Considerations and Guidelines
SRD regulations
International regulations and national laws
regulate the use of radio receivers and
transmitters. SRDs (Short Range Devices)
for licence free operation are allowed to
operate in the 433 and 868-870 MHz
bands in most European countries. In the
United States such devices operate in the
260–470 and 902-928 MHz bands. CC1050
is designed to meet the requirements for
operation in all these bands. A summary
of the most important aspects of these
regulations can be found in Application
Note AN001 SRD regulations for licence
free transceiver operation, available from
Chipcon’s web site.
Low cost systems
In systems where low cost is of great
importance the CC1050 is the ideal choice.
Very few external components keep the
total cost at a minimum. The oscillator
crystal can then be a low cost crystal with
50 ppm frequency tolerance.
Battery operated systems
In low power applications the power down
mode should be used when not being
active. Depending on the start-up time
requirement, the oscillator core can be
powered during power down. See page 21
for information on how effective power
management can be implemented.
Crystal drift compensation
A unique feature in CC1050 is the very fine
frequency resolution of 250 Hz. This can
be used to do the temperature
SWRS044
compensation of the crystal if the
temperature drift curve is known and a
temperature sensor is included in the
system. Even initial adjustment can be
done using the frequency programmability.
This eliminates the need for an expensive
TCXO and trimming in some applications.
In less demanding applications a crystal
with low temperature drift and low ageing
could
be
used
without
further
compensation. A trimmer capacitor in the
crystal oscillator circuit (in parallel with C4)
could be used to set the initial frequency
accurately.
High output power systems
The CHP_OUT (LOCK) pin can be
configured to control an power amplifier.
This is controlled by LOCK_SELECT in
the LOCK register.
Frequency hopping spread spectrum
systems
Due to the very fast frequency shift
properties of the PLL, the CC1050 is also
suitable for frequency hopping systems.
Hop rates of 1-100 hops/s are usually
used depending on the bit rate and the
amount of data to be sent during each
transmission. The two frequency registers
(FREQ_A and FREQ_B) are designed
such that the ‘next’ frequency can be
programmed while the ‘present’ frequency
is used. The switching between the two
frequencies is done through the MAIN
register.
Page 28 of 40
CC1050
PCB Layout Recommendations
A two layer PCB is highly recommended.
The bottom layer of the PCB should be the
“ground-layer”. Chipcon provide reference
designs that should be followed in order to
achieve the best performance.
The top layer should be used for signal
routing, and the open areas should be
filled with metallisation connected to
ground using several vias.
The ground pins should be connected to
ground as close as possible to the
package pin using individual vias. The decoupling capacitors should also be placed
as close as possible to the supply pins
and connected to the ground plane by
separate vias.
The external components should be as
small as possible and surface mount
devices should be used.
Precaution should be used when placing
the microcontroller in order to avoid
interference with the RF circuitry.
In certain applications where the ground
plane for the digital circuitry is expected to
be noisy, the ground plane may be split in
an analogue and a digital part. All AGND
pins and AVDD de-coupling capacitors
should be connected to the analogue
ground plane. All DGND pins and DVDD
de-coupling
capacitors
should
be
connected to the digital ground. The
connection between the two ground
planes should be implemented as a star
connection with the power supply ground.
A development kit with a fully assembled
PCB is available, and can be used as a
guideline for layout.
Antenna Considerations
CC1050 can be used together with various
types of antennas. The most common
antennas for short range communication
are monopole, helical and loop antennas.
Monopole
antennas
are
resonant
antennas with a length corresponding to
one quarter of the electrical wavelength
(λ/4). They are very easy to design and
can be implemented simply as a “piece of
wire” or even integrated into the PCB.
Non-resonant monopole antennas shorter
than λ/4 can also be used, but at the
expense of range. In size and cost critical
applications such an antenna may very
well be integrated into the PCB.
Helical antennas can be thought of as a
combination of a monopole and a loop
antenna. They are a good compromise in
size critical applications. But helical
antennas tend to be more difficult to
optimise than the simple monopole.
Loop antennas are easy to integrate into
the PCB, but are less effective due to
SWRS044
difficult impedance matching because of
their very low radiation resistance.
For low power applications the λ/4monopole antenna is recommended giving
the best range and because of its
simplicity.
The length of the λ/4-monopole antenna is
given by:
L = 7125 / f
where f is in MHz, giving the length in cm.
An antenna for 869 MHz should be 8.2
cm, and 16.4 cm for 434 MHz.
The antenna should be connected as
close as possible to the IC. If the antenna
is located away from the input pin the
antenna should be matched to the feeding
transmission line (50 Ω).
For a more thorough primer on antennas,
please refer to Application Note AN003
SRD Antennas available from Chipcon’s
web site.
Page 29 of 40
CC1050
Configuration registers
The configuration of CC1050 is done by
programming the 19 8-bit configuration
registers. The configuration data based on
selected system parameters are most
easily found by using the SmartRF®
Studio software. A complete description of
the registers are given in the following
tables. After a RESET is programmed all
the registers have default values.
REGISTER OVERVIEW
ADDRESS
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
40h
41h
42h
43h
44h
45h
46h
Byte Name
MAIN
FREQ_2A
FREQ_1A
FREQ_0A
FREQ_2B
FREQ_1B
FREQ_0B
FSEP1
FSEP0
CURRENT
XOSC
PA_POW
PLL
LOCK
CAL
Not used
Not used
MODEM0
Not used
FSCTRL
PRESCALER
TEST6
TEST5
TEST4
TEST3
TEST2
TEST1
TEST0
Description
MAIN Register
Frequency Register 2A
Frequency Register 1A
Frequency Register 0A
Frequency Register 2B
Frequency Register 1B
Frequency Register 0B
Frequency Separation Register 1
Frequency Separation Register 0
Current Consumption Control Register
Crystal Oscillator Control Register
PA Output Power Control Register
PLL Control Register
LOCK Status Register and signal select to CHP_OUT (LOCK) pin
VCO Calibration Control and Status Register
Not used
Not used
Modem Control Register
Not used
Frequency Synthesiser Control Register
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Prescaler Control Register
Test register for PLL LOOP
Test register for PLL LOOP
Test register for PLL LOOP (must be updated as specified)
Test register for VCO
Test register for Calibration
Test register for Calibration
Test register for Calibration
SWRS044
Page 30 of 40
CC1050
MAIN Register (00h)
REGISTER
NAME
MAIN[7]
MAIN[6]
F_REG
Default
value
-
MAIN[5]
MAIN[4]
MAIN[3]
MAIN[2]
MAIN[1]
TX_PD
FS_PD
CORE_PD
BIAS_PD
-
H
H
H
H
MAIN[0]
RESET_N
-
L
FREQ_2A Register (01h)
REGISTER
NAME
FREQ_2A[7:0]
FREQ_A[23:16]
FREQ_1A Register (02h)
REGISTER
NAME
FREQ_1A[7:0]
FREQ_A[15:8]
FREQ_0A Register (03h)
REGISTER
NAME
FREQ_0A[7:0]
FREQ_A[7:0]
FREQ_2B Register (04h)
REGISTER
NAME
FREQ_2B[7:0]
FREQ_B[23:16]
FREQ_1B Register (05h)
REGISTER
NAME
FREQ_1B[7:0]
FREQ_B[15:8]
FREQ_0B Register (06h)
REGISTER
NAME
FREQ_0B[7:0]
FREQ_B[7:0]
FSEP1 Register (07h)
REGISTER
FSEP1[7:3]
FSEP1[2:0]
FSEP_MSB[2:0]
FSEP0 Register (08h)
REGISTER
FSEP0[7:0]
NAME
NAME
FSEP_LSB[7:0]
Active
-
Description
Not used
Selection of Frequency Register, 0 : Register A, 1 :
Register B
Not used
Power Down of Signal Interface and PA
Power Down of Frequency Synthesiser
Power Down of Crystal Oscillator Core
Power Down of BIAS (Global_Current_Generator)
and Crystal Oscillator Buffer
Reset, active low. Writing RESET_N low will write default
values to all other registers than MAIN. Bits in MAIN do
not have a default value, and will be written directly
through the configurations interface. Must be set high to
complete reset.
Default
value
01110101
Active
Default
value
10100000
Active
Default
value
11001011
Active
Default
value
01110101
Active
Default
value
10100101
Active
Default
value
01001110
Active
Default
value
000
Active
Default
value
01011001
-
8 MSB of frequency control word A
-
Description
Bit 15 to 8 of frequency control word A
-
Description
8 LSB of frequency control word A
-
Description
8 MSB of frequency control word B
-
Description
Bit 15 to 8 of frequency control word B
-
Description
8 LSB of frequency control word B
-
Description
Not used
3 MSB of frequency separation control
Active
SWRS044
Description
-
Description
8 LSB of frequency separation control
Page 31 of 40
CC1050
CURRENT Register (09h)
REGISTER
NAME
CURRENT[7:4]
VCO_CURRENT[3:0]
Default
value
1100
Active
-
Description
Control of current in VCO core
0000 : 160µA
0001 : 320µA
0010 : 480µA
0011 : 630µA
0100 : 790µA
0101 : 950µA
0110 : 1100µA
0111 : 1250µA
1000 : 1560µA, use for f< 500 MHz
1001 : 1720µA
1010 : 1870µA
1011 : 2030µA
1100 : 2180µA
1101 : 2340µA
1110 : 2490µA
1111 : 2640µA, use for f>500 MHz
CURRENT[3:2]
CURRENT[1:0]
PA_DRIVE[1:0]
10
Not used
Control of current in VCO buffer for PA
00 : 1mA
01 : 2mA, use for TX, f<500 MHz
10 : 3mA
11 : 4mA, use for TX, f>500 MHz
XOSC Register (0Ah)
REGISTER
XOSC[7:1]
XOSC[0]
NAME
XOSC_BYPASS
Default
value
0
Active
SWRS044
-
Description
Not used
0 : Internal XOSC enabled
1 : Power-Down of XOSC, external CLK used
Page 32 of 40
CC1050
PA_POW Register (0Bh)
REGISTER
PA_POW[7:4]
PA_HIGHPOWER[3:0]
Default
value
0000
PA_POW[3:0]
PA_LOWPOWER[3:0]
1111
-
NAME
Default
value
Active
EXT_FILTER
0
-
PLL Register (0Ch)
REGISTER
PLL[7]
PLL[6:3]
NAME
REFDIV[3:0]
0010
Active
-
-
Description
Control of output power in high power array.
Should be 0000 in PD mode . See
Table 3 page 25 for details.
Control of output power in low power array
Should be 0000 in PD mode. See
Table 3 page 25 for details.
Description
1 : External loop filter
0 : Internal loop filter
1-to-0 transition samples F_COMP
comparator when BREAK_LOOP=1
(TEST3)
Reference divider
0000 : Not allowed
0001 : Not allowed
0010 : Divide by 2
0011 : Divide by 3
...........
PLL[2]
ALARM_DISABLE
0
h
PLL[1]
ALARM_H
-
-
PLL[0]
ALARM_L
-
-
SWRS044
1111 : Divide by 15
0 : Alarm function enabled
1 : Alarm function disabled
Status bit for tuning voltage out of range
(too close to VDD)
Status bit for tuning voltage out of range
(too close to GND)
Page 33 of 40
CC1050
LOCK Register (0Dh)
REGISTER
LOCK[7:4]
NAME
LOCK_SELECT[3:0]
Default
value
0000
Active
Description
-
Selection of signals to CHP_OUT (LOCK) pin
0000 : Normal, pin can be used as CHP_OUT
0001 : LOCK_CONTINUOUS (active high)
0010 : LOCK_INSTANT (active high)
0011 : ALARM_H (active high)
0100 : ALARM_L (active high)
0101 : CAL_COMPLETE (active high)
0110 : Not used
0111 : REFERENCE_DIVIDER Output
1000 : TX_PDB (active high, activates external
PA when TX_PD=0)
1001 : Not used
1010 : Not used
1011 : Not used
1100 : Not used
1101 : Not used
1110 : N_DIVIDER Output
1111 : F_COMP
LOCK[3]
PLL_LOCK_
ACCURACY
0
-
0 : Sets Lock Threshold = 127, Reset Lock
Threshold = 111. Corresponds to a worst case
accuracy of 0.7%
1 : Sets Lock Threshold = 31, Reset Lock
Threshold =15. Corresponds to a worst case
accuracy of 2.8%
LOCK[2]
PLL_LOCK_
LENGTH
LOCK_INSTANT
LOCK_CONTINUOUS
0
-
0 : Normal PLL lock window
1 : Not used
-
-
Status bit from Lock Detector
Status bit from Lock Detector
LOCK[1]
LOCK[0]
CAL Register (0Eh)
REGISTER
NAME
CAL[7]
Active
CAL_START
Default
value
0
CAL[6]
CAL_DUAL
0
H
CAL[5]
CAL_WAIT
0
H
↑
CAL[4]
CAL_CURRENT
0
H
CAL[3]
CAL_COMPLETE
0
H
CAL[2:0]
CAL_ITERATE
101
H
SWRS044
Description
↑ 1 : Calibration started
0 : Calibration inactive
CAL_START must be set to 0 after
calibration is done
1 : Store calibration in both A and B
0 : Store calibration in A or B defined by
MAIN[6]
1 : Normal Calibration Wait Time
0 : Half Calibration Wait Time
The calibration time is proportional to the
internal reference frequency. 2 MHz
reference frequency gives 14 ms wait time.
1 : Calibration Current Doubled
0 : Normal Calibration Current
Status bit defining that calibration is
complete
Iteration start value for calibration DAC
000 - 101: Not used
110 : Normal start value
111 : Not used
Page 34 of 40
CC1050
MODEM0 Register (11h)
REGISTER
NAME
MODEM0[7]
MODEM0[6:4]
BAUDRATE[2:0]
Default
value
010
MODEM0[3:2]
DATA_FORMAT[1:0]
01
-
MODEM0[1:0]
XOSC_FREQ[1:0]
00
-
FSCTRL Register (13h)
REGISTER
NAME
FSCTRL[7:4]
FSCTRL[3:1]
FSCTRL[0]
PRESCALER[5:4]
-
Active
FS_RESET_N
1
L
PRE_SWING[1:0]
PRE_CURRENT
[1:0]
Default
value
00
-
-
-
PRESCALER[3]
BYPASS_R
0
H
PRESCALER[2]
DISCONNECT_C
0
-
PRESCALER[1:0]
-
-
-
SWRS044
Description
Not used
Reserved
Separate reset of frequency synthesizer
Active
00
Description
Not used
000 : 0.6 kBaud
001 : 1.2 kBaud
010 : 2.4 kBaud
011 : 4.8 kBaud
100 : 9.6 kBaud
101 : 19.2 kBaud
110 : 38.4 kBaud
111 : 76.8 kBaud
00 : NRZ operation.
01 : Manchester operation
10 : Transparent Asyncronous UART operation
11 : Not used
Selection of XTAL frequency range
00 : 3MHz - 4MHz crystal, 3.6864MHz
recommended
01 : 6MHz - 8MHz crystal, 7.3728MHz
recommended
10 : 9MHz - 12MHz crystal, 11.0592 MHz
recommended
11 : 12MHz - 16MHz crystal, 14.7456MHz
recommended
Default
value
-
PRESCALER Register (1Ch)
REGISTER
NAME
PRESCALER[7:6]
Active
Description
Prescaler swing. Fractions for
PRE_CURRENT[1:0] = 00
00 : 1 * Nominal Swing
01 : 2/3 * Nominal Swing
10 : 7/3 * Nominal Swing
11 : 5/3 * Nominal Swing
Prescaler current scaling
00 : 1 * Nominal Current
01 : 2/3 * Nominal Current
10 : 1/2 * Nominal Current
11 : 2/5 * Nominal Current
Bypass the resistor in the PLL loop filter
0 : Not bypassed
1 : Bypassed
Disconnect the capacitor in the PLL loop filter
0 : Capacitor connected
1 : Capacitor disconnected. Use for data rate
38.4 and 76.8 kBaud only.
Not used
Page 35 of 40
CC1050
TEST6 Register (for test only, 40h)
REGISTER
NAME
TEST6[7]
LOOPFILTER_TP1
Default
value
0
TEST6 [6]
LOOPFILTER_TP2
0
-
TEST6 [5]
CHP_OVERRIDE
0
-
TEST6[4:0]
CHP_CO[4:0]
10000
-
Active
TEST5 Register (for test only, 41h)
REGISTER
NAME
Active
-
TEST5[7:6]
TEST5[5]
CHP_DISABLE
Default
value
0
TEST5[4]
VCO_OVERRIDE
0
-
TEST5[3:0]
VCO_AO[3:0]
1000
-
Default
value
100101
Active
Active
TEST4 Register (for test only, 42h)
REGISTER
NAME
TEST4[7:6]
TEST4[5:0]
L2KIO[5:0]
TEST3 Register (for test only, 43h)
REGISTER
NAME
-
h
TEST3[7:5]
TEST3[4]
BREAK_LOOP
Default
value
0
TEST3[3:0]
CAL_DAC_OPEN
0100
-
Default
value
-
Active
Default
value
-
Active
Default
value
-
Active
TEST2 Register (for test only, 44h)
REGISTER
NAME
TEST2[7:5]
TEST2[4:0]
CHP_CURRENT
[4:0]
TEST1 Register (for test only, 45h)
REGISTER
NAME
TEST1[7:4]
TEST1[3:0]
CAL_DAC[3:0]
TEST0 Register (for test only, 46h)
REGISTER
NAME
TEST0[7:4]
TEST0[3:0]
VCO_ARRAY[3:0]
SWRS044
-
-
-
-
Description
1 : Select testpoint 1 to CHP_OUT
0 : CHP_OUT tied to GND
1 : Select testpoint 2 to CHP_OUT
0 : CHP_OUT tied to GND
1 : use CHP_CO[4:0] value
0 : use calibrated value
Charge_Pump Current DAC override value
Description
Not used
1 : CHP up and down pulses disabled
0 : normal operation
1 : use VCO_AO[3:0] value
0 : use calibrated value
VCO_ARRAY override value
Description
Not used
Constant setting charge pump current
scaling/rounding factor. Sets Bandwidth of
PLL. Use 3Fh for 38.4 and 76.8 kBaud
Description
Not used
1 : PLL loop open
0 : PLL loop closed
Calibration DAC override value, active when
BREAK_LOOP =1
Description
Not used
Status vector defining applied
CHP_CURRENT value
Description
Not used
Status vector defining applied Calibration
DAC value
Description
Not used
Status vector defining applied VCO_ARRAY
value
Page 36 of 40
CC1050
SWRS044
Page 37 of 40
CC1050
Package Description (TSSOP-24)
Note: The figure is an illustration only.
TSSOP 24
Min
Max
All dimensions in mm
Thin Shrink Small Outline Package (TSSOP)
E1
E
A
A1
E
B
4.30
0.05
0.19
6.40
0.65
7.9
4.50
1.20
0.15
0.30
D
7.7
L
0.45
Copl.
α
0°
0.75
0.10
8°
Soldering Information
Recommended soldering profile is according to IPC/JEDEC J-STD-020B, July 2002.
Plastic Tube Specification
TSSOP 4.4mm (.173”) antistatic tube.
Package
Tube Width
TSSOP 24
268 mil
Tube Specification
Tube Height
Tube
Length
80 mil
20”
Units per Tube
62
Carrier Tape and Reel Specification
Carrier tape and reel is in accordance with EIA Specification 481.
Package
Tape Width
TSSOP 24
16 mm
Tape and Reel Specification
Component
Hole
Reel
Pitch
Pitch
Diameter
8 mm
4 mm
13”
SWRS044
Units per Reel
2500
Page 38 of 40
CC1050
Ordering Information
Ordering part number
CC1050
CC1050/T&R
CC1050DK-433
CC1050DK-868
CC1050SK
Description
Single Chip RF Transceiver
Single Chip RF Transceiver
CC1050 Development Kit, 433 MHz
CC1050 Development Kit, 868/915 MHz
CC1050 Sample Kit (5 pcs)
MOQ
62 (tube)
2500 (tape and reel)
1
1
1
MOQ = Minimum Order Quantity
General Information
Document Revision History
Revision
Date
1.1
April 2004
1.2
August 2004
Description/Changes
Shaping feature removed
L1 changed to 0603 size
Crystal oscillator information added
Preliminary version removed
Minor corrections and editorial changes
Application circuit and BOM simplified
Description in the FSCTRL register changed
KOA inductor removed in BOM
Additional information on LC-filter
Disclaimer
Chipcon AS believes the information contained herein is correct and accurate at the time of this printing. However,
Chipcon AS reserves the right to make changes to this product without notice. Chipcon AS does not assume any
responsibility for the use of the described product; neither does it convey any license under its patent rights, or the
rights of others. The latest updates are available at the Chipcon website or by contacting Chipcon directly.
To the extent possible, major changes of product specifications and functionality will be stated in product specific
Errata Notes published at the Chipcon website. Customers are encouraged to sign up for the Developer’s Newsletter
for the most recent updates on products and support tools.
When a product is discontinued this will be done according to Chipcon’s procedure for obsolete products as
described in Chipcon’s Quality Manual. This includes informing about last-time-buy options. The Quality Manual can
be downloaded from Chipcon’s website.
Trademarks
SmartRF® is a registered trademark of Chipcon AS. SmartRF® is Chipcon's RF technology platform with RF library
cells, modules and design expertise. Based on SmartRF® technology Chipcon develops standard component RF
circuits as well as full custom ASICs based on customer requirements and this technology.
All other trademarks, registered trademarks and product names are the sole property of their respective owners.
Life Support Policy
This Chipcon product is not designed for use in life support appliances, devices, or other systems where malfunction
can reasonably be expected to result in significant personal injury to the user, or as a critical component in any life
support device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness. Chipcon AS customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Chipcon AS for any damages resulting
from any improper use or sale.
© 2004, Chipcon AS. All rights reserved.
SWRS044
Page 39 of 40