TRF2432
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SLWS177A – APRIL 2005 – REVISED DECEMBER 2005
Dual-Band IQ/IF TRANSCEIVER WITH DUAL VCO SYNTHESIZERS
•
FEATURES
•
•
•
•
•
•
Highly Integrated 802.11 a/b/g Radio IQ/IF
Transceiver PLL ASIC
Fully Integrated IF and RF VCOs and
Synthesizers
Super Heterodyne Architecture for Superior
Performance
Internal PLL Reference Oscillator with Clock
Output for Base-Band ASICs
Internal AGC and Power Control Function
IQ DC Offset Calibration Function and
Anti-Aliasing Filters Integrated
•
•
•
•
•
•
Differential LO and IF Interface for Enhanced
Spurious Immunity
Lead Free Package
RF LO Frequency Range:
– 2651 – 3150 MHz
Phase Noise 0.5 Degrees RMS Typical over
Channel BW
Reference Frequency: 40 or 44 MHz
Single 3.3-V Power Supply
IF = 374 MHz (Both Bands)
42
41
40
39
38
37
36
35
34
33
32
31
30
29
15
16
17
18
19
20
21
22
23
24
25
26
27
28
1
2
3
4
5
6
7
8
9
10
11
12
13
14
GND
RXQP
RXQN
RXIP
RXIN
GND
V+IFLO
STATUS
PE
TR
PAEN
RSVD1
IFLOBP
IFLOTUN
RSVD3
XTALO
V+D
CLKON
XTALBYP
CLKOP
V+CLK
CLK
DATA
EN
CALEN
XTALI
GND
REFDIV
RFPD
PAPDA
PAPDB
ABSEL
V+RFLO
GND
LON
LOP
GND
V+CP
RSVD2
RFLOBP
RFLOTUN
RFLOCP
56
55
54
53
52
51
50
49
48
47
46
45
44
43
V+TR
IFP
IFN
RXAGC
TXGC(0)
TXGC(1)
TXGC(2)
TXGC(3)
TXGC(4)
RXCMADJ
TXIP
TXIN
TXQP
TXQN
TBD PACKAGE
(TOP VIEW)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005, Texas Instruments Incorporated
TRF2432
www.ti.com
SLWS177A – APRIL 2005 – REVISED DECEMBER 2005
DESCRIPTION
The TRF2432 is a fully integrated IQ transceiver specifically for use in 802.11 applications. The TRF2432 is
designed to perform the IQ conversion at 374MHz IF as well as provide an RFLO and control logic to a TI RFFE
(Radio Frequency Front End). The TRF2432 uses a common IF frequency for both bands, which eliminates the
need for an additional IF filter in dual band applications. The TRF2432 has an internal IQ DC offset calibration
function for the receive IQ interface. Combined with a TI integrated RFFE, the TRF2432 completes the TI WLAN
two-chip radio.
The TRF2432 incorporates all of the system blocks from the modem to the RFFE except for the IF filtering and
the reference crystal. The ASIC uniquely incorporates an internal PLL reference oscillator where only a crystal is
needed, and also provides a clock output for base-band/MAC ASICs. TRF2432 includes two synthesizers with
VCOs, IQ modulator, IQ demodulator, anti aliasing filters, IF amplifiers, receive AGC circuit, transmit power
control and serial interface.
Functional Block Diagram
RX
AGC
RXAGC
CALEN
LPF
LPF
2
DC Offset
Calibration
RXI
RXQ
2
90
o
STATUS
T/R
IF
Synth
XTALI
T/R
IF
2
XTALO
RF
Synth
LO
2
/2
2
RFPD
PWR
CTRL
PAPDA
PAPDB
A/B
Control
ABSEL
90
TX
GC
Serial
Dec.
3
CLKOUT
REFDIV
PE
PAEN
SERIAL
TR
o
5
2
TXGC
TXQ
TXI
2
DEVICE INFORMATION
Table 1. TERMINAL FUNCTIONS
TERMINAL
I/O
TYPE
DESCRIPTION
1
O
Analog
RFFE sleep output
2
O
Analog
PA band A select to RFFE
3
O
Analog
PA band B select to RFFE
NAME
NO.
RFPD
PAPDA
PAPDB
2
TRF2432
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SLWS177A – APRIL 2005 – REVISED DECEMBER 2005
DEVICE INFORMATION (continued)
Table 1. TERMINAL FUNCTIONS (continued)
TERMINAL
I/O
TYPE
DESCRIPTION
4
O
Analog
A or B band select to RFFE
V+RFLO
5
I
Power
+3.3V Power Supply. RF VCO bias
GND
6
I
Analog
Connect to ground per suggested layout for normal operation
LON
7
O
RF Dif.
Positive going LO output
LOP
8
O
RF Dif.
Negative going LO output
GND
9
I
Analog
Connect to ground per suggested layout for normal operation
V+CP
10
I
Power
+3.3V Power Supply. Synthesizer Charge Pumps bias
RSVD2
11
-
-
RFLOBP
12
O
Analog
Bypass Capacitor for LO1 (RF)
RFLOTUN
13
I
Analog
VCO Synthesizer 1 (RF) Tuning port
RFLOCP
14
O
Analog
Synthesizer 1 (RF) Charge pump output
RSVD3
15
-
-
XTALO
16
I/O
Analog
Negative crystal connection
V+D
17
I
Power
+3.3V Power Supply. Digital Bias
CLKON
18
O
Digital
Negative going reference clock output (40,44,20 or 22MHz)
XTALBYP
19
O
Analog
Bypass Capacitor for crystal oscillator
CLKOP
20
O
Digital
Positive going reference clock output (40,44,20 or 22MHz)
V+CLK
21
I
Power
+3.3V Power Supply. Reference Clock Bias
CLK
22
I
Digital
Clock line of 3-wire serial bus
DATA
23
I
Digital
Data line of 3-wire serial bus
EN
24
I
Digital
Load enable line of 3-wire serial bus
CALEN
25
I
Digital
A transition high in RX active mode initiates DC offset calibration. Low disables
calibration circuit. Internal pull down
XTALI
26
I/O
Analog
Positive crystal connection. Also input for external XO reference
GND
27
I
Analog
Connect to ground per suggested layout for normal operation
REFDIV
28
I
Digital
Sets reference clock divider. Set HIGH to activate divide by 2. Internal pull down.
IFLOTUN
29
I
Analog
VCO Synthesizer 2 (IF) Tune port. CP2 Connected internally
IFLOBP
30
O
Analog
Bypass Capacitor for LO2 (IF)
RSVD1
31
-
-
PAEN
32
I
Digital
PA enable. HIGH enables RFFE PA. Enables PAPDA or PAPDB. Internal pull
down.
TR
33
I
Digital
Transmit or Receive control line. TX=HIGH, RX=LOW. Internal pull down.
PE
34
I
Digital
Power enable. HIGH is enabled. Not defined internally.
STATUS
35
O
Digital
RF, IF and REF synthesizer lock detect and calibration status.
V+IFLO
36
I
Power
+3.3V Power Supply. IF VCO bias
GND
37
I
Analog
Connect to ground per suggested layout for normal operation
RXIN
38
O
Analog
Receiver in-phase negative going output.
RXIP
39
O
Analog
Receiver in-phase positive going output.
RXQN
40
O
Analog
Receiver quadrature negative going output.
RXQP
41
O
Analog
Receiver quadrature positive going output.
GND
42
I
Analog
Connect to ground per suggested layout for normal operation
TXQN
43
I
Analog
Transmitter quadrature negative going output.
TXQP
44
I
Analog
Transmitter quadrature positive going output.
TXIN
45
I
Analog
Transmitter in-phase negative going output.
TXIP
46
I
Analog
Transmitter in-phase positive going output.
NAME
NO.
ABSEL
Reserved. Leave open
Reserved. Leave open
Reserved. Leave open.
3
TRF2432
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SLWS177A – APRIL 2005 – REVISED DECEMBER 2005
DEVICE INFORMATION (continued)
Table 1. TERMINAL FUNCTIONS (continued)
TERMINAL
NAME
NO.
I/O
TYPE
DESCRIPTION
RXCMADJ
47
I
Analog
Connect resistor to ground to adjust common mode output voltage
TXGC[4]
48
I
Digital
TX Gain Control bit 4 (MSB). Logic LOW induces 16dB Atten. Internal pull down.
TXGC[3]
49
I
Digital
TX Gain Control bit 3. Logic LOW induces 8dB Atten. Internal pull down.
TXGC[2]
50
I
Digital
TX Gain Control bit 2. Logic LOW induces 4dB Atten. Internal pull down.
TXGC[1]
51
I
Digital
TX Gain Control bit 1. Logic LOW induces 2dB Atten. Internal pull down.
TXGC[0]
52
I
Digital
TX Gain Control bit 0 (LSB). logic LOW induces 1dB Atten. Internal pull down.
RXAGC
53
I
Analog
Receiver automatic gain control pin.
IFN
54
I/O
RF Dif.
IF positive going input or output.
IFP
55
I/O
RF Dif.
IF negative going input or output.
V+TR
56
I
Power
+3.3V Power Supply. TX and RX IF amplifier bias.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
UNIT
DC supply voltage, VCC
0 to 5.5 V
DC supply current, ICC
RF input power
600 mA
Any port and any mode
+10 dBm
Digital input voltage, VID
-0.3 V to VCC+0.3 V
Analog input voltage, VIA
0 to 3.6 V
Junction temperature, TJC
125°C
Thermal resistance junction-to-case, θJC
25°C/W
Operating temperature, TA
-20°C to +85°C
Storage temperature, Tstg
Lead temperature
-40°C to +105°C
40 sec maximum
+220°C
DC CHARACTERISTICS
PARAMETER
VCC
TEST CONDITIONS
MIN
2.7
TYP
UNIT
Supply votlage
Specification compliant
3.3
3.6
V
Transmit Mode Supply Current
TR = High, Active mode
100
125
mA
Receive Mode Supply Current
TR = Low, Active mode
90
110
mA
Idle Mode Supply Current
70
85
mA
Standby Mode Supply Current
10
15
mA
10
µA
Sleep Mode Supply Current
DC current, V+RFLO
DC current, V+CP
4
MAX
VCC = 3.3 V, 0 < V+RFLO < V+TR Standby
+ 0.6V
Idle
V+TR - 0.6V < V+CP < V+TR +
0.6V
0
0
Tx
11
Rx
11
Standby
0
Idle
0.6
Tx
0.6
Rx
0.6
TRF2432
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SLWS177A – APRIL 2005 – REVISED DECEMBER 2005
DC CHARACTERISTICS (continued)
PARAMETER
DC current, V+D
DC current, V+CLK
DC current, V+IFLO
TEST CONDITIONS
V+TR - 0.6V < V+D < V+TR +
0.6V
V+TR - 0.6V < V+CLK < V+TR +
0.6V
0 < V+IFLO < V+TR + 0.6V
MIN
Standby
50/30
Tx
50/30
Rx
50/30
Standby
4
Idle
4
Tx
4
Rx
4
Standby
0
Idle
0
UNIT
8.5
Rx
3.6 V max
MAX
8.5
Idle
Tx
DC current, V+TR
TYP
8.5
Standby
0.35
Idle
0.35
Tx
33/21
Rx
20
RECEIVER CHARACTERISTICS
TA = 25°C and VCC = 3.3 V (unless otherwise noted)
PARAMETER
fIF
TEST CONDITIONS
MIN
IF input frequency
Voltage gain
Gain control < 0.3 V
62
Analog Gain Control Range
VAGC from .3 to 2.2V
55
Gain Control Sensitivity
Monotonic.
Gain Control Linearity
From linear
Gain settling time
Full range to within 0.5dB final gain
setting
Output P-1dB
TYP
MAX
MHz
71
dB
dB
-40
-50
0.25
µs
4.8
Vppd
-7
From Full Gain to 40dB gain. Not to
increase more than 1dB per 1dB of
gain change thereafter.
IQ differential impedance
I, Q outputs (0-11MHz)
Output load impedance
Single ended
dBm
7
dB
100
2||10
1000
Measured into 200-Ω differential
Output common mode voltage
Adjustable by one resistor to ground.
Vcom = 0.56 + 0.48 × RADJ, RADJ is
kΩ
I/Q gain mismatch
0 to 11 MHz band
I/Q phase imbalance
0 to 11 MHz band
I/Q differential DC offset
Ω
kΩ||pF
Output swing
Input return loss
dB/V
±3
Output 3rd order intercept point
Noise figure
UNIT
374
9
mVpd
dB
1.4
V
0.1
0.5
dB
0.9
3
°
After calibration. Min Gain
10
mV
Before calibration
50
mV
DC offset calibration time
With 40 MHz reference. See
calibration instructions
LPF attenuation
25 MHz
10.55 MHz
0.6
20
32
µs
25
dB
1
dB
5
TRF2432
www.ti.com
SLWS177A – APRIL 2005 – REVISED DECEMBER 2005
TRANMITTER CHARACTERISTICS
TR = High, 2dB base band filter loss in RX band, MIN, TYP, and MAX rating are at 25°C and VCC = 3.3 V (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
ZID
Differential input impedance
I, Q inputs. (0 – 11MHz)
10
VIC
Common-mode input voltage
Effected by V+. TRF2432
1.1
VI
Input voltage
I, Q inputs, differential.
fIF
IF input frequency
Voltage gain
TX Gain Control Word} = {11111} (1),
200-Ω differential output
3
Gain control range
(1)
Gain step size
Per bit
Sideband suppression
0 to 11 MHz band
IFLO leakage
Max. gain settings. TX IQ DC offset
< 1 mV
Output 1dB compression
Maximum gain setting
Output noise
Maximum Gain. Decreasing 1dB per
dB attenuation until 15 dB
16 to 31dB down from max gain.
25
TYP
UNIT
kΩ
2.1
V
0.3
Vpd
374
MHz
5
dB
31
dB
1
dB
30
dB
-40
2
MAX
-35
dBm
-137
-131
dBm/Hz
-145
-144
dBm/Hz
4
dBm
Gain is referenced to the amplitude of either the I or Q signal, when they are in quadrature. i.e. For I = 0.5 × sin (wmt) and Q = 0.5 ×cos
(wmt) input in differential volts. The output at a gain of 0dB would ideally be a single tone at 0.5V differential across the 200-Ω outputs.
COMMON ELECTRICAL CHARACTERISTICS
MIN, TYP, and MAX ratings are at 25°C and VCC = 3.3 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
IF IO differential impedance
TYP
MAX
UNIT
Ω
200
SYNTHESIZER CHARACTERISTICS
RF SYNTHESIZER CHARACTERISTICS
PARAMETER
TEST CONDITIONS
Frequency range
MIN
TYP
2650
Tuning step
MAX
UNIT
3150
MHz
250
kHz
60
µs
Settling time
±10kHz of final frequency. From
Standby to Idle measured from
enable
Phase noise (VCO)
4.5 MHz offset
-130
dBc/Hz
20 MHz offset
-143
dBc/Hz
Integrated phase error
10 kHz to 10 MHz
Spurious suppression
0.25 < ∆f < 3 MHz offset
0.6
°rms
-45-7∆f
dBc
-70
dBc
-2
0
dBm
MIN
TYP
> 3 MHz offset
Power output
Into 100 Ω differential. With
matching
INTEGER MODE IF SYNTHESIZER CHARACTERISTICS
fREF = 44 MHz
PARAMETER
6
TEST CONDITIONS
Frequency
With 44 MHz crystal
Settling time
±10kHz of final frequency. From
Standby to Idle measured from
enable
MAX
UNIT
374
MHz
60
µs
TRF2432
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SLWS177A – APRIL 2005 – REVISED DECEMBER 2005
INTEGER MODE IF SYNTHESIZER CHARACTERISTICS (continued)
fREF = 44 MHz
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Integrated phase error
10 kHz to 10 MHz
0.2
°rms
Spurious suppression
> 3 MHz offset
-70
dBc
FRACTIONAL MODE IF SYNTHESIZER CHARACTERISTICS
fREF = 40 MHz
PARAMETER
TEST CONDITIONS
Frequency
With 44 MHz crystal
Settling time
MIN
TYP
MAX
UNIT
374
MHz
±10kHz of final frequency. From
Standby to Idle measured from
enable
60
µs
Integrated phase error
10 kHz to 10 MHz
0.1
°rms
Spurious suppression
0.25 < ∆f < 3 MHz offset
-45-7∆f
dBc
-70
dBc
> 3 MHz offset
PLL REFERENCE/CLOCK OUTPUT CHARACTERISTICS
The TRF2432 synthesizers operate from a single 40 or 44 MHz reference. The TRF2432 can generate its own
PLL reference using an internal oscillator or it may also be driven from an external reference. The TRF2432
provides a user selectable, buffered clock output for base-band ASICs.
PLL REFERENCE OSCILLATOR SPECIFICATIONS
PARAMETER
fREF
TEST CONDITIONS
MIN
Reference frequency
TYP
MAX
40 or 44
Start-up time
From power on. Depends on Crystal
characteristics
Degradation to Crystal Reference
Accuracy
From crystal series resonance.
Jitter
External XO drive
Square-wave, must be AC Coupled
Equivalent input load
Single ended
0.8
UNIT
MHz
0.5
ms
0.25
PPM
5
10
1
2
ps
Vpp
Ω||pF
500||10
RECOMMENDED CRYSTAL SPECIFICATIONS
PARAMETER
TEST CONDITIONS
MIN
MAX
40 or 44
UNIT
f
Frequency
ESR
Effective series resistance
C
Shunt capacitance
20
pF
Maximum power handling
50
µW
20
PPM
MAX
UNIT
Frequency accuracy
Series resonant, fundamental or 3rd
overtone
TYP
MHz
100
Over Temperature and Process
Ω
CLOCK OUTPUT CHARACTERISTICS
PARAMETER
fCLK
Clock output frequency
Output voltage swing
DC
Duty cycle
TEST CONDITIONS
MIN
TYP
REFDIV = 1
fREF/2
MHz
REFDIV = 0
fREF
MHz
1
Vppd
Differential
0.4
50%
7
TRF2432
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SLWS177A – APRIL 2005 – REVISED DECEMBER 2005
CLOCK OUTPUT CHARACTERISTICS (continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tr
Rise time
3
tf
Fall time
3
ns
CL
Capacitance load
8
pF
Per side
ns
DIGITAL INTERFACE CHARACTERISTICS
PARAMETER
TEST CONDITIONS
VIH
High-level input voltage
VIL
Low-level input voltage
VOH
High-level output voltage
100-µA load current
VOL
Low-level output voltage
-100-µA load current
MIN
TYP
MAX
1.7
UNIT
V
0.5
2
V
V
0.2
V
SERIAL INTERFACE TIMING REQUIREMENTS
TEST CONDITIONS
MIN
Power Enable to Serial port on
PARAMETER
From Sleep mode to standby mode.
PE High transition.
0.5
µs
Enable clock
Time to activate the serial port to
receive clocked and data.
10
ns
Hold time, data to clock
10
ns
Setup time, data to clock
10
ns
Clock low duration
10
ns
Clock high duration
10
ns
Setup time, clock to enable
10
ns
10
ns
Enable time
Should be held high when not
programming
TYP
MAX
CH
CLK
...
CD
DATA
D 15
DC
D 14
CL
D 13
...
CE
EN
EN
ON
PE
...
...
Figure 1. Serial Interface Timing Diagram
8
D0
EH
UNIT
TRF2432
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SLWS177A – APRIL 2005 – REVISED DECEMBER 2005
SERIAL REGISTERS
Data is written to the registers per the following format:
Table 2. Serial Interface Data Format
REGISTERS
ADDRESS
(MSB) 1st BIT IN
LAST BIT IN (LSB)
#
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
1
GCX
TX_H
P
REF_
S
FN_IF
X
A/B
PS1
PS0
1
1
0
1
1
0
1
0
2
CP
GC4
GC3
GC2
GC1
GC0
1
1
0
1
1
1
1
1
3
P
MR6
MR5
MR4
MR3
MR2
MR1
MR0
1
1
0
1
1
1
0
1
4
X
FI6
FI5
FI4
FI3
FI2
FI1
FI0
1
1
0
1
1
0
0
0
5
X
MI6
MI5
MI4
MI3
MI2
MI1
MI0
1
1
0
1
1
0
0
1
S_INV REF_
M
6
DI4
DI3
DI2
DI1
DI0
SI2
SI1
SI0
1
1
0
1
1
0
1
1
7
XO_L
P
FR6
FR5
FR4
FR3
FR2
FR1
FR0
1
1
0
1
1
1
0
0
8
DR4
DR3
DR2
DR1
DR0
SR2
SR1
SR0
1
1
0
1
1
1
1
0
Table 3. Serial Register Definitions
SYMBOL
# OF
BITS
DEFAULTS (1)
Power mode
PS
2
0
Determines mode of operation: Standby, Idle, or Active.
(see Table 17)
Band A or B select
A/B
1
0
Selects TX and RX band. 1 = A band and 0 = B Band
TX gain control
GC
5
[x,x,x,x,x]
S_INV
1
1
Sets both the TX I/Q modulator and RX I/Q demodulator for
spectral inversion. S_INV = 1 for spectral inversion. S_INV
= 0 for no inversion.
Crystal pre-scalar
P
1
1
Sets the crystal or reference pre-scalar divider.
RF PLL frequency
DR
5
[0,1,0,1,0] = 10
SR
3
[0,0,0] = 0
FR
7
[0,1,1,0,0,0,0]=48
MR
7
[1,0,0,1,1,1,1]=79
DI
5
X
SI
3
X
NAME
Spectral inversion
IF PLL frequency
DESCRIPTION
Controls gain setting of TX if CGX=0 (see below). {11111}
is max gain and {00000} is minimum gain.
Registers used to program the RF synthesizer operation
frequency.
Registers used to program the IF synthesizer operation
frequency. These registers are only effective, when the IF
synthesizer is in fractional-N mode (i.e. FN_IF=1)
FI
7
X
MI
7
X
GCX
1
1
GCX=0 switches the Tx gain control to the serial port.
GCX=1 switches the Tx gain control to the parallel input
pins.
FN_IF
1
0
FN_IF =1 enables the fractional N IF synthesizer FN = 0
sets the IF synthesizer to a fixed frequency
REF_S
REF_S
1
0
Always set REF_S = 0
REF_M
REF_M
1
0
Always set REF_M = 0
CP
1
0
CP = 1 puts charge pump for reference and fixed
synthesizers into continuous current mode. CP = 0 puts
synthesizers into current saving mode.
XO_LP
1
1
XO_LP =1 puts crystal oscillator in low power mode.
XO_LP = 0 puts the crystal oscillator full-power mode for
better noise performance, and start-up time.
TX gain control MUX
Fractional N IF synthesizer
Charge Pump Current
Setting
XO low power mode
(1)
Default values are the initial values after power up or after PE goes HIGH. “x” indicates undefined.
9
TRF2432
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SLWS177A – APRIL 2005 – REVISED DECEMBER 2005
Table 3. Serial Register Definitions (continued)
SYMBOL
# OF
BITS
DEFAULTS (1)
Fractional N IF synthesizer
FN_IF
1
0
FN_IF =1 enables the fractional N IF synthesizer when in
idle or active mode. FN = 0 sets the IF synthesizer to a
fixed frequency (374 MHz with 44 MHz crystal) for low
power consumption.
TX output buffer high power
TX_HP
1
0
TX_HP = 1 puts IF amplifier in high linearity mode. TX_HP
= 0 puts the IF amplifier into normal linearity mode to save
current. This does not change linearity of the RFFE.
NAME
DESCRIPTION
MODES OF OPERATION
Power Modes
Active Mode
−Tx or RX on depending on
TR setting
−VCOs on
−PA on if PAEN=HIGH and
TR=HIGH
− Can calibrate Rx DC I&Q offset
if TR=LOW
Serial CMD
Serial CMD
Standby Mode
− Crystal oscilator on
− REFOUT buffer on at
crystal frequency only.
− All registers active
− SERIAL port is active.
Idle Mode
Serial CMD
Standby Mode +
− RF/IF VCOs on
PE=
PE=
Sleep Mode
Power On
& PE=LOW
Figure 2. Power Modes
10
Power Off
Vcc=0V
TRF2432
www.ti.com
SLWS177A – APRIL 2005 – REVISED DECEMBER 2005
MODES OF OPERATION (continued)
Table 4. Power Mode Desriptions
MODE
PS1
PS0
RFFE
TX
RX
IF PLL
RF
PLL
CLK
OUT
XO
SERIA
L
Active
1
1
X
X
X
X
X
X
X
X
TR_SEL controls
Transmit/Receive mode
Idle
0
1
X
X
X
X
X
Register settings retained
X
X
X
Register settings retained
Standb
y
0
Sleep
COMMENTS
Settings not required
Input/Output Modes
The TRF2432 is designed to control power and band status for a TI RFFE. The TRF2432 is designed to drive
external P-MOSFETs to power up and down the appropriate sections of the RFFE. Table 4 lists the various
modes of the TRF2432 and the input parameters required to enter each mode. The corresponding outputs to the
RFFE are also described. Figure 4 illustrates the power control interface and recommended P-MOSFET circuit.
Table 5. Inputs/Outputs and Operational States
OPERATION
STATE
INPUT PARAMETERS
PINS
OUTPUT DRIVERS
INTERNAL FUNCTIONS
REGISTERS
PE
TR
PAEN
CALEN
PS1
PS0
A/B
PAPDA
PAPDB
RFPD
ABSEL
TX
RX
SYNTH
ESIZER
S
CRYST
AL
OSC.
AND
DRIVE
R
SERIAL
BUS
Sleep mode
Low
X
X
X
X
X
X
High
High
High
Low
Off
Off
Off
Off
Off
Standby mode
High
X
X
X
X
0
X
High
High
High
Low
Off
Off
Off
On
On
Idle mode
High
X
X
X
0
1
X
High
High
High
Low
Off
Off
Enabled
On
On
Active mode (PA
disabled)
High
X
Low
X
1
1
X
High
High
Low
=(A/B)
Enabled
Enabled
Enabled
On
On
Active mode (RX
A band)
High
Low
Low
X
1
1
1
High
High
Low
High
Off
On
Enabled
On
On
Active mode (TX
A band)
High
High
High
X
1
1
1
Low
High
Low
High
On
Off
Enabled
On
On
Active mode (RX
B band)
High
Low
Low
X
1
1
0
High
High
Low
Low
Off
On
Enabled
On
On
Active mode (TX
B band)
High
High
High
X
1
1
0
High
Low
Low
Low
On
Off
Enabled
On
On
Active mode
(RX-Cal.)
High
Low
Low
Rising
Edge
1
1
X
High
High
High (1)
=(A/B)
Off
On
Enabled
On
On
(1)
Held in open state until calibration is complete or disabled (CAL_EN = High -> Low).
SYNTHESIZER PROGRAMMING
The RF synthesizer frequency is programmed with four bytes: DR, SR, FR and MR and the crystal pre-scalar: P.
See digital interface characteristics for programming instructions). The RF PLL locking frequency is calculated as
follows:
f RFLO f RCF
FR
8 (DR 3) SR (MR 1)
(P 1)
(1)
fREF is the crystal reference frequency. On power-up the default register values (P=1, DR=10, SR=0, FR=48 and
MR=79) with a 40-MHz crystal will attempt to lock the RFLO to 2068 MHz. The valid register ranges are listed
below.
Table 6. Valid RF Register Ranges
REGISTER
MIN
MAX
DR
7
31
SR
0
7
11
TRF2432
www.ti.com
SLWS177A – APRIL 2005 – REVISED DECEMBER 2005
Table 6. Valid RF Register Ranges (continued)
REGISTER
MIN
MAX
FR
0
MR
MR
32
127
The IF frequency synthesizer defaults to integer mode (FN_IF =0) to operate from a 44 MHz reference and is
preset for 374 MHz IF. When using a 40 MHz reference, the synthesizer must be set to fractional mode (FN_IF
=1) and programmed. The synthesizer is programmed with four bytes DI, SI, FI and MI. The register
programming values for the IF synthesizer when using a 40 MHz reference are listed in Table 21.
Table 7. IF Register Values for 40-MHz Reference
REGISTER
VALUE
DI
16
SI
2
FI
32
MI
79
RFFE POWER CONTROL INTERFACE
The TRF2432 will control the RFFE power for all radio operational modes through three external P-MOSFETs.
The suggested circuit is illustrated in Figure 4.
+3.3V
IQ
XCVR
RFFE
Figure 3.
IQ DC Calibration
The TRF2432 receiver has an IQ DC offset calibration function. This operation can be performed in receiver
active mode only. The calibration process is entered by a rising edge on CALEN, which remains high as long as
the calibration is required. The calibration procedure is as follows:
1. Set to RX active mode
2. Wait for RF and IF Synthesizers to lock: STATUS=HIGH
3. Set Rx AGC to min gain
12
TRF2432
www.ti.com
SLWS177A – APRIL 2005 – REVISED DECEMBER 2005
4. Set CALEN=HIGH to enter calibration mode:
a. IQ Transceiver turns off RFFE
b. Internal calibration process runs
c. The Status bit is low during calibration procedure and returns high once the calibration is complete
5. Hold CALEN HIGH to maintain calibration
6. Return to RX active Mode
Notes on Calibration:
1. Calibration is retained as long as CALEN=HIGH and the RF2432 is not put into Sleep Mode.
2. To Reset calibration, set CALEN=LOW.
3. If CALEN is held LOW then calibration circuit is completely disabled, and does not contribute to any DC
offset.
IQ DC Calibration Timing
Table 8. Calibration Timing Requirements
PARAMETER
TEST CONDITIONS
MIN
Calibration reset
TYP
MAX
4
Status low
Calibration time
1 tick = 44/fREF (e.g., fREF = 44 MHz,
tick = 1 µs)
UNIT
µs
1
µs
68
tick
t CAL
STATUS
tSL
CALEN
t RS
Figure 4. Calibration Timing
13
TRF2432
www.ti.com
SLWS177A – APRIL 2005 – REVISED DECEMBER 2005
TYPICAL CHARACTERISTICS
80
70
60
Rx Gain (dB)
50
+25 C
+85 C
0C
−30 C
40
30
20
10
0
0
0.5
1
Rx Gain vs. Temperature
1.5
2
2.5
VAGC(V)
Figure 5. RX Gain Control vs Temperature
50
RX Output IM (−dBc)
45
40
V+=3.6V
35
V+=3.0V
V+=2.7V
30
500
1000
1500
2000
Common Mode Voltage(mV)
Rx Output IM vs. Common Mode Voltage
Note: Output set for 1000 mVpp total swing.
Input −40 dBm/tone.
Figure 6. RX Intermod Level vs Common-Mode Votlage
14
2500
TRF2432
www.ti.com
SLWS177A – APRIL 2005 – REVISED DECEMBER 2005
TYPICAL CHARACTERISTICS (continued)
55
50
Rx_IM(dBc)
45
40
35
500mVpp
30
1000mVpp
1500mVpp
25
500
1000
1500
2000
Rx Common Mode Voltage(mV)
Rx IM vs. Output Voltage Swing (V+=3.0V)
Figure 7. RX Intermod. Level vs Output Voltage Swing
3.0
2.0
P1dB (dBm)
1.0
0.0
3.6V
−1.0
3.3V
3.0V
2.7V
−2.0
−3.0
0.8
1
1.2
Tx OP1dB vs Vcm and V+
1.4
1.6
1.8
2
2.2
2.4
2.6
2.8
3
Vcm (V)
Figure 8. TX OP1dB vs Common-Mode Input Votlage
15
TRF2432
www.ti.com
SLWS177A – APRIL 2005 – REVISED DECEMBER 2005
RF SYNTHESIZER PERFORMANCE
Figure 9. RFLO Phase Noise
3400
3300
3200
LO frequency(MHz)
3100
3000
2900
2800
+85 C
2700
+25 C
2600
0C
−30 C
2500
2400
2300
2200
0.60
0.80
1.00
RC2432 RFLO Tuning vs Temperature
1.20
1.40
1.60
1.80
2.00
2.20
2.40
Vtune(V)
Figure 10. RF VCO Tuning Curves vs Voltages
16
2.60
2.80
3.00
TRF2432
www.ti.com
SLWS177A – APRIL 2005 – REVISED DECEMBER 2005
RF SYNTHESIZER PERFORMANCE (continued)
3100
3000
2900
LO frequency(MHz)
2800
2700
2600
3.6V
3.3V
2500
3.0V
2400
2.7V
2300
2200
2100
0.60
0.80
1.00
1.20
1.40
1.60
1.80
2.00
2.20
Vtune(V)
RC2432 RFLO Tuning vs V+
Figure 11. RF VCO Tuning Curves vs Temperature
900
800
Tuning Sensitivity (MHz/V)
3.6V
3.3V
700
3.0V
2.7V
600
500
400
300
0.60
0.80
1.00
RC2432 RFLO Tuning Sensitivity vs V+
1.20
1.40
1.60
1.80
2.00
2.20
Vtune(V)
Figure 12. RF VCO Tuning Sensitivity vs VCC
17
TRF2432
www.ti.com
SLWS177A – APRIL 2005 – REVISED DECEMBER 2005
RF SYNTHESIZER PERFORMANCE (continued)
1000
900
+85 C
Tuning Sensitivity (MHz/V)
800
+25 C
0C
700
−30 C
600
500
400
300
200
0.60
0.80
1.00
1.20
RC2432 RFLO Tuning Sensitivity vs Temperature
1.40
1.60
1.80
2.00
2.20
2.40
Vtune(V)
Figure 13. RFLO Tuning Sensitivity vs Temperture
IF SYNTHESIZER PERFORMANCE
Figure 14. IF Synthesizer Phase Noise
18
2.60
2.80
3.00
TRF2432
www.ti.com
SLWS177A – APRIL 2005 – REVISED DECEMBER 2005
IF SYNTHESIZER PERFORMANCE (continued)
450
LO frequency(MHz)
400
350
+85 C
+25 C
0C
−30 C
300
250
0.60
0.80
1.00
1.20
1.40
1.60
IFLO Tuning vs Temperature
1.80
2.00
2.20
2.40
2.60
2.80
3.00
Vtune(V)
Figure 15. IFLO Tuning Curves vs Temperature
120
110
+85 C
Tuning Sensitivity (MHz/V)
100
+25 C
0C
90
−30 C
80
70
60
50
40
0.60
0.80
1.00
1.20
IFLO Tuning Sensitivity vs Temperature
1.40
1.60
1.80
2.00
2.20
2.40
2.60
2.80
3.00
Vtune(V)
Figure 16. IFLO Tuning Sensitivity vs Temperature
19
TRF2432
www.ti.com
SLWS177A – APRIL 2005 – REVISED DECEMBER 2005
IF SYNTHESIZER PERFORMANCE (continued)
Figure 17. Reference Clock Differential Output
20
TRF2432
www.ti.com
SLWS177A – APRIL 2005 – REVISED DECEMBER 2005
APPLICATION INFORMATION
Figure 18. Package Dimensions
21
TRF2432
www.ti.com
SLWS177A – APRIL 2005 – REVISED DECEMBER 2005
APPLICATION INFORMATION (continued)
W2
P
W1
D1
D2
Feed Direction
Tape and Reel specifications defined per EIA−481−1A and EIA−481−2A.
Package Description
Parts
per Reel
Pitch P
(mm)
Tape Width
W1 (mm)
Reel Size
D (Inches)
Reel Width
W2 (mm)
8mm x 8mm LPCC56 Pin
3500
12
16
13
22.2
Figure 19. Tape and Reel Specifications
22
Hub Dia.
D2 (mm)
102
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